JP2005209230A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide structure of low power consumption of peripheral equipment and a peripheral equipment controller. <P>SOLUTION: This peripheral controller connected to a bus for controlling the peripheral equipment to a processing means such as a processor connected to the bus is provided with an activation start detecting means for detecting the start of an access from the processing means through the bus, an activation end detecting means for detecting the end of an operation based on the access and a power consumption control means for controlling the power consumption of the peripheral controller corresponding to the outputs of the activation start detecting means and the activation end detecting means. Low power consumption of the peripheral equipment and the peripheral equipment controller is realized. In addition, an LSI for peripheral control capable of reducing the power consumption as much as possible as relieving a burden of an external processor, etc. Furthermore, in the peripheral controller, the power consumption at a command standby state from the external processor, etc. is reduced and satisfactory responsiveness is maintained. Especially, current consumption of an SCSI system is easily reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a configuration for reducing power consumption of a peripheral device such as a workstation or a personal computer, particularly a semiconductor integrated circuit of a peripheral device control device.

  Conventionally, various studies have been made on the reduction of power consumption of peripheral devices such as workstations and personal computers and peripheral control LSIs (Large Scale Integrated) for controlling the peripheral devices.

  For example, a peripheral control LSI has a dedicated input terminal for designating a low power consumption mode, and is configured to maintain the low power consumption mode for an instructed period by an output signal from an external microprocessor or a low power consumption controller. . As a result, in the peripheral circuit LSI, for example, in a digital circuit that operates with a reference clock, a part or all of the clock is stopped for the specified period described above, thereby reducing power consumption. Also in the analog circuit inside the peripheral control LSI, the power consumption is reduced by cutting off part or all of the current source circuit during the designated period.

  As another conventional example, in a peripheral device such as a hard disk, a CDROM (Compact Disk Read Only Memory), and a floppy (registered trademark) disk, a small hard disk device issued by Alps Electric Co., Ltd., DRR040C product specification (first) In order to reduce the size and weight of the system, the power consumption is reduced except when a command is received and executed from a microprocessor or the like constituting the host computer.

  FIG. 20 shows a schematic configuration diagram of DRR040C. The DRR040C includes a disk 1801 made of a magnetic material, a head 1802 that reads magnetic information recorded on the disk 1801, a head actuator 1803 that moves the head 1802 to a target position on the disk 1801, and the disk 1801. A spindle motor 1804 for rotating the head, an actuator control circuit 1805 for controlling the operation of the head actuator 1803, a CPU (Central Processing Unit) 1806 for controlling the entire operation of the DRR040C, and the spindle motor 1804 is controlled by a control signal from the CPU 1806. Spindle motor control circuit 1807, digital information from CPU 1806 is converted into analog information and transferred to actuator control circuit 1805, D / A converter 1808, read from head 1802 The read / write circuit 1810 that shapes the received signal into a pulse train, the hard disk controller 1811 that converts the pulse train generated by the read / write circuit 1810 into parallel data, and the read / write circuit 1810 detect A / D converter 1809 which converts analog information such as head positioning into digital information and passes it to CPU 1806, a signal read from disk 1801 or a signal given from AT bus 1812 is temporarily stored, and AT bus 1812 A buffer 1813 for adjusting the reading speed difference of the plate 1801 and an AT bus control circuit 1814 controlled by the CPU 1806 and controlling the AT bus 1812 are configured.

  Here, the AT bus means a bus having an interface of PC / AT (which is a registered trademark of IBM Corporation in the United States).

  When the DRR040C receives and does not execute a command from the AT bus, the DRR040C controls as follows to suppress power consumption.

  1. When all the commands received from the AT bus are completed, the DRR 040C is in the idle mode (1). When in the idle mode (1), the CPU 1806 in the DRR 040C stops the hard disk controller 1811 and turns off the power supply of the READ / WRITE circuit 1810.

  2. DRR040C enters the idle mode (2) when it is not accessed from the AT bus for another 5 seconds after entering the idle mode (1). When in the idle mode (2), the CPU 1806 in the DRR 040C cuts off the power to the actuator control circuit 1805, the D / A converter 1808, and the A / D converter 1809.

  3. DRR040C enters standby mode when it is not accessed from the AT bus for a certain period of time after entering idle mode (2) (default is 3 minutes). When in the standby mode, the CPU 1806 in the DRR 040C turns off the spindle motor control circuit 1807 and the spindle motor 1804. Further, the CPU 1806 also enters a sleep state.

  4). Upon receipt of the sleep command from the AT bus, DRR040C enters the sleep mode, which is a complete low power consumption mode. When in the sleep mode, the DRR040C further sets the AT bus control circuit 1814 to the sleep state from the standby mode. When in the sleep mode, the DRR040C does not accept commands from the AT bus, and can start the drive only by RESET. By operating as described above, the DRR040C can reduce power consumption when a command is not received and executed from the host computer.

  Among the above-described conventional techniques, in the former, the microprocessor or controller outside the peripheral control LSI instructs the low power consumption mode. Therefore, in order to achieve the maximum reduction in power consumption, it is necessary for an external microprocessor or the like to issue a low power consumption mode command many times, and there is a problem that the burden on the external microprocessor or the like is too great. there were.

  Also, since external microprocessors cannot accurately grasp the internal operating state of the peripheral control LSI that instructs low power consumption, detailed control for low power consumption cannot be performed, and maximum low power consumption is achieved. There was a problem that electric power could not be realized.

  On the other hand, in the latter conventional example, the current consumed in the AT bus control circuit 14 is not considered in the standby mode, and there is a problem in that the power consumption increases. Also, in the sleep mode, which is a complete low power consumption mode, no commands are accepted, it can be activated only by a reset from the host computer or the like, the response point is not considered, and the overhead of the host computer is large. There was a problem of becoming.

  An object of the present invention is to provide a configuration for reducing power consumption of peripheral devices and peripheral device control devices.

  It is another object of the present invention to provide a peripheral control device such as a peripheral control LSI that can reduce power consumption to the maximum while reducing the burden on an external processor or the like.

  A further object of the present invention is to provide a peripheral control device capable of deleting power consumption in a state waiting for a command from an external processor or the like.

  Still another object of the present invention is to provide a peripheral control device with good responsiveness even when power consumption in a command waiting state from an external processor or the like is reduced.

  Another object of the present invention is to provide a SCSI bus control device capable of easily reducing current consumption of a SCSI (Small Computer System Interface) system.

  To achieve the above object, in the present invention, a peripheral control device connected to a bus to which external processing means such as a processor is connected, the activation start detecting means for detecting the start of access from the external processing means And an activation end detection means for detecting the end of the access operation and a power consumption control means. The output of the activation start detection means causes the power consumption control means to release the low power consumption mode and activate In accordance with the output of the end detection means, the power consumption control means is controlled to return to the low power consumption mode.

  Access to the peripheral control device by the external processing means is started when a command is set from the external processing means to the peripheral control device, or when the status of the peripheral control device is detected by the external processing means.

  Furthermore, in the present invention, in a SCSI system in which the bus connecting the host computer and the main CPU and peripheral devices is a SCSI bus, a selection phase in which access to the peripheral device control device and peripheral control LSI by the host computer or the like is started. The ID recognizing means for detecting the SCSI ID at this time is the above-described activation start detecting means.

  In the present invention, the peripheral control device or the peripheral control LSI is set to a low power consumption mode in a state of waiting for a command from a host computer such as an external microprocessor, and the command setting / status detection from the host computer. Cancel the low power consumption mode at the start of access. As a result, it is possible to reduce cumulative and useless power loss in the device and LSI, and to realize thorough reduction in power consumption.

  The above-described activation start detection means, activation end detection means, and power consumption control means are located inside the peripheral device control device and the peripheral control LSI. The peripheral device control device is a peripheral device control device for the main CPU, and means, for example, a file controller, a display controller, a keyboard controller, a printer controller, and a communication controller, and the peripheral control LSI means a semiconductor integrated circuit thereof. .

  In the present invention, the power consumption control means cuts off the power source of the digital circuit or the analog circuit in the main part of the device or LSI in the sleep mode, which is the low power consumption mode, to thereby remove the main power of the device or LSI. The operation of the part is stopped and the low power consumption state is maintained. When the access from the host computer or the main CPU by the command setting or status detection is started, the activation start detecting means operating at all times detects the access start, and based on this detection, the power consumption control means Cancels the low power consumption mode. Further, when the activation end detection unit detects the end of the operation accompanying the start of access, the power consumption control unit sets the low power consumption mode again.

  In the SCSI system according to the present invention, the SCSI ID recognition means is separated from other functional blocks, and in the command waiting state, the other functional blocks are set in the sleep mode, thereby reducing the power consumption of the SCSI system. Reduction can be easily performed.

  The outline of the present invention has been described above, but the present invention is not limited to these descriptions. Other aspects of the present invention will become apparent from the embodiments of the present invention described below.

  According to the present invention, the power consumption of the peripheral device and the peripheral device control device can be reduced. In addition, it is possible to provide a peripheral control LSI that can reduce power consumption to the maximum while reducing the burden on an external processor or the like. Further, in the peripheral control device, it is possible to reduce the power consumption in a state waiting for a command from an external processor or the like and to maintain a good responsiveness. In particular, it is possible to easily reduce the current consumption of the SCSI system.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 3 shows a configuration example of an information processing apparatus in which the peripheral device control apparatus or the peripheral control LSI of the present invention is used. This information processing apparatus has a basic configuration such as a workstation or a personal computer, and a main CPU 14, a ROM 15, and a RAM 16 are connected to a bus 50. A file controller 17, a display controller 18, a keyboard controller 19, a printer controller 20, a communication controller 21, etc. are connected to the bus 50. These controllers are connected to a file device 22, a liquid crystal display, a CRT display 23, a keyboard 24, a printer 25, and a communication path.

  The peripheral control device or peripheral control LSI of the present invention means the file controller 17, the display controller 18, the keyboard controller 19, the printer controller 20, the communication controller 21 and the like in such an information processing device.

  FIG. 1 is a diagram showing a peripheral control device or a one-chip peripheral control LSI according to an embodiment of the present invention. The power consumption control circuit 2 shown in the figure stops the internal clock when the device or LSI shown in the figure does not receive any command setting or command access from the main CPU 14 via the bus 50, and registers 8 10 to 10, power consumption control means for stopping the operation of the I / O control circuits 11 to 13 and preventing loss of power consumption in the sleep mode, and also has a function of activation detection means. At this time, the power consumption control circuit 2, the address latch 3, the latch 6, the address decoder 4, and the gate 5 are always in an operating state.

  Thereafter, when a command setting from the main CPU 1806 occurs, the power consumption control circuit 2 starts command setting, that is, activates by the chip select, write strobe, etc. from the main CPU 14 and the output of the address coder 4 and gate 5. Then, the internal clock is supplied to the register groups 8 to 10 and the I / O control circuits 11 to 13.

  As a result, the register groups 8 to 10 and the I / O control circuits 11 to 13 become operable, and the command held in the latch 6 is transferred to the command registers in the register groups 8 to 10. Therefore, the command execution state from the main CPU 1806 is entered. When this command processing is completed, the I / O control circuits 11 to 13 output a command end signal to the NOR gate 1 as the activation end detection means, and these NOR gate 1 outputs are input to the power consumption control circuit 2. Is done. Thus, the power consumption control circuit 2 stops the internal clock output again and returns to the low power consumption mode.

  Next, in accesses other than command setting from the main CPU 14, the power consumption control circuit 2 detects access start, that is, activation by chip select, write strobe or read strobe, and operates the control LSI or control device. Enable and cancel the low power consumption mode. At this time, the address latch 3 and the latch 6 are always in an operating state. Write data is output to the inside via the latch 6, and read data is output to the outside via the gate 7. In addition, since such intermittent access is short in one cycle, the end of the activation is detected by the activation end detecting means provided in the power consumption control circuit 2 and returned to the low power consumption mode.

Next, an example of the internal configuration of the power consumption control circuit 2 will be described with reference to the block diagram of FIG. 2 and the timing charts of FIGS. 4 and 5. When the address and command data are sent from the main CPU 14 together with control signals such as chip select and write strobe, the power consumption control circuit 2 switches the gate 26 and gate 28 from the chip select and write strobe as shown in FIG. Then, the RS flip-flop 29 is set (time point t ₁ ).

At this time, the command data is held in the latch 6 by the latch enable signal output from the gate 43, and the address is similarly held in the address latch 3 by the output address latch enable of the gate 28. The output of the RS flip-flop 29 is cycled by the edge trigger flip-flops 31 and 32, and the output of the flip-flop 32 operates the internal clock via the gate 33 to release the low power consumption mode (time point t ₂ ). .

As a result, the internal write strobe that is the output of the flip-flop 34 is output, and the command write strobe output is input to the flip-flop 41 via the address decoder 4 (time point t ₃ ). At this time, the command held in the latch 6 by the command write strobe is transferred to the command registers of the register groups 8 to 9, and processing in each of the I / O control circuits 11 to 13 is started. Further, the output of the flip-flop 41 is made ready to accept a command end signal via the gate 1 of the I / O control circuits 11-13.

Thereafter, when the command processing of each of the I / O control circuits 11 to 13 ends, a command end signal via the gate 1 is input to the gate 38 of the power consumption control circuit 2 (time point t ₄ ), and the gate 39 and flip-flop 40 The RS flip-flop 29 is reset via time (time t ₅ ). The output of gate 29 controls the gate 33 through the flip-flops 31 and 32, stopping the internal clock, back to the low power consumption mode (time t _6).

Next, access operations other than command setting of the main CPU 14 will be described with reference to FIG. The sequence for canceling the low power consumption mode is the same as in the case of FIG. 4, but the return to the low power consumption mode is performed by the internal write strobe that is the output of the flip-flop 34 of FIG. When a certain internal read strobe is asserted (time t ₁₀ ), the RS flip-flop 29 is reset as shown in FIG. 5 via the gates 35, 37 and 39 and the flip-flop 40 (time t ₁₁ ). The output of the RS flip-flop 29 controls the gate 33 through the flip-flops 31 and 32, to return to the low power consumption mode stops the internal clock (time t _12). That is, in the present embodiment, the flip-flops 34, 36, 40 and the gate groups 35, 37, 38, 39 function as activation end detection means.

  In the above description of the embodiment, the reduction in power consumption in the digital circuit has been described. However, in the analog circuit, the output of the flip-flop 32 or the output of the RS flip-flop 29 in FIG. By cutting off the current source, low power consumption can be realized.

  Now, the second embodiment of the present invention will be described in detail with reference to FIG. 6 and subsequent drawings. The second embodiment relates to a system in which the present invention is applied to a SCSI (Small Computer System Interface). The SCSI system is applied when a SCSI bus is used as the bus 27 (FIG. 3) to which the various peripheral devices and peripheral control devices described above are connected.

  As a general SCSI control LSI for controlling the SCSI bus, there is one described in the data sheet of NCR's advanced SCSI controller 53C90A, 53C90B, but low power consumption is not considered. . For the basic protocol of the SCSI bus, refer to, for example, SCSI-2 proposed by ANSI (American National Standard for Information System) on March 9, 1990.

  FIG. 6 shows the principle configuration of the second embodiment. In the figure, the SCSI system includes a SCSI bus 601 and a SCSI controller 602. The SCSI controller 602 is separated and independent from the SCSI ID recognition unit 603 and other functional blocks 604 in terms of power supply. Still another functional block 604 has a sleep function. Reference numeral 605 denotes a sleep release signal that means activation start. As will be described in detail later, this function block 604 disconnects the clock input and enters the sleep mode, which is a low power consumption mode, when the execution of all the commands in the command queue is completed. In the command waiting state, the operation is stopped except for the ID recognition unit 603 and no current is consumed. Therefore, current consumption can be kept small.

  The ID recognition unit 603 has a function of detecting that the SCSI system has been selected by another SCSI system via the SCSI bus. When the ID recognizing unit 603 detects that it has been selected by another SCSI system by the function as the activation start detecting means, the function block 604 activates a part or all of the minimum necessary circuits. Send a wake-up signal. That is, a clock can be input and activated to a part or all of the minimum necessary circuits. Further, the ID recognition unit 603 and the other function block 604 have separate power sources, and the function block 604 is turned off when it enters the sleep state. Since the connection is made when the sleep cancel signal 605 sent from the ID recognition unit 603 is received, the power consumption in the sleep mode can be minimized.

  Further, the SCSI control LSI in the present embodiment has a sleep state activation register or a sleep state activation input signal, and when the sleep state setting value is set or the sleep state activation signal is asserted, Except for the ID recognition unit 603, the circuit enters a sleep state. Further, when the SCSI control LSI receives the sleep release signal sent from the ID recognition unit 603, the SCSI control LSI performs sleep release for each circuit block in accordance with a value set in a register for managing sleep release information for each circuit block. Therefore, the current consumption can be controlled to be minimum depending on the selection state in the ID recognition unit 603 and the system configuration. Further, the SCSI control LSI has an external circuit wake-up signal 605 output from the ID recognition unit 603 in addition to a normal interrupt signal, and recognizes that the SCSI control LSI is selected from another SCSI system. Since the ID recognizing unit 603 asserts the sleep release signal 605 of the external circuit, it is possible to connect the power circuit for another functional block that has been disconnected while waiting for a command from another SCSI system. Can wake up from sleep.

  A specific configuration for realizing the principle of the second embodiment described above is shown in FIG. In the figure, reference numerals 1801 to 1813 denote the same elements as those of the conventional structure shown in FIG. A SCSI bus control circuit 701 that is controlled by the internal CPU 1806 to control the SCSI bus 601 and a sleep signal 837 given from the internal CPU 1806 are used to cut off the power of all circuits except for some circuits of the SCSI bus control circuit 701. Further, a power supply control circuit 835 as a power consumption control means for controlling power supply to the internal CPU 1806, the SCSI bus control circuit 701 and the buffer 1813 by a sleep release signal 833 output from the SCSI bus control circuit 701 is a new component. is there.

  FIG. 8 shows a block diagram of an example of the SCSI bus control circuit 701. For convenience of illustration, it should be noted that the right side of the figure is connected to the SCSI bus 601 and the left side of the figure is connected to the internal bus 1815, which is reversed to the left and right of FIG. The SCSI bus control circuit 701 is roughly divided into functional blocks 841, 842, 843 divided by broken lines.

  In the figure, an internal CPU data bus 801 is a data bus for accessing the SCSI bus control circuit 701 from the CPU 1806, and constitutes a part of the internal bus 1815. The read / write controller 802 receives internal registers 803 to 811 of the SCSI bus control circuit 701 based on signals such as RD /, WR /, CS /, DACK /, DWR /, DRD /, etc., output from the CPU 1806, the hard disk controller 1811, and the like. , 815 to 818, 1608, FIFO 819, and the like. In this specification, “/” after the signal name means an inverted signal. Internal registers 803, 804, 805, 806, 807, 808, 809, 810, 811 are respectively transfer count value register, destination ID register, command register, config 1 register, config 2 register, synchronous offset register, synchronous transfer period register , A time-out register and a clock conversion register. The CPU 1806 can control the SCSI protocol by setting values in these register groups.

  Reference numeral 812 denotes a SCSI data bus single end receiver, and reference numeral 813 denotes a SCSI data bus single end 48 mA sink driver. 814 is a SCSI bus control signal single-ended receiver, and 824 is a SCSI bus control signal single-ended 48 mA sink driver. Reference numerals 815, 816, 817, and 818 denote a transfer counter, a status register, an interrupt register, and a sequence step counter, respectively, and the CPU 1806 can know the SCSI protocol execution status by reading these register groups.

  Reference numerals 819 and 820 denote FIFOs having a function of temporarily storing data transferred from the CPU 1806 or the buffer 1813 to the SCSI bus or from the SCSI bus or buffer 1813 to the CPU 1806. Reference numeral 821 denotes a parity detector and a parity generator for data transferred from the CPU 1806 and buffer 1813 to the SCSI bus or from the SCSI bus to the CPU 1806 and buffer 1813. A sequencer 823 can control the SCSI protocol according to the settings of the registers 803 to 811 and the value of the SCSI bus control signal given from the receiver 814. The result is output to the status register 816 and the interrupt register 817.

  Reference numeral 825 denotes an ID recognition unit as a main part in the present embodiment, which corresponds to the ID recognition unit 603 as the activation start detection unit shown in FIG. The ID recognizing unit 825 monitors the values of the SCSI bus control signals BSY / and SEL /, and when BSY / is at a high level and SEL / is at a low level, the OWNID that is the ID of the present embodiment and the SCSI data bus SDBO. Compared with the value of / ˜SDB7 /, if they match, a sleep cancel signal 833 is output.

  Reference numeral 826 denotes a sleep control circuit. The sleep control circuit 826 asserts the sleep control signal 828, the sleep control signal 829, and the sleep signal 827 by the sleep setting signal 830 given from the sequencer 823, and the sleep control signal 833 by the sleep release signal 833 given from the ID recognition unit 825. 828, 829 and sleep signal 827 are negated. The clock 834 is obtained by ANDing the sleep control signals 828 and 829 and is a clock signal used as a clock for the function block 842 and the function block 843, respectively.

  Reference numeral 835 denotes a current control circuit as power consumption control means, which includes a switch 836 and a power supply Vcc that are controlled by a sleep signal 837 or the like given from the CPU 1806. The current control circuit 835 includes a power supply Vcc2 that supplies a current to a functional block 841 including an ID recognition unit 825, a sleep control circuit 826, a receiver 812, and a receiver 814, and a power supply Vcc1 that supplies a current to the functional blocks 842 and 843. Are supplied independently. That is, the current control circuit 835 controls the switch 836 so that Vcc1 is turned off by the sleep signal 837 given from the CPU 1806 and Vcc1 is turned on by the sleep release signal 833 given from the ID recognition unit 825.

  Next, a detailed configuration of the receiver 812 and the receiver 814 will be described with reference to FIGS.

  As shown in FIG. SDBO / ˜SDB7 / 1101, 1106, 1110, 1114, 1118, 1122, 1126, 1130 and receiver with hysteresis 1102, 1107, 1111, 1115, 1119, 1123, 1127, 1131, 1135, respectively, From the three-stage synchronization circuits 1104, 1108, 1112, 1116, 1120, 1124, 1128, 1132, and 1136 that synchronize these output signals with a clock 1103 (a clock equivalent to the clock 834 in FIG. 8). Composed. Three-stage periodic circuits 1104 to 1136 output SDBO to SDBP internal signals 1105 to 1137, respectively.

  On the other hand, the receiver 814 basically has SCSI control bus signals BSY / 1201, SEL / 1205, REQ / 1209, ACK / 1213, I / O / 1217, C / D / 1221, MSG as shown in FIG. / 1225, ATN / 1229, RST / 1233 (For the functions of these signals, refer to the above-mentioned SCSI protocol standards), receivers with hysteresis 1202, 1206, 1210, 1214, 1218, respectively. 1222, 1226, 1230, 1234, and three-stage periodic circuits 1203, 1207, 1211, 1215, 1219, 1223, 1227, 1231, 1235 for synchronizing the signals output by the clock 1103. The three-stage periodic circuits 1203 to 1235 are respectively a BSY internal signal 1204, a SEL internal signal 1208, a REQ internal signal 1212, an ACK internal signal 1216, an I / O internal signal 1220, a C / D internal signal 1224, an MSG internal signal 1228, and an ATN. The internal signal 1232 and the RST internal signal 1236 are output.

  In this embodiment, the receiver 814 receives the sleep signal 827 from the sleep control circuit 826, as is apparent from FIG. In order to correspond to the sleep signal 827, the receiver 814 in the present embodiment has its REQ / 1209, ACK / 1213, I / O / 1217, C / D / 1221, MSG / 1225, ATN / 1229, RST / 1233. The receiver circuit portion for inputting is configured as shown in FIG. In FIG. 10, the receiver circuit portion corresponding to MSG / 1225 is shown, but the same applies to REQ / 1209, ACK / 1213, I / O / 1217, C / D1221, ATN / 1229, and RST / 1233. It becomes composition.

  Here, as described above, the sleep signal 827 is a signal for setting the receiver 814 to the sleep mode. When the sleep signal 827 is activated, the circuit shown in FIG. 10 has REQ / 1209, AGK / 1213, I / O / 1217, C / D / 1221, MSG / 1225, ATN / 1229, and RST / 1233. Regardless of the value, the REQ internal signal 1212 to the RST internal signal 1236 are kept in the inactive state. In the figure, reference numerals 1001, 1002, and 1003 denote an inverter circuit, a two-input NOR circuit, and a two-input OR circuit, respectively, and these operations will be described later.

  The receiver circuit portion corresponding to BSY 1201 and SEL / 1205 is the signal necessary for the ID recognition of the SCSI protocol as shown in FIGS. 18 and 19 to leave the configuration shown in FIG. This is because it is necessary to always operate, and since signals other than these are not signals necessary for SCSI protocol ID recognition, the configuration of FIG. 10 controlled by the sleep signal 827 is adopted.

  Next, an exemplary configuration of the ID recognition unit 825 in FIG. 8 will be described with reference to FIG. The ID recognition unit 825 receives the BSY internal signal 1204 and the SEL internal signal 1208 from the receiver 814, and receives the SDB 0 to SDB 7 internal signals 1105 to 1133 from the receiver 812. Then, a sleep cancel signal 833 is output. In the figure, reference numeral 901 denotes an OWNID register that holds the ID of the SCSI system of the present embodiment, reference numeral 902 denotes an inverter, reference numerals 903 to 912 denote two-input AND circuits, and reference numeral 913 denotes an eight-input OR circuit. Details of the operation of the ID recognition unit 825 will be described later.

  Next, the configuration of an example of the sleep control circuit 826 in FIG. 2 will be described with reference to FIG. As apparent from FIG. 8, the sleep control signal 833 from the ID recognition unit 825 and the sleep setting signal 830 from the sequencer 823 are input to the sleep control circuit 826. Then, a sleep control signal 828 for setting the functional block 843 of the SCSI bus control circuit 703 of this embodiment to the sleep state and a sleep control signal 829 for setting the functional block 842 to the sleep state are output signals.

  In FIG. 13, 1301 is a sleep release selection register, 1302 and 1303 are 2-input AND gates, 1304 and 1305 are set / reset type latch circuits for holding sleep control signals 828 and 829, and 1306 is a 2-input OR gate. is there.

  Now, the operation of the above-described second embodiment of the present invention will be described with reference to FIG.

  First, prior to the description of the main part of the present embodiment, a general SCSI sequence will be outlined with reference to FIG. 17, FIG. 18, and FIG. The SCSI system includes a host computer as an initiator that issues a command such as the main CPU 14 shown in FIG. 3, and a peripheral device as a target such as the file controller 17 shown in FIG.

  As shown in FIG. 17, the SCSI system is in a bus-free phase after reset by power-on. This bus free phase is a state in which the SCSI bus is not used by any SCSI system. As shown in FIG. 18, when the SCSI system is in the bus free phase, BSY / 1201, SEL / 1205, SDB0 / to SDB7 / 1101-1130, and SDBP / 1134 are held in a negated state, that is, at a high level. Next, the initiator starts an arbitration phase to acquire the bus right. That is, BSY / 1201 is asserted, and the OWNID that is the device number of the initiator is output to SDB0 / ˜SDB7 / 1101-1130 and SDBP1134. The initiator checks the ID on the SCSI bus in the arbitration phase, and acquires the bus right when the OWNID is the ID with the highest priority. When the initiator acquires the bus right, the initiator asserts SEL / 1205.

  Next, the initiator starts a selection phase to select a target for which a command is to be issued. That is, BSY / 1201 is negated and PARTNERID, which is the target device number, is output to SDB0 / ˜SDB7 / 1101-1130 and SDBP / 1134 in addition to OWNID. When the target detects that BSY / 1201 is negated and SEL / 1205 is asserted, the target compares the ID on the SCSI bus with the OWN ID of the target.

  If the ID on the SCSI bus matches the OWN ID of the target, the target asserts BSY / 1201 and responds to the initiator. When the initiator confirms that BSY / 1201 is asserted, the initiator negates SEL / 1205 and ends the selection phase. When the selection phase ends, the SCSI enters the information transfer phase. In the information transfer phase, commands, data, messages and status are exchanged between the connected initiator and target in the selection phase.

  When the exchange of all commands, data, messages, and status is completed, the target negates BSY / 1201 and enters the bus free phase. Even if all commands, data, messages, and status have not been exchanged, if the target takes time to process, the target must negate BSY / 1201 and enter the bus-free phase. I can do it. In this case, the target can start the arbitration phase when internal processing is completed, select an initiator in the reselection phase, and continue to send and receive commands, data, messages, and statuses. In addition, the initiator can simultaneously accept commands from a plurality of initiators by adding a queue tag message to the command transferred to the target.

  The conventional SCSI control LSIs 53C90A and 53C90B manufactured by NCR, for example, always monitor all the signals on the SCSI bus by the receiver when waiting for access, and check with the sequencer, so that BSY / is negated and SEL The operation of the selection phase is performed by detecting that / is in the asserted state, taking the ID on the SCSI bus into the FIFO, and comparing it with its own ID in the sequencer. For this reason, the entire SCSI bus control circuit including the sequencer and the internal circuit is always operating even in the command waiting state from the initiator, and the power consumption increases.

  Now, the operation of this embodiment will be described. The CPU 1806 (FIG. 7) completes the execution of the commands given from the SCSI bus 601 and outputs a sleep signal 837 to the power supply control circuit 835 when the command queue defined by the SCSI protocol becomes empty. The power supply control circuit 835 sets Vcc1 to the off state, and excludes the functional block 841 except for the ID recognition unit 825 of the SCSI bus control circuit 701, the sleep control circuit 826, the receiver 812, the receiver 814, and two two-input AND circuits. The power source driving all the circuits 842 and 843 is cut off, and the sleep mode is entered.

  Further, as shown in FIGS. 10 and 12, the receiver 814 of this embodiment is input with a sleep signal 827 except for the input circuit of BSY / 1201 and SEL / 1205, and the sleep signal 827 is high in the sleep state. At the level, the output of the 2-input NOR circuit 1002 (FIG. 10) is always fixed at a low level. Further, the output of the two-input OR circuit 1003 is always fixed at the high level. Therefore, even if the MSG / 1225 of the SCSI bus changes, the internal signal 1228 is fixed at the low level and does not change. In general, these circuits are made of CMOS and do not consume current when the signal does not change. Therefore, in the sleep mode, the receiver 814 does not consume current except for the input circuit of BSY / 1201 and SEL / 1207. become.

  Next, when the SCSI bus enters the arbitration phase and enters the selection phase, BSY / 1201 goes high and SEL / 1205 goes low. Since the ID recognition unit 825 has the configuration shown in FIG. 9, the output of the inverter 902 becomes high level, and the output of the 2-input AND gate 903 becomes high level. When the ID value held in the OWNID register 901 matches the values of SDB0 / to SDB7 / 1105 to 1133, the sleep release signal 833 becomes high level.

  For example, if OWNID is set to “3”, the SDB3 internal signal 1117 becomes high level when the SDB3 / 1114 is low level, and the output of the 2-input AND circuit 908 becomes high level. Therefore, the output of the 8-input OR circuit 913 is at a high level. Therefore, the output of the 2-input AND circuit 912 becomes high level, the sleep release signal becomes high level, and functions as an activation start signal. Therefore, the current control circuit 835 turns on Vcc1 and turns on the power to the functional blocks 843 and 842.

  On the other hand, since the sleep control circuit 826 has the configuration shown in FIG. 13, when the sleep release signal 833 becomes high level, the sleep state latch 1304 and the sleep state latch 1305 are reset according to the value of the sleep release selection register 1301. Control signals 828 and 829 are negated. The sleep control signal 828 sets only the sequencer 823, the parity generator / detector 821, and the FIFO 819 to the sleep state. The sleep control signal 829 sets the circuits in the SCSI bus control circuit 701 other than the circuit controlled by the sleep control signal 828 to the sleep mode. For example, when the value of the sleep cancel selection register 1301 is “10” and the sleep cancel signal 833 becomes high level, the output of the 2-input AND circuit 1302 becomes high level, and the output of the 2-input AND circuit 1303 becomes low level. Become.

  Thus, sleep state latch 1304 is reset and sleep state latch 1305 remains set. Therefore, the sleep control signal 828 is at a low level and the sleep control signal 829 is at a high level. Therefore, only the sequencer 823, the parity detector / generator 821, and the FIFO 819 are released from the sleep state. The sequencer 823 confirms that no parity error has occurred in the parity detector / generator 821, confirms that no ID error has occurred, and then returns the other circuits from the sleep mode. If a parity error or an ID error has occurred, the sequencer 823, the parity detector / generator 821, and the FIFO 819 again enter the sleep mode. This is the reason why the functional blocks 842 and 843 are controlled by the separate sleep control signals 829 and 828 in this embodiment.

  The CPU 1806 waits for an interrupt signal from the SCSI bus control circuit 701 for a certain period of time. If no interrupt signal is received, the CPU 1806 outputs the sleep signal 837 to the power supply control circuit 835 again, and the function block 841 of the SCSI bus control circuit 701 is displayed. Turn off the power supply that drives all circuits except the above.

  According to the first embodiment of the present invention described in detail above, the current consumption in the command waiting state can be minimized without impairing the responsiveness.

  Next, a third embodiment of the present invention will be described with reference to FIGS.

  Generally, since each SCSI bus uses a 48 mA sink open collector or open drain driver, as shown in FIG. 14, the signal lines of each SCSI bus may be a system with a scale where reflection is not a problem. , 220Ω and 330Ω termination resistors are required, and a current of 5V / 550Ω × 18 = 164 mA always flows through the termination resistors.

  Therefore, in the present embodiment, as shown in FIG. 15, the SCSI bus control circuit 1500, the SCSI bus 601, 220Ω × 18 resistors 1502, 330Ω × 18 resistors 1503, 440Ω × 18 resistors 1504, 660Ω. It is composed of x18 resistors 1506 and switches 1501 and 1505.

  The configuration of the SCSI bus control circuit 1500 in this embodiment is as shown in FIG. In the figure, an external CPU data bus 801 is a data bus for accessing a SCSI bus control circuit 1500 from a CPU 1806 (FIG. 7). In the figure, blocks denoted by the same reference numerals as those in FIG. 8 have the same functions as those in FIG. 8 and will not be described in detail here. Reference numeral 1601 denotes a sequencer for controlling the SCSI bus control circuit 1500 of this embodiment, and 1602 and 1603 are selectors. Reference numerals 1604 and 1606 denote SCSI data bus single-ended 48 mA sink drivers, which correspond to the drivers 813 and 824 in the previous embodiment. Reference numerals 1605 and 1607 denote SCSI data bus single-ended 24 mA sink drivers. The functions of the selectors 1602 and 1603 have a function of switching between 48 mA sink drivers 1604 and 1606 and 24 mA sink drivers 1605 and 1607 as will be described later. A selector switching register 1608 holds selector switching information written by the CPU 1806.

  Although the schematic configuration of the hard disk device shown in FIG. 7 is not particularly shown here, the power supply control device 835 is not necessary in this embodiment, and a bit switch that provides selector switching information to the CPU 1806 is provided to the CPU 1806. Functionally added as input means.

  Next, the operation of the present embodiment will be described. In this embodiment, based on the user's bit switch operation, the CPU 1806 generates a control signal for the SCSI bus control circuit 1500 to select either the 48 mA sink driver or the 24 mA sink driver by the selectors 1602 and 1603. That is, the CPU 1806 takes in the value of the bit switch and writes the value into the selector switching register 1608 using the internal CPU data bus 801. The selector switching register 1608 sends a selector switching signal 1609 to each of the selectors 1602 and 1603 according to this value.

  For example, when connecting to a relatively large system in which the SCSI system shown in FIG. 16 is connected to 8 units, the external CPU 1806 writes the value of the bit switch that has been switched by the user to support the 48 mA sink driver in the selector switching register 1608, The selector switching register 1608 controls the control signal 1609 according to the value, and the selectors 1602 and 1603 select the 48 mA sink drivers 1604 and 1606.

  Further, the user sets the switch 1501 in FIG. 15 to the connected state and the switch 1505 to the disconnected state. By connecting in this way, a SCSI bus driver according to the SCSI protocol can be configured, and a maximum of 6 meters can be connected. However, in the all terminal assert state, a current of 48 mA × 18 = 864 mA is consumed, and in the all terminal negated state, a current of 164 mA is consumed.

  Next, when incorporated in a relatively small system such as a notebook personal computer that does not care about reflection, a 48 mA sink driver is not necessary. Therefore, the external CPU 1806 uses a selector 1602, a selector 1602, based on a bit switch switched to support a 24 mA sink driver. Set 1603 to select the 24 mA sink driver. Further, the user sets the switch 1505 in FIG. 15 to the connected state and the switch 1501 to the disconnected state. By connecting in this way, a SCSI bus driver using a 24 mA sink driver can be configured. In the all-terminal asserted state, the current consumption is 24 mA × 18 = 432 mA, and in the all-terminal negated state, the current consumption is 82 mA. The current consumption can be reduced to about half that in the case of using the 48 mA sink driver.

  That is, the SCSI control LSI according to the present embodiment has both a SCSI bus driver with a small pull-in current and a 48 mA sink SCSI bus driver. Therefore, a normal SCSI system uses a 48 mA sink SCSI bus driver. In the case of a small-scale SCSI system that does not care about reflection, the current consumption at the time of assertion of each terminal can be reduced by using a SCSI bus driver having a small pull-in current. Furthermore, when using a SCSI bus driver with a small pull-in current, by using a termination resistor according to the pull-in current, compared to using a termination resistor of 220Ω and 330Ω by using a 48 mA sink SCSI bus driver, Since the resistance value of the termination resistor is large, in the case of a small-scale SCSI system that does not bother reflection, current consumption at the time of negating each terminal can be reduced.

  Furthermore, the SCSI system of the present embodiment can be switched between a SCSI bus driver with a small pull-in current and a SCSI bus driver with a 48 mA sink, and when using a SCSI bus driver with a small pull-in current, a termination resistor corresponding to the pull-in current is connected. When a 48 mA sink SCSI bus driver is used, the termination resistor of 220 Ω and 330 Ω is connected, so that the most suitable SCSI bus driver can be selected according to the size of the system, and the current consumption is minimized. Can be limited.

It is a circuit block diagram which shows one Embodiment of the peripheral control apparatus by this invention. FIG. 2 is a circuit configuration diagram illustrating an example of a power consumption control circuit 2 illustrated in FIG. 1. It is a block diagram which shows an example of the information processing apparatus in which the peripheral control apparatus and peripheral control LSI of this invention are used. FIG. 2 is a first timing chart for explaining the operation of the embodiment shown in FIG. 1. FIG. FIG. 4 is a second timing chart for explaining the operation of the embodiment shown in FIG. 1. It is a schematic block diagram for demonstrating the principle of 2nd Embodiment which applied this invention to the SCSI system. FIG. 7 is a schematic configuration diagram when the SCSI system according to the second embodiment of the present invention shown in FIG. 6 is applied to a hard disk device. FIG. 8 is a circuit block diagram illustrating an example of a SCSI bus control circuit 701 in FIG. 7. FIG. 9 is a circuit diagram showing an example of an ID recognition unit 825 in the SCSI bus control circuit shown in FIG. 8. FIG. 9 is a partial circuit diagram of an example of the receiver 814 shown in FIG. 8. FIG. 9 is a circuit diagram of an example of a receiver 812 shown in FIG. 8. FIG. 9 is a schematic circuit diagram of the whole receiver 814 shown in FIG. 8. FIG. 9 is a circuit diagram of an example of a sleep control circuit 826 shown in FIG. 8. It is a circuit diagram for demonstrating the termination resistance of the SCSI bus to which this invention is applied. It is a circuit diagram which shows an example of the SCSI bus in the 3rd Embodiment of this invention. It is a block diagram which shows an example of the SCSI bus control circuit in the 3rd Embodiment of this invention. It is a state transition diagram in the SCSI system to which the second and third embodiments of the present invention are applied. It is explanatory drawing for demonstrating the schematic sequence of the SCSI protocol in the SCSI system to which the 2nd, 3rd embodiment of this invention is applied. It is another explanatory drawing for demonstrating the schematic sequence of the SCSI protocol in the SCSI system to which the 2nd, 3rd embodiment of this invention is applied. It is the schematic which shows an example of the hard disk device using the conventional AT bus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 2 ... Power consumption control circuit, 3 ... Address latch, 4 ... Address decoder, 6 ... Latch, 7 ... Gate, 8-10 ... Register group, 11-13 ... I / O control circuit, 601 ... SCSI bus, 602 ... SCSI Controller, 603... ID recognition unit, 604... Functional block other than ID recognition unit, 605.

Claims (8)

A storage device comprising a storage medium and a controller that executes processing in response to external access,
The controller has a low power consumption mode for cutting off the power of some circuits in the controller,
The controller outputs read data to the outside after canceling the low power consumption mode in response to the access from the outside, and returns to the low power consumption mode after finishing outputting the read data. A storage device characterized. A storage device comprising a storage medium and a controller that receives a command from the outside and executes processing according to the command,
The controller has an activation mode for executing processing according to the command, and a low power consumption mode in which the controller consumes less power than the activation mode,
When the controller receives a select signal and the command from the outside during the low power consumption mode, the controller transitions from the low power consumption mode to the activation mode, and responds to the command in the activation mode. A storage device characterized by executing a process and transitioning from the activation mode to the low power consumption mode when the process according to the command is completed.   3. The storage device according to claim 2, wherein the controller reduces power consumption of the controller by stopping supply of a clock to a part of circuits in the controller in the low power consumption mode.   The storage device according to claim 2, wherein the controller reduces power consumption of the controller by cutting off power supplies of some circuits in the controller in the low power consumption mode.   5. The storage device according to claim 4, wherein power is supplied to the other circuit of the controller in the low power consumption mode as in the activation mode. Some circuits in the controller execute processing according to the command in the activation mode,
5. The storage device according to claim 4, wherein the other circuit in the controller supplies power to a part of the circuit in the controller in the activation mode. Some circuits in the controller send an end signal indicating the end of the process according to the command to the other circuit in the controller when the process according to the command is completed,
5. The storage device according to claim 4, wherein the other circuit in the controller cuts the power supply of a part of the circuit in the controller when the end signal is received from the part of the circuit in the controller. A part of the circuit of the controller includes a register for holding the command from another circuit in the controller, and an input / output control circuit,
The other circuit of the controller receives the select signal and the command, controls a transition between the low power consumption mode and the activation mode, and holds a first address held from the outside. 5. The storage device according to claim 3, further comprising: a holding circuit; and a second holding circuit that holds the external data.

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