JP4649926B2 - Data processing device - Google Patents

Description

  The present invention relates to a data processing apparatus, and in particular, can solve a problem caused by a power saving state of a CPU or DRAM even when a general-purpose I / O interface apparatus is used.

  In recent years, the demand for environmentally friendly products has increased, and the demand for reducing power consumption during standby has also increased in office automation equipment such as printers. FIG. 1 shows a configuration example of a conventional printer. As shown in FIG. 1, the printer 10 includes a transfer device 100 and a substrate circuit unit (also referred to as an electrical sub system) 200. The substrate circuit unit 200 includes, for example, a CPU 201, a cache memory 202, a bus bridge circuit 203, and a memory bus 204. DRAM 205, 206, PCI bus 207, video interface circuit 208, Ethernet (trademark) interface circuit 209, USB interface circuit 210, parallel interface circuit 211, and the like. The printer 10 is connected to a communication network (Ethernet ™) 30 via an Ethernet interface circuit 209, accepts a print job from a remote host device, and is connected to the communication network 30 or a stand-alone host device (personal computer). ) 40 via the USB interface circuit 210 or the parallel interface 211, and accepts a print job from the host device 40.

  In such a printer or the like, as a means for reducing power consumption, a method of using an energy saving function in which the CPU 201 and the DRAMs 205 and 206 are incorporated in a circuit element such as a sleep mode and a self-refresh mode is generally used (FIG. 2). ).

  On the other hand, when the CPU 201 is put into a deep power saving state (the state where the energy saving effect is the highest) such as a sleep mode, the operation of the data bus is not a condition for releasing the power saving. The data is discarded because the data is written without releasing the data, or the cache memory 202 does not perform the bus snoop, so the data in the cache memory 202 and the data in the DRAMs 205 and 206 are inconsistent. Will occur (FIG. 3).

  As a technique for avoiding this, an I / O ASIC (specific application IC) 220 that controls I / F with an external IO device has a means for generating an interrupt to the CPU when data is received. There is known a technique for solving the above problem by starting desired data transfer after returning (FIGS. 4 and 5). Specifically, when the I / O ASIC 220 receives data from the host device, the CPU 201 performs an SMI (System Management Interrupt) interrupt to return the CPU 201 from the sleep mode, and transfers the data to the bus 207 accordingly.

  By the way, since a general-purpose component does not have a function of generating an interrupt before starting data transfer when data is received from an external interface, it is necessary to design a customized component such as an ASIC. On the other hand, since a new interface appears in a short period of time as seen in the PC interface, there is a problem that customization parts need to be recreated in a short period of time and the investment amount increases. Therefore, when the investment amount is suppressed, there is a problem that it is unavoidable to use a general-purpose product and cannot enter a deep power saving state as pointed out earlier.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data processing technique capable of entering a deep power saving state even if a general-purpose product is used.

  In the basic configuration example of the present invention, in order to achieve the above-described object, a low-power consumption comparable to that when a customized part is used is realized using a general-purpose part while realizing a new function. Specifically, the DMA function signal line of the general-purpose component is used to detect the start timing of data transfer to restore power saving, and at the same time, after returning from the power saving state by controlling this signal line The problem is solved by starting the data transfer.

  That is, the data processing apparatus includes a CPU for processing input data, a memory for storing data, and an I / O interface circuit (also referred to as an I / O device) having a function of communicating data with the outside. The power saving function is provided in the CPU, memory, etc., and the power saving state at the location necessary for data transfer is canceled before data transfer between the I / O device and memory or between the I / O devices during power saving. .

  Release of power saving is typically performed by inputting a signal to the power saving release trigger detection means.

  The input signal to the power saving release trigger detection means is created from, for example, a data transfer request signal of the I / O device.

  When the I / O device issues a data transfer request during power saving, the data transfer request processing is performed after the power saving state is released.

  Further, the present invention will be described.

  According to one aspect of the present invention, in order to achieve the above object, a CPU that processes input data, a memory that stores data, and the like, and an I / O interface that has a function of performing data communication with the outside A data processing apparatus having a power saving function in the CPU or the memory: a data transfer request receiving means for receiving a data transfer request from the I / O interface circuit; and the CPU and the memory When receiving the data transfer request in the power saving state, there is provided an interrupt request transmitting means for sending an interrupt request for making a power saving release request to the CPU; and a power saving release notification receiving means for receiving a power saving release notification from the CPU. In response to the power saving cancellation notification, the I / O interface circuit is permitted to transfer data.

  Typically, both the CPU and the memory are provided with a power saving function, but the present invention is not limited to this. For example, only the CPU may have a power saving function. The memory broadly refers to a memory device including a memory controller, and even when the memory controller is provided with a power saving function, the memory is included in the memory with the power saving function referred to here. For example, the memory controller is arranged in a bus bridge or the like, but is not limited thereto.

  In this configuration, a general-purpose I / O interface circuit itself can be used, and data transfer can be performed after the power saving state is canceled.

  This configuration typically assumes an architecture that arbitrates bus requests using a bus arbitration circuit. In this specific architecture, the power saving cancellation notification receiving means sends a bus request to the bus arbitration circuit when receiving the power saving cancellation notification, and the bus arbitration circuit sends a bus permission notification for the bus request to the I / O interface. Configure to send to circuit.

  The I / O interface specific application IC includes an I / O interface specific application IC. The I / O interface specific application IC shifts to a power saving state in response to a power saving transition instruction from the CPU and receives a data transfer request. An interrupt request for making a power saving release request may be sent to receive a power saving release notification from the CPU, and data transfer may be started in response thereto.

  Further, a video interface circuit may be provided, and a printing unit may be connected to the video interface circuit.

  These and other aspects of the invention are set forth in the appended claims and will be described in detail below with reference to examples.

  According to the present invention, a low-power consumption comparable to that of using a customized part is realized while realizing a new function by using a general-purpose part.

  Examples of the present invention will be described below.

  FIG. 6 shows an embodiment in which the present invention is applied to a printer. In this figure, parts corresponding to those in FIG. The PCI bus arbiter 219 of FIG. 6 is not shown for convenience in FIG. 4, but actually exists in the configuration example of FIG. The PCI bus arbiter 219 is a bus arbitration circuit that provides a function for appropriately giving the right to use the PCI bus 207. In addition, the portion indicated as general-purpose I / O LSI 221 is a new IF LSI that cannot be provided by I / O ASIC 220, and when this is directly connected to the circuit shown in FIG. There is a problem that it can not be used (can only be put into shallow power saving mode). In order to solve this problem, a power saving circuit 222 shown in FIG. 6 is newly provided.

  The PCI bus arbiter 219 receives the signal / REQ from each PCI device, and provides the signal / GNT to only one device. The PCI device obtains the right to use the PCI bus 207 only when it receives the signal / GNT, and can use the PCI bus 207. The PCI bus arbiter 219 may be built in the bus bridge circuit 203 or may exist as an independent circuit outside.

  In the configuration of this embodiment, the signal / REQ of the general-purpose I / O LSI 221 is sent to the / REQ terminal of the power saving circuit 222. When the power saving circuit 222 receives the signal / REQ from the general-purpose I / O LSI 221, the signal / SMI is sent to the CPU 201, and the CPU 201 returns the signal / QACK to the power saving circuit 222 after canceling the power saving state. The power saving circuit 222 sends a signal / REQ to the PCI bus arbiter 219 instead of the general-purpose I / O LSI 221 only after receiving the signal / QACK from the CPU 201. When the bus access right is granted after arbitration, the signal / GRT is sent from the PCI bus arbiter 219. It is sent to the general purpose I / O LSI 221. As a result, the general-purpose I / O LSI 221 can use the PCI bus 207.

  Next, with reference to FIGS. 7 to 9 as well, the operation will be described focusing on the general-purpose I / O LSI 221. FIG.

  7 illustrates the transition to the power saving mode, FIG. 8 illustrates the correlation between the system state and the signal, FIG. 9 illustrates the state transition diagram of the power saving correspondence circuit 222, and FIG. 10 illustrates the state transition. The truth table of the output signal of power saving correspondence circuit 222 is shown.

  First, when the entire system shifts to the power saving mode, as shown in FIG. 7, the power saving corresponding circuit 222 is instructed to shift to the Power-Save mode via the general-purpose bus 223 of the I / O ASIC 220 (S10). ). Specifically, a setting is made in a register provided in the power saving circuit 222. Before and after this, the transition setting to the power saving mode is performed for each device including the I / O ASIC 220 (S11). When these power saving mode preparations are completed, the CPU 201 is finally transferred to the power saving mode (S12). When the setting is performed according to this flow, the / QACK output of the CPU 201 transitions from the H level to the L level as shown in FIG. 6, and the power saving corresponding circuit 222 may detect that the CPU 201 has shifted to the power saving mode due to this transition. It becomes possible.

  When the general-purpose I / O LSI 221 receives data during power saving, the / REQ signal for requesting permission to use the PCI bus 207 is asserted (outputs L level) in order to transfer the data to the DRAMs 205 and 206. The power saving support circuit 222 detects that the / REQI input has become L level, and asserts the / SMI signal to the CPU 201 to perform an interrupt operation for restoring power saving. When the CPU 201 returns from the power saving mode, the / QACK output of the CPU 201 is negated (H level output), so that the power saving corresponding circuit 222 can know that the CPU 201 has returned from the power saving mode. The power saving circuit 222 detects that the signal / QACK is negated, and asserts the / REQO output to the PCI bus arbiter 219. As a result of the bus arbitration, a bus use right is given to the general-purpose I / O LSI 221 and data transfer is started. By performing the above operation, even if the system is shifted to the deep power saving mode while using the general-purpose IO LSI 221, normal PCI data transfer is started after the system returns from the power saving mode. The problem that has been done will not occur.

  In order to perform this operation, the bus parking during the transition to the power saving mode must be other than the general-purpose I / O LSI (if the general-purpose I / O LSI is a parking device, the PCI bus has already been (According to the PCI specification, it is advisable to transfer data without outputting a signal / REQ because it has been acquired, in order to avoid the problem of causing problems as a result).

  In this embodiment, it is assumed that the existing ASIC is mixed with the existing ASIC, and the existing ASIC has a mechanism in which the SMI is first issued when the PCI bus is required during power saving. The output is input so that there is no conflict with the internal state.

  Next, the correlation between the state of the system and the signal line will be described with reference to FIG. When the system is in the normal state, when the general-purpose IO I / F receives data, the / REQ output is asserted to acquire the PCI bus. This signal enters the / REQI input of the power saving circuit, but when the power saving circuit is in a normal state, the value is output as it is to the / REQO output. The / REQO output of the power saving circuit is added to the / REQ input of the PCI bus arbiter, and prioritization is performed according to an arbitration algorithm (for example, round robin) set in the arbiter, and signals are sent to the general-purpose IO I / F with appropriate priorities. Assert / GNT and pass the right to use PCI. When the system enters the power saving state, SW processing is performed in accordance with the flowchart for shifting to the power saving mode shown in FIG. By this processing, the CPU finally enters the power saving state. This state is detected by the power saving circuit because the / QACK output signal is asserted. When the general-purpose IO I / F receives data during power saving, the / REQ output is asserted to acquire the right to use the PCI bus, and the / REQI input of the power saving circuit becomes L level. When the / REQI input is asserted in the Power Save state, the power saving circuit first asserts the / SMI output and generates a power saving return interrupt to the CPU. When the CPU that has received the power saving return interrupt returns from the power saving state and the / QACK output shifts to the H level, the power saving circuit can detect the return from the power saving state. The power saving circuit asserts the / REQO output, issues a PCI bus use permission request for the general-purpose IO I / F to the PCI bus arbiter, and gives the right to use the bus to the general-purpose IO I / F. By performing the above operation, it is possible to transfer data safely even in the deep power saving state while using the general-purpose IO I / F.

  FIG. 9 shows a state transition diagram of the power saving circuit used in this embodiment, and FIG. 10 shows a truth table of output signals of the power saving circuit with respect to the state transition.

  In this embodiment, the case where only one general-purpose IO I / F is connected has been described. However, even in a system in which a plurality of general-purpose IO I / Fs are connected, it can be handled by a simple circuit configuration change. Is possible.

  In the present embodiment, a method of preventing data transfer during power saving by controlling the / REQ input to the PCI bus arbiter is used, but a method of controlling the / GNT output can also be used. However, when the signal / GNT is controlled, the output of the / GNT is masked by the power saving circuit, so that the PCI bus parking is not performed. As a result, there is a concern that the input signal level becomes unstable and causes latch-up. In order to avoid this concern, for example, while masking the signal / GNT, a signal parking / parking is performed by giving a signal / GNT to a device other than the general-purpose IO I / F (Bridge, etc.), or a PCI bus is appropriately pulled In addition to the Up or Pull-Down processing method, a method using a Buffer having a bus hold function can be used.

  In this embodiment, the PCI bus arbiter is described as one functional block. However, this arbiter may be incorporated in, for example, Bridge or the like. Further, although the power saving circuit has a circuit configuration different from that of the PCI bus arbiter, it is possible to add a function to the PCI bus arbiter and to implement a bus arbitration function and a power saving function in the same circuit.

  In the above embodiment, the printer is taken as an example, but any data processing system adopting a CPU and DRAM having a power saving function may be used.

It is a figure explaining the structure of the conventional data processing apparatus (printer). It is a figure explaining the state in power saving of the data processor of FIG. It is a figure explaining the malfunction which generate | occur | produces when the data processor of FIG. 1 is in power saving. It is a figure explaining the structural example which eliminated the malfunction of the conventional data processing apparatus by specific application IC. It is a figure explaining operation | movement of the structural example of FIG. It is a figure explaining the structure of the Example of this invention. It is a figure explaining the transfer to the power saving mode in an Example. It is a time chart which shows the correlation of the state of the system and signal in an Example. It is a state transition diagram of the power saving circuit of the embodiment. It is a figure explaining the output truth value table of the power-saving corresponding | compatible circuit of an Example.

Explanation of symbols

10 Printer 30 Communication Network 40 Host Device 100 Transfer Device 200 Substrate Circuit Unit 201 CPU
202 Cache memory 203 Bus bridge circuit 204 Memory bus 205, 206 DRAM
207 PCI bus 208 Video interface circuit 209 Ethernet interface circuit 209 Interface circuit 210 USB interface circuit 211 Parallel interface 211 Parallel interface circuit 219 PCI bus arbiter 220 I / O ASIC
221 General-purpose I / O LSI
222 Power saving circuit 223 General purpose bus

Claims (2)

A CPU that processes input data, a memory that stores data, an I / O interface circuit that has a function of performing data communication with the outside, and the CPU, the memory, and the I / O interface circuit In a data processing apparatus including a bus arbitration circuit that arbitrates a bus request for transmitting and receiving data via a PCI bus, and having a power saving function in the CPU or the memory,
When a bus request for the PCI bus is received from the I / O interface circuit and the bus request is received when the CPU or the memory is in a power saving state, an interrupt request for performing a power saving release request is sent to the CPU, A power saving circuit that receives a power saving cancellation notification from the CPU and supplies a bus request for the PCI bus to the bus arbitration circuit with respect to the I / O interface circuit based on the power saving cancellation notification;
The data processing apparatus, wherein the bus arbitration circuit sends a bus permission notice to the I / O interface circuit based on a bus arbitration result. The data processing apparatus according to claim 1, further comprising a video interface circuit, wherein the printing unit is connected to the video interface circuit.

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