JP5105690B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a thin film transistor (hereinafter referred to as TFT) and a capacitor (capacitor), and a manufacturing method thereof. The present invention also relates to a display device including a semiconductor device including a TFT and a capacitor, in particular, an electronic device in which a liquid crystal display device, an EL display device, and a projector are mounted as components, and a manufacturing method thereof. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and a display device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a semiconductor device having an integrated circuit formed by using a thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface and having an integrated circuit has been developed. A typical example is an active matrix liquid crystal display device. In particular, a TFT using a crystalline silicon film as an active region has high field effect mobility, and thus various functional circuits can be formed.
[0003]
For example, in an active matrix liquid crystal display device, a pixel circuit that displays an image for each functional block, a pixel circuit such as a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, or a sampling circuit is controlled. The driver circuit can be formed over one substrate, and the circuit can be formed using TFTs.
[0004]
In addition, semiconductor devices typified by active matrix liquid crystal display devices are increasingly used, and as a result, convenience is required, and miniaturization, high brightness, high definition, and low cost are required. Developments to continue are being continued.
[0005]
For example, a pixel portion of an active matrix liquid crystal display device used for a display portion of a liquid crystal projector or an electronic device is composed of millions of pixels, and each pixel is provided with a TFT. A counter electrode is provided on the counter substrate side with the liquid crystal interposed therebetween, and a kind of capacitor using the liquid crystal as a dielectric is formed. Next, the charge stored in this capacitor is controlled by the switching function of the TFT. Thus, the liquid crystal is driven by controlling the potential applied to each pixel, and the image is displayed by controlling the amount of light transmitted or reflected.
[0006]
In particular, in a small-sized and high-definition transmissive liquid crystal display device used for a liquid crystal projector, it is fully expected that the pixel size will continue to be reduced as long as high-definition is required simultaneously with downsizing. For example, in order to realize a high-definition display of XGA (1024 × 768 pixels) in a 0.7 inch diagonal liquid crystal display device, each pixel has an extremely small area of 14 μm × 14 μm. ing.
[0007]
In a transmissive liquid crystal display device, when a capacitor is formed in a pixel portion using a capacitor wiring to secure a sufficient capacitance, the aperture ratio must be sacrificed. Currently, we have addressed these problems by increasing the aperture ratio for higher brightness, and increasing the number of pixels for higher definition. It is an extremely difficult problem to design a pixel structure that can simultaneously satisfy the improvement in the rate and the increase in the number of pixels and can secure a sufficient capacity.
[0008]
As a solution to the above problem, in order to increase the aperture ratio, the area of the TFT that becomes a dead space and the area of the capacitor element are reduced, the width of the gate electrode and the source wiring is reduced, and the bonding margin between the TFT substrate and the counter substrate is reduced. Improvements such as reduction have been made. In particular, using a stack capacitor to reduce the area of the capacitive element is an effective solution. (Patent Document 1)
[0009]
A stack capacitor is a capacitor element having a structure in which three or more capacitor electrodes are stacked via two or more dielectric layers. In this specification, only the case where the capacitor electrode has three layers will be described; however, the structure is not limited thereto, and a plurality of capacitor electrodes may be provided. In this specification, the first capacitor electrode is formed at the same time as the TFT semiconductor layer, the second capacitor electrode is formed at the same time as the gate electrode, and the dielectric layer that separates the two is the gate insulating film. Although described, it is not necessarily limited to this configuration.
[0010]
FIG. 2 shows a conventional method for manufacturing a stacked capacitor. The semiconductor film formed on the substrate is selectively etched using a known technique relating to patterning and etching to form the TFT semiconductor film 14 and the first capacitor electrode 15 of the stack capacitor, and then the first An insulating film 13 serving as a dielectric is formed. Next, the gate electrode 32 and the second capacitor electrode 33 are formed. The second capacitor electrode 33 is a capacitor wiring whose potential is fixed to the ground potential or the like. Thereafter, a second insulating film 34 serving as a second dielectric is formed. (FIG. 2 (A)).
[0011]
After part of the first insulating film and the second insulating film is etched to form the contact hole 40, the second conductive film 35 to be a source electrode, a drain electrode and a third capacitor electrode which are connection wirings is formed. It is formed so as to be connected to the semiconductor film 14 of the TFT. (FIG. 2 (C)).
[0012]
Subsequently, after the second conductive film is etched to form the source electrode, the drain electrode 41, and the third capacitor electrode 42, the source electrode, the drain electrode, the second insulating film, and the third capacitor electrode are covered. A third insulating film 36 is formed. (FIG. 2 (D)). Thereafter, a part of the third insulating film is etched to form contact holes reaching the source electrode and the drain electrode, and then a third conductive film is formed and selectively etched to form the connection wiring 38. To do. (FIG. 2 (E)). Although not shown in FIG. 1, the first capacitor electrode 15 and the third capacitor electrode 42 are electrically connected and connected to other wirings or TFTs so that a predetermined voltage is applied.
[0013]
In the capacitor element, it is possible to hold more capacitive charges by reducing the thickness of the dielectric.
[0014]
However, when the thickness of the dielectric is reduced, when a subsequent conductive film is formed by the sputtering method, the dielectric is easily damaged due to the impact of sputtering. Specifically, when the second capacitor electrode 33 and the third capacitor electrode 42 are formed, defects occur in the first dielectric 13 and the second dielectric 34 that are in contact with the electrodes, As a result, a short circuit may occur between the first capacitor electrode 15 and the second capacitor electrode 33, or between the second capacitor electrode 33 and the third capacitor electrode 42.
[0015]
In addition, when the second conductive film 35 is formed on the dielectric insulating film 34, the stress of the conductive film 35 causes a problem that the semiconductor film 14 of the TFT and the first capacitor electrode 15 are cracked and cracked. .
[0016]
As a countermeasure for this problem, it is possible to use a material that does not apply excessive stress to the lower structure when forming the second conductive film. However, in this case, the material of the second conductive film is limited. For example, the case where a semiconductor film in which phosphorus is introduced into an impurity element is used as the second conductive film 35 is described. The semiconductor film into which phosphorus is introduced and the semiconductor film forming the n-channel TFT can be electrically connected. However, a pn junction is formed in the semiconductor film forming the p-channel TFT, and conduction cannot be obtained. End up. For this reason, it is necessary to form conductive films made of different materials for the capacitor electrode of the n-channel TFT and the capacitor electrode of the p-channel TFT. This causes a problem that the number of processes increases.
[0017]
[Patent Document 1]
JP-A-5-243519 (2nd to 3rd pages, FIG. 1)
[0018]
[Problems to be solved by the invention]
In view of the above problems, the present invention relates to a semiconductor device including a TFT and a plurality of capacitor elements. A semiconductor device having a higher aperture ratio, higher luminance, and higher definition than conventional ones can be obtained with a high yield. It is an object to produce.
[0019]
[Means for Solving the Problems]
The present invention is a semiconductor device having a plurality of capacitor elements and thin film transistors vertically stacked on an insulating surface, and is characterized in that a buffer layer is provided between a dielectric of the capacitor element and a capacitor electrode.
[0020]
That is, a semiconductor device having a thin film transistor, a first capacitor element, and a second capacitor element formed over an insulating surface, wherein the first capacitor element and the second capacitor element are formed on the insulating surface. The first capacitor element has a first capacitor electrode and a second capacitor electrode that are formed via a first dielectric, and the second capacitor element includes: The thin film transistor includes an active region and a gate electrode formed of a semiconductor film, and a connection connected to the active region, the second capacitor electrode and the third capacitor electrode formed via a second dielectric. A first insulating film formed between the wiring and the gate electrode and the connection wiring; between the second dielectric and the third capacitor electrode; and the first insulating film and the A buffer layer is formed between the connecting wires And features.
[0021]
The buffer layer is a film that relieves stress generated when the third capacitor electrode and the connection wiring are formed. Typically, it is formed of a crystalline semiconductor film, an amorphous semiconductor film, or the like, and has a thickness of 10 to 100 nm.
[0022]
The buffer layer is not in contact with the active region of the thin film transistor. Note that the connection wiring is a source electrode and a drain electrode, and is connected to the active region of the thin film transistor.
[0023]
According to the present invention, a first capacitor element having a first capacitor electrode and a second capacitor electrode formed on an insulating surface, and a second capacitor electrode having a second capacitor electrode and a second capacitor electrode are provided. A method for manufacturing a semiconductor device including a capacitor and a thin film transistor, wherein a semiconductor film is formed over an insulating surface, and then the semiconductor film is etched to form an active region of the thin film transistor and the first capacitor electrode. A first insulating film and a first conductive film are sequentially formed on the active region and the first capacitor electrode, and the first conductive film is etched to form a gate electrode of the thin film transistor and the second capacitor; After forming the electrode, a third insulating film and a second conductive film are formed, and the second conductive film, the third insulating film, and the second insulating film are etched to activate the thin film transistor Expose part of the area Then, a third conductive film is formed to connect the third conductive film and the active region of the thin film transistor, and the second conductive film and the third conductive film are etched to form a connection wiring, and The third capacitor electrode is formed.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
A manufacturing process of a semiconductor device that can be manufactured according to the present invention will be described with reference to FIGS.
[0025]
A base insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a synthetic quartz glass substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Further, a plastic substrate that can withstand the processing temperature may be used. As the base insulating film 11, an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used. Although an example in which a single layer structure is used as the base insulating film 11 is shown here, a structure in which two or more insulating films are stacked may be used. Note that since the base insulating film suppresses diffusion of impurity elements from the substrate, the base insulating film is not necessarily formed when a quartz glass substrate or the like is used for the substrate.
[0026]
Next, a semiconductor film is formed over the base insulating film. A semiconductor film is formed with a thickness of 25 to 200 nm (preferably 30 to 100 nm) by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and then the semiconductor film is etched into a desired shape. A semiconductor film 15 to be an active region 14 of the TFT and a first capacitor electrode of the capacitor is formed. In FIG. 1, the semiconductor film of the active region of the TFT and the semiconductor film of the capacitor element are formed separately, but they may be connected without being separated. In FIG. 1A, the first capacitor element is formed as a conductive film by adding impurities to a semiconductor film; however, the present invention is not limited to this. That is, any film having conductivity may be used.
[0027]
In addition, when a semiconductor film formed by a known means has an amorphous structure, a known crystallization process (laser crystallization method, thermal crystallization method, or thermal crystallization using a catalyst such as nickel) Etc.) to form a crystalline semiconductor film, and then it is desirable to etch into a desired shape. Note that there is no limitation on the material of the semiconductor film, but the semiconductor film is preferably formed of silicon, a silicon germanium (SiGe) alloy, or the like.
[0028]
Next, a first insulating film 13 that covers the semiconductor films 14 and 15 is formed. The first insulating film functions as a gate insulating film. The first insulating film is formed by a known means (plasma CVD method, sputtering method, etc.) with a thickness of 40 to 150 nm and a single layer or a stacked structure of insulating films.
[0029]
Next, a first conductive film is formed, and the first conductive film is selectively etched using a known technique to form the gate electrode 32 and the second capacitor electrode 33. The second capacitor electrode is a capacitor wiring whose potential is fixed to the ground potential or the like. As a material of the first conductive film, an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing these elements as a main component is formed. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Although the first conductive film has a single-layer structure here, two or more layers may be stacked.
[0030]
Next, a second insulating film 34 is formed so as to cover the gate electrode 32 and the first capacitor electrode 33. The second insulating film 34 is formed by a known means (plasma CVD method, sputtering method, etc.) with a thickness of 40 to 150 nm and a single layer or a laminated structure of insulating films.
[0031]
Next, using the gate electrode 32 as a mask, an impurity element is selectively introduced into the semiconductor film 14 to form the impurity region 16. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is introduced. FIG. 1 shows an example in which p-type impurities are introduced. Subsequently, heat treatment is performed to activate the impurity element. (Fig. 1 (A))
[0032]
Next, the second conductive film 20 is formed over the second insulating film 34 (FIG. 1B). FIG. 1 illustrates the case where two conductive films are stacked. The buffer layer (the second conductive film 20 formed over the second insulating film 34 in FIG. 1B) is formed in order to relieve stress applied from the upper conductive film 21 formed later. To do. Therefore, the second conductive film is formed using a material that can relieve stress. For example, a crystalline silicon film to which phosphorus is added has conductivity, can be formed by an LPCVD method with good step coverage, and is more flexible than a metal element film, so that the upper conductive film 21 is the second insulating film. The stress applied to the film 34 can be relaxed. In FIG. 1, the crystalline silicon film to which phosphorus is added is used as the second conductive film; however, the present invention is not limited to this, and an amorphous silicon film can also be used. In addition, organic conductive materials (for example, polyphenylene vinylene derivatives, polyfluorene derivatives, polythiophene derivatives, polyphenylene derivatives and copolymers thereof, oligophenylene, oligothiophene, pentacene, tetracene, copper phthalocyanine, fluorine-substituted phthalocyanine, perylene derivatives, etc.) It can also be used. In FIG. 1, the impurity added regions (source region and drain region) of the TFT are p-type, but the second conductive film 20 is a crystalline silicon film to which phosphorus is added and is an n-type semiconductor. The second conductive film and the impurity doped region of the TFT cannot be directly connected. Therefore, the second conductive film is formed before opening a contact hole for directly connecting the second conductive film and the TFT semiconductor film.
[0033]
Next, an etching process for forming a contact hole reaching the semiconductor film 14 is performed. The etching process is performed under the following first to third etching conditions. Needless to say, in the case where the layers are stacked using the same material, etching can be performed under the same conditions, and in some cases, etching can be performed under the same conditions even when using different materials. In addition, it is desirable to perform any etching conditions by dry etching methods represented by RIE (Reactive ion etching) method, ECR (Electron Cyclotron Resonance) method, and the like. This is because dry etching is easier to perform anisotropic etching than wet etching.
[0034]
First, the second conductive film 20 is partially etched under the first etching conditions, and the second insulating film 34 is partially exposed. Next, the resist mask is left as it is, and the second insulating film 34 is etched under the second etching condition to partially expose the first insulating film 13. Further, the first insulating film 13 is etched under the third etching condition to expose a part of the semiconductor film 14. A contact hole reaching the semiconductor film 14 is formed by the processing as described above.
[0035]
Next, a third conductive film 21 is formed over the second conductive film 20. The third conductive film 21 is preferably a metal element film so that it can be connected to both the p-type impurity region and the n-type impurity region of the TFT. It is also desirable that the film be made of a material that does not easily react with the TFT semiconductor film. Typically, a metal element film containing an element such as Ta, W, Ti, Mo, Al, Cu, Cr, or Nd can be used. In this embodiment mode, a tungsten film is formed. (FIG. 1C).
[0036]
Next, after the second conductive film 20 and the third conductive film 30 are selectively etched to form the source and drain electrodes 22 and the third capacitor electrode 23 which are connection wirings of the TFT, The insulating film 24 is formed. Note that the etching for forming the source electrode, the drain electrode 22 and the third capacitor electrode is an isotropic etching because it is an etching before the step of the gate electrode is flattened. A crystalline silicon film to which tungsten and phosphorus are added is a material that enables isotropic etching. The source electrode and the drain electrode are preferably formed so as to cover part of the gate electrode. With this structure, stray light (light that is not blocked by the light-shielding film formed above the TFT) can be prevented from entering the semiconductor film of the TFT, and the off-current of the TFT can be suppressed. (FIG. 1 (D)). Although the second conductive film is provided as a buffer layer, it has conductivity, and thus functions as a capacitor electrode in the same manner as the third capacitor electrode 23.
[0037]
After the third insulating film 24 is formed, the third insulating film 24 is partially etched to expose the TFT source and drain electrodes 22 to form contact holes. Thereafter, a fourth conductive film 26 is formed. As a material for the fourth conductive film, aluminum (Al), titanium (Ti), tungsten (W), copper (Cu), or the like can be used. Alternatively, a laminated structure in which Al or Cu is formed on the TaN film and a Ti film is further formed may be employed.
[0038]
Although not shown, the semiconductor film 15 of the stack capacitor and the third capacitor electrode 23 are electrically connected to each other to be given a predetermined potential.
[0039]
Through the above process, the TFT and the stack capacitor can be formed at the same time. Note that the stack capacitor includes a first capacitor element and a second capacitor element, and the second capacitor element is stacked on the first capacitor element. That is, the first capacitor element includes a first capacitor electrode and a second capacitor electrode formed via a first dielectric, and the second capacitor element is formed via a second dielectric. The second capacitor electrode and the third capacitor electrode are formed. In this embodiment mode, since the first capacitor element and the second capacitor element are stacked, a sufficient capacitance charge can be secured while reducing the area of the capacitor element.
[0040]
In addition, since the second conductive film 20 is formed as a buffer layer between the second insulating film 34 and the third conductive film 21, the second impact is caused by the sputtering impact generated when the third conductive film 21 is formed. The insulating film 34 can be protected, and the second insulating film 34 can be thinned. As a result, sufficient capacitive charge can be maintained without increasing the surface area of the dielectric.
[0041]
In addition, by having the second conductive film, it is possible to relieve stress generated when the third conductive film 21 is formed. For this reason, it is possible to suppress the phenomenon of semiconductor film cracking due to stress, and an improvement in yield can be realized.
[0042]
Further, the second conductive film is not directly connected to the TFT semiconductor film. Therefore, an n-type semiconductor film and a p-type semiconductor film can be used for the second conductive film. That is, it is not necessary to match the polarity of the second conductive film in accordance with the n-channel TFT and the p-channel TFT, and the buffer layer can be formed with the minimum number of steps.
[0043]
When the present invention is applied to a projection-type liquid crystal display device such as a projector, the aperture ratio of pixels can be increased, and as a result, a display device capable of obtaining high-intensity and high-definition display is manufactured with high yield. Can do.
[0044]
The present invention having the above configuration will be described in more detail with reference to the following examples.
[0045]
【Example】
[Example 1]
In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. Note that in this specification, a substrate in which a driver circuit which is a CMOS circuit and a pixel portion including a pixel TFT and a capacitor are formed over the same substrate is referred to as an active matrix substrate for convenience.
[0046]
First, a first base film (not shown) having a thickness of 10 to 150 nm (preferably 50 to 100 nm) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 500. The base film may have a laminated structure of two or more layers or may not be formed. Next, a conductive film formed of a conductive material such as Ta, W, Cr, Mo, or Si that can withstand the processing temperature of this embodiment is formed, the conductive film is formed into a desired shape, and a lower light shielding film is formed. To do. The lower light shielding film also has a function as a gate wiring. In this embodiment, a crystalline silicon film having a film thickness of 85 nm is formed, and then tungsten silicide (WSi) having a film thickness of 170 nm is formed. _x (X = 2.0 to 2.8)) is formed, and unnecessary portions are etched to form lower light shielding films 501 and 502. In this embodiment, a two-layer film is used as the lower light-shielding film, but a single-layer film may be used.
[0047]
In this embodiment, a synthetic quartz glass substrate is used as the substrate 500. An insulating film is formed on the surface of a glass substrate such as barium borosilicate glass or alumino borosilicate glass represented by Corning # 7059 glass or # 1737 glass, a silicon substrate, a metal element substrate, or a stainless steel substrate. You may use what you did. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0048]
Next, a second base film having a thickness of 10 to 650 nm (preferably 50 to 600 nm) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film on the substrate 500 and the lower light shielding films 501 and 502. 503 is formed. Although a single layer structure is used as the second base film 503 in this embodiment, a structure in which two or more insulating films are stacked may be used. In this embodiment, a plasma CVD method is used as the second base film 503, and SiH is used. _Four And N ₂ A 100-nm-thick silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) is formed using O as a reaction gas.
[0049]
Next, a semiconductor film 504 is formed over the second base film 503. As the semiconductor film 504, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 200 nm (preferably 30 to 100 nm) by a known means (such as sputtering, LPCVD, or plasma CVD). There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy. (Fig. 3 (A))
[0050]
Next, the semiconductor film is crystallized by a known crystallization process (laser crystallization method, thermal crystallization method, thermal crystallization method using a catalyst such as nickel). In this example, a nickel acetate solution (weight-concentration concentration 5 ppm) is applied to the entire surface of the film by spin coating and exposed to a nitrogen atmosphere at a temperature of 600 ° C. for 12 hours. (Fig. 3 (B))
[0051]
When laser crystallization is also applied to the crystallization method of the amorphous semiconductor film, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YLF laser, YVO _Four Laser or YAlO _Three A laser or the like can be used. In the case of using these lasers, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 800 mJ / cm. ² (Typically 200-700mJ / cm ² ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 300 Hz, and the laser energy density is 300 to 1000 mJ / cm. ² (Typically 350-800mJ / cm ² ) Next, a laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser beam at this time is set to 50 to 98%. May be.
[0052]
Subsequently, gettering is performed in order to remove or reduce the metal element used to promote crystallization from the semiconductor film serving as the active region. For the gettering, a method disclosed in JP-A-10-270363 may be applied. In this embodiment, a silicon oxide film with a thickness of 70 nm is formed as a mask, and etching is performed to obtain silicon oxide films 508a to 508d having desired shapes. Next, Ar (argon) is selectively implanted into the semiconductor film to form impurity regions 510a to 510f, and heat treatment is performed to remove metal elements from the semiconductor films 511a to 511d to be active regions or to obtain semiconductor characteristics. It can be reduced to the extent that it does not affect. The metal elements removed from 511a to 511d are etched and removed together with 510a to 510f in a later step. Since the TFT having an active region manufactured in this manner has a low off-current value and good crystallinity, high field-effect mobility can be obtained, so that favorable current-voltage characteristics can be achieved. (Figure 3 (C))
[0053]
Next, the crystalline semiconductor film is etched to form 511a to 511d into semiconductor films having a desired shape. The details of this process are not shown. Note that after forming the semiconductor films 511a to 511d, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0054]
Next, a first gate insulating film 512 is formed to cover the semiconductor films 511a to 511d. (FIG. 4 (A)). As the first gate insulating film 512, an insulating film having a thickness of 20 to 150 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 35 nm is formed by plasma CVD. Note that the gate insulating film is not limited to the silicon oxynitride film, and other insulating films may be used.
[0055]
In the case where a silicon oxide film is used for the first gate insulating film 512, TEOS (Tetraethyl Orthosilicate) and O2 are formed by plasma CVD. ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0056]
Next, the gate insulating film is partially etched to expose the semiconductor film 511d that serves as one of the electrodes of the capacitor, and an impurity element is introduced into the semiconductor film 511d to form a first capacitor electrode. (FIG. 4B). At this time, since other regions are covered with the resist 513, no impurity element is introduced. In this embodiment, P (phosphorus) is used as the impurity element, the acceleration voltage is 10 keV, and the impurity atom dose is 5 × 10. ¹⁴ / cm ² As a doping process.
[0057]
Subsequently, a second gate insulating film 515 is formed. The second gate insulating film 515 is formed using an insulating film having a thickness of 20 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed with a thickness of 50 nm by plasma CVD. Note that the second gate insulating film is not limited to the silicon oxynitride film, and other insulating films may be used.
[0058]
In this embodiment, in order to make the insulating film functioning as a dielectric in the capacitor element thinner than the gate insulating film of the TFT, the gate insulating film is formed in two steps. good.
[0059]
Next, after forming a contact hole connected to the lower light-shielding film, a first conductive film 516a with a thickness of 20 to 100 nm and a second conductive film 516b with a thickness of 100 to 400 nm are stacked. (FIG. 4C). In this embodiment, a first conductive film 516a made of an n-type crystalline silicon film with a thickness of 150 nm and a tungsten silicide (WSi film with a thickness of 150 nm) are formed. _x ) A second conductive film 516b made of a film is stacked. The n-type crystalline silicon film is formed by a plasma CVD method. Also, tungsten silicide (WSi) _x ) Film is tungsten silicide (WSi) _x ) Using a sputtering method.
[0060]
In this embodiment, the first conductive film 516a is an n-type crystalline silicon film, and the second conductive film 516b is WSi. _x However, it is not particularly limited, and any of them may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. . Further, an AgPdCu alloy may be used.
[0061]
Next, an etching process for forming the gate electrode and the second capacitor electrode is performed. (FIG. 5A). In this embodiment, ICP (Inductively Coupled Plasma) etching is used as an etching condition, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ The gas flow ratio is 25:25:10 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Conductive films 517 to 521 are formed. In this step, other known etching methods such as RIE method and ECR method can be applied.
[0062]
Next, second doping treatment is performed to introduce an impurity element imparting n-type into the semiconductor film. The doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount of impurity atoms is 1 × 10. ¹³ ~ 5x10 ¹⁴ /cm ² And an acceleration voltage of 30 to 80 keV. In this embodiment, the dose amount of impurity atoms is 1.5 × 10 5. ¹³ /cm ² The acceleration voltage is 70 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive films 517 to 521 serve as a mask for the impurity element imparting n-type, and the low-concentration impurity regions 523 and 524 are formed in a self-aligning manner. The low concentration impurity regions 523 and 524 have 1 × 10 ¹⁸ ~ 1x10 ²⁰ /cm ^Three An impurity element imparting n-type in the concentration range is introduced. Here, a resist mask 522 is formed on the semiconductor film forming the p-channel TFT, and an impurity element imparting n-type conductivity is not introduced.
[0063]
Next, as shown in FIG. 5B, a third doping process is performed. The condition of the ion doping method is that the dose amount of impurity atoms is 1 × 10. ¹³ ~ 1x10 ¹⁵ /cm ² The acceleration voltage is set to 30 to 120 keV. At this time, a mask 525b is formed so as not to introduce an impurity element imparting n-type into the semiconductor film for forming the p-channel TFT, and a high concentration is selectively applied to the semiconductor film for forming the n-channel TFT. Masks 525a and 525c are formed to form impurity regions. In this embodiment, the dose amount of impurity atoms is 1 × 10. ¹⁵ / Cm ² The acceleration voltage was 40 keV. Thus, high concentration impurity regions 526 and 529 are formed.
[0064]
Next, after removing the resist mask, the resist masks 532a and 532b are newly patterned, and a fourth doping process is performed as shown in FIG. 5C. By this fourth doping treatment, an impurity region 533 into which an impurity element imparting p-type conductivity is introduced is formed in the semiconductor film that becomes the active layer of the p-channel TFT. Using the second conductive film 518 as a mask for the impurity element, an impurity element imparting p-type conductivity is introduced to form an impurity region in a self-aligning manner. In this embodiment, diborane (B ₂ H ₆ ) Is added to the semiconductor film to form an impurity region 533. Ion doping method conditions are as follows: impurity atom dose 1 × 10 ¹³ ~ 1x10 ¹⁴ /cm ² And an acceleration voltage of 30 to 120 keV. In the fourth doping process, the semiconductor film forming the n-channel TFT is covered with resist masks 532a and 532b.
[0065]
Next, as shown in FIG. 6A, a fifth doping process is performed. The condition of the ion doping method is that the dose amount of impurity atoms is 1 × 10. ¹³ ~ 1x10 ¹⁵ /cm ² The acceleration voltage is set to 20 to 120 keV. At this time, masks 534a and 534c are formed so as not to introduce an impurity element imparting p-type into the semiconductor layer for forming the n-channel TFT, and the semiconductor layer for forming the p-channel TFT is selectively formed. A mask 534b is formed to form a high concentration impurity region. In this embodiment, the dose amount of impurity atoms is 1 × 10. ¹⁵ / Cm ² And the acceleration voltage is 40 keV. Thus, a high concentration impurity region 535 and a low concentration impurity region 536 are formed.
[0066]
Through the above steps, a high concentration impurity region and a low concentration impurity region are formed in each semiconductor film.
[0067]
Next, as shown in FIG. 6B, the masks 534a to 534c made of resist are removed, and a first interlayer insulating film 538 is formed. The first interlayer insulating film 538 is formed of an insulating film having a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 538 is not limited to the silicon oxynitride film, and another insulating film such as a silicon nitride film may be used as a single layer or a stacked structure.
[0068]
Next, third heat treatment is performed to recover the crystallinity of the semiconductor film and to activate the impurity element introduced into each semiconductor film. Here, using an electric furnace, heat treatment is performed at 950 ° C. for 30 minutes in a nitrogen atmosphere with an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In addition to the heat treatment, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In this embodiment, since the synthetic quartz is used for the substrate, the third heat treatment can be performed at a high temperature. However, when glass or plastic having a low heat resistant temperature is used for the substrate, the third heat treatment is performed at a temperature lower than the heat resistant temperature of the substrate. It is necessary to heat-treat.
[0069]
Further, heat treatment may be performed before the first interlayer insulating film 538 is formed. However, when the first conductive film and the second conductive film material are vulnerable to heat, the first interlayer insulating film is used to protect the first conductive film, the second conductive film, and the like as in this embodiment. It is preferable to perform heat treatment after forming (an insulating film containing silicon as a main component, for example, a silicon nitride film).
[0070]
Next, hydrogenation can be performed by performing heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating dangling bonds in the semiconductor film with hydrogen contained in the first interlayer insulating film 538. Note that the semiconductor film can be hydrogenated regardless of the presence of the first interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen may be performed. good.
[0071]
Next, as illustrated in FIG. 6C, a third conductive film 600 is formed over the first interlayer insulating film 538. As a material of the third conductive film 600, a conductive film typified by a crystalline silicon film doped with an n-type impurity element such as phosphorus having a thickness of 10 to 100 nm is preferable. When the thickness of the third conductive film is less than 10 nm, the effect of relieving stress generated when a tungsten film, which is a third conductive film to be formed later, is formed is low. When the thickness of the third conductive film is 100 nm or more, it is difficult to uniformly control the width of each line when forming a source electrode, a drain electrode, and a second capacitor electrode which will be formed later. In this embodiment, as the third conductive film 600, an n-type crystalline silicon film with a thickness of 50 nm is formed by LPCVD.
[0072]
Next, as shown in FIG. 6C, contact holes reaching the respective high concentration impurity regions of the semiconductor film of the TFT are formed. In this embodiment, the etching condition is CF by etching gas by RIE etching. _Four And Cl ₂ And O ₂ Etching is performed by setting each gas flow rate ratio to 25:25:10 (sccm) and applying RF (13.56 MHz) power of 500 W to the electrode at a pressure of 106.4 Pa.
[0073]
Next, a tungsten film which is the fourth conductive film 607 is formed over the third conductive film 600 and the semiconductor film by a sputtering method. The thickness of the fourth conductive film 607 is preferably 50 to 150 nm. This is because if the film thickness of the fourth conductive film is less than 50 nm, the function as an etching stopper for a contact hole to be formed later is lost, and if the film thickness is 150 nm or more, the source electrode, the drain electrode, and This is because it is difficult to uniformly control the width of each line because isotropic etching is performed when the third capacitor electrode is formed. In this embodiment, a tungsten film with a thickness of 100 nm is formed. Note that the material of the fourth conductive film 607 is not limited to tungsten. For example, a wiring may be formed by forming an aluminum (Al) film or a copper (Cu) film on a tantalum nitride (TaN) film, and further etching a laminated film formed with a titanium (Ti) film.
[0074]
Next, as shown in FIG. 7A, the third conductive film and the fourth conductive film are selectively etched to form source and drain electrodes 608 to 613 which are connection wirings and a third capacitor electrode 614a. Form. First, as the first etching condition, the etching gas is changed to SF by the RIE etching method. ₆ The fourth conductive film 607 is partially etched by applying 300 W of RF (13.56 MHz) power to the electrode, using a gas flow ratio of 20:20 (sccm). Subsequently, as a second etching condition, the etching gas is changed to SF by the RIE etching method. ₆ And He are used, the gas flow rate ratio is 20:20 (sccm), and 300 W of RF (13.56 MHz) power is applied to the electrode to partially etch the third conductive film. Note that the etched third conductive film 614b is provided as a buffer layer; however, since it is conductive, it functions as a capacitor electrode together with the fourth conductive film.
[0075]
Next, as shown in FIG. 7B, a second interlayer insulating film 615 is formed. The second interlayer insulating film 615 is formed using an insulating film having a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon nitride film having a thickness of 120 nm is formed by plasma CVD.
[0076]
Next, a third interlayer insulating film 539 made of an inorganic insulating material or an organic insulating material is formed over the second interlayer insulating film 615. In this embodiment, a silicon nitride oxide film having a thickness of 0.45 μm is formed.
[0077]
Next, contact holes reaching the source and drain electrodes 608 to 613 are formed, and wirings 540 to 544 that are electrically connected to the source and drain electrodes 608 to 613 are formed.
[0078]
These wirings include a titanium (Ti) film with a thickness of 60 nm, a titanium nitride (TiN) film with a thickness of 40 nm, an alloy film (alloy film of Al and Si) with a thickness of 300, and tungsten (W) with a thickness of 100 nm. The laminated film is formed by etching.
[0079]
Next, as illustrated in FIG. 8A, a fourth interlayer insulating film 560 made of an inorganic insulating film material or an organic insulating material is formed over the third interlayer insulating film 539 and the wirings 540 to 544. In this embodiment, a silicon nitride oxide film having a thickness of 0.45 μm is formed.
[0080]
Next, a light-shielding film 561 or 562 is formed on the fourth interlayer insulating film 560 by etching a film having a high light-shielding property such as Al, Ti, W, Cr, or black resin into a desired shape. The light shielding films 561 and 562 are arranged in a mesh shape so as to shield light other than the pixel openings.
[0081]
Next, as illustrated in FIG. 8B, a fifth interlayer insulating film 563 is formed so as to cover the light shielding films 561 and 562. After that, a contact hole leading to the connection wiring 544 is formed, a conductive film is formed to a thickness of 100 nm, and etched into a desired shape to form pixel electrodes 564 and 565. In this embodiment, the pixel electrode is formed using a film made of ITO. A liquid crystal display device to be formed later using this substrate is a transmissive liquid crystal display device. On the other hand, when a film made of a highly reflective element such as silver or aluminum is used for the pixel electrode, a substrate for a reflective liquid crystal display device can be formed.
[0082]
As described above, the pixel portion 556 including the driver circuit 555 including the n-channel TFT 551 and the p-channel TFT 552, the pixel TFT 553, and the capacitor 554 can be formed over the same substrate. Thus, the active matrix substrate is completed.
[0083]
[Example 2]
In this embodiment, a process for manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 9 is used for the description.
[0084]
First, after obtaining an active matrix substrate in the state of FIG. 8B according to Embodiment 1, an alignment film 567 is formed on at least the pixel electrodes 564 and 565 on the active matrix substrate of FIG. I do. In this embodiment, before the alignment film 567 is formed, a columnar spacer for maintaining the substrate interval may be formed at a desired position by etching an organic resin film such as an acrylic resin film. In this embodiment, in order to form a reflective liquid crystal display device, the pixel electrode is formed of an aluminum film.
[0085]
Next, a counter substrate 569 is prepared. Next, a colored layer 570 and a planarization film 573 are formed over the counter substrate 569.
[0086]
Next, a counter electrode 576 made of a transparent conductive film is formed over the planarization film 573 in at least the pixel portion, an alignment film 577 is formed over the entire surface of the counter substrate, and a rubbing process is performed.
[0087]
Next, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are bonded to each other with a sealant 568. A filler is mixed in the sealing material 568, and the filler and the columnar spacer can be bonded together while keeping the distance between the two substrates uniform. Thereafter, a liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. In this way, the reflection type liquid crystal display device shown in FIG. 9 is completed. Next, if necessary, the active matrix substrate and the counter substrate are divided into desired shapes. Further, a polarizing plate (not shown) is attached only to the counter substrate 569. Next, an FPC is attached using a known technique (not shown).
[0088]
The liquid crystal display device manufactured as described above is formed by vertically stacking a plurality of capacitor elements, and can increase the aperture ratio while securing a sufficient capacity. For this reason, it is possible to realize high-luminance and high-definition display.
[0089]
In addition, since the buffer layer is formed between the conductive film to be the capacitor electrode and the dielectric, the stress generated when the conductive film to be the capacitor electrode is formed can be relieved. Therefore, it is possible to suppress the phenomenon of semiconductor film cracking due to stress, and it is also possible to manufacture a liquid crystal display device with improved yield and improved operating characteristics and reliability.
[0090]
That is, a liquid crystal display device capable of obtaining a high-luminance and high-definition display can be manufactured with high yield. In particular, when the liquid crystal display device of the present invention is used in a projection display device such as a projector, the luminance can be increased, and high-luminance and high-definition display is possible.
[0091]
Further, such a liquid crystal display device can be used as a display unit of various electronic devices.
[0092]
[Example 3]
In this example, an example in which a light-emitting device is manufactured using the present invention will be described. In this specification, the light emitting device is a general term for a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which an IC is mounted on the display panel. is there. Note that the light-emitting element includes a layer (hereinafter, referred to as an EL layer) containing a compound that can obtain luminescence (Electro Luminescence) generated by applying an electric field, an anode layer, and a cathode layer. Luminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state, and either or both of them. Includes luminescence.
[0093]
Note that in this specification, all layers formed between an anode and a cathode in a light-emitting element are defined as EL layers. Specifically, the EL layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, a light-emitting element has a structure in which an anode layer, a light-emitting layer, and a cathode layer are sequentially laminated. In addition to this structure, an anode layer, a hole injection layer, a light-emitting layer, a cathode layer, and an anode layer , A hole injection layer, a light emitting layer, an electron transport layer, and a cathode layer may be laminated in this order.
[0094]
FIG. 10 is a cross-sectional view of the light emitting device of this example. A driver circuit provided over the substrate 700 is formed using the driver circuit 555 in FIG. Therefore, the description of the structure may be referred to the description of the n-channel TFT 551 and the p-channel TFT 552 of Embodiment 1. In this embodiment, the TFT has a single gate structure, but it may have a double gate structure or a triple gate structure.
[0095]
The wirings 701 to 703 function as source wirings and drain wirings of the CMOS circuit. In addition, the wirings 704 and 705 function as wirings for electrically connecting the source wiring and the source region of the switching TFT to the drain wiring and the drain region of the switching TFT, respectively. In FIG. 10, a switching TFT 603 provided over a substrate is formed using the n-channel TFT 551 in FIG. Therefore, for the description of the structure, the description of the n-channel TFT 551 described in Embodiment 1 may be referred to.
[0096]
In this embodiment, the switching TFT 603 has a double gate structure in which two channel forming regions are formed. However, the switching TFT 603 has a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed. Also good.
[0097]
The capacitor 605 is formed using the capacitor 554 in FIG. Therefore, for the description of the structure, the description of the capacitor 554 of Embodiment 1 may be referred to.
[0098]
The current control TFT 604 is formed using the p-channel TFT 552 of FIG. Therefore, the description of the structure may be referred to the description of the p-channel TFT 552 in Embodiment 1. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.
[0099]
A wiring 706 is a source wiring (corresponding to a power supply line) of the current control TFT, and the wiring 707 electrically connects the pixel electrode 711 and the current control TFT 604 by overlapping the pixel electrode 711 of the current control TFT. Electrode.
[0100]
Note that the pixel electrode 711 is a pixel electrode (anode of a light emitting element) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Alternatively, a transparent conductive film into which gallium is introduced may be used. The pixel electrode 711 is formed on the flat interlayer insulating film 710 before forming the wiring. Since a light emitting layer formed later has a very thin film thickness, a light emission failure may occur due to a step. For this reason, it is desirable to planarize the interlayer insulating film before forming the pixel electrode.
[0101]
After the wirings 701 to 708 are formed, a bank 712 is formed as shown in FIG. The bank 712 may be formed by etching an inorganic insulating film or organic resin film having a thickness of 100 to 400 nm.
[0102]
Note that since the bank 712 is an insulating film, attention must be paid to electrostatic breakdown of elements during film formation. In this embodiment, carbon particles and metal element particles are introduced into the insulating film as the material of the bank 712 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ ~ 1x10 ¹² Ωm (preferably 1 × 10 ⁸ ~ 1x10 ^Ten The amount of carbon particles and metal element particles introduced may be adjusted so that Ωm).
[0103]
An EL layer 713 is formed over the pixel electrode 711. In this embodiment, an organic light emitting material is used. Although only one pixel is shown in FIG. 10, in this embodiment, EL layers corresponding to each color of R (red), G (green), and B (blue) are separately formed. In this embodiment, the EL layer is formed using a low molecular weight organic light emitting material by vapor deposition. Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a tris-8-quinolinolato aluminum complex (Alq) having a thickness of 70 nm is formed thereon as a light emitting layer. _Three ) A laminated structure provided with a film. Alq _Three The emission color can be controlled by introducing a fluorescent dye such as quinacridone, perylene or DCM1.
[0104]
However, the above example is an example of a light emitting material that can be used as an EL layer, and it is not necessary to limit to this. The light emitting layer may be formed using an organic material and an inorganic material. In addition, an EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the EL layer is shown, but a medium molecular weight organic light emitting material or a high molecular weight organic light emitting material may be used. Note that in this specification, an organic light-emitting material that does not have sublimation and has 20 or less molecules or a chain molecule length of 10 μm or less is referred to as a medium molecular organic light-emitting material. As an example of using a polymer organic light emitting material, a 20 nm polythiophene (PEDOT) film is provided by a spin coating method as a hole injection layer, and a paraphenylene vinylene (PPV) film of about 100 nm is provided thereon as a light emitting layer. Alternatively, a laminated structure may be used. If a PPV π-conjugated polymer is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. Known materials can be used for these organic light emitting materials and inorganic materials.
[0105]
Next, a cathode 714 made of a conductive film is provided over the EL layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (magnesium and silver alloy film) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film into which those elements are introduced may be used.
[0106]
When the cathode 714 is formed, the light emitting element 715 is completed. Note that the light-emitting element 715 here refers to a diode formed with a pixel electrode (anode) 711, an EL layer 713, and a cathode 714.
[0107]
It is effective to provide a passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a combination thereof. At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen and can suppress oxidation of the organic light emitting layer 713. Therefore, the problem that the EL layer 713 is oxidized during the subsequent sealing process can be prevented.
[0108]
Further, a sealing material 717 is provided over the passivation film 716 and a cover material 718 is attached thereto. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In this embodiment, the cover member 718 is formed by forming a carbon film (preferably a diamond-like carbon film) on both surfaces of a glass substrate, a synthetic quartz glass substrate, or a plastic substrate (including a plastic film).
[0109]
Thus, a light emitting device having a structure as shown in FIG. 10 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber type (or in-line type) film formation apparatus without releasing to the atmosphere. . Further, it is possible to continuously process the process up to the step of bonding the cover material 718 without releasing to the atmosphere.
[0110]
Thus, an n-channel TFT 601, a p-channel TFT 602, a switching TFT (n-channel TFT) 603, a current control TFT (p-channel TFT) 604 and a capacitor 605 are formed on the substrate.
[0111]
Further, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other logic circuits such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.
[0112]
Further, the light-emitting device of this example after performing the sealing (or sealing) process for protecting the light-emitting element will be described with reference to FIG. In addition, the code | symbol used in FIG. 10 is quoted as needed.
[0113]
11A is a top view illustrating a state where the light-emitting element is sealed, and FIG. 11B is a cross-sectional view taken along line CC ′ in FIG. 11A. In FIG. 11A, 801 indicated by a dotted line is a source side driver circuit, 806 is a pixel portion, and 807 is a gate side driver circuit. Reference numeral 901 denotes a cover material, reference numeral 902 denotes a first sealing material, reference numeral 903 denotes a second sealing material, and a sealing material 907 is provided on the inner side surrounded by the first sealing material 902.
[0114]
Reference numeral 904 denotes wiring for transmitting signals input to the source side driver circuit 801 and the gate side driver circuit 807, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 905 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only a light-emitting device body but also a state in which an FPC or a PWB is attached thereto.
[0115]
Next, a cross-sectional structure along CC ′ in FIG. 11A will be described with reference to FIG. A pixel portion 806 and a gate side driver circuit 807 are formed above the substrate 700, and the pixel portion 806 is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 711 electrically connected to the drain thereof. . The gate side driver circuit 807 is formed using a CMOS circuit (see Embodiment 1 and FIG. 10) in which an n-channel TFT 601 and a p-channel TFT 602 are combined.
[0116]
The pixel electrode 711 functions as an anode of the light emitting element. A bank 712 is formed at both ends of the pixel electrode 711, and an EL layer 713 and a cathode 714 of a light emitting element are formed on the pixel electrode 711.
[0117]
The cathode 714 also functions as a wiring common to all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate side driver circuit 807 are covered with a cathode 714 and a passivation film 716.
[0118]
Further, a cover material 901 is bonded to the first seal material 902. Note that a spacer made of a resin film may be provided in order to secure a space between the cover material 901 and the light emitting element. Next, a sealing material 907 is filled inside the first sealing material 902. Note that an epoxy-based resin is preferably used as the first sealing material 902 and the sealing material 907. The first sealing material 902 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a hygroscopic effect or a substance having an antioxidant effect may be contained in the sealing material 907.
[0119]
The sealing material 907 provided so as to cover the light emitting element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, or acrylic can be used as the material of the plastic substrate 901 constituting the cover material 901.
[0120]
In addition, after the cover material 901 is bonded using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second sealing material 903 can use the same material as the first sealing material 902.
[0121]
By encapsulating the light emitting element in the sealing material 907 with the above structure, the light emitting element can be completely blocked from the outside, and a substance that promotes deterioration due to oxidation of the organic light emitting layer such as moisture and oxygen from the outside can be obtained. Intrusion can be prevented. Therefore, a highly reliable light emitting device can be obtained.
[0122]
Wiring in the light-emitting device manufactured as described above is in sufficient contact with the semiconductor film, and the operating characteristics and reliability of the light-emitting device can be sufficient. In addition, when an active matrix substrate using the structure of the present invention is used for a light-emitting device, the light-emitting device can be manufactured with high yield. Next, such a light-emitting device can be used as a display portion of various electronic devices.
[0123]
Note that this embodiment can be freely combined with Embodiment 1.
[Example 4]
By applying the present invention, various display devices (active matrix liquid crystal display devices, active matrix light-emitting devices) can be manufactured. That is, the present invention can be applied to various electronic devices in which these display devices are incorporated in a display portion.
[0124]
Such electronic devices include video cameras, digital cameras, projectors, head-mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples thereof are shown in FIG. 12, FIG. 13 and FIG.
[0125]
FIG. 12A illustrates a personal computer, which includes a main body 3001, an image input portion 3002, a display portion 3003, a keyboard 3004, and the like. By applying the present invention, a personal computer with low power consumption capable of high-definition display with high yield can be manufactured.
[0126]
FIG. 12B illustrates a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, an image receiving portion 3106, and the like. By applying the present invention, a video camera capable of high-definition display with high yield can be manufactured.
[0127]
FIG. 12C illustrates a mobile computer, which includes a main body 3201, a camera unit 3202, an image receiving unit 3203, an operation switch 3204, a display unit 3205, and the like. By applying the present invention, a low-power consumption mobile computer (mobile computer) capable of high-definition display with high yield can be manufactured.
[0128]
FIG. 12D illustrates a goggle type display, which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. By applying the present invention, a goggle type display capable of high-definition display with high yield can be manufactured.
[0129]
FIG. 12E shows a player that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. By applying the present invention, a player capable of high-definition display with high yield can be manufactured.
[0130]
FIG. 12F illustrates a digital camera, which includes a main body 3501, a display portion 3502, an eyepiece portion 3503, an operation switch 3504, an image receiving portion (not shown), and the like. By applying the present invention, a low power consumption digital camera capable of high-definition display with high yield can be manufactured.
[0131]
FIG. 13A illustrates a front projector, which includes a projection device 3601, a screen 3602, and the like. By applying the present invention, a high-luminance front projector can be manufactured with high yield.
[0132]
FIG. 13B illustrates a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. By applying the present invention, a high-luminance rear projector can be manufactured with high yield.
[0133]
Note that FIG. 13C is a diagram illustrating an example of the structure of the projection devices 3601 and 3702 in FIGS. 13A and 13B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0134]
FIG. 13D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 13D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0135]
However, the projector shown in FIG. 13 shows a case where a transmissive liquid crystal display device is used, and an application example in a reflective liquid crystal display device is not shown.
[0136]
FIG. 14A shows a cellular phone, which includes a main body 3901, an audio output portion 3902, an audio input portion 3903, a display portion 3904, operation switches 3905, an antenna 3906, and the like. By applying the present invention, a mobile phone with low power consumption that can display with high yield and high definition can be manufactured.
[0137]
FIG. 14B illustrates a portable book (electronic book), which includes a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, an antenna 4006, and the like. By applying the present invention, a portable book with low power consumption and high-definition display with high yield can be manufactured.
[0138]
FIG. 14C illustrates a display, which includes a main body 4101, a support base 4102, a display portion 4103, and the like. A display to which the present invention is applied is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).
[0139]
As described above, the applicable range of the present invention is so wide that the present invention can be applied to electronic devices in various fields. Moreover, the electronic device of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-4.
[0140]
【Effect of the invention】
By adopting the configuration of the present invention, the following significance can be obtained.
[0141]
In a semiconductor device in which a TFT and a plurality of capacitive elements are stacked vertically with respect to a substrate, a conductive film that is a buffer layer that relieves stress of a conductive film that is formed later is formed over an insulating film that is a dielectric of the capacitive element. Then, contact holes are formed in part of the buffer layer and the insulating film. Thereafter, a conductive film is formed and etched to form a source electrode and a drain electrode. With this structure, it is possible to form a semiconductor device having a TFT and a plurality of capacitor elements while suppressing stress cracking of a semiconductor film or a capacitor wiring.
[0142]
In a semiconductor device in which a capacitive element is stacked vertically with respect to a TFT and a substrate, it is possible to protect the dielectric film from sputtering impact by forming the buffer layer on the dielectric film. Become. For this reason, it becomes possible to form a capacitive electrode by a sputtering method, and the selection method of the formation method and material for forming a capacitive electrode increases.
[0143]
By forming the source electrode and the drain electrode so as to cover a part on the gate electrode of the TFT, the electrode functions as a light-shielding film, so that stray light can be blocked and off-current of the TFT can be suppressed. .
[0144]
That is, according to the present invention, a semiconductor device capable of holding a high capacity can be manufactured with a high yield. In particular, when the semiconductor device is a display device, the aperture ratio can be increased, and thus a display device capable of realizing high-luminance and high-definition display while ensuring sufficient capacity is manufactured with high yield. can do.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of the concept of the present invention.
FIG. 2 is a diagram showing a conventional example.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT;
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 9 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 10 is a cross-sectional structure diagram of a driver circuit and a pixel portion of a light-emitting device.
FIG. 11A is a top view of a light-emitting device.
FIG. 5B is a cross-sectional structure diagram of a driver circuit and a pixel portion of a light emitting device.
FIG 12 illustrates an example of an electronic device.
FIG. 13 illustrates an example of an electronic device.
FIG 14 illustrates an example of an electronic device.

Claims (2)

A first capacitor element having a first capacitor electrode and a second capacitor electrode formed on an insulating surface; a second capacitor element having the second capacitor electrode and the third capacitor electrode; a thin film transistor; A method for manufacturing a semiconductor device having
After forming a semiconductor film on the insulating surface, the semiconductor film is etched to form an active region of the thin film transistor and the first capacitor electrode,
A first insulating film and a first conductive film are sequentially formed on the active region and the first capacitor electrode;
Etching the first conductive film to form the gate electrode of the thin film transistor and the second capacitor electrode;
A second insulating film and a second conductive film are sequentially formed on the gate electrode and the second capacitor electrode of the thin film transistor;
Etching the second conductive film, the second insulating film, and the first insulating film to expose a part of the active region;
Forming a metal film, connecting the metal film and the active region,
Etching the second conductive film and the metal film to form a connection wiring of the thin film transistor and the third capacitor electrode,
The second conductive film is a crystalline semiconductor film or an amorphous semiconductor film;
The method for manufacturing a semiconductor device, wherein the thickness of the second conductive film is 10 to 100 nm (excluding 100 nm). A first capacitor element having a first capacitor electrode and a second capacitor electrode formed on an insulating surface; a second capacitor element having the second capacitor electrode and the third capacitor electrode; a thin film transistor; A method for manufacturing a semiconductor device having
After forming a semiconductor film on the insulating surface, the semiconductor film is etched to form an active region of the thin film transistor and the first capacitor electrode,
Forming a first insulating film on the active region and the first capacitor electrode;
After partially etching the first insulating film with a resist so that the upper surface of the first capacitor electrode is exposed, an impurity element is introduced into the first capacitor electrode;
A second insulating film and a first conductive film are sequentially formed on the first insulating film and the first capacitor electrode with the upper surface exposed;
Etching the first conductive film to form the gate electrode of the thin film transistor and the second capacitor electrode;
Forming a third insulating film and a second conductive film in order on the gate electrode and the second capacitor electrode of the thin film transistor;
Etching the second conductive film, the third insulating film, the second insulating film, and the first insulating film to expose a part of the active region;
Forming a metal film, connecting the metal film and the active region,
Etching the second conductive film and the metal film to form a connection wiring of the thin film transistor and the third capacitor electrode,
The method for manufacturing a semiconductor device, wherein the second conductive film is a crystalline semiconductor film or an amorphous semiconductor film.

Images