JPH01235352A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH01235352A
JPH01235352A JP6384588A JP6384588A JPH01235352A JP H01235352 A JPH01235352 A JP H01235352A JP 6384588 A JP6384588 A JP 6384588A JP 6384588 A JP6384588 A JP 6384588A JP H01235352 A JPH01235352 A JP H01235352A
Authority
JP
Japan
Prior art keywords
film
etching
deposited
semiconductor device
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6384588A
Other languages
Japanese (ja)
Inventor
Noboru Sato
昇 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6384588A priority Critical patent/JPH01235352A/en
Publication of JPH01235352A publication Critical patent/JPH01235352A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To uniformly deposit a passivating film to be formed on a metal electrode film upper layer by a method wherein a conductive film is etched by an isotropic etching method in a first process and by an anisotropic etching method in a second process so that it can be etched continuously. CONSTITUTION:A silicon oxide film 2, a gate silicon oxide film 4 and a polysilicon film 3 are formed on a P-type silicon substrate 1. After that, an N-type conductive film 5 is formed by an ion implantation method; after that, a BPSG film 6 is deposited. In succession, a polysilicon film 14 is deposited on a substrate where a contact hole has been opened selectively; an Al film 8 is applied; a conductive film of a two-layer structure is formed. A resist mask 13 is patterned. After that, the Al film 8 is etched isotropically. Then, the Al film 8 and the conductive film composed of the polysilicon film are etched down to an end in the thickness direction by an anisotropic etching method. By this setup, a passivating film to be formed on a metal electrode film upper layer can be deposited uniformly; a crack or the like is not produced in the passivating film due to a temperature stress or the like when a semiconductor device is mold-packaged; the moistureproofness can be enhanced furthermore.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に金属膜をエ
ツチングして電極配線を形成する方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming electrode wiring by etching a metal film.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置の製造方法においては、第4
図に示す様に、アルミニウム膜8をスパッタ法等により
堆積した後、ホトレジストを用い、ドライエツチング法
でエツチングガスの圧力およびエツチングパワーを一定
にしてエツチングを行ない電極配線を形成していた。ま
な、他の従来例ではアルミニウム膜8のような金属膜を
ホトレジストを用い例えば、40〜60℃程度のリン酸
液等で湿式エツチングを行なって電極配線を形成してい
た。
Conventionally, in the manufacturing method of this type of semiconductor device, the fourth
As shown in the figure, after an aluminum film 8 is deposited by sputtering or the like, etching is performed using a photoresist using a dry etching method with constant etching gas pressure and etching power to form electrode wiring. In other conventional examples, electrode wiring was formed by wet etching a metal film such as the aluminum film 8 using photoresist, for example, with a phosphoric acid solution at about 40 to 60°C.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置の製造方法では、電極配線の
金属電極膜の側面が下地であるボロン添加のリンケイ酸
ガラス膜、つまりBPSG膜6に対し垂直又は、逆テー
パー状になる結果、金属電極膜の上層に常圧CVD法に
より低濃度PSG膜9およびプラズマ窒化膜10を堆積
する際、低濃度PSG膜9およびプラズマ窒化膜10の
段差被覆性が極度に悪化し、第4図に示す様に、プラズ
マ窒化膜10が金属電極膜くアルミニウム膜8)のコー
ナ一部で膜厚か極度に薄くなったり、あるいはプラズマ
窒化[10がアルミニウム膜8を完全に覆うことが不可
能になることがあり、結果として半導体装置をモールド
パッケージンクする際の温度ストレス等により、プラズ
マ窒化膜10の膜厚が薄い領域にプラズマ窒化膜クラッ
クおよび低PSG膜クラックが発生すると同時に、プラ
ズマ窒化膜10の開口部により半導体装置の耐湿性が極
度に低下し、製品の信頼性が損なわれるという大きな欠
点を有する。また、従来の半導体装置の製造方法では、
前述した様に金属電極膜(8)のエツチング面が下地の
BPSG膜6に対し垂直又は逆テーパーになる結果、電
極配線の2層構造を有する半導体装置では、下層電極配
線上の眉間絶縁膜の段差被覆性が極度に悪化するため、
上層電極配線と下層電極配線が交差する領域に於て、上
層電極配線の膜厚が極度に薄くなる場合、又は断線する
場合が発生するという大きな欠点を有する。
In the conventional semiconductor device manufacturing method described above, the side surface of the metal electrode film of the electrode wiring becomes perpendicular or inversely tapered to the underlying boron-doped phosphosilicate glass film, that is, the BPSG film 6, and as a result, the metal electrode film When the low concentration PSG film 9 and the plasma nitride film 10 are deposited on the upper layer by the atmospheric pressure CVD method, the step coverage of the low concentration PSG film 9 and the plasma nitride film 10 is extremely deteriorated, as shown in FIG. The thickness of the plasma nitride film 10 may become extremely thin at some corners of the metal electrode film or the aluminum film 8), or it may become impossible for the plasma nitride film 10 to completely cover the aluminum film 8). As a result, plasma nitride film cracks and low PSG film cracks occur in thin areas of the plasma nitride film 10 due to temperature stress during mold packaging of semiconductor devices. This has a major drawback in that the moisture resistance of the semiconductor device is extremely reduced and the reliability of the product is impaired. In addition, in conventional semiconductor device manufacturing methods,
As mentioned above, as a result of the etching surface of the metal electrode film (8) becoming perpendicular or inversely tapered with respect to the underlying BPSG film 6, in a semiconductor device having a two-layer electrode wiring structure, the glabellar insulating film on the lower electrode wiring is Because step coverage deteriorates extremely,
This method has a major drawback in that the film thickness of the upper layer electrode wire may become extremely thin or the wire may be disconnected in the region where the upper layer electrode wire and the lower layer electrode wire intersect.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、基板上に被着した導
電膜を選択的に除去して電極配線を形成するエツチング
工程を有する半導体装置の製造方法において、前記エツ
チング工程は前記導電膜をその初期膜厚の途中まで等方
性エツチング法で除去する第1工程と、続いて終りまで
異方性エツチング法で除去する第2工程とからなるとい
うものである。
The method of manufacturing a semiconductor device of the present invention includes an etching step of selectively removing a conductive film deposited on a substrate to form an electrode wiring, wherein the etching step removes the conductive film from the substrate. The method consists of a first step in which the initial film thickness is removed by isotropic etching up to the middle, and a second step in which the film is removed by anisotropic etching up to the end.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(f)は本発明の第1の実施利金説明す
るための工程順に配置した半導体チップの断面図である
FIGS. 1(a) to 1(f) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the first embodiment of the present invention.

まず、第1図(a)に示すように、P型シリコン基板1
上に、ホトリソグラフィ技術によりi■択的に酸化シリ
コン膜2を形成する。
First, as shown in FIG. 1(a), a P-type silicon substrate 1
A silicon oxide film 2 is selectively formed thereon by photolithography.

続いて、第1図(b)に示すように、ゲート酸化シリコ
ン膜4を熱酸化法により厚さ50nm形成し、さらにポ
リシリコン膜をCVD法により堆積し、リン拡散を施し
ポリシリコンの導電性を上げた後、ホトレジストを用い
て選択的にエツチングをしてポリシリコン膜3を形成す
る。
Subsequently, as shown in FIG. 1(b), a gate oxide silicon film 4 is formed to a thickness of 50 nm by thermal oxidation, a polysilicon film is further deposited by CVD, and phosphorus is diffused to increase the conductivity of the polysilicon. After increasing the temperature, a polysilicon film 3 is formed by selectively etching using photoresist.

その後、イオン注入法により、N型導電層5を形成した
後常圧CVD法により、BPSG膜6を厚さ11000
n程度堆積する。
Thereafter, an N-type conductive layer 5 was formed by ion implantation, and then a BPSG film 6 was formed to a thickness of 11,000 by atmospheric pressure CVD.
About n is deposited.

続いて、第1図(c)に示すように、BPSG膜6を9
00℃で熱処理し、BPSG膜6のリフローを施し、続
けてドライエツチング法によりコンタクトホールを選択
的に開口したものを基板としてその上にポリシリコン膜
14をCVD法により厚さ200nm程度堆積し、続け
て、スパッタ法によりアルミニウム膜8を厚さ1l10
0n被着し、ポリシリコン膜/アルミニウム膜の2層構
造の導電膜を形成する。その後、第1図(d)に示すよ
うにホトレジストを用いて電極配線形成用のレジストマ
スク13をパターニングする。
Subsequently, as shown in FIG. 1(c), the BPSG film 6 is
Heat treated at 00° C., reflowed the BPSG film 6, and then selectively opened contact holes using a dry etching method. Using the substrate as a substrate, a polysilicon film 14 was deposited to a thickness of about 200 nm using the CVD method. Subsequently, an aluminum film 8 is formed to a thickness of 1l10 by sputtering.
A conductive film having a two-layer structure of polysilicon film/aluminum film is formed. Thereafter, as shown in FIG. 1(d), a resist mask 13 for forming electrode wiring is patterned using photoresist.

その後、ドライエツチング法により、CCe4−CF4
 、 BCJ?3の混合ガスの圧力を17Paに保ち、
かつエツチングパワーを400Wとし、アルミニウム膜
を厚さ方向に500nm程度ドライエツチングを施す。
After that, by dry etching method, CCe4-CF4
, BCJ? Maintain the pressure of the mixed gas in step 3 at 17 Pa,
At an etching power of 400 W, the aluminum film is dry-etched to a thickness of about 500 nm in the thickness direction.

この条件では等方性エツチングが行なわれろく第1工程
)。
Under these conditions, isotropic etching is difficult (first step).

さらに続けて、第1図(e)に示すように前述した混合
ガスの圧力を7Pa程度に保ち、かつエツチングパワー
を100OWまで上昇し、アルミニウム膜とポリシリコ
ン膜からなる導電膜を厚さ方向に終りまでエツチングす
る。この条件では異方性エツチングから行われる(第2
工程)。
Further, as shown in FIG. 1(e), the pressure of the above-mentioned mixed gas was maintained at about 7 Pa, and the etching power was increased to 100 OW to etch a conductive film consisting of an aluminum film and a polysilicon film in the thickness direction. Etching until the end. Under these conditions, anisotropic etching is performed (second
process).

次に、第1図(f)に示すようにレジストマスク13を
低温灰化処理により除去し、さらに水洗を施した後、常
圧CVDにより、低濃度PSG膜9を厚さ11000n
程度堆積し、続けて、プラズマCVD法により、プラズ
マ窒化膜10を厚さ300nm程度堆積して半導体チッ
プが完成する。第2図に部分拡大断面図を示しておく。
Next, as shown in FIG. 1(f), the resist mask 13 is removed by low-temperature ashing, and after washing with water, a low concentration PSG film 9 is formed to a thickness of 11,000 nm by normal pressure CVD.
Then, a plasma nitride film 10 is deposited to a thickness of about 300 nm by plasma CVD to complete the semiconductor chip. FIG. 2 shows a partially enlarged sectional view.

なお、前述の混合ガスの場合、圧力15〜18Pa、エ
ツチングパワー400〜500Wで等方性エツチングと
なり、第1工程で除去する導電膜の厚さは初期膜厚の3
0〜70%が適当であり、又、圧力8〜10Pa、エツ
チングパワ−800〜iooowで異方性エツチングと
なる。単にカスの圧力とエツチングパワーを変えて等方
性、異方性エツチングの切りかえか行えるので具合がよ
い。
In addition, in the case of the above-mentioned mixed gas, isotropic etching is performed at a pressure of 15 to 18 Pa and an etching power of 400 to 500 W, and the thickness of the conductive film removed in the first step is 3 times the initial film thickness.
A suitable range is 0 to 70%, and anisotropic etching is achieved at a pressure of 8 to 10 Pa and an etching power of 800 to iooow. It is convenient because it is possible to switch between isotropic and anisotropic etching simply by changing the pressure of the scrap and the etching power.

従来の等方性エツチングのみによる導電膜のエツチング
によるものに比べ電極配線の断面形状がなだらかになる
ので低濃度PSG膜及びプラズマ窒化膜の段差被覆性が
よくなり、耐湿性が向上する。
Compared to conventional etching of a conductive film using only isotropic etching, the cross-sectional shape of the electrode wiring becomes gentler, so that step coverage of the low concentration PSG film and plasma nitride film is improved, and moisture resistance is improved.

第3図は本発明の第2の実施例を説明するための半導体
チップの断面図である。
FIG. 3 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

本実施例はアルミニウム電極膜を2層用いた場合の半導
体装置の製造方法であり、第1の実施例と同様にして、
アルミニウム膜8を被着し、等方性エツチングと異方性
エツチングの2段階エツチングにより下層電極配線を形
成したのちホトレジストマスクを除去し、水洗を施した
後、プラズマCVD法によりプラズマ窒化膜11を厚さ
11000n堆積する。
This example is a method for manufacturing a semiconductor device using two layers of aluminum electrode films, and in the same manner as the first example,
After depositing an aluminum film 8 and forming a lower layer electrode wiring by two-step etching of isotropic etching and anisotropic etching, the photoresist mask was removed, and after washing with water, a plasma nitride film 11 was formed by plasma CVD. Deposit to a thickness of 11,000 nm.

続けて、プラズマ窒化膜11にホトレジストを用いて選
択的にスルーホールを開口し、その後、他のアルミニウ
ム膜12を被着し、さらにホトレジストを用い選択的に
このアルミニウム膜12を前述した方法と同じ手段によ
り、等方性エツチングおよび異方性エツチングを施しパ
ターンニングして上層電極配線を形成する。続けて、常
圧CVD法により低濃度PSG13を厚さ11000n
程度堆積し、その後、プラズマ窒化膜14を堆積する。
Subsequently, through holes are selectively opened in the plasma nitride film 11 using photoresist, and then another aluminum film 12 is deposited, and this aluminum film 12 is selectively formed using photoresist in the same manner as described above. By means of isotropic etching and anisotropic etching, patterning is performed to form upper layer electrode wiring. Next, low concentration PSG13 was deposited to a thickness of 11,000 nm using the normal pressure CVD method.
After that, a plasma nitride film 14 is deposited.

この実施例では下層のアルミニウム膜8を比救的厚く形
成した場合に於ても上層のアルミニウム膜12は下層の
アルミニウム膜との交差部で段切れか発生することがな
く、信頼性の高い半導体装置が得られる。
In this embodiment, even when the lower aluminum film 8 is formed relatively thick, the upper aluminum film 12 does not break at the intersection with the lower aluminum film, resulting in a highly reliable semiconductor. A device is obtained.

尚、以上の実施例では導電膜をエツチングする際、第1
工程である等方性エツチングをドライエツチング法によ
り実施しているが湿式のエツチング法を用いた場合にも
同様の効果があることは言うまでもない。
In the above embodiments, when etching the conductive film, the first
Although the isotropic etching step is carried out by a dry etching method, it goes without saying that a similar effect can be obtained if a wet etching method is used.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、導電膜のエツチングを行
うのに第1工程で等方性エツチングを用い、第2工程で
異方性エツチングを用いて、連続的にエツチングを施す
ことにより金属電極膜(電極配線)のエツチング面の形
状がなたらになる結果、金属電極膜上層に形成するパッ
シベーション膜の段差被覆性が改良され、パッシベーシ
ョン膜が均一に堆積されるため、半導体装置をモールド
パッケージングする際の温度ストレス等によるパッシベ
ーション膜のクラック等が発生することがなく耐湿性が
一段と向上し製品の信頼度が高くなる効果がある。
As explained above, the present invention uses isotropic etching in the first step to etch the conductive film, and anisotropic etching in the second step, thereby etching the metal electrode continuously. As the shape of the etched surface of the film (electrode wiring) becomes more uniform, the step coverage of the passivation film formed on the metal electrode film is improved, and the passivation film is deposited uniformly, making it easier to mold package semiconductor devices. This has the effect of further improving moisture resistance and increasing the reliability of the product, since cracks in the passivation film do not occur due to temperature stress, etc. during the process.

また、金属電極膜を2層用いた構造の半導体装置では眉
間絶縁膜の段差被覆性が改良されるため、上層電極配線
と下層電極配線が交差する領域での上層電極配線が断線
することがなく、かつ下層電極配線の膜厚も厚く形成す
ることが可能である為、下層電極配線とその下のシリコ
ン基板とのコンタクト部における断切れ等も是正するこ
とが可能となるという大きな効果かある。
In addition, in a semiconductor device with a structure using two layers of metal electrode films, the step coverage of the glabella insulating film is improved, so that the upper layer electrode wire is not disconnected in the area where the upper layer electrode wire and the lower layer electrode wire intersect. In addition, since the film thickness of the lower electrode wiring can be formed thicker, it is possible to correct disconnections at the contact portion between the lower electrode wiring and the silicon substrate therebelow, which is a great effect.

以上説明した様に本発明を用いた半導体装置の製造方法
を用いることにより、半導体装置の温度ストレスおよび
耐湿性さらには、パッシベーション膜厚を厚く形成でき
るので、モールドパッケージング時に発生するモールド
樹脂のフィラーによる損傷対策にもなり、信頼度の高い
半導体装置を安価に提供できる。
As explained above, by using the method of manufacturing a semiconductor device using the present invention, it is possible to improve the temperature stress and moisture resistance of the semiconductor device, and also to form a thick passivation film, so that the mold resin filler generated during mold packaging can be reduced. This also serves as a countermeasure against damage caused by damage, and highly reliable semiconductor devices can be provided at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は本発明の第1の実施例を説明す
るための工程順に配置した半導体チップの断面図、第2
図は第1図(f)の部分拡大断面図、第3図は第2の実
施例を説明するための半導体チップの断面図、第4図は
従来例を説明するための半導体チップの断面図である。 1・・・P型シリコン基板、2・・・酸化シリコン膜、
3・・・ポリシリコン膜、4・・ゲート酸化シリコン膜
、5・・・N型導電層、6・・・BPSG膜、8・・・
アルミニウム膜、9・・・低濃度PSG膜、10.11
・・・プラズマ窒(ヒ膜、12・・・アルミニウム膜、
13・・・低濃度PSG膜、14・・・プラズマ窒化膜
、15・・・N型ウェル、16・・・P型導電層。 代理人 弁理士  内 原  音 第1図
1(a) to 1(f) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the first embodiment of the present invention;
The figure is a partially enlarged sectional view of FIG. 1(f), FIG. 3 is a sectional view of the semiconductor chip for explaining the second embodiment, and FIG. 4 is a sectional view of the semiconductor chip for explaining the conventional example. It is. 1... P-type silicon substrate, 2... silicon oxide film,
3... Polysilicon film, 4... Gate silicon oxide film, 5... N-type conductive layer, 6... BPSG film, 8...
Aluminum film, 9...Low concentration PSG film, 10.11
...Plasma nitride (arsenic film, 12...aluminum film,
13...Low concentration PSG film, 14...Plasma nitride film, 15...N type well, 16...P type conductive layer. Agent Patent Attorney Oto Uchihara Figure 1

Claims (1)

【特許請求の範囲】[Claims]  基板上に被着した導電膜を選択的に除去して電極配線
を形成するエッチング工程を有する半導体装置の製造方
法において、前記エッチング工程は前記導電膜をその初
期膜厚の途中まで等方性エッチング法で除去する第1工
程と、続いて終りまで異方性エッチング法で除去する第
2工程とからなることを特徴とする半導体装置の製法方
法。
In a method for manufacturing a semiconductor device, the method includes an etching step of selectively removing a conductive film deposited on a substrate to form an electrode wiring, wherein the etching step includes isotropically etching the conductive film to the middle of its initial film thickness. 1. A method for manufacturing a semiconductor device, comprising a first step of removing the semiconductor device by a method, and a second step of removing the device by an anisotropic etching method.
JP6384588A 1988-03-16 1988-03-16 Manufacture of semiconductor device Pending JPH01235352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6384588A JPH01235352A (en) 1988-03-16 1988-03-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6384588A JPH01235352A (en) 1988-03-16 1988-03-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01235352A true JPH01235352A (en) 1989-09-20

Family

ID=13241076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6384588A Pending JPH01235352A (en) 1988-03-16 1988-03-16 Manufacture of semiconductor device

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04323821A (en) * 1991-04-23 1992-11-13 Rohm Co Ltd Semiconductor device and manufacture of conductor for electrode of same
JP2004241750A (en) * 2002-03-26 2004-08-26 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
US8368071B2 (en) 2002-03-26 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including a thin film transistor and capacitor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04323821A (en) * 1991-04-23 1992-11-13 Rohm Co Ltd Semiconductor device and manufacture of conductor for electrode of same
JP2004241750A (en) * 2002-03-26 2004-08-26 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
US8368071B2 (en) 2002-03-26 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including a thin film transistor and capacitor
US9070773B2 (en) 2002-03-26 2015-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including a thin film transistor and a capacitor

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