JPH0360153A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the connection deterioration between a semiconductor region and wiring layers and realize superior connection, by forming a protecting film for impurity diffusion on the surface of an interlayer insulating film containing impurity, and connecting a high melting point wiring layer with the semiconductor region, via a contact hole of the protecting film. CONSTITUTION:On a first conductivity type semiconductor region 3a or 16, an interlayer insulating film 33 containing second conductivity type impurity is formed, on the surface of which insulating film 33 protecting films 38a, 34 for impurity diffusion are formed, and a high melting point wiring layer 9 or 20 is connected with the first conductivity type semiconductor region 3a or 16, via a contact hole 35 or 36. A flow film is used as said interlayer insulating film 33. The high melting point wiring layer 9 or 20 is formed by using a conductive layer such as polycrystalline silicon and polycide. Since the protecting film 38a for impurity diffusion is formed on the surface of the interlayer insulating film 33, second conductivity type impurity contained in the interlayer insulating film 33 is prevented from diffusing into the first conductivity type semiconductor region 3a or 16 or the high melting point wiring layer 9 or 20, so that superior wiring connection is realized.

Description

[Detailed description of the invention] [Industrial application field] The present invention uses As5G for a semiconductor device, particularly an interlayer insulating film.

The present invention relates to a semiconductor device using a so-called flow film such as BPSG.

[Summary of the invention]

The present invention relates to a semiconductor device using a flow film such as As5G or BPSG for the glabellar insulating film, in which an impurity diffusion prevention film is formed on the surface of the interlayer insulating film having a contact hole, and a high melting point wiring layer is formed through the contact hole. By connecting the high-melting point wiring layer to the semiconductor region, a good connection between the high melting point wiring layer and the semiconductor region is made possible.

[Prior art] DR having conventional stacked capacitor type memory cells
Examples of AM (Dyna 5 RAM) are shown in Figures 2 and 3.
As shown in the figure. In the memory cell section of FIG. 1, (1) indicates a p-type silicon substrate, for example, on which a field insulation N (2) is formed, and on this silicon substrate (1), for example, an n-type source and Drain regions (3a) and (3b) are formed, both regions (3a)
and (3b), a gate electrode or word line (6) made of a polycide film, for example, a metal silicide film (5) laminated on a polycrystalline silicon film (4) via a gate insulating film.
is formed. Of the source/drain regions, a bit line (9) is formed in one source/drain region (3a) through a contact hole (8) in the glabella insulating film (7), and a bit line (9) is formed in one source/drain region (3a) through a contact hole (8) in the glabella insulating film (7). ) is connected to a capacitor lower electrode (so-called storage node) (12) of a stacked capacitor via a contact hole (11) in an interlayer insulating film (10).

A capacitor lower electrode (12) is formed for each memory cell, and a capacitor upper electrode (14) is formed on this via a dielectric film (13).
12), dielectric film (13) and capacitor upper electrode (1
A capacitor (15) is constructed by the laminated structure of 4).

In addition, in the peripheral circuit of a DRAM, as shown in Fig. 2, a p shadow region (16) and an n shadow region (1
7) is formed, a wiring layer (18) formed simultaneously with the gate electrode (6) is formed, an interlayer insulating film (7) is formed, and then a bit line (9) is formed through a contact hole (19). A wiring layer (20) formed at the same time is connected to the p shadow region (16) and the wiring layer (18). Furthermore, an interlayer insulating film (21)
An wiring (23) via the contact hole (22)
is connected.

[Problem to be solved by the invention]

By the way, in a stacked capacitor type DRAM of 4M bits or more having the above-mentioned configuration, the bit line (9).

The wiring layer (20) is formed of a polycide film consisting of a polycrystalline silicon film (4) and a metal silicide film (5). Note that the polycrystalline silicon film (4) constituting the polycide film of the bit line (9) is doped with n-type impurities, and the wiring layer (2) is doped with n-type impurities.
Polycrystalline silicon film (4) constituting the polycide film of 0)
is doped with p-type impurities. The reason why the bit line (9) and the wiring N (20) are made of polycide film is that when 11 is used as the bit line (9) and the wiring layer (20), the /l coverage at the contact part and the This is to prevent the reliability of the DRAM from deteriorating due to deterioration of the scission coverage. However, in the case of a stacked capacitor type DRAM, because the level difference in the base is severe, the bit line (9) of the polycide film and the glabella insulating film (7) under the wiring layer (20) are covered with a normal SiO□ film (not a flow film). If this method is used, fine patterning of the bit line (9), wiring layer (20), etc. becomes difficult.

On the other hand, in order to facilitate processing, a so-called flow film such as BPSG (boron phosphorus silicate glass) or As5G (arsenic silicate glass) is used as the glabellar insulating film (7) with the aim of flattening the underlying interlayer insulating film. , high concentration of impurities (e.g. n-type impurities) contained in these flow membranes.
For example, it diffuses into the polycrystalline silicon film (4) (or p shadow region (16)) of the wiring layer (20) in the peripheral circuit area, and connects the p shadow region (16) and the wiring layer (20). It will cause it to deteriorate. In addition, in the memory cell part, impurities (for example, p-type impurities) in the flow film as the glabella insulating film (7) are removed from the polycrystalline silicon film (4) (or n-type source/drain region) of the bit line (9). (3a)), and similarly spreads into the bit line (9) and source/drain region (3a).
) connection deteriorates.

Further, directly depositing a polycrystalline silicon film on a flow film such as BPSG or As5G itself has problems such as abnormal growth of polycrystalline silicon, which makes it difficult to put into practical use.

Incidentally, the problems when using the above-mentioned flow film as a glabellar insulating film and polycide wiring occur not only in DRAMs but also in other semiconductor devices.

The present invention solves the above-mentioned problems and provides a semiconductor device with improved reliability.

[Means to solve the problem]

The semiconductor device of the present invention includes a first conductivity type semiconductor region (3a)
(or (16) ) Contact hole (35) on top
(or (36)), and form an impurity diffusion prevention film (38a) and (34) on the surface of this interlayer insulating film. The high melting point wiring J! is connected to the first conductivity type semiconductor region (3a) (or (16)) through the hole (35) (or (36)). ! (9) (or (20)) are connected.

As the glabella insulating film (33), a flow film such as As5G or BPSG is used. Also, high melting point wiring J! (9) (or (
20) ) can be formed from a conductive layer such as polycrystalline silicon or polycide.

[Effect]

According to the configuration of the present invention, since the interlayer insulating film (33) is a so-called flow film, it is flattened and the wiring JWr9) thereon is flattened.
(or (20)) can be performed, and a thicker insulating film can be formed on the interlayer insulating film (33), so that the so-called wiring capacitance is reduced.

In particular, since the impurity diffusion prevention film (38a) is formed on the surface of the interlayer insulating film (33),
), the second conductivity type impurity contained in the first conductivity type semiconductor region (3a) (or (16)) or the high melting point wiring layer (9) (
or (20) ) Good wiring connections are made without diffusion into the interior.

Furthermore, by forming an impurity diffusion prevention film (34) on the surface of the glabella insulating film (33) containing impurities, a high melting point wiring layer (
9) (or (20)), there is no abnormal growth of polycrystalline silicon.

〔Example〕

Hereinafter, a case where an example of the semiconductor device according to the present invention is applied to a stacked capacitor type DRAM will be described with reference to FIG.

In FIG. 1, (31) indicates a memory cell section, and (32) indicates a peripheral circuit section. In the memory cell section (31), as described above, a p-type silicon substrate (1) on which a field insulating layer (2) is formed is provided with, for example, an n-type source/drain having an LDD (low concentration drain) structure, which constitutes a switching transistor. regions (3a) and (3b) are formed;
A metal silicide film (5) is placed on the polycrystalline silicon film (4) via a gate insulating film between the peripheral regions (3a) and (3b).
A gate electrode, ie, a word line (6), is formed of a polycide film laminated with polycide. Source/drain region (3a)
The capacitor lower electrode (storage node) (12) of the stacked capacitor is connected through the contact hole (11) of the glabella insulating film (10), and the dielectric film (
A capacitor upper electrode (14) is formed via the capacitor (13) to constitute a capacitor (15).

In the peripheral circuit section (32), a P shadow region (16) and an N shadow region (17) are formed on the p-type silicon substrate (1) in the same manner as described above, and a gate electrode, that is, a word line (6), is formed at the same time. A wiring layer (18>) is formed.

In this example, as shown in FIG. 1A, a flow film (33) made of BPSG or As5G, which will serve as an insulating film between the eyebrows, is spread over the memory cell section (31) and the peripheral circuit section (32), for example, by several thousand layers. The film is deposited to a film thickness of about 0.000 C and then annealed at 800'C to 900C to planarize it. Then the thickness 1000 on the flow 11g (33)
A non-doped SiO2 film (34) of about 2,000 layers is deposited.

Next, as shown in FIG. 1B, in the memory cell section (31), contact holes (
35), and the peripheral circuit section (32) has a p shadow area (1
6) Contact hole (36) on top and wiring layer (18)
) and (37), contact holes (35
).

For example, the entire surface including (36) and (37) has a thickness of several tens of
The film was deposited on a 540g film (38) of about 0.000 and 0.000 g.

Next, as shown in FIG. 1C, the SiO□ film (38) is anisotropically etched back to form contact holes (35),
(36).

(37) Leave 540 g of film on the side wall. That is, the side walls of the contact holes (35), (36), and (37) are covered with the SiO□ side wall portion (38a). Thereafter, for example, a bit line (9) and a wiring layer (20) made of a polycide film in which a polycrystalline silicon film (4) and a metal silicide film (5) are laminated are simultaneously formed, and the bit line (
9) to the source/drain region (3a) through the contact hole (35), and connect the wiring layer (20) to the p shadow region (16) through the contact hole (36) (37).
and connected to the wiring layer (18). Here, the bit line (9
) The polycrystalline silicon film (4) is doped with n-type impurities, and the wiring! The polycrystalline silicon film (4) of (20) has p
doped with shape impurities. In the peripheral circuit section (32), after forming the wiring layer (20), Aj2 wiring (33) is further formed via a flow film (39) such as As5G or BPSG.

According to the above configuration, the contact hole (35).

(36) and (37), the surface of the flow membrane (33) is completely covered with the non-doped 5in2 film (34) and the Sin□ sidewall (38a), so the flow membrane ( 33) The impurities contained in the bit line (
9) or without diffusing into the wiring layer (20) or into the source/drain region (3a) or the p shadow region (16), therefore, the pitch H,m (9) and the source/drain region (3a)
) or the connection between the wiring layer (20) and the P shadow area (16).

Further, since the flow film (33) is used as the glabellar insulating film, the film is flattened, and therefore the SiO□ film (34) thereon can be formed thickly, thereby further reducing the wiring capacitance. In addition, since a flat interlayer insulating film is formed by the flow film (33), the bit line (9) formed on it is
), the fine processing, that is, patterning, of the wiring layer (20) becomes easy.

Further, in the memory cell part (31), a contact hole (3
By forming the SiO□ sidewall portion (38a) in 5), the contact portion can be made substantially smaller, and therefore the distance between the bit line and the contact portion, that is, the flow film (33
) can be made smaller, and the memory cell of the stacked capacitor type DRAM can be made smaller.

Furthermore, non-doped 5tO2 is placed on the flow membrane (33).
Since the film (34) is formed, there is no abnormal growth when forming the polycrystalline silicon film (4), and a good polycide film can be formed.

In addition, on the upper side, a stacked capacitor type DRAM
In addition, As5G was used as an interlayer insulating film.

Of course, the present invention can also be applied to a semiconductor device in which a flow film such as BPSG is used and a wiring layer (including electrodes) made of polycrystalline silicon or polycide is connected through the contact hole.

〔Effect of the invention〕

According to the present invention, an impurity diffusion prevention film is formed on the surface of the impurity-containing interlayer insulating film, and the high melting point wiring layer is connected to the semiconductor region through the contact hole. Connection deterioration can be avoided and a good connection can be obtained. Since the impurity-containing interlayer insulating film is a so-called flow film, a flattened interlayer insulating film can be obtained, and a wiring layer with a fine pattern can be formed on it, and an insulating film can be further formed on the flow film. Since it is possible to form a thick layer, the wiring capacitance between the layer and the lower layer can be reduced.

Therefore, a highly reliable and high-density semiconductor device can be provided.

[Brief explanation of drawings]

FIGS. 1A-1C are cross-sectional views showing an example of a semiconductor device according to the present invention in the order of steps, and FIGS. 2 and 3 are cross-sectional views of a conventional semiconductor device. (1) is the silicon substrate, (3a) (3b) is the source
Drain region, (4) is a polycrystalline silicon film, (5) is a metal silicide film, (6) is a word line, (16) is a P shadow region, (33) is an interlayer insulating film such as As5G, BPSG, etc.
(34) is Si0g film, (38a) is SiO□ side wall part,
(9) is a bit line, and (20) is a wiring layer. Agent Hidemori Matsukuma Conventional Eve 1 II/r city map Figure 2 1 ------- Silico) Late autumn 2 ------- Field test A 3a, 3b ---- Source Drain moxa 4・---
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Claims (1)

[Scope of Claims] An interlayer insulating film containing a second conductivity type impurity having a contact hole on the first conductivity type semiconductor region is formed, an impurity diffusion prevention film is formed on the surface of the interlayer insulating film, and the contact hole A semiconductor device comprising a high melting point wiring layer connected to the first conductivity type semiconductor region via.