JPH11307743A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the capacitance of a DRAM memory capacitor by a comparatively simple and sure manufacturing method. SOLUTION: This manufacturing method comprises forming an SiN film on a layer insulation film 6, forming a laminated structure of polysilicon films 8, 10 via an Si oxide film thereon, forming storage contacts, utilizing polysilicon sidewalls 12, filling the storage contacts with polysilicon films 14, 15, processing the polysilicon films 8, 10, 14, 15 into a pattern of storage node electrodes, removing the Si oxide film between the polysilicon films 8, 10 through the wet etching, and forming a dielectric film 16 and cell plate electrodes 17 on the storage node electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynami
(c) Random Access Memory) and a method of manufacturing the same.

[0002]

2. Description of the Related Art A DRAM which stores a charge by storing a charge in a memory capacitor has a problem that it becomes difficult to secure a sufficient charge storage capacity with the high integration. This is because the planar area of the memory cell is reduced due to the high integration, and therefore, the planar area of the storage node electrode of the memory capacitor is reduced.

In order to solve this problem, various devices have been proposed. For example, in a stack type memory cell, a so-called fin type memory cell in which a storage node electrode is formed to project in a fin shape in a horizontal direction. A structure has been proposed.

For example, in Japanese Patent Application Laid-Open No. 7-169853, a LOCOS method is used to form a silicon oxide layer between two polysilicon layers, and the silicon oxide layer is etched away to form a fin. A method of forming a storage node electrode of a type has been proposed.

In Japanese Patent Application Laid-Open No. 8-83893,
After forming a storage contact using the polysilicon sidewall formed on the side wall of the silicon nitride film as an etching mask, the silicon nitride film is used as an interlayer film between the two polysilicon films, and the silicon nitride film is removed by etching. Then, a method of forming a fin-type storage node electrode has been proposed.

[0006]

However, the method disclosed in Japanese Patent Application Laid-Open No. 7-169853 requires a minimum of three photolithography steps, which makes the manufacturing process relatively complicated. Was.

In the method disclosed in Japanese Patent Application Laid-Open No. H8-83893, when the silicon nitride film is removed by wet etching, the etching selectivity between the silicon nitride film and the silicon oxide film is only about 10 to 30 at most. As a result, the underlying silicon oxide film is unexpectedly etched, and its flatness may be impaired or even a short circuit may occur.

It is an object of the present invention to provide a semiconductor memory device capable of securing the capacity of a memory capacitor by a relatively simple and reliable method, and a method of manufacturing the same.

[0009]

According to a method of manufacturing a semiconductor memory device of the present invention, which solves the above-described problems, a transistor structure serving as an access transistor of a memory cell is formed on a main surface of a semiconductor substrate, and an interlayer is formed over the entire surface. Forming an insulating film, forming a first insulating film on the interlayer insulating film, forming a first conductive film on the first insulating film, Forming a second insulating film having a material different from that of the first insulating film on the conductive film, forming a second conductive film on the second insulating film;
A first opening penetrating through the second conductive film, the second insulating film, the first conductive film, and the first insulating film located immediately above one diffusion layer of the transistor structure. Forming, forming a sidewall made of a third conductive film on a side wall of the first opening, and forming the first insulating film on the interlayer insulating film by using the sidewall as an etching mask. Forming a second opening that is continuous with the opening and reaches the one diffusion layer of the transistor structure; and forming a fourth conductive layer on the entire surface so as to fill the first and second openings. Forming a film, and forming the fourth conductive film, the second conductive film, the second insulating film, and the first conductive film into a memory including the first and second aperture regions; Processing the lower electrode pattern of the capacitor;
Removing the second insulating film from the lower electrode pattern to form a lower electrode of the memory capacitor; forming a capacitor dielectric film on the surface of the lower electrode; Forming the upper electrode of the memory capacitor.

In one embodiment of the present invention, a polycrystalline silicon film is formed as each of the first to fourth conductive films.

In one embodiment of the present invention, after forming a relatively thin polycrystalline silicon film as the fourth conductive film, a polycrystalline silicon film is formed thereon so as to fill the first and second openings. A silicon film is formed.

In one embodiment of the present invention, a silicon nitride film is formed as the first insulating film, and a silicon oxide film is formed as the second insulating film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: forming a transistor structure serving as an access transistor of a memory cell on a main surface of a semiconductor substrate; and forming an interlayer insulating film on the entire surface. Forming a first insulating film on the interlayer insulating film;
Forming a first polycrystalline silicon film on the first insulating film, and forming a first hemispherical polycrystalline silicon on the surface of the first polycrystalline silicon film to form the first polycrystalline silicon film. Forming an uneven part on the surface of the silicon film; and forming the first part on the first polycrystalline silicon film having the uneven part on the surface.
Forming a second insulating film having a material different from that of the second insulating film, forming a second hemispherical polycrystalline silicon on the second insulating film, and forming the second hemispherical polycrystalline silicon on the second insulating film. Etching the surface of the second insulating film using silicon as a mask,
Forming a concavo-convex portion on the surface of the second insulating film; forming a second polycrystalline silicon film on the second insulating film having the concavo-convex portion on the surface; A first opening penetrating through the second polycrystalline silicon film, the second insulating film, the first polycrystalline silicon film, and the first insulating film just above one of the diffusion layers is formed. Forming, forming a sidewall made of a third polycrystalline silicon film on a side wall of the first opening, and forming the sidewall on the interlayer insulating film by using the sidewall as an etching mask. Forming a second opening continuous with the first opening and reaching the one diffusion layer of the transistor structure; and forming a fourth opening on the entire surface so as to fill the first and second openings. Forming a polycrystalline silicon film of A lower electrode of a memory capacitor including the first and second opening regions by using the polycrystalline silicon film, the second polycrystalline silicon film, the second insulating film, and the first polycrystalline silicon film. Processing into a pattern, removing the second insulating film from the lower electrode pattern, and forming a lower electrode of the memory capacitor;
Forming a capacitor dielectric film on the surface of the lower electrode; and forming an upper electrode of the memory capacitor on the capacitor dielectric film.

In one embodiment of the present invention, after forming a relatively thin polycrystalline silicon film as the fourth polycrystalline silicon film, the fourth polycrystalline silicon film is so thick as to fill the first and second openings. A polycrystalline silicon film is formed.

In one embodiment of the present invention, a silicon nitride film is formed as the first insulating film, and a silicon oxide film is formed as the second insulating film.

According to another aspect of the present invention, there is provided a semiconductor memory device having a memory cell including an access transistor and a memory capacitor, wherein the lower electrode of the memory capacitor is connected to one of the diffusion layers of the access transistor. Comprises a first horizontal electrode portion formed of a polycrystalline silicon layer provided along the main surface of the semiconductor substrate, and a polycrystalline silicon layer disposed opposite to the first horizontal electrode portion at a predetermined interval. A second horizontal electrode portion, and a vertical connecting portion made of polycrystalline silicon for connecting the first and second horizontal electrode portions to each other, and a hemisphere is provided on a surface facing the first and second horizontal electrode portions. An uneven portion made of polycrystalline silicon is provided.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to preferred embodiments.

[First Embodiment] First, a method of manufacturing a DRAM according to a first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1A, a field oxide film 2 is formed on a main surface of a silicon semiconductor substrate 1 by, for example, a LOCOS (selective oxidation) method, and is surrounded by the field oxide film 2. A gate insulating film 3 is formed on the surface of the silicon semiconductor substrate 1 in the element forming region. As the gate insulating film 3, a thermal oxide film, a nitrided oxide film containing nitrogen, or the like can be used. Next, a polysilicon film is formed on the entire surface, and the polysilicon film is patterned to form a gate electrode wiring 4. Note that the gate electrode wiring 4 may be a polycide wiring in which a titanium silicide film, a tungsten silicide film, or the like is stacked on a polysilicon film. Next, impurities are ion-implanted into the surface regions of the silicon semiconductor substrate 1 on both sides of the gate electrode wiring 4 to form an impurity diffusion layer 5 serving as a source / drain of the transistor. The illustrated example shows a structure in which two memory cells sharing one diffusion layer of an access transistor are formed in one element formation region.

Next, an interlayer insulating film 6 is formed on the entire surface, and its surface is flattened. As a method of this flattening, for example, BPSG (Boro Phospho Silic
ate glass) film, and the BPSG film is
Reflow at a temperature of 0 ° C. Although not shown, after forming a first interlayer insulating film as the interlayer insulating film 6, a bit line is formed in a direction orthogonal to the gate electrode wiring 4, and a second interlayer insulating film is formed thereon. An insulating film is formed. The bit line contacts the diffusion layer 5 of the access transistor shared by the two memory cells.

Next, a silicon nitride film 7, a polysilicon film 8, a silicon oxide film 9 and a polysilicon film 10 are sequentially laminated on the interlayer insulating film 6, and these laminated films are formed by photolithography and dry etching. The opening 11 is formed at a predetermined position, that is, a position immediately above the diffusion layer 5 that is not shared by the access transistors.

Next, as shown in FIG.
The polysilicon film formed on the entire surface including the inside is anisotropically etched to form a sidewall 12 made of polysilicon on the side wall in the opening 11.

Next, as shown in FIG. 2A, the interlayer insulating film 6 is dry-etched using the side wall 12 made of polysilicon as an etching mask. Diffusion layer 5
Is formed. As described above, by performing etching using the polysilicon sidewall 12 as an etching mask, for example, the opening 13 having a diameter smaller than the exposure limit of photolithography can be formed.

Next, in order to reduce the resistance of the storage contact thus formed, as shown in FIG. 2B, a polysilicon film 14 doped with phosphorus (P) is formed on the entire surface. The polysilicon film 14 is not always necessary, and can be omitted.

Next, as shown in FIG. 3A, after a polysilicon film 15 is formed on the entire surface so as to bury the storage contact, the polysilicon film 15 and the polysilicon film 14 are formed by photolithography and dry etching. Then, the polysilicon film 10, the silicon oxide film 9 and the polysilicon film 7 are processed into a pattern of a storage node (lower electrode) of a memory capacitor including a storage contact region.

Thereafter, the silicon oxide film 9 is removed by wet etching using hydrofluoric acid (HF). In the wet etching of the silicon oxide film 9, the etching selectivity to the silicon nitride film 7 can be set to about 100 or more, and therefore, the silicon nitride film 7 can be used as an etching stopper.

Next, as shown in FIG. 3B, a capacitor dielectric film 16 such as a silicon nitride film and a silicon oxide film is formed on the surface of the fin-type storage node electrode formed as described above. An NO film or ONO film, which is a composite laminated film, or a high dielectric film such as Ta ₂ O ₅ is formed, and a polysilicon film 17 doped with phosphorus (P) serving as a cell plate electrode is further formed thereon. Form.

According to the manufacturing method described above, the photolithography step at the time of forming the capacitor structure is performed by the steps shown in FIG.
Only the patterning step in FIG. 3A and the patterning step in FIG.
The manufacturing process is simplified as compared with the method disclosed in Japanese Patent No. 169853.

Further, at the time of wet etching of the silicon oxide film 9 for forming the fin structure, the silicon nitride film 7 effectively functions as an etching stopper, so that the above-mentioned problem in JP-A-8-83893 is also solved.

In the structure of the first embodiment, when the storage node electrode is patterned or wet-etched with hydrofluoric acid, the polysilicon film 8 under the electrode is unexpectedly etched and the electrode structure collapses. In order to prevent this, the concentration of impurities, for example, phosphorus (P) introduced into the polysilicon film is changed between the polysilicon film 8 and the polysilicon films 10, 14, and 15 above the electrodes. Is also good. For example, the polysilicon films 10, 14, and 15 above the electrodes are 1 × 10 ²⁰ to 1 × 10 ^21.
/ Cm ³ is introduced at a high concentration, and the polysilicon film 8 under the electrode has a detection limit (about 1 × 10 ¹² / cm ³ ).
P is introduced below. As a result, the etching rate of the polysilicon film 8 below the electrode becomes smaller than that of the polysilicon films 10, 14, 15 above the electrode, thereby preventing unexpected etching.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIGS.

In the second embodiment, parts corresponding to those in the above-described first embodiment are denoted by the same reference numerals as those in the above-described first embodiment, and are described in detail. Is omitted.

First, as shown in FIG. 4A, a silicon semiconductor substrate 1 is formed in the same manner as in the first embodiment.
After an access transistor structure and the like are formed thereon and an interlayer insulating film 6 is formed, a silicon nitride film 7 and a polysilicon film 8 are sequentially formed thereon.

Next, in the second embodiment, for example, source gas: SiH ₄ , gas flow rate: 50 to 150 s
ccm, substrate temperature: about 590 to 610 ° C., pressure: 0.
A rough polysilicon film (referred to as “hemispherical poly (polycrystalline) silicon” or “HSG”) 8 on the polysilicon film 8 by a low pressure CVD method of about 2 Torr.
is deposited to make the surface of the polysilicon film 8 uneven.

Next, as shown in FIG. 4 (b), a silicon oxide film 9 is formed on the polysilicon film 8 whose surface is formed in an uneven shape, and further thereon, the same conditions as described above are applied. To deposit the HSG 10a. And the HSG10a
Is used as an etching mask, the surface of the silicon oxide film 9 is wet-etched, and as shown in FIG.
Is made uneven. The surface of the silicon oxide film 9 may be made uneven by, for example, an ashing process without using the HSG 10a.

Thereafter, as shown in FIG. 5A, a polysilicon film 10 is formed on the silicon oxide film 9. As a result, the lower surface of the polysilicon film 10 is formed in an uneven shape.

Thereafter, as shown in FIG. 5B, the formation of the opening 11 and the formation of the polysilicon sidewall 12 are performed in the same manner as in the first embodiment.

Further, as shown in FIG. 6A, after forming the storage contact, the polysilicon films 14, 15 are formed.
Is formed, and further, the storage node electrode is patterned. Then, the silicon oxide film 9 is removed by wet etching. As a result, as shown in the figure, a storage node electrode is obtained in which the concave and convex portions are formed on the facing surfaces of the polysilicon films 8 and 10 in the fin portions, respectively.

As shown in FIG. 6B, a capacitor dielectric film 16 is formed on the storage node electrode, and a cell plate 17 made of a polysilicon film is formed thereon.
Are sequentially formed to complete the capacitor structure.

In the second embodiment, the unevenness is provided on the surface of the fin of the storage node electrode.
The effective surface area of the storage node electrode is increased and the capacitance of the capacitor is increased as compared with the structure of the first embodiment described above.

In the second embodiment, HSG may be formed on the surface of the polysilicon film 15 to further increase the capacitance of the capacitor.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to these embodiments. For example, in the above-described embodiment, one fin structure including the polysilicon films 8 and 10 is provided, but a plurality of fin structures may be provided. This can be easily realized, for example, by repeatedly forming a laminated structure of the polysilicon film 8, the silicon oxide film 9, and the polysilicon film 10.

[0043]

According to the present invention, for example, the capacity of a DRAM memory capacitor can be increased by a relatively simple and reliable manufacturing method.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a method for manufacturing a DRAM according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a schematic sectional view showing a method for manufacturing a DRAM according to a second embodiment of the present invention in the order of steps.

FIG. 5 is a schematic cross-sectional view showing a method for manufacturing a DRAM according to a second embodiment of the present invention in the order of steps.

FIG. 6 is a schematic cross-sectional view showing a method of manufacturing a DRAM according to the second embodiment of the present invention in the order of steps.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Field oxide film 3 Gate insulating film 4 Gate electrode wiring 5 Diffusion layer 6 Interlayer insulating film 7 Silicon nitride film 8, 10, 14, 15 Polysilicon film (storage node) 8a, 10a HSG 9 Silicon oxide film 12 Polysilicon sidewall 16 capacitor dielectric film 17 polysilicon film (cell plate)

Claims (8)

[Claims] A step of forming a transistor structure to be an access transistor of a memory cell on a main surface of a semiconductor substrate, and then forming an interlayer insulating film on the entire surface; and forming a first insulating film on the interlayer insulating film. Forming, forming a first conductive film on the first insulating film, and forming a second insulating material on the first conductive film, the second insulating material having a material different from that of the first insulating film. A step of forming a film; a step of forming a second conductive film on the second insulating film; and a step of forming the second conductive film immediately above one diffusion layer of the transistor structure; Forming a first opening penetrating the insulating film, the first conductive film, and the first insulating film; and forming a third conductive film on a side wall of the first opening. Forming a sidewall, and using the sidewall as an etching mask Stomach,
Forming a second opening in the interlayer insulating film that is continuous with the first opening and reaches the one diffusion layer of the transistor structure; and forming the first and second openings. Forming a fourth conductive film on the entire surface so as to be buried; and forming the fourth conductive film, the second conductive film, the second insulating film, and the first conductive film in the first and second conductive films. Forming a lower electrode of the memory capacitor by removing the second insulating film from the lower electrode pattern; and forming the lower electrode of the memory capacitor by removing the second insulating film from the lower electrode pattern. Forming a capacitor dielectric film on the surface of the semiconductor memory device; and forming an upper electrode of the memory capacitor on the capacitor dielectric film. 2. The method according to claim 1, wherein a polycrystalline silicon film is formed as each of the first to fourth conductive films. 3. After forming a relatively thin polycrystalline silicon film as the fourth conductive film, a thick polycrystalline silicon film is formed thereon so as to fill the first and second openings. 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein: 4. The method according to claim 1, wherein a silicon nitride film is formed as the first insulating film, and a silicon oxide film is formed as the second insulating film. A method for manufacturing a semiconductor storage device. 5. A step of forming a transistor structure serving as an access transistor of a memory cell on a main surface of a semiconductor substrate and then forming an interlayer insulating film over the entire surface; Forming a first polycrystalline silicon film on the first insulating film; forming a first hemispherical polycrystalline silicon on a surface of the first polycrystalline silicon film. Forming a concave and convex portion on the surface of the first polycrystalline silicon film; and forming the first insulating film on the first polycrystalline silicon film having the concave and convex portion on the surface. Forming a different second insulating film, forming a second hemispherical polycrystalline silicon on the second insulating film, and using the second hemispherical polycrystalline silicon as a mask, The surface of the second insulating film is etched by etching the surface of the second insulating film. Forming an uneven portion on the surface; and forming a second portion on the second insulating film having the uneven portion on the surface.
Forming the second polycrystalline silicon film, the second insulating film, and the first polycrystalline silicon film located immediately above one of the diffusion layers of the transistor structure.
Forming a first opening penetrating them in the polycrystalline silicon film and the first insulating film; and forming a side wall made of a third polycrystalline silicon film on a side wall of the first opening. Forming, and using the sidewalls as an etching mask,
Forming a second opening in the interlayer insulating film that is continuous with the first opening and reaches the one diffusion layer of the transistor structure; and forming the first and second openings. Forming a fourth polycrystalline silicon film on the entire surface so as to be embedded, the fourth polycrystalline silicon film, the second polycrystalline silicon film, the second insulating film, and the first polycrystalline silicon Processing the film into a lower electrode pattern of a memory capacitor including the first and second aperture regions; and removing the second insulating film from the lower electrode pattern to form a lower electrode of the memory capacitor. Forming a capacitor dielectric film on the surface of the lower electrode; and forming an upper electrode of a memory capacitor on the capacitor dielectric film. of Production method. 6. A relatively thin polycrystalline silicon film is formed as the fourth polycrystalline silicon film, and a thick polycrystalline silicon film is formed thereon so as to fill the first and second openings. 6. The method according to claim 5, wherein the semiconductor memory device is formed. 7. The semiconductor memory device according to claim 5, wherein a silicon nitride film is formed as the first insulating film, and a silicon oxide film is formed as the second insulating film. Method. 8. A semiconductor memory device having a memory cell having an access transistor and a memory capacitor, wherein a lower electrode of the memory capacitor connected to one of the diffusion layers of the access transistor is provided on a main surface of a semiconductor substrate. A first horizontal electrode portion made of a polycrystalline silicon layer provided along the first horizontal electrode portion, and a second horizontal electrode portion made of a polycrystalline silicon layer opposed to the first horizontal electrode portion at a predetermined interval. A vertical connecting portion made of polycrystalline silicon for connecting the first and second horizontal electrode portions to each other, and a concave / convex portion made of hemispherical polycrystalline silicon on a surface facing the first and second horizontal electrode portions. Are provided, respectively.