JP4990479B2 - 多層リソグラフィープロセスに関する新規な平坦化方法 - Google Patents
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- H01L21/3105—After-treatment
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24851—Intermediate layer is discontinuous or differential
Description
連邦政府の委託研究/開発プログラム
本発明は、米国標準技術局(NIST)によって認定された先進技術プログラム♯70NANB1H3019の下で米国政府の援助を受けてなされたものである。本発明に関して、米国政府は一定の権利を有する。
本願は、2002年2月27日付で出願され、この参照によって本開示に含まれる、第60/360,374号の多層リソグラフィープロセスに関する新規な平坦化方法と題された先の出願の優先権の利益を主張する。
本発明は、概して、マイクロエレクトロニック、フォトニクス、オプトエレクトロニック、オプティカル、マイクロエレクトロメカニカルシステム(MEMS)、バイオチップ、およびセンサーデバイスの製造、ならびにリソグラフィープロセスを必要とする他のプロセスのための、熱可塑性、熱硬化性、および、光硬化性の平坦化材料を利用した、新規な接触平坦化方法に関する。
市場は、マイクロエレクトロニックデバイスに対して、デバイス内により小さな微細構造を構築するための必要性を推進する、小さな物理的特性をもつことを要求する。さらに、そのようなデバイスは、さらなるエネルギー効率の良さや非常にすぐれた機能性を期待される、一方で、生産効率の向上も期待される。上記の目的を達成するために、集積回路(IC)上にあるデバイスの加工寸法をますます小さくする必要がある。従って、ライン、トレンチ、ビア、およびホール等の、より小さな微細構造を有し、相互に接続された多くの層が、デバイス基板上で、パターン形成されるべきである。現在、フォトリソグラフィーが、これらの微細構造をデバイス基板上に構築するために使用されている。このプロセスは、一般的に、単層のフォトレジスト層を用いて達成される。新興のリソグラフィー技術、例えば、インプリントリソグラフィー、ナノインプリントリソグラフィー、ホットエンボスリソグラフィー、および、スタンピングパターントランスファー等が提案されている。これらの技術は、基板表面にパターンを転写するために、フォトリソグラフィックパターンニングの代わりに、パターン形成されたモールド(型)を使う。
本発明は、概して、新規な接触平坦化方法、および、スタンピングパターンプロセスと同様にフォトリソグラフィー、インプリントリソグラフィー、ナノインプリントリソグラフィー、およびホットエンボスリソグラフィーのために、全体的に平坦な表面を提供する本方法によって形成される前駆体に関し、これにより従来技術の問題点を抑制または防止する。
図3(a)において、基板32が図示されている。基板32は、その上に構造または加工部34を備える表面を含む。これらの構造または加工部34は、前駆体の最終的な利用目的に依存して変化する凹凸形状および加工寸法を有している。ここで使用した、“凹凸形状”は、構造の高さまたは深さを表すのに対して、“加工寸法”は、構造の幅および長さを表す。幅と長さとが異なる場合は、より小さい数を加工寸法とみなすことが一般的である。
ビアウェハ上の光硬化性平坦化材料
20gのエポキシ(D.E.R.354LV,ダウ ケミカル カンパニー)と、80gのPGME(アルドリッチ)と、1.2gのSarcat KI−85(サートマーから入手可能な光酸発生剤)とを、イエローライトを使用したラボで混合して光硬化性材料を用意する。材料を、0.2μmのフィルタによってフィルタし、洗浄済みの茶色の瓶に保存した。
トレンチウェハ上の光硬化性平坦化材料
20gのエポキシ(D.E.R.354LV,ダウ ケミカル カンパニー)と、80gのPGME(アルドリッチ)と、1.2gのSarcat KI−85(サートマーから入手可能な光酸発生剤)とを、イエローライトを使用したラボで混合して光硬化性材料を用意する。材料を、0.2μmのフィルタによってフィルタし、洗浄済みの茶色の瓶に保存した。
ビアウェハ上の熱硬化性平坦化材料
20gのエポキシ(D.E.R.354LV,ダウ ケミカル カンパニー)と、80gのPGME(アルドリッチ)と、1.0gのNACURE Super XC−A230 Catalyst(熱酸発生剤、キング インダストリーから入手可能)とを、イエローライトを使用したラボで混合して熱硬化性平坦化材料を用意する。材料を、0.2μmのフィルタによってフィルタし、洗浄済みの茶色の瓶に保存した。
Claims (35)
- (a) 表面を有し、前記表面に複数の凹凸形状の加工部を含む基板を提供する工程と、
(b) 前記表面上に平坦化層を形成する工程であって、前記平坦化層が、エポキシ、アクリレート、ビニルエーテル、ポリエステル、ポリイミド、ビニル含有化合物、およびそれらの混合物の、ポリマー、モノマー、オリゴマー、およびそれらの混合物からなる群から選択される化合物を含む工程と、
(c) 前記平坦化層と部材の平坦面とを1秒から120分の時間接触させて、前記平坦面の平坦性を前記平坦化層に転写し、前記接触の間または後に、前記平坦化層をキュアリングまたはハードニングする工程であって、平坦化され、キュアリングまたはハードニングされた平坦化層が0.1〜1μmの膜厚を有し、後続の層の塗布が可能な全体的に平坦な表面を有する工程と、
(d) 前記平坦化層の全体的に平坦な表面上に一つ以上の中間層を形成する任意の工程と、
(e) 超小型電子の前駆体を作製するためのイメージング層を、前記中間層がある場合は前記中間層上に、前記中間層が無い場合は前記平坦化層の全体的に平坦な表面上に形成する工程と、
(f) 前記イメージング層にパターンを形成する工程と、
(g) 前記中間層がある場合は前記中間層と前記平坦化層とに前記パターンを転写する前記パターンの転写工程とを含み、
前記パターンの転写工程後に、前記基板の表面が、元々の凹凸の少なくとも一部を保持することを特徴とする超小型電子の前駆体を形成する方法。 - さらに、前記平坦化層は、酸、酸発生剤、塩基、塩基発生剤、界面活性剤、光開始剤、熱開始剤、およびそれらの混合物からなる群から選択される成分を含む請求項1に記載の方法。
- 前記キュアリングまたはハードニングする工程は、前記平坦化層を実質的にキュアリングするために、前記平坦化層をUV光にさらす、請求項1に記載の方法。
- 前記キュアリングまたはハードニングする工程は、前記平坦化層を実質的にハードニングするために、前記平坦化層を加熱する、請求項1に記載の方法。
- 前記キュアリングまたはハードニング工程は前記平坦化層をそのTg以下に冷却する、請求項4に記載の方法。
- 前記加熱は、放射熱源を用いて前記平坦化層を加熱する、請求項4に記載の方法。
- 前記加熱は、赤外線加熱を使用して前記平坦化層を加熱する、請求項4に記載の方法。
- 工程(c)の前記接触が、大気圧下で行われる請求項1に記載の方法。
- 工程(c)の前記接触が、減圧下で行われる請求項1に記載の方法。
- 工程(c)の前記接触が、高圧で行われる請求項1に記載の方法。
- 工程(c)の前記接触が、人工的な雰囲気下で実行される請求項1に記載の方法。
- 前記接触工程が、1〜1,000psiの押圧力で行われる請求項1に記載の方法。
- 前記接触工程が、室温前後から350℃の温度で行われる請求項1または12に記載の方法。
- 1つ以上の中間層を含み、また、各々の中間層は全く金属を含まない請求項1に記載の方法。
- 前記イメージング層はフォトレジスト層を含み、
前記パターンの形成工程は、UV光で前記フォトレジスト層の一部を選択的に露光することを含み、
前記パターンの転写工程は、前記フォトレジスト層、前記中間層があれば当該中間層、および前記平坦化層を現像することを含む請求項1に記載の方法。 - 前記イメージング層はインプリント層を含み、
前記パターンの形成工程は、前記パターンの反転パターンを含む押圧面を有するネガと前記インプリント層とを接触させることを含み、
前記パターンの転写工程は、前記中間層があれば当該中間層と、前記平坦化層とを通して前記パターンをエッチングすることを含む請求項1に記載の方法。 - 前記パターンの形成工程は、イメージング層中にパターンをスタンピングして、スタンピングされたパターンを形成することを含み、
前記パターンの転写工程は、前記中間層があれば当該中間層と、前記平坦化層とを通して、前記パターンをエッチングすることを含む請求項1に記載の方法。 - さらに、前記超小型電子の前駆体に対して少なくとも工程(a)〜(g)のいくつかを繰り返す工程を含む請求項1に記載の方法。
- マスク層、バリア層、および反射防止層からなる群から選択される、少なくとも1つの中間層を含む請求項1に記載の方法。
- 工程(c)により、各々の基板の凹凸形状の加工部を全て覆う、250Å未満の凹凸形状を有する平坦化層を得る請求項1に記載の方法。
- 工程(c)により、少なくとも二つの異なる形状密度領域が存在する、10,000μmの基板表面の長さにわたって、600Å未満の凹凸形状を有する平坦化層を得る請求項1に記載の方法。
- 表面とおよび該表面上に複数の凹凸形状の加工部を有する基板と、
前記表面上にある全体的に平坦なキュアリングまたはハードニングされた平坦化層であって、部材の平坦面と1秒から120分の時間接触させて、前記平坦面の平坦性を転写して形成され、エポキシ、アクリレート、ビニルエーテル、ポリエステル、ポリイミド、ビニル含有化合物、およびそれらの混合物の、ポリマー、モノマー、オリゴマー、およびそれらの混合物からなる群から選択される化合物を含む構成物から形成され、0.1〜1μmの膜厚を有する平坦化層と、
前記平坦化層上に設けられる1つ以上の任意の中間層と、および
前記中間層がある場合には当該中間層上、または、前記中間層が無い場合には前記平坦化層上にあるイメージング層とを含む組合体。 - 前記基板が、シリコンウェハ、化合物半導体ウェハ、SOIウェハ、ガラス基板、石英基板、有機ポリマー基板、複合材料基板、誘電体基板、金属基板、合金基板、シリコンカーバイド基板、シリコンナイトライド基板、サファイア基板、セラミック基板、および、耐熱性材料で形成された基板からなる群より選択される請求項22に記載の組合体。
- 前記構成物が、さらに酸、酸発生剤、塩基、塩基発生剤、界面活性剤、光開始剤、熱開始剤、およびそれらの混合物からなる群から選択される成分を含む請求項22に記載の組合体。
- 少なくとも1つの中間層を有し、前記中間層がマスク層、バリア層、および反射防止層からなる群から選択される請求項22に記載の組合体。
- 前記イメージング層が、フォトレジスト層、インプリント層、およびスタンピングされた層からなる群から選択される請求項22に記載の組合体。
- 前記平坦化層が、10,000μmの距離にわたって10%未満の膜厚変化率を有する請求項22に記載の組合体。
- 前記平坦化層が、各々の基板の凹凸形状の加工部を全て覆う、250Å未満の凹凸形状を有する請求項22に記載の組合体。
- 前記平坦化層が、少なくとも二つの異なる形状密度領域が存在する、10,000μmの基板表面の長さにわたって、600Å未満の凹凸形状を有する請求項22に記載の組合体。
- (a) 表面を有し、前記表面上に複数の凹凸形状を含む基板を提供する工程と、
(b) 前記表面に平坦化層を形成する工程であって、前記平坦化層が、エポキシ、アクリレート、ビニルエーテル、ポリエステル、ポリイミド、ビニル含有化合物、および、それらの混合物の、ポリマー、モノマー、オリゴマー、およびそれらの混合物からなる群から選択される化合物を含む工程と、
(c) 前記平坦化層と部材の平坦面とを1秒から120分の時間接触させて、前記平坦面の平坦性を前記平坦化層に転写し、前記接触の間または後に、前記平坦化層をキュアリングまたはハードニングする工程であって、平坦化され、キュアリングまたはハードニングされた平坦化層が0.1〜1μmの膜厚を有し、後続の層の塗布が可能な全体的に平坦な表面を示す工程と、
(d) 1つ以上の実質的に金属を含まない中間層を前記平坦化層の全体的に平坦な表面上に形成する任意の工程と、
(e) 前記中間層がある場合には当該中間層の上に、前記中間層が無い場合には前記平坦化層の全体的に平坦な表面上に、超小型電子の前駆体を作製するためのイメージング層が設けられる工程と、
を含むことを特徴とする超小型電子の前駆体の製造方法。 - (a) 表面を有し、前記表面上に複数の凹凸形状を含む基板を提供する工程と、
(b) 前記表面に平坦化層を形成する工程であって、前記平坦化層が、エポキシ、アクリレート、ビニルエーテル、ポリエステル、ポリイミド、ビニル含有化合物、およびそれらの混合物の、ポリマー、モノマー、オリゴマー、およびそれらの混合物からなる群から選択される化合物を含む工程と、
(c) 前記平坦化層と部材の平坦面とを1秒から120分の時間接触させて、前記平坦面の平坦性を前記平坦化層に転写し、前記接触の間または後に、前記平坦化層をキュアリングまたはハードニングする工程であって、平坦化され、キュアリングまたはハードニングされた平坦化層が0.1〜1μmの膜厚を有し、後続の層の塗布が可能な全体的に平坦な表面を示す工程と、
(d) 1つ以上の中間層を前記平坦化層の全体的に平坦な表面上に形成する任意の工程と、
(e) 前記中間層がある場合には当該中間層の上に、前記中間層が無い場合には前記平坦化層の全体的に平坦な表面上に、超小型電子の前駆体を作製するためのイメージング層が設けられる工程と、
を含むことを特徴とする超小型電子の前駆体の製造方法。 - 表面と前記表面上に複数の凹凸形状とを有する超小型電子の基板と、
前記表面上に設けられ、全体的に平坦で、キュアリングまたはハードニングされた平坦化層であって、部材の平坦面と1秒から120分の時間接触させて、前記平坦面の平坦性を転写して形成され、エポキシ、アクリレート、ビニルエーテル、ポリエステル、ポリイミド、ビニル含有化合物、およびそれらの混合物の、ポリマー、モノマー、オリゴマー、およびそれらの混合物からなる群から選択される化合物を含む組成物から形成され、0.1〜1μmの膜厚を有する平坦化層と、
平坦化層上に設けられる、実質的に金属を含まない1つ以上の任意の中間層と、
前記中間層がある場合には前記中間層の上に、前記中間層が無い場合には前記平坦化層の上に設けられたイメージング層とを含むことを特徴とする組合体。 - 前記部材がオプティカルフラットを含む、請求項1に記載の方法。
- 前記部材がオプティカルフラットを含む、請求項30に記載の方法。
- 前記部材がオプティカルフラットを含む、請求項31に記載の方法。
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US7455955B2 (en) | 2008-11-25 |
JP2005532576A (ja) | 2005-10-27 |
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EP1485949A2 (en) | 2004-12-15 |
AU2003217804A8 (en) | 2003-09-09 |
WO2003073164A3 (en) | 2003-12-18 |
TW200405122A (en) | 2004-04-01 |
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