JP4913018B2 - Despreading circuit and electronic equipment - Google Patents

Description

  The present invention relates to a despreading circuit and an electronic device that receive a spectrum-spread signal and perform despreading on the receiving side.

  In recent years, high-speed downlink packet access (HSDPA), which is a high-speed packet communication standard extending W-CDMA (Wideband Code division Multiple Access), is used as a high-speed communication service for mobile phones, personal computers, and the like. Is being offered. In the service provided by HSDPA, the communication speed is defined as a different maximum speed corresponding to the service category, and further changes according to the communication environment.

  In HSDPA, a terminal receives packet data via a high speed physical downlink shared channel (HS-PDSCH). In general, in the CDMA system, one channel is encoded by one spreading code, that is, a channelization code, and decoded by this channelization code. However, in HS-PDSCH, data is divided into several parts. The divided data is encoded by a plurality of different channelization codes called multicodes. Since the data is divided and encoded, the number of data that can be simultaneously received by the terminal increases. As a result, the communication speed is improved.

  A fast Hadamard transform circuit (FHT: Fast Hadamard Transform) that performs an operation on received data and a Hadamard matrix is often used to perform a despreading process for the spreading process using the multicode. In the despreading process, it is considered that the channelization code matrix and the matrix calculation of the received signal are performed. The Hadamard matrix and the channelization code matrix coincide with the other matrix by exchanging the rows of one matrix. This is the reason why the FHT arithmetic circuit can be used as the despreading process.

  The FHT arithmetic circuit is efficient because it can simultaneously decode a plurality of spreading codes by multicode. Therefore, despreading processing is normally performed on the HS-PDSCH using the FHT arithmetic circuit.

  On the other hand, a primary common pilot channel (PCPICH: Primary Common Control Physical Channel) is simultaneously received as a pilot signal for receiving HS-PDSCH. Since this PCPICH has not been subjected to multi-code processing, a despreader that applies the channelization code of PCPICH is used for normal despreading processing without using an FHT circuit. Therefore, at present, independent despreading processing units are used for HS-PDCH and PCPICH. If different despreading processing units are provided in this way, the circuit scale increases, which is not desirable.

  In the CDMA communication system, it has been proposed to reduce the circuit scale from the prior art regardless of the increase / decrease in the number of multiplexed codes (see Patent Document 1), but this does not solve the above problem.

JP 2004-172650 A

  In view of the above problems, an object of the present invention is to provide a despreading circuit and an electronic device that can reduce circuit scale and current consumption.

  This deconversion circuit outputs a despread result that is the sum of all received data out of the output of the high-speed Hadamard transform circuit and the high-speed Hadamard transform circuit that outputs the despread result from the spread spectrum received data that is sequentially input. And the storage unit stores the despreading result added a predetermined number of times.

  The electronic apparatus includes an electronic receiver having a radio receiving unit that receives a spectrum spread signal, and the radio receiving unit outputs a despread result from sequentially input spread spectrum received data. And a despreading circuit that stores a despreading result that is the sum of all received data out of the output of the high-speed Hadamard transform circuit, and the despreading result is stored a predetermined number of times in the storage unit It is added and stored.

  An adder interposed between the high-speed Hadamard transform circuit and the storage unit; a selector connected to the output of the storage unit; and a feedback circuit that feeds back the output of the selector to the adder. The selector may output zero after outputting the despreading result stored in the storage unit a predetermined number of times.

  Further, the fast Hadamard transform circuit may be a fast Hadamard transform circuit corresponding to a spreading factor of 16, and the selector may output the despread result 16 times.

  Further, the result obtained by adding the despreading result, which is the sum of all the received data of the high-speed Hadamard transform circuit, 16 times is the despread result of the primary common pilot channel, and the other despreading results of the fast Hadamard transform circuit The output data may be the result of despreading of the high speed physical downlink shared channel.

  Thereby, it is possible to provide an inverse conversion circuit and an electronic device that can reduce the circuit scale and current consumption.

  Hereinafter, embodiments will be described with reference to the drawings, but before that, it will be described that HS-PDCH and PCPICH cannot be simply processed by one FHT circuit.

  FIG. 1 is a diagram illustrating a calculation procedure by an FHT circuit for HS-PDSCH (SF = 16) having a spreading factor (SF) of 16, which is assumed in the present embodiment. The FHT circuit is generally configured by combining a plurality of butterfly operation circuits. The number of stages required for the despreading process varies depending on the spreading factor. Since HS-PDSCH has a spreading factor (SF) of 16, the number of butterfly computation stages of the FHT circuit is four. As shown in FIG. 1, the FHT circuit for HS-PDSCH includes a reception stage 20 and a first stage 21 to a fourth stage 24. Thereby, the despreading results corresponding to all the channelization codes CC # 0 to CC # 15 appear in the fourth stage.

  The receiving stage 20 receives received data 0 to 15 divided by 16 chips from many pieces of chip data input in time series. Then, the butterfly calculation of the first stage 21 is performed as illustrated. The solid line in FIG. 1 indicates addition, and the broken line indicates subtraction. For example, the first-stage data 21-0 is obtained by adding the reception data 0 and the reception data 8. The first-stage data 21-15 is obtained by subtracting the reception data 15 from the reception data 7. The second-stage data 22-0 is obtained by adding the first-stage data 21-0 and 21-4. The third-stage data 23-0 includes the second-stage data 22-0 and 22-2. It is an addition. Finally, the fourth stage data 24-0 is calculated as the sum of the third stage data 23-0 and 23-1.

  For example, the first-stage data 21-7 is obtained by adding the reception data 7 and the reception data 15. The first-stage data 21-15 is obtained by subtracting the reception data 15 from the reception data 7. The second stage data 22-7 is obtained by subtracting 21-7 from the first stage data 21-2, and the third stage data 23-7 is obtained by subtracting 22-7 from the second stage data 22-5. Is. Finally, the fourth stage data 24-7 is calculated as the result of subtracting 23-7 from the third stage data 23-6. The fourth stage data 24-7 is a result of despreading corresponding to CC # 14. In this way, outputs appearing in the fourth stage of the FHT circuit are CC # 0, CC # 8, CC # 4, CC # 12, CC # 2, CC # 10, CC # 6, CC # in order from the upper stage of the figure. The output corresponds to # 14, CC # 1, CC # 9, CC # 5, CC # 13, CC # 3, CC # 11, CC # 7, and CC # 15.

  If PCPICPH is to be processed by the FHT circuit, since the spreading factor is 256, eight stages are required. FIG. 2 is a diagram showing the calculation procedure of the 8-stage FHT circuit as a reference. Despreading processing is performed by performing 8-stage butterfly computation based on 256 received data. As described above, two FHT circuits having different numbers of stages cannot be simply constituted by one FHT circuit.

  By the way, since the channelization code CC # 0 is assigned to the PCPICH, the despreading result of the PCPICH is output by the channelization code CC # 0 of the FHT circuit of SF = 256. In other words, the PCPICH despreading result is simply the sum of the data from 0 to 255. In the present embodiment, the despreading result of the channelization code CC # 0 does not include subtraction of data, and uses that all consist of addition. That is, when SF = 16, the result of despreading using channelization code CC # 0 is the sum of 16 data. Therefore, if the sum of 16 data is added 16 times, the sum of 256 data is obtained, and the PCPICH despread result is obtained.

となる。 Hereinafter, description will be made using mathematical expressions. As described above, in the FHT circuit with SF = 256, the output corresponding to the channelization code CC # 0 is the sum of 256 received data. If the received data is DT _n and the output corresponding to the channelization code CC # 0 from the FHT circuit with SF = 256 is FHT ₂₅₆ OUT _i ,

It becomes.

となる。 On the other hand, in the FHT circuit with SF = 16, the output corresponding to the channelization code CC # 0 is the sum of 16 received data. If the output corresponding to the channelization code CC # 0 from the FHT circuit with SF = 16 is FHT ₁₆ OUT _i ,

It becomes.

具体例としてｉ＝０のＦＨＴ₂₅₆ＯＵＴ₀を考えると、次ぎのようになる。

In the FHT circuit with SF = 16, 16 pieces of received data are sequentially input, and the calculation result is output. Therefore, when the output corresponding to the channelization code CC # 0 of the FHT circuit with SF = 16 is further added 16 times, the channelization code CC # 0 of the FHT circuit with SF = 256 is obtained as shown in the following equation (3). Corresponding output.

As a specific example, when FHT ₂₅₆ OUT ₀ with i = 0 is considered, it is as follows.

As described above, the output of FHT ₂₅₆ corresponding to channelization code CC # 0 is equal to the output of FHT ₁₆ corresponding to channelization code CC # 0 added 16 times.

  FIG. 3 is a diagram illustrating a despreading processing circuit for HS-PDCH and PCPICH according to the present embodiment. The despreading processing circuit 10 includes an FHT circuit 1 having a spreading factor 16 for outputting the HS-PDCH despreading results to the channelization codes CC # 1 to CC # 15. An adder 2 is connected to the output terminal 1-1 corresponding to the channelization code CC # 0 of the FHT circuit 1. The output from the FHT circuit 1 and the output of the selector 4 connected to the memory 3 are input to the memory 3 connected to the adder 2 through the feedback line 5.

  Here, the input from the FHT circuit 1 to the adder 2 is IN_fht, the input from the selector to the adder 2 is IN_sel, and the output of the adder 2 is OUT.

OUT = IN_fht + IN_sel
It becomes. When the output from the FHT circuit 1 is d (i) (i = 0 to 15), the first output from the adder is

OUT = d (0) + 0 = d (0)
It becomes. This OUT (= d (0)) is held in the memory 3 and becomes the next IN_sel, so the second output from the adder 2 is

OUT = d (1) + d (0) = d (0) + d (1)
It becomes. Since this OUT (= d (0) + d (1)) becomes the next IN_sel, the outputs from the adder 2 are sequentially added, and the 16th output is

OUT = d (0) + d (1) +... + D (14) + d (15)
It becomes. That is, 16 outputs are added to the output of the FHT circuit.

  Since the number of additions for obtaining the PCPICH despreading result is 16, it is necessary to reset and start a new addition when the 16 additions are completed. Accordingly, when 16 additions are completed, “0” is input from the other input of the selector 4, and the selector 4 selects to output 0 instead of the value held in the memory. The zero input to this selector can be performed based on a value obtained by counting 16 additions. As a result, IN_sel which is the output of the selector 4 becomes 0, and 16 new additions are started.

  In this manner, the value stored in the memory 3 is normally output from the selector 4, and the output despread by the channelization code CC # 0 via the line 5 is added to the memory 3 one after another. The Then, after adding 16 times, that is, adding 256 bits, “0” is input to the other input of the selector. As a result, 0 is input to the adding circuit 2, and the next 16 additions are started.

  In the embodiment, HS-PDSCH has been described as an example, but it can also be used for a signal obtained by spreading DPCH (Dedicated Physical Data Channel) with multicode. However, since DPCH has a variable spreading factor, it is necessary to deal with it separately. (For example, although not desirable in terms of circuit scale, an FHT circuit for each SF is prepared.)

  As described above, in the despreading circuit of this embodiment, a predetermined number of outputs corresponding to the channelization code CC # 0 of one FHT circuit are added, whereby HS-PDSCH and PCPICH are simply one FHT circuit. Thus, it is not necessary to provide a despreading circuit for each. As a result, a compact circuit configuration capable of reducing power consumption can be realized.

  The despreading circuit of this embodiment can be incorporated in a wireless reception unit of an electronic device including an information processing device such as a mobile phone, a PDA (Personal Digital Assistant), or a notebook personal computer. FIG. 4 shows an appearance of a mobile phone which is an example of an electronic device incorporating the despreading circuit of this embodiment. A cellular phone 10 as an example of the electronic apparatus shown in FIG. 4 is a foldable cellular phone including first and second cases 12 and 14 pivotally attached to each other. The first case 12 has a display unit 16 on the inner surface side. The second case 14 includes a push button 18 capable of inputting alphanumeric characters and other operation means. By incorporating the despreading circuit of this embodiment into such a mobile phone 10, a compact electronic device that can reduce power consumption can be realized.

It is a figure which shows the calculation procedure by the FHT circuit (SF = 16) used as the premise of this embodiment. It is a figure which shows the calculation procedure by a FHT circuit (SF = 256) for reference. It is a figure which shows the de-spreading circuit by this embodiment. It is a figure which shows an example of the electronic device which can incorporate the de-spreading circuit by this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 FHT circuit 2 Adder 3 Memory 4 Selector 5 Feedback line 10 Mobile phone 12 1st case 14 2nd case 16 Display part 18 Push button

Claims (6)

A high-speed Hadamard transform circuit that outputs a despreading result from sequentially input spread spectrum received data;
A storage unit for storing a despreading result of a predetermined channelization code, which is a sum of all received data among outputs of the high-speed Hadamard transform circuit;
An adder interposed between the high-speed Hadamard transform circuit and the storage unit;
A selector connected to the output of the storage unit;
A feedback circuit that feeds back the output of the selector to the adder,
When the selector outputs the despread result stored in the storage unit for the predetermined number of times, the selector then outputs zero to obtain the despread result of the pilot channel . The fast Hadamard transform circuit is a fast Hadamard transform circuit corresponding to a spreading factor of 16,
2. The despreading circuit according to claim 1, wherein the selector outputs zero after the despreading result is output 16 times.   The result obtained by adding the despreading result that is the sum of all the received data of the high-speed Hadamard transform circuit 16 times is the despread result of the primary common pilot channel (PCPICH), and the other despread results of the fast Hadamard transform circuit. The despreading circuit according to claim 2, wherein the spreading result is a despreading result of a high-speed physical downlink shared channel (HS-PDSCH). An electronic device having a wireless receiver for receiving a spread spectrum signal,
The wireless receiver is
A high-speed Hadamard transform circuit that outputs a despreading result from sequentially input spread spectrum received data;
A storage unit for storing a despreading result of a predetermined channelization code, which is a sum of all received data among outputs of the high-speed Hadamard transform circuit;
An adder interposed between the high-speed Hadamard transform circuit and the storage unit;
A selector connected to the output of the storage unit;
A feedback circuit that feeds back the output of the selector to the adder,
The electronic device is characterized in that after the despreading result stored in the storage unit is output the predetermined number of times, the selector outputs a despreading result of the pilot channel by outputting zero next . The fast Hadamard transform circuit is a fast Hadamard transform circuit corresponding to a spreading factor of 16,
5. The electronic device according to claim 4, wherein the selector outputs zero after outputting the despreading result 16 times.   The result obtained by adding the despreading result that is the sum of all the received data of the high-speed Hadamard transform circuit 16 times is the despread result of the primary common pilot channel (PCPICH), and the other despread results of the fast Hadamard transform circuit. 6. The electronic device according to claim 5, wherein the spreading result is a despreading result of a high-speed physical downlink shared channel (HS-PDSCH).

Images