EP2058952A1 - Despreading circuit and electronic apparatus - Google Patents
Despreading circuit and electronic apparatus Download PDFInfo
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- EP2058952A1 EP2058952A1 EP20080163575 EP08163575A EP2058952A1 EP 2058952 A1 EP2058952 A1 EP 2058952A1 EP 20080163575 EP20080163575 EP 20080163575 EP 08163575 A EP08163575 A EP 08163575A EP 2058952 A1 EP2058952 A1 EP 2058952A1
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- Prior art keywords
- despreading
- output
- circuit
- result
- hadamard transform
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/709—Correlator structure
- H04B1/7093—Matched filter type
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/709—Correlator structure
- H04B1/7093—Matched filter type
- H04B2001/70935—Matched filter type using a bank of matched fileters, e.g. Fast Hadamard Transform
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70701—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation featuring pilot assisted reception
Definitions
- the present invention relates to a despreading circuit that receives a spread-spectrum signal and despreads the received signal at the receiving end, and an electronic apparatus incorporating the same.
- High Speed Downlink Packet Access a high-speed packet communication standard developed as an extension of W-CDMA (Wideband Code Division Multiple Access)
- W-CDMA Wideband Code Division Multiple Access
- each terminal receives packet data via a High Speed Physical Downlink Shared Channel (HS-PDSCH).
- HS-PDSCH High Speed Physical Downlink Shared Channel
- one channel is coded by one spreading code, i.e., a channelization code, and is decoded by the same channelization code.
- HS-PDSCH data is split into a number of data. The split data are coded by a plurality of different channelization codes called multi-code. Since the data is split and coded for transmission, the number of data that can be simultaneously received at the terminal increases. This results in an improvement in communication speed.
- FHT Fast Hadamard Transform
- the FHT circuit is efficient because a plurality of multi-code spread data can be decoded simultaneously. Accordingly, for HS-PDSCH, despreading is usually performed by using an FHT circuit.
- a primary common pilot channel (PCPICH) is also received at the same time. Since the PCPICH is not multi-coded, despreading is usually performed by using a despreader that applies the channelization code of the PCPICH, and that does not use an FHT circuit. Therefore, at the current state of the art, independent despreaders are used for HS-PDCH and for PCPICH, respectively. Using different despreaders in this way is not desirable because the amount of circuitry increases.
- the despreading circuit comprises: a fast Hadamard transform circuit for outputting results of despreading of sequentially input spread-spectrum received data; and a storage unit for storing a result of despreading representing the sum of all the received data from among the results of despreading output from the fast Hadamard transform circuit, wherein the result of despreading is added up a predetermined number of times for storing in the storage unit.
- the electronic apparatus is an electronic apparatus having a radio receiving section for receiving a spread-spectrum signal, the radio receiving section having a despreading circuit comprising: a fast Hadamard transform circuit for outputting results of despreading of sequentially input spread-spectrum received data; and a storage unit for storing a result of despreading representing the sum of all the received data from among the results of despreading output from the fast Hadamard transform circuit, wherein the result of despreading is added up a predetermined number of times for storing in the storage unit.
- the despreading circuit may further comprise an adder interposed between the fast Hadamard transform circuit and the storage unit, a selector connected to an output of the storage unit, and a feedback circuit for feeding back an output of the selector to the adder; in this case, when the result of despreading stored in the storage unit has been output the predetermined number of times, the selector may subsequently output zero.
- the fast Hadamard transform circuit may be a fast Hadamard transform circuit that supports a spreading factor of 16; in this case, when the result of despreading has been output 16 times, the selector may subsequently output zero.
- the result of despreading output from the fast Hadamard transform circuit as representing the sum of all the received data may represent, when added up 16 times, the result of despreading of a primary common pilot channel, and the other results of despreading output from the fast Hadamard transform circuit may represent the results of despreading of a high speed physical downlink shared channel.
- the despreading circuit and the electronic apparatus thus configured can reduce the amount of circuitry while also reducing current consumption.
- the FHT circuit is constructed by combining a plurality of stages of butterfly computation circuits. The number of stages necessary for despreading differs depending on the spreading factor. Since the spreading factor (SF) of the HS-PDSCH is 16, four butterfly computation stages become necessary in the FHT circuit.
- the FHT circuit dedicated to HS-PDSCH comprises a receiving stage 20 and first to fourth stages 21 to 24. With this configuration, the results of despreading corresponding to all the channelization codes CC#0 to CC#15 are output at the fourth stage.
- first-stage data 21-0 is the result of the addition of the received data 0 and 8.
- first-stage data 21-15 is the result of the subtraction of the received data 15 from the received data 7.
- Second-stage data 22-0 is the result of the addition of the first-stage data 21-0 and 21-4
- third-stage data 23-0 is the result of the addition of the second-stage data 22-0 and 22-2.
- fourth-stage data 24-0 is calculated as the result of the addition of the third-stage data 23-0 and 23-1.
- first-stage data 21-7 is the result of the addition of the received data 7 and 15.
- first-stage data 21-15 is the result of the subtraction of the received data 15 from the received data 7.
- Second-stage data 22-7 is the result of the subtraction of the first-stage data 21-7 from the first-stage data 21-2
- third-stage data 23-7 is the result of the addition of the second-stage data 22-7 from the second-stage data 22-5.
- fourth-stage data 24-7 is calculated as the result of the subtraction of the third-stage data 23-7 from the third-stage data 23-6.
- the fourth-stage data 24-7 represents the result of despreading corresponding to CC#14.
- the outputs appearing at the fourth stage of the FHT correspond to CC#0, CC#8, CC#4, CC#12, CC#2, CC#10, CC#6, CC#14, CC#1, CC#9, CC#5, CC#13, CC#3, CC#11, CC#7, and CC#15 in this order from the top to the bottom of the figure.
- FIG. 2 is a diagram showing the computation procedure of the eight-stage FHT circuit for reference. Despreading is performed by performing eight stages of butterfly computations based on 256 received data. Such being the case, two FHT circuits with different stages cannot be simply implemented in a single FHT circuit.
- the result of despreading of the PCPICH is simply equal to the sum of the data 0 to 255.
- the output corresponding to the channelization code CC#0 is equal to the sum of the 16 received data.
- FHT 256 ⁇ OUT 0 DT 0 + DT 1 + ... DT 255
- FHT 16 ⁇ OUT 0 DT 0 + DT 1 + ... DT 15
- FHT 16 ⁇ OUT 1 DT 16 + DT 17 + ... DT 31
- FHT 16 ⁇ OUT 15 DT 240 + DT 241 + ... DT 255
- FHT 256 ⁇ OUT 0 FHT 16 ⁇ OUT 0 + FHT 16 ⁇ OUT 1 + ... + FHT 16 ⁇ OUT 15
- the output of FHT 256 corresponding to the channelization code CC#0 is equal to the result obtained by adding up the output of FHT 16 corresponding to the channelization code CC#0 16 times.
- FIG. 3 is a diagram showing a despreading circuit for HS-PDCH and PCPICH according to the present embodiment.
- the despreading circuit 10 comprises an FHT circuit 1 with a spreading factor of 16 which outputs the results of despreading of the HS-PDCH.
- An adder 2 is connected to the FHT circuit 1 at an output terminal 1-1 thereof corresponding to the channelization code CC#0.
- the adder 2 is connected to a memory 3 to which an output from the FHT circuit 1 and an output from a selector 4 connected to the memory 3 are input via a feedback line 5.
- the selector 4 usually outputs the value stored in the memory 3, and the result of the despreading by the channelization code CC#0 is successively input via the line 5 and added for input to the memory 3. Then, after completing the 16 additions, i.e., the addition of 256 bits, a 0 is applied to the other input of the selector. As a result, 0 is input to the adder 2, to start the next series of 16 additions.
- HS-PDSCH Dedicated Physical Data Channel
- the invention can also be applied to signals despread by multi-code for transmission on DPCH (Dedicated Physical Data Channel).
- DPCH Dedicated Physical Data Channel
- the despreader circuit must be adapted accordingly. For example, an FHT circuit must be provided for each SF, though it is not desirable from the standpoint of reducing the amount of circuitry.
- the output that the single FHT circuit produces for the channelization code CC#0 is added up a predetermined number of times, thereby making it possible to simply process HS-PDSCH and PCPICH by the same FHT circuit and thus eliminating the need to provide different despreader circuits for them.
- a circuit configuration can be achieved that is compact and that can reduce power consumption.
- the despreading circuit of the present embodiment can be incorporated into a radio receiver section of an electronic apparatus such as a portable telephone, a PDA (Personal Digital Assistant), a notebook computer, and other information processing apparatus.
- Figure 4 shows an external view of a portable telephone as an example of the electronic apparatus incorporating the despreading circuit of the present embodiment.
- the portable telephone 10 shown in Figure 4 as an example of the electronic apparatus is a folding type portable telephone comprising first and second cases 12 and 14 joined together so that one can be turned to open and close relative to the other.
- the first case 12 has a display unit 16 on its inside surface.
- the second case 14 has pushbuttons 18 and other operating means that can be used to enter alphanumeric characters, etc.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
- The present invention relates to a despreading circuit that receives a spread-spectrum signal and despreads the received signal at the receiving end, and an electronic apparatus incorporating the same.
- In recent years, communication services using High Speed Downlink Packet Access (HSDPA), a high-speed packet communication standard developed as an extension of W-CDMA (Wideband Code Division Multiple Access), have come to be provided as high-speed communication services for mobile telephones, personal computers, etc. In the services provided using HSDPA, different maximum communication speeds are defined for different service categories, and the communication speed changes according to the communication environment.
- In HSDPA, each terminal receives packet data via a High Speed Physical Downlink Shared Channel (HS-PDSCH). Generally, in CDMA systems, one channel is coded by one spreading code, i.e., a channelization code, and is decoded by the same channelization code. In HS-PDSCH, however, data is split into a number of data. The split data are coded by a plurality of different channelization codes called multi-code. Since the data is split and coded for transmission, the number of data that can be simultaneously received at the terminal increases. This results in an improvement in communication speed.
- For despreading of such multi-code spreading, use is often made of a Fast Hadamard Transform (FHT) circuit which performs computation between the received data and a Hadamard matrix. Despreading involves a matrix computation between a channelization code matrix and a received signal. The Hadamard matrix and the channelization code matrix coincide with each other if the rows of either one of the matrices are interchanged. This is the reason that the FHT circuit can be used for despreading.
- The FHT circuit is efficient because a plurality of multi-code spread data can be decoded simultaneously. Accordingly, for HS-PDSCH, despreading is usually performed by using an FHT circuit.
- On the other hand, as a pilot signal for receiving the HS-PDSCH, a primary common pilot channel (PCPICH) is also received at the same time. Since the PCPICH is not multi-coded, despreading is usually performed by using a despreader that applies the channelization code of the PCPICH, and that does not use an FHT circuit. Therefore, at the current state of the art, independent despreaders are used for HS-PDCH and for PCPICH, respectively. Using different despreaders in this way is not desirable because the amount of circuitry increases.
- While a technique for reducing the amount of circuitry compared with the prior art, regardless of the number of code multiplexed signals, is proposed for use in a CDMA communication system (refer to Japanese Unexamined Patent Publication No.
2004-172650 - In view of the above problem, it is an object of the present invention to provide a despreading circuit and an electronic appliance that can reduce the amount of circuitry while also reducing current consumption.
- The despreading circuit comprises: a fast Hadamard transform circuit for outputting results of despreading of sequentially input spread-spectrum received data; and a storage unit for storing a result of despreading representing the sum of all the received data from among the results of despreading output from the fast Hadamard transform circuit, wherein the result of despreading is added up a predetermined number of times for storing in the storage unit.
- The electronic apparatus is an electronic apparatus having a radio receiving section for receiving a spread-spectrum signal, the radio receiving section having a despreading circuit comprising: a fast Hadamard transform circuit for outputting results of despreading of sequentially input spread-spectrum received data; and a storage unit for storing a result of despreading representing the sum of all the received data from among the results of despreading output from the fast Hadamard transform circuit, wherein the result of despreading is added up a predetermined number of times for storing in the storage unit.
- The despreading circuit may further comprise an adder interposed between the fast Hadamard transform circuit and the storage unit, a selector connected to an output of the storage unit, and a feedback circuit for feeding back an output of the selector to the adder; in this case, when the result of despreading stored in the storage unit has been output the predetermined number of times, the selector may subsequently output zero.
- The fast Hadamard transform circuit may be a fast Hadamard transform circuit that supports a spreading factor of 16; in this case, when the result of despreading has been output 16 times, the selector may subsequently output zero.
- The result of despreading output from the fast Hadamard transform circuit as representing the sum of all the received data may represent, when added up 16 times, the result of despreading of a primary common pilot channel, and the other results of despreading output from the fast Hadamard transform circuit may represent the results of despreading of a high speed physical downlink shared channel.
- The despreading circuit and the electronic apparatus thus configured can reduce the amount of circuitry while also reducing current consumption.
-
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Figure 1 is a diagram showing a computation procedure performed by an FHT circuit (SF = 16) subsumed under the present embodiment. -
Figure 2 is a diagram showing for reference a computation procedure performed by an FHT circuit (SF = 256). -
Figure 3 is a diagram showing a despreading circuit according to the present embodiment. -
Figure 4 is a diagram showing one example of an electronic apparatus capable of incorporating the despreading circuit according to the present embodiment. - An embodiment will be described below with reference to drawings, but before that, an explanation will be given of the reason why HS-PDCH and PCPICH cannot be simply processed by a single FHT circuit.
-
Figure 1 is a diagram showing a computation procedure performed by an FHT circuit dedicated to HS-PDSCH whose spreading factor (SF) is 16 (SF = 16), as an example of the present embodiment. Generally, the FHT circuit is constructed by combining a plurality of stages of butterfly computation circuits. The number of stages necessary for despreading differs depending on the spreading factor. Since the spreading factor (SF) of the HS-PDSCH is 16, four butterfly computation stages become necessary in the FHT circuit. As shown inFigure 1 , the FHT circuit dedicated to HS-PDSCH comprises a receivingstage 20 and first tofourth stages 21 to 24. With this configuration, the results of despreading corresponding to all the channelizationcodes CC# 0 toCC# 15 are output at the fourth stage. - A large number of chip data being input in time series are divided at every 16 chips, and the resulting received
data 0 to 15 are input to the receivingstage 20. Then, butterfly computations at thefirst stage 21 are performed as shown infigure 1 . InFigure 1 , a solid line indicates an addition, while a dashed line indicates a subtraction. For example, first-stage data 21-0 is the result of the addition of the receiveddata data 15 from the receiveddata 7. Second-stage data 22-0 is the result of the addition of the first-stage data 21-0 and 21-4, and third-stage data 23-0 is the result of the addition of the second-stage data 22-0 and 22-2. Finally, fourth-stage data 24-0 is calculated as the result of the addition of the third-stage data 23-0 and 23-1. - For example, first-stage data 21-7 is the result of the addition of the received
data data 15 from the receiveddata 7. Second-stage data 22-7 is the result of the subtraction of the first-stage data 21-7 from the first-stage data 21-2, and third-stage data 23-7 is the result of the addition of the second-stage data 22-7 from the second-stage data 22-5. Finally, fourth-stage data 24-7 is calculated as the result of the subtraction of the third-stage data 23-7 from the third-stage data 23-6. The fourth-stage data 24-7 represents the result of despreading corresponding toCC# 14. In this way, the outputs appearing at the fourth stage of the FHT correspond toCC# 0,CC# 8,CC# 4,CC# 12,CC# 2,CC# 10,CC# 6,CC# 14,CC# 1,CC# 9,CC# 5,CC# 13,CC# 3,CC# 11,CC# 7, andCC# 15 in this order from the top to the bottom of the figure. - If PCPICPH is to be processed by an FHT circuit, eight stages become necessary since the spreading factor is 256.
Figure 2 is a diagram showing the computation procedure of the eight-stage FHT circuit for reference. Despreading is performed by performing eight stages of butterfly computations based on 256 received data. Such being the case, two FHT circuits with different stages cannot be simply implemented in a single FHT circuit. - Incidentally, since the channelization
code CC# 0 is assigned to the PCPICH, the output that the FHT circuit with SF = 256 produces for the channelizationcode CC# 0 provides the result of despreading of the PCPICH. In other words, the result of despreading of the PCPICH is simply equal to the sum of thedata 0 to 255. The present embodiment utilizes the fact that the result of despreading by the channelizationcode CC# 0 does not involve any data subtraction but wholly consists of additions. That is, in the case of SF = 16, the result of despreading by the channelizationcode CC# 0 will be given as the sum of the 16 data. Accordingly, if the sum of the 16 data is added up 16 times, the sum of 256 data will be obtained which represents the result of despreading of the PCPICH. - This will be explained using mathematical expressions. As described above, in the FHT circuit with SF = 256, the output corresponding to the channelization
code CC# 0 is equal to the sum of the 256 received data. Here, let DTn denote the received data and FHT256OUTi the output that the FHT circuit with SF = 256 produces for the channelizationcode CC# 0. Then -
- The received data are sequentially input, 16 data at a time, to the FHT circuit with SF = 16, which then outputs the results of the computations. Accordingly, if the output that the FHT circuit with SF = 16 produces for the channelization
code CC# 0 is successively added up 16 times, the result is the same as the output that the FHT circuit with SF = 256 produces for the channelizationcode CC# 0. -
- As shown above, the output of FHT256 corresponding to the channelization
code CC# 0 is equal to the result obtained by adding up the output of FHT16 corresponding to the channelizationcode CC# 0 16 times. -
Figure 3 is a diagram showing a despreading circuit for HS-PDCH and PCPICH according to the present embodiment. For the channelizationcodes CC# 1 toCC# 15, thedespreading circuit 10 comprises anFHT circuit 1 with a spreading factor of 16 which outputs the results of despreading of the HS-PDCH. Anadder 2 is connected to theFHT circuit 1 at an output terminal 1-1 thereof corresponding to the channelizationcode CC# 0. Theadder 2 is connected to amemory 3 to which an output from theFHT circuit 1 and an output from aselector 4 connected to thememory 3 are input via afeedback line 5. - Here, let IN_fht denote the input to the
adder 2 from theFHT circuit 1, IN_sel the input to theadder 2 from the selector, and OUT the output of theadder 2. ThenFHT circuit 1 is denoted by d(i) (i = 0 to 15), the first output from the adder is given asmemory 3 and provides the next IN_sel, the second output from theadder 2 is given asadder 2 is successively added, and finally, the 16th output is given asFHT circuit 16 times. - Since the number of additions required to obtain the result of despreading of the PCPICH is 16, when the 16th addition ends, a reset must be done before starting a new series of additions. For this purpose, when the 16th addition ends, a 0 is applied to the other input of the
selector 4 which, in response, selects 0 for output, not the value held in the memory. The application of the 0 to the selector can be effected based on the count value obtained by counting the 16 additions. Thereupon, the output of theselector 4, i.e., IN_sel, is reset to 0, and a new series of 16 additions is initiated. - In this way, the
selector 4 usually outputs the value stored in thememory 3, and the result of the despreading by the channelizationcode CC# 0 is successively input via theline 5 and added for input to thememory 3. Then, after completing the 16 additions, i.e., the addition of 256 bits, a 0 is applied to the other input of the selector. As a result, 0 is input to theadder 2, to start the next series of 16 additions. - The above embodiment has been described by taking HS-PDSCH as an example, but the invention can also be applied to signals despread by multi-code for transmission on DPCH (Dedicated Physical Data Channel). However, since the spreading factor of DPCH is variable, the despreader circuit must be adapted accordingly. For example, an FHT circuit must be provided for each SF, though it is not desirable from the standpoint of reducing the amount of circuitry.
- As described above, in the despreader circuit of the present embodiment, the output that the single FHT circuit produces for the channelization
code CC# 0 is added up a predetermined number of times, thereby making it possible to simply process HS-PDSCH and PCPICH by the same FHT circuit and thus eliminating the need to provide different despreader circuits for them. As a result, a circuit configuration can be achieved that is compact and that can reduce power consumption. - The despreading circuit of the present embodiment can be incorporated into a radio receiver section of an electronic apparatus such as a portable telephone, a PDA (Personal Digital Assistant), a notebook computer, and other information processing apparatus.
Figure 4 shows an external view of a portable telephone as an example of the electronic apparatus incorporating the despreading circuit of the present embodiment. Theportable telephone 10 shown inFigure 4 as an example of the electronic apparatus is a folding type portable telephone comprising first andsecond cases first case 12 has adisplay unit 16 on its inside surface. Thesecond case 14 haspushbuttons 18 and other operating means that can be used to enter alphanumeric characters, etc. By incorporating the despreading circuit of the present embodiment into such aportable telephone 10, an electronic apparatus can be achieved that is compact and that can reduce power consumption.
Claims (8)
- A despreading circuit comprising:a fast Hadamard transform circuit for outputting results of despreading of sequentially input spread-spectrum received data; anda storage unit for storing a result of despreading representing the sum of all the received data from among the results of despreading output from the fast Hadamard transform circuit, whereinthe result of despreading representing the sum of all the received data is added up a predetermined number of times for storing in the storage unit.
- A despreading circuit as claimed in claim 1, further comprising:an adder interposed between the fast Hadamard transform circuit and the storage unit;a selector connected to an output of the storage unit; anda feedback circuit for feeding back an output of the selector to the adder, whereinwhen the result of despreading stored in the storage unit has been output the predetermined number of times, the selector subsequently outputs zero.
- A despreading circuit as claimed in claim 2, wherein the fast Hadamard transform circuit is a fast Hadamard transform circuit that supports a spreading factor of 16, and
when the result of despreading has been output 16 times, the selector subsequently outputs zero. - A despreading circuit as claimed in claim 3, wherein the result of despreading output from the fast Hadamard transform circuit as representing the sum of all the received data represents, when added up 16 times, the result of despreading of a primary common pilot channel (PCPICH), and the other results of despreading output from the fast Hadamard transform circuit represents the results of despreading of a high speed physical downlink shared channel (HS-PDSCH).
- An electronic apparatus having a radio receiving section for receiving a spread-spectrum signal, the radio receiving section having a despreading circuit comprising:a fast Hadamard transform circuit for outputting results of despreading of sequentially input spread-spectrum received data; anda storage unit for storing a result of despreading representing the sum of all the received data from among the results of despreading output from the fast Hadamard transform circuit, whereinthe result of despreading is added up a predetermined number of times for storing in the storage unit.
- An electronic apparatus as claimed in claim 5, wherein the despreading circuit further comprises:an adder interposed between the fast Hadamard transform circuit and the storage unit;a selector connected to an output of the storage unit; anda feedback circuit for feeding back an output of the selector to the adder, and whereinwhen the result of despreading stored in the storage unit has been output the predetermined number of times, the selector subsequently outputs zero.
- An electronic apparatus as claimed in claim 6, wherein the fast Hadamard transform circuit is a fast Hadamard transform circuit that supports a spreading factor of 16, and
when the result of despreading has been output 16 times, the selector subsequently outputs zero. - An electronic apparatus as claimed in claim 7, wherein the result of despreading output from the fast Hadamard transform circuit as representing the sum of all the received data represents, when added up 16 times, the result of despreading of a primary common pilot channel (PCPICH), and the other results of despreading output from the fast Hadamard transform circuit represent the results of despreading of a high speed physical downlink shared channel (HS-PDSCH).
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JP2007293487A JP4913018B2 (en) | 2007-11-12 | 2007-11-12 | Despreading circuit and electronic equipment |
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JP3712156B2 (en) * | 1997-09-30 | 2005-11-02 | ソニー株式会社 | Pseudo-noise code synchronization acquisition apparatus and reception apparatus |
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JP2004172650A (en) | 2002-11-15 | 2004-06-17 | Mitsubishi Electric Corp | Communication apparatus for code division multiple access |
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US8565286B2 (en) | 2013-10-22 |
JP2009124257A (en) | 2009-06-04 |
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