JP4874588B2 - Storage device and host device - Google Patents

Description

  The present invention relates to a storage device and a host device (electronic device) using the storage device, and in particular, a non-volatile semiconductor storage device, a storage device such as a memory card using the non-volatile semiconductor storage device, and further mounting and using the storage device The present invention relates to an electronic device such as a recording device such as a digital still camera or a digital video camera. In addition, a storage device such as a USB (Universal Serial Bus) flash, and an electronic device such as a PC (Personal Computer) and a PDA (Personal Digital Assistant) are also included in the scope of the present invention.

  In recent years, memory cards equipped with a nonvolatile semiconductor memory have become widespread as storage devices that store various digital information typified by image data and music data. The data in the non-volatile semiconductor memory is not likely to be lost even when the power is turned off, and can be rewritten. As a non-volatile memory, a flash memory such as a NAND type is frequently used (for example, Japanese Patent Laid-Open No. 2003-30993 (Patent Document 1)).

  Recently, the storage capacity of flash memory has increased due to advances in semiconductor manufacturing technology, and flash memory in GB units has also appeared.

  By the way, when a storage device such as a memory card having a built-in flash memory is used in a host device, conventionally, the host device directly controls the flash memory in the storage device (for example, JP 2002-73409 A). Publication (Patent Document 2)). For this reason, the host device can grasp the program time of the flash memory, and from this, it is possible to predict the storage performance and the storable time to some extent.

  However, in recent years, storage devices often have a built-in controller, and the control method has become complicated, so that storage performance is no longer required for simple calculations. In addition, although the transfer speed parameter of the bus connecting the host device and the storage device is defined, this is not the actual speed at which the host device writes to the storage device, so it could not be a means for identifying the performance.

In addition, in order to obtain the performance of a storage device that stores a NAND flash ^TM memory or the like, it is necessary to perform a calculation in combination with a block processing method by a host device. For this reason, the performance could not be determined only on the storage device side.
Japanese Patent Laid-Open No. 2003-30993 JP 2002-73409 A

  Therefore, there is a demand for an electronic device, a performance prediction method, and a storage device having a simple method that can estimate the storage device performance to some extent even when a large-capacity storage device is controlled via a controller.

A storage device according to a first aspect of the present invention is provided with a semiconductor memory that stores data, a controller that instructs to write data to the semiconductor memory in response to a request from the outside, and a controller that is provided in the controller according to performance. And a register for holding performance parameter information related to the performance of the semiconductor memory and the controller, and in response to an instruction from the outside, A storage device configured to output information of one performance class to the outside, wherein the one performance class satisfies the minimum performance defined for each of the plurality of performance classes. indicates that is, the performance parameter information, the management unit area by the host apparatus using the storage device is used Comprises of come, the management unit area is comprised of a plurality of write unit, depending on the boundary in storage space of the semiconductor memory, the write unit is a unit used in the data write instruction from the outside, it It is characterized by.

A host device according to a second aspect of the present invention is a host device having a plurality of write modes having different bit rates and an application for transferring data to a storage device, wherein the storage device is the storage device maintains performance parameters related to the performance parameters include sexual performance class information, said has definite minimum bit rate of the storage device by the performance class information, the at least one write mode from said plurality of write modes, The bit rate of the selected write mode is selectable so as to be equal to or lower than the minimum bit rate of the storage device .

  According to the present invention, it is possible to provide a storage device and a host device having a simple method capable of estimating storage device performance to some extent even when a large-capacity storage device is controlled via a controller.

  Embodiments according to the present invention will be described below with reference to the drawings. These embodiments do not limit the present invention.

(First embodiment)
The first embodiment relates to a storage device incorporating a nonvolatile semiconductor memory device and a host device using the storage device.

[1] Configuration of Storage Device and Host Device A case where a NAND flash ^TM memory is used as an example of a nonvolatile semiconductor memory device built in a storage device used in the host device according to the first embodiment of the present invention will be described. To do.

FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device (semiconductor memory) when the semiconductor memory device according to the present embodiment is realized by a NAND flash ^TM memory.

  In FIG. 1, reference numeral 11 denotes a memory cell array. In the memory cell array 11, a plurality of word lines, selection gate lines, and bit lines are provided (not shown). A plurality of memory cells (not shown) are connected to the plurality of word lines and bit lines. The plurality of memory cells are divided into a plurality of blocks as will be described later.

  A data holding circuit 12 and a row decoder circuit 13 are connected to the memory cell array 11. The data holding circuit 12 includes a plurality of latch circuits. The row decoder circuit 13 selectively drives a plurality of word lines and select gate lines.

  The data holding circuit 12 temporarily holds data read via the bit line when reading data from the memory cell array 11, and temporarily holds write data when writing data to the memory cell array 11, and stores data via the bit line. Supply to the cell array 11.

  An input / output buffer (I / O buffer) 14 and a column decoder circuit 15 are connected to the data holding circuit 12. At the time of data reading, only the data selected according to the output of the column decoder circuit 15 out of the read data held by the data holding circuit 12 is read outside the semiconductor memory device via the input / output buffer 14. At the time of data writing, write data supplied from the outside of the semiconductor memory device via the input / output buffer 14 is held by a latch circuit in the data holding circuit 12 selected according to the output of the column decoder circuit 15.

  The row decoder circuit 13 selectively drives a word line and a select gate line in the memory cell array 11 at the time of reading and writing data so that one page of memory cells in the memory cell array 11 is simultaneously selected. To do.

  The address latch 16 latches an address input, supplies a row address to the row decoder circuit 13, and supplies a column address to the column decoder circuit 15.

  The command latch 17 receives a command input. A command decoder 18 is connected to the command latch 17. The command decoder 18 decodes the command and outputs various control signals. Based on the control signal output from the command decoder 18, the operations of the data holding circuit 12, the row decoder circuit 13, the input / output buffer 14, the column decoder circuit 15, the address latch 16, and the like are controlled.

For NAND flash ^TM memory, (not shown) connected to and the address latch and the command latch in the output buffer 14, address and command are supplied from the input-output pin of the NAND flash ^TM memory.

  This semiconductor memory device is provided with a high voltage / intermediate voltage generation circuit (not shown) in addition to the above-described circuits. The high voltage / intermediate voltage generation circuit generates a high voltage and an intermediate voltage supplied to the row decoder circuit 13 and the memory cell array 11 when data is written and erased.

FIG. 2 illustrates an example of a storage device incorporating the memory of FIG. 1 and an example of a host device using the storage device. The storage device 19 is a memory card, for example. As an example of this memory card, for example, an SD ^™ memory card can be considered. Details on the use of the SD ^™ memory card will be described later.

As shown in FIG. 2, the memory card includes a flash memory (a storage area 21 in the figure) and a device controller 22 for controlling the flash memory. The flash memory has the configuration shown in FIG.
The device controller 22 includes a version information register 23, a performance identification code register 24, and a performance parameter register 25. The version information register 23 holds version information, and the version information is used for identifying the version of the memory card. The performance identification code register 24 holds a performance identification code, and the performance identification code is used to identify a performance category (performance class). The performance parameter register 25 holds performance parameters (detailed later) of the storage device.

  When the storage device 19 is connected to the host device 20, the host device 20 controls the built-in host controller 26 by the built-in processor 28, and exchanges data with the storage device 19.

  When sending data from the host device 20, first, the data is temporarily stored in a built-in host buffer (buffer memory) 27, and then sent to the storage device 19 via the host controller 26. The host buffer 27 can absorb the performance variation due to the time of the storage device to some extent.

  The host buffer 27 may be realized by using a part of the system memory 29. By doing this, it is not necessary to have a special memory as the host buffer 27, and usually a large host buffer 27 is required, so it is efficient to secure it in the system memory 29.

  The host device 20 can write data with one multi-block write command (command for writing a plurality of consecutive blocks with one write command).

[2] Performance Definition of Card Standard In order for the host device 20 to know the performance of the storage device 19, the storage device 19 holds information on performance classes according to its own performance and various performance parameters. is doing. Hereinafter, the definition of the performance parameter will be described. Hereinafter, a memory card, particularly an SD ^™ memory card, will be described as an example of the storage device 19.

  It is assumed that the data transmission performance from the host device 20 to the storage device (memory card) 19 is the transmission speed on the control bus. Here, the control bus 30 corresponds to a thick arrow connecting the host controller 26 and the device controller 22 in FIG. Note that this transmission rate assumes that the host device 20 writes data in an optimum state.

[2-1] Definition of Performance Curve [2-1-1] Storage Area Division First, storage area division by the host device 20 and the storage device 19 necessary for explanation of the performance curve used for defining the performance class explain.

  The host device 20 divides the storage area 21 into units called 16 kB recording units (RU), for example, and writes moving image data and the like for each RU. That is, the RU (write unit area) corresponds to a unit written by one multi-block write command.

The RU may be considered to be the same as the cluster defined in the SD ^™ file system or an integer multiple thereof.

  The unit of RU is arbitrary, such as 32 kB, 64 kB, and 128 kB. As will be described later, the host device 20 can calculate the remaining recording time by counting the number of RUs capable of recording moving image data and the like.

  FIG. 3 shows an outline of the division of the storage area 21 when viewed from the host device 20 and an outline of the division of the storage area 21 actually performed by the memory card 19. The left side of FIG. 3 corresponds to the division of the storage area 21 assumed by the host device 20, and the right side of FIG. 3 corresponds to the actual division of the storage area 21 in the storage device 19.

As shown in FIG. 3, when viewed from the host device 20, the RU 32 is a storage unit, and the allocation unit (AU) 31 is defined as a set of a plurality of RUs 32. The AU (management unit area) is a management unit, and is defined as dividing all the storage areas 21 of the storage device 19 into AU dimensions _SAU .

  The relationship between the RU 32 and the AU 31 is similar to the relationship between the page 34 and the block 33 when the storage area 21 is viewed from the storage device 19 (device controller 22) side shown in FIG. The page 34 is an access unit when the device controller 22 writes to or reads from the storage area 21. The block 33 includes a plurality of pages 34 and is a unit when the device controller 22 erases the storage area 21.

For example when using the NAND flash ^TM memory TC58512FT Toshiba as a storage area 21, the size of the page 34 is 512B, the size of the block 33 is 16 kB (Note that ignores the capacity of the redundant portion for convenient ) Also, in addition to this, it is also possible that the page size to use 2kB, the NAND flash ^TM memory, such as 4kB.

Page 34 and RU 32 need not match, and RU 32 can be an integer multiple of page 34. Similarly, the AU dimension S _AU is an integral multiple of the RU dimension. The AU 31 can be an integer multiple of the block 33. In the following description, RU32 and AU31 will be described as basic units.

[2-1-2] Method for Determining Performance Curve For example, when the host device 20 sequentially enters data in units of RUs from location A to location B in the memory area 21, 4 will be described.

  As a typical example, the area from A to B corresponds to AU31. Consider a case where data is newly entered in the AU 31 including the used RU 31. As shown in FIG. 4, the logical address of this AU 31 is LA. When data is newly written to each RU 32 in the AU 31, the data of the RU (Used in the figure) 32 in which data has already been written (used) in the physical block PAA in which the data has been actually written. Must be copied to the RU 32 in another physical block PAB, and the data to be newly written must be written. After the completion of this work, the physical block PAB is newly associated with the logical address LA.

  When this operation is performed, the time for newly writing data in the RU 32 in which no data is initially written (Free in the figure) simply corresponds to the writing time. This time is defined as the write performance Pw.

  On the other hand, when copying already written data to another RU 32, it takes time to read data from the original RU 32 (eg, RU 32a) in addition to the time to write data to the RU 32 (eg, RU 32b) in the new physical block PAB. .

  Further, when there is a used RU 32 in the old physical block PAA, it is skipped and written into an empty RU (for example, RU marked with Data 3 in the figure). In addition, before writing new data, it is necessary to write to the RU 32 (for example, RU 32b) to which the data of the used RU 32 is moved. During the process of moving the data of the used RU, writing of new data is stopped. The time required for these is the data movement performance Pm. The total time required for new data entry is the total time of the total writing time and the total moving time.

  From the above description, the average performance P (Nu) is expressed as [Expression 1].

[Formula 1]
Average performance: P (Nu)
= [Sc × (Nt−Nu)] / [Sc × (Nt−Nu) / Pw + Sc × Nu / Pm]
= [(Nt−Nu) × Pm × Pw] / [(Nt−Nu) × Pm + Nu × Pw]
here,
Sc: RU size Nt: Total number of RUs sequentially written from A to B (number of RUs constituting AU)
Nu: Number of used RUs between A and B (number of used RUs in AU)
Pw: Write performance (MB / sec unit)
Pm: Movement performance (MB / sec unit)
It is.

  This equation assumes that the performance is determined by the write performance Pw and the movement performance Pm.

  The write performance Pw varies depending on the program time of the memory card 19 (flash memory (storage area 21)). The write performance Pw is defined as the average minimum value of performance when all RUs 32 in a certain AU 31 are unused and continuously written to all RUs 32 in the AU 31.

Note that the write performance varies depending on the processing time on the front end side. The front-end processing time depends on the SD clock frequency, taking an SD ^™ memory card as an example. This will be described below. FIG. 5 shows an example of the write operation timing when the multi-block write command is used. In the first stage of the write operation, the back end side waits until write data arrives from the front end side. In the second stage, both the back end side and the front end side operate. Therefore, it is necessary to consider the writing time for multi-block writing separately for the front end and the back end. In the second stage, the write time on the back end side is more dominant than that on the front end side.

The back-end write time t _WB is the total time from the start of writing to the flash memory (storage area 21) to the completion of all writing.

The other front-end processing time t _WF is the total time from the start of the multi-block write command to the start of writing to the flash memory. Further, as described above, when an SD ^™ memory card is taken as an example, the front-end processing time t _WF depends on the SD clock frequency. Therefore, the front end processing time t _WF can be expressed by the coefficient C _SD and the SD clock period f _SD . For this reason, in the SD ^™ memory card, t _WF can be expressed as [Equation 2].

[Formula 2]
Front-end processing time: t _WF = C _SD / f _SD
Further, considering the case of recording in one AU 31, the front end processing time t _WF is proportional to the number of write commands. The number of write commands is equivalent to the number NRU of _RUs 32 described above. As N _RU increases, that is, as the RU dimension S _RU decreases, the writing efficiency decreases.

  The movement performance Pm is defined as the average minimum value of the minimum movement performance. This can be calculated as the minimum value when moving consecutive RUs 32 to one complete AU 31. The time for the move operation is defined on the back end side and is not affected by the SD clock frequency. If the memory card 19 does not necessarily need to move the RU 32, the movement performance Pm may be considered infinite. This means “1 / Pm = 0”.

  Further, the movement performance Pm varies depending on the read time described later and the data movement method in addition to the program time of the flash memory. The data movement is processed inside the memory card 19 and is not directly controlled by the host device 20.

  The following two are defined for the read performance.

1) Read performance for data Read performance for data (may be referred to as read performance) Pr is defined as the lowest value of the average value of read performance when reading is performed in units of RU 32 at random. The average can be calculated by randomly reading RU32 units 256 times. The time required for ECC (Error Correcting Code) correction for each block 33 should be considered in the worst case. The read performance Pr needs to be greater than or at least equal to the write performance Pw.

2) File system (FAT) read time The read time T _FR (4 kB) of a file system such as FAT (file allocation table) is defined as the maximum time for reading a 4 kB FAT. This requires satisfying the condition that FAT reading is possible during writing. This is because in consideration of the case of real-time recording, the host device 20 has no choice but to perform FAT reading between RU writes. The ECC correction time for each block 33 should take into account the worst case. File System Dimensions (FR size) FAT read time with respect to S _FR by using a sealing function (CEIL function), it can be described as follows.

FAT read time for file system dimension S _FR [kB]: T _FR (S _FR )

  FIG. 6 shows the performance of the memory card 19 obtained according to [Formula 1]. FIG. 6 shows the performance when the number Nt of RUs 32 constituting the AU 31 is 16.

  As shown in FIG. 6, a performance curve is obtained by obtaining the performance (vertical axis) for each used RU ratio r (horizontal axis) and connecting the performance of each used RU ratio r. Performance curves are important information for host equipment manufacturers.

  The performance curve is defined by the writing performance Pw and the movement performance Pm. The write performance Pw is equivalent to the full performance when the used RU ratio r = 0.

Here, the used RU ratio r is obtained by using the number Nt of RUs 32 in the AU 31 and the number Nu of the used RUs 32.
r = Nu / Nt
Can be described.

this is,
Nu = r × Nt
Can also be described.

  The used RU ratio r is variable in the range of 0 to 1. r = 0 means that all RUs 32 are unused, and r = 1 means that all RUs 32 are used, that is, the performance is zero. In other words, P (1) = 0.

  This shows that any performance curve passes through the point (1, 0). When [Formula 1] is rewritten using r, [Formula 3] is obtained.

[Formula 3]
Average performance curve: P (r)
= [(1-r) * Pw * Pm] / [r * Pw + (1-r) * Pm]
However, 0 ≦ r ≦ 1. FIG. 6 is plotted using this equation.

[2-1-3] Storage Area Position and Performance Accuracy When the start address of the RU 32 to which data is written is not the boundary of the block 33 of the storage area 21, the data that has been written so that the write start position matches the boundary of the block 33 Need time to move. For this reason, in such a case, the actual performance is inferior to the expected performance. Therefore, in order to measure accurate performance, it is a requirement that the addresses A and B coincide with the boundary of the erase unit (block 33). This is why the allocation unit is defined.

[2-2] Parameters related to file system update during recording When the file system update is inserted into the write sequence, the overall (actually obtained) performance at the time of writing decreases. For this reason, when the host device 20 calculates the performance of the memory card 19 as will be described later, it requires parameters relating to the update of the file system. The host device 20 can use this parameter to calculate the actual performance degradation due to the file system update being inserted into the write sequence.

  FIG. 7 shows a typical sequence of file system updates during real-time recording. Hereinafter, a case where FAT is used as a typical example of a file system will be described as an example.

File system (FAT) updates can occur during writes to any RU 32. FAT updates are carried out periodically, the number of RU32 written between certain file system update and the next file system update is specified by file system update interval T _FU. The number of RUs 32 written during this file system update is Nd.

  The FAT write cycle consists of three write operations. FAT1 and FAT2 are FAT information writes to FAT1 and FAT2, respectively, using one multi-block write command. File system (FAT) writing can start from any byte address and can be defined as writing to any length up to 16 kB.

In the figure, DIR is a directory entry, which is generated prior to recording, and only the changed portion 512B of the directory entry is written. The file system write time T _FW is defined as the total time of the file system write cycle, that is, the total write time of the above FAT1, FAT2, and DIR. The file system write time T _FW varies depending on the specifications of the device controller 22.

[2-2-1] File system write measurement condition file system write time T _FW average time T _FW is defined as a value obtained by the average of several measurements. [Formula 4] is an expression that defines the average file system write time T _FW (ave.). As can be seen from [Formula 4], for example, the worst value of the average value of any eight file system write cycles is used as the average file system write time T _FW (ave.).

[Formula 4]
Average file system write time: (T _FW (ave.))
= [Max (T _FW (1) + T _FW (2) +... + T _FW (7) + T _FW (8))] / 8
[2-2-2] Maximum File System Write Time As described later, the host device 20 temporarily stores data by the host buffer 27 during the file system update. Therefore, when determining the size of the host buffer 27, it is necessary to consider the maximum file system update time. The request for the size of the host buffer 27 will be further described in [4-5].

[Formula 5] is an expression that defines the worst value of the file system (FAT) writing time.

[Formula 5]
Worst value of file system (FAT) writing time: (T _FW (max)) ≦ 750 [ms]
[2-2-3] Independent of data writing and file system writing File system writing can be inserted between any RUs or AUs during real-time recording. The device controller 22 needs to be able to control so that the file system writing does not affect the data writing performance Pw itself.

  In order to eliminate the influence of the file system write on the write performance Pw, for example, the write at the restart of the data write interrupted by the file system write is changed to the area following the physical area written last before the interruption. It can be realized by doing.

  In order to realize this, for example, a cache block for writing a file system is provided, and the device controller 22 can perform the following control. As shown in FIG. 8A, the storage area 21 includes a normal physical block area and a cache block. As shown in FIG. 8 (a), when a file system write request is received while sequential data is being sequentially written in a normal physical block, file management is performed as shown in FIG. 8 (b). Information is sequentially written in the free area (page 34) of the cache block. Thereafter, as shown in FIG. 8C, data writing is resumed from an area (page 34) subsequent to the last written area before the interruption.

  If the writing position when resuming data writing is a physical area that is not a continuation of the last written physical area (for example, an area in a new block (such as BLOCK2)) as in the prior art, moving writing occurs. The write performance Pw itself varies depending on the file system write.

  Note that selection between normal data and file management information can be realized, for example, by examining addresses, sizes, and sequences.

[3] Classification of Memory Cards In order to facilitate matching between the performance of the memory card 19 and the performance required by the host device 20, the memory card 19 has a plurality of classes (performance classes) according to the card performance. are categorized. Each class is classified according to performance parameters such as the performance curve and the file system writing time _TFW . The class information is held in the device controller as the performance identification code 24 of the memory card 19.

The memory card 19 displays its own class in a manner that can be recognized visually. FIG. 9 exemplifies a label indicating a class display. This figure illustrates the case where the storage device 19 is an SD ^™ memory card.

  For example, as shown in FIG. 9, the memory card 19 includes an outer enclosure 71 that covers at least a part of the storage area 21 and the device controller 22, and has a label 72 that displays a class on the outer enclosure 71.

  A class is also set in the host device 20. In this case, it means that the maximum performance can be obtained by using the memory card 19 of the same class. Even when a lower-class memory card 19 is used, the maximum performance cannot be obtained, but recording is possible. Although the host class display is not indispensable, FIG. 9 shows an example in which a label 74 for displaying a class is provided in the enclosure 73 of the host device 20.

[3-1] Request from Application The application of the host device 20 requires high performance from the memory card 19 used by the application. Typical examples are shown below.

(1) Digital video recording In MPEG2 and Motion JPEG, direct recording to the memory card 19 is required. In order to obtain standard television image quality and resolution, a card performance of about 2 MB / sec is required. For high-quality image recording, card performance of about 4 MB / sec is required.

(2) Digital Still Camera Having Continuous Shooting Function Digital still camera manufacturers need a high-performance memory card 19 to realize the continuous shooting function. The digital still camera maker can calculate the possible continuous shooting rate from the card performance and the control method of the host device 20 when clearly showing to the user.

[3-2] Classification FIG. 10 shows the relationship between the performance curve and the class. FIG. 10 shows three regions when divided by two performance curves. As shown in FIG. 10, in the performance curves of class 2 and class 4, the area composed of the vertical axis P (r) and the horizontal axis r is divided into three areas. Note that. The vertical axis P (r) indicates the performance, and the horizontal axis r indicates the used RU ratio.

  The conventional card belongs to the class 0 (Class 0 in the figure), the area closest to the origin among these three areas. This is the category with the worst performance in the figure.

  A class 1 performance curve means the minimum performance of a class 2 card. This curve is defined by two parameters Pw1 (intersection of class 2 performance curve and Y axis) and Pm1.

  Similarly, a class 4 performance curve means the minimum performance of a class 4 card. This curve is defined by two parameters Pw2 (intersection of the class 4 performance curve and the Y axis) and Pm2.

  If the application requirements are further increased, it will be necessary to define higher-level class 8 and class 10 performance curves, but the basic concept need not be changed. When a class 8 performance curve is defined, the performance is lower than that of the class 8 performance curve, the performance area above the class 6 performance curve becomes the class 6 area, and the performance area above the class 8 performance curve. Is the class 8 area.

  FIG. 11 shows an example of characteristics required for each class. Examples of performance parameters required for a class 2 (CLASS2) card, class 4 (CLASS4), class 6 (CLASS6), and card are as shown below and FIG.

CLASS2: Pw = 2 [MB / sec], Pm = 1 [MB / sec], Pr = 2 [MB / sec]
CLASS4: Pw = 4 [MB / sec], Pm = 2 [MB / sec], Pr = 4 [MB / sec]
CLASS6: Pw = 6 [MB / sec], Pm = 3 [MB / sec], Pr = 6 [MB / sec]
The average file system write time T _FW (ave.), The maximum file system write time T _FW (max), and the file system read time T _FR (4 kB) are the same for each class, for example, 100 [ms], 750 [ms] and 4 [ms].

  According to the example of FIG. 11, the performance curve of the class 2 card intersects with the Y axis at the point of 2 [MB / sec], intersects with the X axis at the point of 1, and becomes a curve according to the origin side in the middle. . In the area of performance beyond that curve, the first quadrant area up to the performance curve of a class 4 card, which will be described later, becomes the area of the class 2 card.

  Similarly, the performance curve of the class 4 card intersects with the Y axis at a point of 4 [MB / sec], intersects with the X axis at the point of 1, and exists in a region further away from the origin than the performance curve of the class 2 card. The area opposite to the origin of the performance curve of this class 4 card is the class 4 card area.

  Similarly, a class 6 performance curve that intersects the Y axis at a point of 6 [MB / sec] can be defined.

FIG. 12 shows an example of measurement conditions for the card requirement characteristics of each class illustrated in FIG. As described above, the write performance Pw is affected by the front end processing time t _WF and the RU dimension S _RU , and the front end processing time t _WF is affected by the SD clock frequency f _SD . The SD clock frequency f _SD and the RU dimension S _RU are set to the values shown in FIG. 12, and the required characteristics of each class are measured. In order to improve performance, it is desirable for the host to access with a large RU size.

[3-3] Relationship between Capacity and AU Maximum Size Another parameter is requested from the host device 20 in relation to the block size. By defining a register that sends out the AU dimension S _{AU according} to the physical standard of the memory card 19, the AU dimension S _AU most suitable for the memory card 19 can be clearly indicated to the host device 20. As a result, the host device 20 can use the AU 31 efficiently. As will be described later, the maximum size of the AU 31 defines the required size of the host buffer 27.

  An example of the maximum AU dimension corresponding to the capacity of the memory card 19 will be given.

Card capacity / maximum AU size = 16 to 128MB / 128kB, 256MB / 256kB, 512MB / 512kB, 1GB / 1MB, 2GB / 2MB, 4 to 32GB / 4MB
[3-4] Read Performance Request When the class 2, class 4, and class 6 cards are read in units of RU32, at least 2 [MB / sec], 4 [MB / sec], and 6 [MB / sec], respectively. Read performance is defined. However, this does not guarantee the read capability from the host device. This is because the above does not consider the environment of the host device.

[3-5] Requirements for Defining Physical Standards of Cards When standardizing the performance defined by the classes and various parameters described above, this performance standard needs to include the current standard and the future standard. In addition to these standards, future memory cards need to be included. For this reason, for example, in the current SD ^™ memory card, parameters such as the write performance Pw, the movement performance Pm, and the fill system write time T _FW need to be defined so as to meet the physical standards 1.01 and 1.10.

  A memory card 19 of a certain class (for example, a high class that will be defined in the future) has a certain physical standard (for example, physical class) due to restrictions on conditions (for example, SD clock frequency) necessary for defining this class. It cannot be manufactured according to standard 1.01). Such a class of memory cards 19 needs to be manufactured according to higher physical standards. For example, since a class 6 card requires a high speed mode, it cannot be manufactured according to the physical standard 1.01. The physical standard must be 1.10 or higher.

[3-6] Retention of data such as class and various parameters In the new standard, for example, class, AU dimension S _AU , movement performance Pm, coefficient C _SD can be retained in the register as status information of the memory card. More specifically, for example, the class is stored in the performance identification code register 24. The AU dimension S _AU , the movement performance Pm, and the coefficient C _SD are stored in the performance parameter register 25.

  As described above, the memory card 19 holds the class and various parameters, thereby enabling the host device 20 that can identify the class to calculate the performance more accurately and use the memory card 19 more efficiently. .

FIG. 13 shows an example of the bit width of the register information in the case of the SD ^™ memory card. In the case of the SD ^™ memory card, the AU dimension S _AU , the movement performance Pm, and the coefficient C _SD can be defined in, for example, the SD card status in the register. These data may be entered in a separately prepared register. For cards that do not support this performance standard, these fields may be set to zero. Such a memory card is recognized as a class 0 card.

  The class information can be defined in a conventional storage device where, for example, a fixed value is read (for example, 0). Thereby, a conventional device that is not compatible with the present embodiment can be identified as a class 0 card that is not subject to performance classification.

  The write performance Pw is determined for each class (the write performance required by the class is determined). For this reason, the host device 20 can know the write performance Pw by reading the class.

  Information in the performance identification code register 24 and the performance parameter register 25 can be output to the host device 20 when a predetermined command is received from the host device 20, for example.

  The values set in the performance identification code register 24 and the performance parameter register 25 can be values written in advance at the time of manufacture or can be determined when the memory card 19 itself is initialized.

In addition, since the current SD ^™ memory card does not have a means (dedicated register) for indicating a specific performance parameter, the performance code and the performance parameter are added to the reserved area of the programmable register so that the host Can see the performance of the card. As a result, the current card controller can be used without being changed.

[4] Operation sequence and requirements of host device when performing real-time recording [4-1] Operation sequence of host device when performing real-time recording The host device 20 when performing real-time recording includes the above performance curve, class, Writing can be performed while performing calculation according to the sequence described below using various parameters. The host device 20 preferably takes the sequence described below during real-time recording.

(1) A performance (hereinafter referred to as application performance) Pa requested from an application installed in the host device 20 is determined.

(2) Select an appropriate number Nd of write RUs between file system updates.

(3) The card performance Pc necessary for realizing the application performance Pa is determined in consideration of the file system update.

(4) The maximum used RU ratio r (Pc) is determined.

(5) Each AU 31 is divided into AU _fast and AU _slow .

(6) The recordable time T _rec is estimated.

(7) Adjust the number of write RUs Nd between file system updates. If the number Nd of write RUs between file system updates is large, the performance is improved.

(8) If sufficient performance and sufficient recordable time are not obtained as a result of the calculation, the card needs to be erased.

  Hereinafter, a specific method for performing the operations (1) to (8) and requirements of the host device 20 will be described.

[4-2] Performance Calculation Method Associated with File System Update A typical file system (FAT) update cycle sequence during real-time recording is as shown in FIG. The host device 20 desirably takes this sequence when updating the file system.

[4-2-1] Card Performance Condition Considering File System Update The host device 20 determines the card performance Pc necessary to satisfy Pa from the application performance Pa and the average file system write time _TFW . As described above, the insertion of the file system write sequence reduces the overall performance during writing. Therefore, the host device 20 generally requires a card having a card performance Pc higher than the application performance Pa.

  Depending on the type of application, some host devices 20 may support several different bit rate modes. In this case, the host device 20 determines the application performance Pa according to the mode selected by the user.

  It is desirable that the host device 20 does not reject the memory card 19 that does not match the application performance Pa, but matches the performance of the host device 20 according to the class of the memory card 19.

  For example, when the card performance of a certain memory card 19 is insufficient with respect to the application performance Pa, the host device 20 desirably switches to a mode that requires a smaller application performance Pa. For example, the host device 20 can adapt to a lower application performance Pa by increasing the data compression rate, decreasing the image resolution, or decreasing the frame rate. In order to realize this method, the host device 20 desirably has several types of write modes in order to make it possible to use the memory card 19 having low performance.

  In addition, since the host device 20 has a plurality of modes having different recording performances, it is possible to perform recording by setting a slower mode even when an abnormal situation occurs. This is because, for example, in the case of a class 0 card, the host device 20 does not know the card performance, so if it does not actually try in a certain mode, it does not know whether that mode operates.

  Card performance (hereinafter referred to as card performance) Pc necessary to satisfy the application performances Pa and Pa is shown in [Formula 6] and [Formula 7], respectively.

[Formula 6]
Performance required by application: Pa
= (Sc × Nd) / (Sc × Nd / Pc + T _FW )
[Formula 7]
Card performance required to satisfy Pa: Pc
= (Sc × Nd × Pa) / (Sc × Nd−Pa × T _FW )
The card performance Pc varies depending on the number of write RUs Nd between file system updates. As can be seen from FIG. 7, the number of write RUs Nd between file system updates varies depending on the frequency of file system updates. Therefore, the card performance Pc is affected by the frequency of updating the file system. The method of determining the frequency of updating the file system will be described in [4-2-2] below.

[4-2-2] Conditions for file system update period In the file system (FAT) update period (period from the file system update to the next file system update), a file system write sequence is inserted between each data transfer. Determined by. Therefore, the file system update period depends on the writing speed, but the accuracy of the period is not important. A simple method may be adopted so that the host device 20 can easily calculate the file system update period.

  A formula for calculating the file system update period is shown in [Formula 8].

[Formula 8]
File system update period: T _PF
= Sc x Nd / Pa
= Sc × Nd / Pc + T _FW (ave.)
The host device 20 may adjust the number of RUs Nd written during the file system update to an appropriate value in consideration of the degree of card performance degradation due to file system writing. However, the file system update period _TPF is preferably 1 second or longer.

  When a larger RU number Nd is selected, the card performance Pc approaches the application performance Pa. As a result, the low performance memory card 19 can satisfy the application performance Pa.

As another method of determining the file system update period, the file system update interval T _FU (equivalent to T _PF ) can be determined using the timer of the host device 20. In this case, T _FU is constant. File system updates are inserted during RU writes. For this reason, the number of write RUs Nd between file system updates varies depending on the file system update interval _TFU .

In this case, the amount of data during the file system update interval _TFU is represented by [Formula 9].

[Formula 9]
Data volume during _TFU : Pa x _TFU
= Pc × (T _FU −T _FW (ave.))
By modifying [Formula 9], the card performance Pc is expressed as [Formula 10].

[Formula 10]
Card performance to satisfy Pa: Pc
= (Pa × T _FU ) / (T _FU −T _FW (ave.))
[4-3] Classification of allocation unit (AU) The host device 20 determines which AU 31 can be used for real-time recording. That is, it is determined whether each AU 31 satisfies the obtained card performance Pc. As can be seen from FIG. 6, the performance of each AU 31 varies depending on the used RU ratio r. Therefore, each AU 31 is determined using the used RU ratio r as a threshold value.

[4-3-1] Maximum Used RU Ratio As shown in FIG. 4, assuming that the write start position A and the end position B coincide with the boundary of the AU 31, respectively, the performance of the AU 31 according to [Formula 3]. Can be calculated.

  The maximum used RU ratio r (Pc) can be derived from the card performance Pc. That is, the maximum used RU ratio r (Pc) is obtained as an inverse function of [Formula 3].

An AU 31 having a used RU ratio r equal to or less than the maximum used RU ratio r (Pc) is an AU that satisfies the card performance Pc. As the used RU ratio r is smaller, the AU is more suitable for real-time recording. As described later, the AU 31 is classified into AU _fast and AU _slow with the maximum used RU ratio r (Pc) as a boundary.

[Formula 11] shows a formula for calculating the maximum used RU ratio r (Pc).

[Formula 11]
Maximum used RU ratio: r (Pc)
= [(Pw−Pc) × Pm] / [(Pw−Pm) × Pc + Pw × Pm]
[4-3-2] Classification of AU into two categories The host device 20 classifies the AU 31 into two categories. One is AU _fast (adaptation management unit area), which has a speed that can sufficiently cope with real-time recording with the card performance Pc. The other is AU _slow (unsuitable management unit area), which is not suitable for real-time recording because the memory area is too fragmented.

The host device 20 counts the number of used RUs Nu for each AU 31, and calculates the used RU ratio r from the number of used RUs Nu. Whether AU _fast or AU _slow can be determined by [Equation 12].

[Formula 12]
If Nu / Nt <r (Pc), AU is AU _fast
If Nu / Nt ≧ r (Pc), AU is AU _slow
That is, when (used Ru number Nu) / (total RU number Nt in AU) is less than the maximum used RU ratio r (Pc), the AU is classified as AU _fast , and the maximum used RU ratio r (Pc) In the above case, it is classified as AU _slow .

FIG. 14 shows allocation of AUs 31 in the storage area 21, and shows an example of distribution in the two types of storage areas 21 of the AU 31 described above. Since the first AU 31 includes a file system, it is an area that is not suitable for real-time recording, and is assigned to AU _slow . The directory entry must not be created in the same AU 31 as the AU 31 that records data.

Although AU1 and AU4 do not include a file system, they are fragmented because (used Ru number Nu) / (total RU number Nt in AU) is equal to or greater than the maximum used RU ratio r (Pc). _Is classified as AU _slow .

[4-4] Recordable Time The host device 20 can calculate the time during which real-time recording is possible using [Formula 13]. In [Formula 13], Nr is the number Nr of writable RUs 32 in all AUs 31 determined to be AU _fast . When the sufficient recordable time cannot be prepared, the host device 20 needs to instruct the user to move the recorded data to another location or to reformat the memory card 19, for example.

[Formula 13]
Recordable time: T _REC
= Sc x Nr / Pa
Alternatively, when the host device 20 increases the number of write RUs Nd during file system update, that is, when the file system update period _TPF is increased, the host device 20 calculates the recording time again. This is because the performance is improved by increasing the number Nd of write RUs between file system updates. That is, the value of the maximum used RU ratio r (Pc) increases, and the number of AU _fasts increases, so the recording time increases.

[4-5] Requirements Necessary for Buffer of Host Device The host buffer 27 needs to have a sufficient size for temporarily storing data. The host buffer 27 is required to satisfy the following requirements.

[4-5-1] Dimensional Requirements for Host Device Buffer The host buffer 27 needs to have a size that satisfies the following requirements.

(1) Request according to file system (FAT) update When the host device 20 updates the file system, the host buffer 27 is used to temporarily store data to be originally written during the file system writing. For this reason, a large buffer size is required. It is defined as the worst value T _FW (max) of the above file system write time. The worst value T _FW (max) of the file system write time is, for example, 750 [ms] as shown in [Formula 5]. Note that the size of the buffer is generally described in terms of recording time as an area in which recording data for a predetermined time can be stored.

(2) Request according to error (error) correction The host buffer 27 is also used to compensate for a delay in correcting an error in write data. When a writing error occurs, the memory card 19 does not return a CRC status or displays an error and stops multi-block writing. The host buffer 27 needs to hold data until the writing is completed so that rewriting can be performed when an error occurs.

In order to allow the host device 20 to continue real-time recording even if an error occurs, the host buffer 27 needs to have a size of, for example, 250 [ms]. This corresponds to the fact that 250 [ms] is defined as the maximum value of the write completion time of the memory card 19. Therefore, it is necessary to have a size combined with the time required for the worst value T _FW (max) of the file system writing time. When the worst value T _FW (max) of the file system writing time is, for example, 750 [ms], a buffer for storing data for 1 [s] is required.

(3) Request according to AU write delay compensation When there is a written RU 32 in the AU 31 including when the used RU 32 gathers at the top of the AU 31, the data stored in the used RU 32 is another RU 32. The write data cannot be written unless it is moved to. Therefore, the write data must be stored in the host buffer 27 while moving the written RU 32.

  FIG. 15 shows the concept of the host buffer 27. As shown in FIG. 15, it is assumed that data is continuously input from the host device 20 to the host buffer 27 at a constant rate Pa. Further, it is assumed that the host device 20 reads data stored in the host buffer 27 and writes it in the AU 31.

  On the other hand, the rate of data output from the host buffer 27 depends on the fragmentation state of the AU 31. That is, as described above, when there is a written RU 32 in the AU 31, the write data is held in the host buffer 27 and is not output. When there is no written RU 32 in the AU 31 or when the movement of the RU 32 is completed, the host buffer 27 outputs data at the rate Pw.

  From the above, the necessary size of the host buffer 27 is obtained from the time when all the used RUs 32 in the AU 31 are moved.

Note that when the size of the host buffer 27 becomes insufficient, the host buffer 27 may overflow (buffer shortage) depending on the data fragmentation state in the AU _fast . For this reason, further examination may be required depending on the size of the host buffer 27 and the AU _fast fragmentation state.

(4) Preparation of write data It takes a certain amount of time for the host device 20 to prepare the write data, and the generation of the write data becomes discrete. This data can be written once from the host controller 26 via the host buffer 27. By doing so, since transfer can be performed without a free time, efficient transfer becomes possible.

  In particular, in the case of real-time recording, the real-time data preparation (calculation) time can be made invisible by temporarily storing the real-time data in the host buffer 27 as a FIFO and then writing it in the memory card 19. That is, data can be efficiently recorded on the memory card 19.

  In addition, when calculating in the system memory and writing the data directly to the memory card 19, the processing is sequential. For this reason, it is necessary to calculate and write data alternately. If the calculation and writing of data are alternately performed, nothing is written in the memory card 19 during data calculation, and it becomes a wasteful time. Therefore, only a lower performance than the class indicated by the memory card 19 can be obtained.

The necessary buffer size can be described as a function of application performance Pa, movement performance Pm, maximum used RU ratio r (Pc), and AU dimension S _AU .

[Equation 14] shows the buffer size S _BUF required. However, the first term (Pa) on the right side of this equation corresponds to the description of (1) and (2) above, and the second term on the right side corresponds to the description of (3) above. The above (4) is not included in [Formula 14]. Further, depending on the standard of the host device 20, an additional buffer is required.

[Formula 14]
Required buffer size: S _BUF > Pa + [r (Pc) × S _AU × Pa] / Pm
If the application performance Pa is smaller than the movement performance Pm and the host buffer 27 has a sufficient size exceeding Pa + _SAU , [Equation 14] is always satisfied.

[4-5-2] Handling when the host buffer size is small The following is a method of finding an AU _fast with a small degree of fragmentation when the size of the host buffer 27 is insufficient, independent of the above discussion. Is described. However, it is preferable that the host buffer 27 has a sufficient size rather than the method described here.

FIG. 16 shows a case where all the used RUs 32 are accumulated on the AU 31. The maximum used RU ratio r (Pc) indicates a place where the used RU 32c and the unused RU 32d are divided. When the host device 20 writes data to the first unused RU 32d, the memory card 19 gives a long busy until the movement of all the used RUs 32c is completed. During this time, write data is stored in the host buffer 27. At this time, the time required to move all the used RUs 32c in the _AU 31 is (r (Pc) × S _AU ) / Pm. Therefore, the size required for the host buffer 27 is shown in [Formula 15].

[Formula 15]
Host buffer size: S _BUF > Pa × [(r (Pc) × S _AU ) / Pm]
From [Formula 15], [Formula 16] is obtained.

[Formula 16]
Used RU ratio limited by the host buffer size = r (Pc) <[(Pm × S _BUF ) / (Pa × S _AU )]
As can be seen from [Equation 16], when the size of the host buffer 27 is small, the maximum used RU ratio r (Pc) is limited by the size of the host buffer 27. In this case, it is necessary to classify the AU 31 using the maximum used RU ratio r (Pc) limited by the size of the host buffer 27 as r (Pc) in [Equation 12].

  If the size of the host buffer 27 is small, the size of the data stored in the host buffer 27 during real-time data recording is observed, and the bit rate of the data is controlled to be temporarily reduced according to the result. Buffer overflow can be avoided in advance by controlling the update interval of the file system. Since it is problematic that the host buffer 27 overflows and data is lost, it is necessary to prevent data loss even if the data quality is degraded.

  When recording is performed with the write performance predicted based on the performance information (performance parameter) of the storage device 19, the host device 20 can store the storage device when an error occurs frequently during the occurrence of buffer overflow or access to the storage device 19. It is possible to switch to a lower speed mode than the speed based on the 19 performance information.

[4-6] Others The host device 20 can have means for comparing the performance information (information such as class and performance parameters) of the memory card 19 with its own performance information (information such as class and performance parameters). .

  The host device 20 includes comparison means for comparing the performance information read from the memory card 19 with its own performance information. This is because, in the relationship between the memory card 19 and the host device 20, no matter how high the performance of one is, the performance of the other does not match that, the data transfer between the host device 20 and the memory card 19 is After all, it is limited by the slower performance.

  If a lower class memory card 19 is used, the performance expected by the user may not be obtained. Therefore, the host device 20 compares the performance information read from the memory card 19 with its own performance information, and notifies the user of the result by screen display or the like.

  For example, after the memory card 19 is inserted into the host device 20, “This device is class M, but the class of the inserted memory card is N (N <M). Is displayed on the screen. As a result, the user can grasp why the expected operation speed cannot be obtained even though the class N memory card is used. This screen display may be automatically performed after the memory card 19 is inserted into the host device 20, or may be displayed on the screen when the user performs a predetermined operation. .

  The performance information comparison function described here is not an essential function for the host device 20 that uses the memory card 19 storing the performance information.

(Second Embodiment)
Next, an SD ^™ memory card to which the first embodiment can be applied will be described in detail.

FIG. 17 is a schematic diagram showing the configuration of the SD ^™ memory card of the second embodiment. An SD ^™ memory card (hereinafter simply referred to as a memory card) 41 exchanges information with the host device 20 via the bus interface 45. The memory card 41 includes a NAND flash ^TM memory (hereinafter simply referred to as a flash memory) chip 42, a card controller 43 that controls the flash memory chip 42, and a plurality of signal pins (first to ninth pins) 44. I have. 45 is a bus interface.

  The card controller 43 corresponds to the device controller 22 of the first embodiment (FIG. 2). The flash memory 42 corresponds to the storage area 21 in FIG.

  The plurality of signal pins 44 are electrically connected to the card controller 43. The assignment of signals to the first to ninth pins in the plurality of signal pins 44 is, for example, as shown in FIG.

  Data 0 to data 3 are assigned to the seventh pin, the eighth pin, the ninth pin, and the first pin, respectively. The first pin is also assigned to the card detection signal. Further, the second pin is assigned to the command, the third and sixth pins are assigned to the ground potential Vss, the fourth pin is assigned to the power supply potential Vdd, and the fifth pin is assigned to the clock signal.

  The memory card 41 is formed so that it can be inserted into and removed from a slot provided in the host device 20. A host controller 26 (not shown) provided in the host device 20 communicates various signals and data with the card controller 43 in the memory card 41 via these first to ninth pins. For example, when data is written to the memory card 41, the host controller 26 sends a write command as a serial signal to the card controller 43 via the second pin. At this time, the card controller 43 captures the write command given to the second pin in response to the clock signal supplied to the fifth pin.

  Here, as described above, the write command is serially input to the card controller 43 using only the second pin. As shown in FIG. 18, the second pin assigned to command input is arranged between the first pin for data 3 and the third pin for ground potential Vss. The plurality of signal pins 44 and the bus interface 45 corresponding thereto are used for communication between the host controller 26 in the host device 20 and the memory card 41.

On the other hand, communication between the flash memory 42 and the card controller 43 is performed by an interface for NAND flash ^TM memory. Therefore, although not shown here, the flash memory 42 and the card controller 43 are connected by an 8-bit input / output (I / O) line.

For example, when the card controller 43 writes data to the flash memory 42, the card controller 43 sends a data input command 80H, a column address, a page address, data, and a program command 10H via these I / O lines to the flash memory. 42 are sequentially input. Here, “H” in the command 80H indicates a hexadecimal number, and an 8-bit signal “10000000” is actually supplied in parallel to the 8-bit I / O line. That is, in the interface for the NAND flash ^TM memory, multi-bit command is supplied in parallel.

Further, the interface for NAND flash ^TM memory, commands and data to the flash memory 42 are communicated the same I / O lines. As described above, the interface in which the host controller 26 in the host device 20 and the memory card 41 communicate is different from the interface in which the flash memory 42 and the card controller 43 communicate.

  FIG. 19 is a block diagram illustrating a hardware configuration of the memory card according to the second embodiment.

  The host device 20 includes hardware and software for accessing the memory card 41 connected via the bus interface 45. The memory card 41 operates upon receiving power supply when connected to the host device 20, and performs processing in accordance with access from the host device 20.

  As described above, the memory card 41 includes the flash memory 42 and the card controller 43. In the flash memory 42, the erase block size (block size of erase unit) at the time of erasing is set to a predetermined size (for example, 256 kB). Data is written to and read from the flash memory 42 in units called pages (for example, 2 kB).

  The card controller 43 manages the internal physical state of the flash memory 42 (for example, what physical block address includes what logical sector address data or which block is in the erased state). . The card controller 43 includes a host interface module 53, an MPU (Micro Processing Unit) 54, a flash controller 55, a ROM (Read-only memory) 56, a RAM (Random access memory) 57, and a buffer 58.

  The host interface module 53 performs an interface process between the card controller 43 and the host device 20 and includes a register unit 59. FIG. 20 shows a detailed configuration of the register unit 59. The register unit 59 includes a card status register and various registers such as CID, RCA, DSR, CSD, SCR, and OCR.

  These registers are defined as follows: The card status register is used in normal operation, and stores, for example, error information described later. CID, RCA, DSR, CSD, SCR, and OCR are mainly used when the memory card is initialized.

  In the CID (Card identification number), the individual number of the memory card 41 is stored. A relative card address (dynamically determined by the host device at initialization) is stored in RCA (Relative card address). A DSR (Driver Stage Register) stores the bus driving force of the memory card 41 and the like.

  A characteristic parameter value of the memory card 41 is stored in CSD (Card specific data), and holds version information, a performance identification code, and a performance parameter of the first embodiment.

  The data arrangement of the memory card 41 is stored in the SCR (SD configuration data register). In an OCR (Operation condition resister), an operation voltage in the case of a memory card with a limited operation range voltage is stored.

  The MPU 54 controls the operation of the entire memory card 41. For example, when the memory card 41 is supplied with power, the MPU 54 reads out firmware (control program) stored in the ROM 56 onto the RAM 57 and executes predetermined processing to create various tables on the RAM 57. To do.

  The MPU 54 also receives a write command, a read command, and an erase command from the host device 20 and executes predetermined processing on the flash memory 42 and controls data transfer processing through the buffer 58.

  The ROM 56 stores a control program controlled by the MPU 54. The RAM 57 is used as a work area for the MPU 54 and stores a control program and various tables. The flash controller 55 performs an interface process between the card controller 43 and the flash memory 42.

  The buffer 58 temporarily stores a certain amount of data (for example, for one page) when data sent from the host device 20 is written to the flash memory 42, and stores data read from the flash memory 42 as a host. When sending to the device 20, a certain amount of data is temporarily stored.

  FIG. 21 shows the data arrangement in the flash memory 42 in the memory card 41. Each page of the flash memory 42 has 2112B (512B data storage unit × 4 + 10B redundant unit × 4 + 24B management data storage unit), and 128 pages have one erase unit (256kB + 8kB (here , K is 1024)). In the following description, for the sake of convenience, the erase unit of the flash memory 42 is assumed to be 256 kB.

  Further, the flash memory 42 includes a page buffer 42A for inputting / outputting data to / from the flash memory 42. The storage capacity of the page buffer 42A is 2112B (2048B + 64B). When writing data, the page buffer 42A executes data input / output processing for the flash memory 42 in units of one page corresponding to its own storage capacity.

  When the storage capacity of the flash memory 42 is, for example, 1 Gbit, the number of 256 kB blocks (erase units) is 512.

  FIG. 21 illustrates the case where the erase unit is a 256 kB block, but it is also practically effective to construct the erase unit to be, for example, a 16 kB block. In this case, each page has 528B (512B worth of data storage part + 16B redundant part), and 32 pages are one erase unit (16kB + 0.5kB).

  As shown in FIG. 19, an area (data storage area) in which data in the flash memory 42 is written is divided into a plurality of areas according to data to be stored. The flash memory 42 includes a management data area 61, a confidential data area 62, a protection data area 63, and a user data area 64 as data storage areas.

  The management data area 61 mainly stores management information related to the memory card, that is, stores card information such as security information of the memory card 41 and a media ID.

  The confidential data area 62 stores key information used for encryption and confidential data used for authentication, and is an area that cannot be accessed from the host device 20.

  The protected data area 63 is an area that stores important data and can be accessed only when the validity of the host device 20 is proved by mutual authentication with the host device 20 connected to the memory card 41.

  The user data area 64 is an area that stores user data and can be freely accessed and used by a user using the memory card 41.

  In the second embodiment, the case where the operation mode of the memory card 41 is the SD4 bit mode will be described as an example. However, the second embodiment can also be applied to the SD1 bit mode and the SPI mode. FIG. 22 shows signal assignments to signal pins in the SD4 bit mode, the SD1 bit mode, and the SPI mode.

  The operation mode of the memory card 41 is roughly divided into an SD mode and an SPI mode. In the SD mode, the memory card 41 is set to the SD4 bit mode or the SD1 bit mode by a bus width change command from the host device 20.

  Here, paying attention to four data 0 pins (DAT0) to 3 data pins (DAT3), in the SD4 bit mode in which data transfer is performed in units of 4 bits, all 4 data 0 pins to 3 data pins are used for data transfer. It is done.

  In the SD1 bit mode in which data transfer is performed in units of 1-bit width, only the data 0 pin (DAT0) is used for data transfer, and the data 1 pin (DAT1) and data 2 pin (DAT2) are not used at all. The data 3 pin (DAT3) is used for, for example, an asynchronous interrupt from the memory card 19 to the host device 20.

  In the SPI mode, the data 0 pin (DAT0) is used for the data signal line (DATA OUT) from the memory card 19 to the host device 20. The command pin (CMD) is used for a data signal line (DATA IN) from the host device 20 to the memory card 19. The data 1 pin (DAT1) and the data 2 pin (DAT2) are not used at all. In the SPI mode, the data 3 pin (DAT3) is used for transmission of the chip select signal CS from the host device 20 to the memory card 19.

  When the flash memory 42 is composed of one chip, the memory card 19 is used when a high-speed operation is not required, and is classified into, for example, a class M (M is zero or a positive integer).

  In the memory card 19 of class N (N is a positive integer larger than M), the flash memory 42 is faster than the one-chip memory card 19, for example, the plurality of flash memory chips 42 are configured by a plurality of chips. . In this way, the card controller 43 can transfer data to another flash memory chip while writing data to one flash memory chip. Therefore, the apparent data transfer rate between the card controller 43 and the flash memory 42 is improved.

  Alternatively, by adopting a flash memory chip having a page copy (or copy back) function, data stored in one page in the flash memory chip can be copied to another page in the same flash memory chip. it can. As a result, the movement performance Pm can be improved.

  In addition, although this invention was demonstrated along 1st Embodiment and 2nd Embodiment, this invention is not limited to this range. As a host device to which the present invention can be applied, a digital still camera, a digital video camera, a PC (personal computer), and a PDA can be considered.

As a semiconductor memory used as the storage device 19 of the first and second embodiments, a memory having a floating gate as a charge storage layer, such as an AND flash memory and a NOR flash ^TM memory in addition to a NAND flash ^TM memory. But it ’s okay. Alternatively, an insulating layer such as a MONOS type may be used as the charge storage layer. Furthermore, non-volatile semiconductor memories such as MRAM (Magnetic Random Access Memory) and FeRAM (Ferromagnetic Random Access Memory) may be used.

1 is a block diagram of a NAND flash ^TM memory according to a first embodiment. FIG. 1 is a diagram illustrating an example of a storage device with a built-in memory according to a first embodiment and an example of a host device that uses the storage device. FIG. 3 is a diagram illustrating an example of storage device area division when viewed from the host device according to the first embodiment and an actual storage area division inside the storage device. The figure explaining the movement of the data in 1st Embodiment. The figure which shows an example of the write-in operation timing when a multiblock write command is used. The figure which shows an example of the performance curve in 1st Embodiment. The figure which shows the example of the file system update in real time recording in 1st Embodiment. The figure which illustrates the sequence of writing. FIG. 3 is a diagram illustrating the appearance of a host device and a storage device according to the first embodiment. The figure which shows the performance curve classification | category in 1st Embodiment. The figure which shows the example of the required characteristic of the card | curd of each class. The figure which shows the example of the measurement conditions of the card | curd request | requirement characteristic of each class. The figure which illustrates the content memorize | stored in the register ^| resistor of an ^SDTM memory card. The figure which illustrates AU classification to the memory card field in a 1st embodiment. The figure which shows the concept of the host buffer in 1st Embodiment. An example in which all used RUs are accumulated at the top of the AU. Schematic which shows the structure of the memory card of 2nd Embodiment of this invention. The figure which shows the signal allocation with respect to the signal pin in the memory card of 2nd Embodiment. The block diagram which shows the hardware constitutions of the memory card of 2nd Embodiment. The figure which shows the detailed structure of the register part in the memory card of 2nd Embodiment. The figure which shows the structure of the memory cell and buffer in the flash memory in the memory card of 2nd Embodiment. The figure which shows the signal allocation with respect to the SD bus signal pin in each operation mode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 19 ... Storage device, 20 ... Host apparatus, 21 ... Storage area, 22 ... Device controller, 23 ... Version information register, 24 ... Performance identification code register, 25 ... Performance parameter register, 26 ... Host controller, 27 ... Host buffer, 28 ... processor, 29 ... system memory.

Claims (13)

A semiconductor memory for storing data;
A controller that issues an instruction to write data to the semiconductor memory in response to an external request;
A register that is provided in the controller and holds information on one performance class among a plurality of performance classes classified according to performance, and performance parameter information on the performance of the semiconductor memory and the controller ;
Comprising
A storage device configured to output information of the one performance class to the outside in response to an instruction from the outside;
Wherein one performance class indicates that the minimum performance is defined for each of the plurality of performance classes said storage device is satisfied,
The performance parameter information includes a size of a management unit area used by a host device that uses the storage device,
The management unit area consists of a plurality of write units, and depends on boundaries in the storage space of the semiconductor memory,
The write unit is a unit used in an external data write instruction.
A storage device characterized by that. The storage device according to claim 1 , wherein the performance parameter information further includes a moving speed required for moving data in the memory. Comprehensive performance including update of file information is managed by the host, and the write performance is maintained before and after the update even if the file information is updated so that the overall performance can be calculated .
The write performance is an average worst-case write performance of the storage device measured under predetermined conditions;
The one performance class indicates that the storage device has a minimum write performance determined by the one performance class;
The storage device according to claim 1. An envelope covering the semiconductor memory and the controller;
A display unit provided on the envelope and displaying the performance class;
The storage device according to claim 1, further comprising: A host device having a plurality of write modes with different bit rates and having an application for transferring data to a storage device,
The storage device holds performance parameters for the storage device;
The performance parameters include sexual performance class information,
A minimum bit rate of the storage device is determined by the performance class information;
At least one write mode from the plurality of write modes is selectable such that the bit rate of the selected write mode is less than or equal to the minimum bit rate of the storage device ;
A host device characterized by that. The host device according to claim 5, wherein the storage device reads the pre-Symbol performance parameters from and performing a calculation using the performance parameter. Managing the memory area of the semiconductor memory in the storage device by a plurality of management unit areas each consisting of a plurality of write unit areas;
Depending on the usage state in the plurality of management unit areas, the plurality of management unit areas can be classified as conformable management unit areas where data can be written with the required performance using the performance parameters and impossible improper Categorized as management unit area,
The host device according to claim 6 . 8. The host device according to claim 7 , wherein the conformity management unit area is used for real-time writing. The remaining recording time during which data can be written with the required performance is calculated using the average data transfer rate when the host device transfers the write data to the storage device and the number of the adaptive management unit areas. The host device according to claim 8 . 6. The host device according to claim 5 , wherein when the performance class information of the storage device is “0”, it is determined that the performance class is not defined in the storage device. 6. The host according to claim 5 , wherein when the performance of the storage device cannot satisfy the first performance required by the host device, data is written to the storage device with a second performance lower than the first performance. machine. 6. The host device according to claim 5 , wherein write data requested to be written is stored in a buffer of the host device while data cannot be written to the storage device. An envelope,
A display unit provided on the envelope and displaying the performance class set in the host device;
The host device according to claim 5 , further comprising:

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