TWI724483B - Data storage device and control method for non-volatile memory - Google Patents

Abstract

High performance data storage device is disclosed, which has a memory controller dynamically maintaining mapping information on a temporary storage memory to relate physical space information to a logical address issued by a host. Using number 1 to number N bits forming the physical space information, the memory controller indicates a physical space within the non-volatile memory or an address within a data cache space provided by the temporary storage memory. In the physical space information, the memory controller does not plan any specific bits to direct to the non-volatile memory or the data cache space. The memory controller uses meaningless values composed by the number 1 to number N bits without corresponding to any physical space of the non-volatile memory to distinguish whether the physical space information directs to the non-volatile memory or the data cache space.

Description

Data storage device and non-volatile memory control method

The present invention relates to data storage devices, and particularly relates to the maintenance of mapping information.

Non-volatile memory has many forms-for example, flash memory, magnetoresistive RAM, ferroelectric RAM, resistive random access Memory (resistive RAM), spin transfer torque random access memory (Spin Transfer Torque-RAM, STT-RAM)... etc. are used for long-term data storage.

Non-volatile memory has its special storage characteristics, and its operation and management require special design.

This case proposes a physical space information format for managing the mapping information of a data storage device.

A data storage device implemented according to an embodiment of the present case includes a non-volatile memory, a memory controller, and a temporary memory. The memory controller accesses the non-volatile memory according to a request of a host. The memory controller plans a data cache space on the temporary memory. The memory controller dynamically maintains mapping information on the temporary memory, and displays the physical space information of the logical address mapping identified by the host. The memory controller uses the first bit to the Nth bit (N is a value greater than 1) of the physical space information to indicate the physical space of the non-volatile memory, or indicate the address in the data cache space. The memory controller does not plan a specific bit in the physical space information to distinguish whether the physical space information points to the non-volatile memory or the data cache space. The memory controller is a value that is meaningless relative to the physical space of the non-volatile memory among the values composed of the first to the Nth bits, and distinguishes whether the physical space information points to the non-volatile memory or the non-volatile memory. Data cache space.

According to the technology in this case, the bits of physical space information are optimally utilized, which is sufficient to cope with large-size non-volatile memory.

In one embodiment, the memory controller uses a mask to process the value obtained by processing the physical space information to identify whether the physical space information is directed to the non-volatile memory or the data cache space.

The memory controller can also identify the value obtained by processing the physical space information by the mask to identify whether the physical space information is dummy data.

In one embodiment, the memory controller processes the physical space information with a mask, and determines that the physical space information is dummy data when a first value is obtained, and determines that the physical space information is when a second value is obtained Point to the data cache space, and determine that the physical space information points to the non-volatile memory when the first value or the second value is obtained.

The memory controller can perform logic and calculation on the physical space information with the mask.

In one embodiment, the non-volatile memory is a flash memory. The plural blocks of the flash memory are distinguished by a block bit number BlkBits. The plural units in each block are distinguished by one unit bit number UnitBits. The memory controller performs calculations: Mask=(((1>> BlkBits)-1)*(1>> UnitBits)), Where Mask is the mask.

The memory controller can also perform calculations: DummySrc = Mask; and DRAMSrc = (((1>> BlkBits)-2)*(1>> UnitBits)), Wherein, DummySrc is the first value, and DRAMSrc is the second value.

The operation of the above memory controller on the non-volatile memory can also be implemented by other structures. In this case, the aforementioned concept can be used to realize the control method of non-volatile memory, including: accessing a non-volatile memory according to the request of a host; planning a data cache space on a temporary memory; in the temporary memory The mapping information is dynamically maintained on the body, showing the physical space information mapped by the logical address identified by the host; the first bit to the Nth bit of the physical space information is used to indicate the physical space of the non-volatile memory or the data The address in the cache space, and no specific bits are planned in the physical space information to distinguish whether the physical space information points to the non-volatile memory or the data cache space; and use the first to the Nth bits Among the constituent values, a value that is meaningless relative to the physical space of the non-volatile memory, distinguishes that the physical space information points to the non-volatile memory or the data cache space.

Hereinafter, embodiments are specially cited, in conjunction with accompanying drawings, to illustrate the content of the present invention in detail.

The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention, and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the scope of the patent application.

Non-volatile memory can be Flash Memory, Magnetoresistive RAM, Ferroelectric RAM, Resistive RAM, RRAM ), Spin Transfer Torque-RAM (STT-RAM), etc., provide storage media for long-term data storage. The following discussion takes the flash memory as an example.

Nowadays, data storage devices often use flash memory as storage media to store user data from the host. There are many types of data storage devices, including memory cards (Memory Card), universal serial bus flash devices (USB Flash Device), solid state drives (SSD)... and other products. One application is to use multi-chip packaging to package flash memory and its controller together-called embedded flash memory modules (such as eMMC).

The data storage device using flash memory as the storage medium can be applied to a variety of electronic devices. The electronic devices include smart phones, wearable devices, tablet computers, virtual reality devices, etc. The computing module of the electronic device can be regarded as a host, which operates the data storage device used to access the flash memory therein.

Data storage devices using flash memory as storage media can also be used to construct data centers. For example, the server can operate a solid state drive (SSD) array to form a data center. The server can be regarded as a host, which operates the connected solid-state drive to access the flash memory.

FIG. 2 is a block diagram illustrating a data storage device 200 implemented according to an embodiment of the present invention, which includes a flash memory 202, a memory controller 204, and a temporary memory 206. The host 208 operates the flash memory 202 through the memory controller 204. The flash memory 202 can also be optimized inside the data storage device 200; for example, the memory controller 204 can perform garbage collection, space trimming, and block data on the flash memory 202. Block Data Transfer...etc. The memory controller 204 uses the temporary memory 206 to temporarily store data when performing operations. The temporary storage memory 206 may be dynamic random access memory (DRAM) or SRAM.

The flash memory 202 has a system information block pool 210 to store a logical-to-physical address mapping table (Logical-to-Physical Addresses Mapping Table, L2P mapping table), and there are many blocks that change between multiple states. The active block 214 from the idle block pool 212 is used to receive the written data requested by the host 208. After the active block 214 is closed (for example, after the end of block (EOB) information is written), it will be regarded as a data block and belong to the data block pool 216. The idle block pool 212 will provide the active block 214 again. After the data block is removed, it can be pushed into the idle block pool 212. The active block 214 can also be configured as a destination for data transfer within the flash memory 202.

The physical space of the flash memory 202 is divided into a plurality of blocks (Blocks) for allocation. Figure 1 illustrates the structure of a block BLK, which includes multiple pages (Pages), for example, page 0...page 255. Each page includes a plurality of sectors (Sectors), for example: 16KB space page can include 32 sectors to store user data, each sector size is 512B. In addition, in the 4KB data management mode, 8 sections can be regarded as the smallest data management unit. At this time, the size of the data management unit is 4KB, which can store user data of 8 sections. In order to simplify the description, the following will take the 4KB data management mode as an example for description, but it is not limited to this.

With the filling of the active block 214, the memory controller 204 can maintain a Physical-Logical Addresses Mapping Table (P2L mapping table) 218 on the temporary memory 206 to display the active block 214 The physical address actually stores the user data of those logical addresses, or the mapping information from the physical address to the logical address. As contained in the P2L mapping table 218, the active block 214 is used to store user data of multiple logical addresses, and its reverse mapping information can be used to update the logical-to-physical address mapping table (Logical-to-Physical Addresses Mapping). Table, L2P mapping table) content. In addition, the memory controller 204 can upload the L2P mapping table (partially or completely) to the space 220 of the temporary memory 206 to speed up the access of the L2P mapping table.

In one embodiment, the memory controller 204 stores the user data in blocks according to the page number, from low to high (for example, page 0 to page 255). In one embodiment, the data storage device 200 adopts multi-channel technology, which regards the blocks between different channels as a super block, and the pages between different channels as super pages. Then, the super block or super page is used as the unit of data erasing or data writing. With this architecture, the data throughput of the data storage device 200 can be improved.

The flash memory 202 has its special storage characteristics. The old data update is not copied in the same space. The new version of the data needs to be written into the free space, and the old space content will be marked as invalid. Blocks may retain valid data sporadically, and garbage collection procedures can be executed to move valid data to idle space. Blocks with invalid data can be erased and reused.

The physical space of the flash memory 202 is dynamically allocated and used. Compared with the host side which uses logical addresses (for example, logical block address LBA or global host page number GHP... etc.) to distinguish user data, which entity of the flash memory actually corresponds to each logical address The location (address) is recorded in the L2P mapping table, where the physical address can be mainly represented by the block number, page number, and data management unit number, and the data management unit number can be represented by the offset (Offset). Under the Multi-Channel Accessing architecture, the physical address can also include information such as channel number, logical unit number (LUN), and plane number.

The memory controller 204 needs to refer to or update the mapping information of the L2P mapping table when operating the flash memory 202. For example, when reading user data from the flash memory 202, it needs to refer to the mapping information. 202 Write user data to update the mapping information. In addition to responding to the host's read and write requirements, the memory controller 204 will also actively or passively perform other operations on the flash memory 202, such as garbage collection, space trimming, block data transfer, etc., the above operations It also involves the reference or update of the mapping information of the L2P mapping table.

In addition to temporarily storing the L2P mapping table, the temporary memory 206 may also have part of its space planned as a data cache (Cache) space 222. When user data is cached in the data cache space 222 of the temporary memory 206, the physical address in the L2P mapping table is the physical address of the temporary memory 206, not the physical location of the flash memory 202 site. In order to avoid confusion between the physical address of the temporary memory 206 and the physical address of the flash memory 202, the memory controller 204 can use one of the bits in the physical address of the L2P mapping table as a flag, for example, The 32-bit (four-byte) physical address plan is as follows: l Bit [31]: UNC bit, used by the UNC command of the non-volatile memory high-speed communication interface (NVMe). l Bit [30: 29]: Information mode (Pattern Mode) bit, 00/01 represents the subsequent bit [28:0] indicates the physical address of the flash memory 202, 10 represents the subsequent bit [28:0 ] Indicates the physical address of the temporary memory 206, and 11 represents that the subsequent bits [28:0] are meaningless dummy data. l Bit [28:0]: The value of the physical address, where bit [28:20] records the block number, bit [19:00] records the page number and additional information, such as: offset (offset ), channel number CH#, logical unit number (LUN), chip enable signal number CE#, plane number, etc.

However, with the evolution of the manufacturing technology of the flash memory 202, each block has more pages, and the flash memory 202 has more data storage space. Therefore, the physical address in the L2P mapping table needs to be used more. The multi-digit number can correctly indicate the storage location of the user data, and the original physical address format is no longer applicable.

Therefore, this case proposes a physical address format that can be applied to the L2P mapping table. The 32-bit physical address plan in this case is as follows: l Bit [31]: UNC bit, used by the UNC command of the non-volatile memory high-speed communication interface (NVMe); l Bit [30:0]: The value of the physical address, where the bit [30:22] records the block number, and the bit [21:00] records the page number and additional information. In addition, the present invention uses the value of the non-existent physical address as the information mode bit. In the present invention, the physical address is represented by 31 bits instead of 29 bits. In theory, 4 times the physical address can be recorded, that is, 4 times the data storage space.

In the physical address format in this case, the information mode bit no longer monopolizes any exclusive bits, but shares bits with the physical address, and uses non-existent values to represent the information mode, for example, the bit that records the block number In [31:0], bit [30:22] records the block number, so the maximum value is 511. However, the maximum value of the block number of the flash memory 202 is 504, so the values 505 to 511 are non-existent or unused values. Therefore, the information mode bits can be replaced by non-existent or unused values. For example, if the value is 508, the physical address is judged as the physical address of the temporary memory 206; if the value is 511, the physical address is judged as meaningless dummy data, where logical operations can be used and, Or, displacement, or mask operations are used to determine the value of bit [30:22].

Figure 3 is a flowchart of the method for judging the entity address category in this case. In step S302, the memory controller 204 receives a host command from the host 208, where the host command includes a command type and a logical address. The command type can be data reading, data writing, space trimming, and so on.

In step S304, the memory controller 204 queries the L2P mapping table according to the host command to obtain the physical address. The memory controller 204 obtains the physical address according to the logical address L2P mapping table of the host command, for example, the obtained physical address Phy[31:0] is 0x1F054321.

In step S306, the memory controller 204 performs a logical operation on the physical address (even the specific bit of the physical address) to obtain the result value. One implementation is to perform logic operations on bits [31:0]. In one embodiment, the memory controller 204 performs a logical operation on the local bits [30:24] of the physical address, and the result value is "7D".

In step S308, the memory controller 204 determines the type of the physical address according to the result value. If it is the first value, the memory controller 204 proceeds to step S310 to determine that the physical address is meaningless dummy data. If it is the second value, the memory controller 204 proceeds to step S312 to determine that the physical address is the physical address of the temporary memory 206. If it is neither the first nor the second value, the memory controller 204 proceeds to step S314 to determine that the physical address is the physical address of the flash memory 202.

Figure 4 is an example (as shown in Table 400) of the first value and the second value in the method of judging the entity address category in this case, where the first value (label: DummySrc) and the second value (label: DRAMSrc) It can be calculated by the following equation: ValidBlk = (TotalFBlk >> ShiftCnt) (Equation 1) Mask=(((1>> BlkBits)-1)*(1>> ShiftCnt)) (Equation 2) DummySrc = Mask (Equation 3) DRAMSrc = (((1>> BlkBits)-2)*(1>> ShiftCnt)) (Equation 4)

Taking the first line in Figure 4 as an example, the total number of blocks in a plane is equal to 504, or the total number of hexadecimal blocks (label: TotalFBlk) is equal to 0x1F8, and the amount of displacement (label: ShiftCnt, or a plurality of blocks in each block (write Input/storage) UnitBits) is equal to 21 bits. According to Equation 1, after shifting TotalFBlk to the left by ShiftCnt, the maximum valid value (label: ValidBlk) is equal to 0x3F000000, and any one is greater than ValidBlk The value of can be used as DummySrc or DRAMSrc.

Choose a value that exceeds ValidBlk as the mask (label: Mask), as shown in Equation 2, set the number of block bits (label: BlkBits) equal to 9 and ShiftCnt equal to 21, and the calculation can get Mask equal to 0x3FE00000, and Mask can be used in this case The operation of step S306 in the method of judging the entity address type.

As shown in Equation 3, Mask is used as DummySrc, that is, Mask is equal to DummySrc and also equal to 0x3FE00000. After that, according to the calculation of Equation 4, it can be known that DRAMSrc is equal to 0x3FC00000, and DummySrc and DRAMSrc can be used for the numerical identification of step S308 in the method of judging the physical address type in this case.

Taking the second line in Figure 4 as an example, the total number of blocks in a plane is equal to 236, or TotalFBlk is equal to 0xEC, and ShiftCnt is equal to 21 bits. According to Equation 1, after shifting TotalFBlk to the left by ShiftCnt, ValidBlk is equal to 0x3B000000. , Let DummySrc be equal to 0x3FC00000 or DRAMSrc be equal to 0x3F800000.

Taking the third line in Figure 4 as an example, the total number of blocks in a plane is equal to 1008, or TotalFBlk is equal to 0x3D0, and ShiftCnt is equal to 21 bits. According to Equation 1, after shifting TotalFBlk to the left by ShiftCnt, it can be calculated that ValidBlk is equal to 0x7E000000. , Let DummySrc be equal to 7FE00000 or DRAMSrc be equal to 0x7FC00000.

The above operation design of the memory controller 204 on the flash memory 202 can also be implemented by other structures. Any use of (Equation 1) physical space to indicate the maximum effective value of ValidBlk or more idle values to distinguish the information mode (Pattern Mode) falls within the scope of this case. In this case, the aforementioned concept can be used to realize the control method of non-volatile memory.

Although the present invention has been disclosed in preferred embodiments as above, it is not intended to limit the present invention. Anyone familiar with the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

200: Data storage device 202: flash memory 204: Memory Controller 206: Temporary memory 208: Host 210: System Information Block Pool 212: Idle Block Pool 214: active block 216: data block pool 218: Physical-Logical Address Mapping Table 220: Space, used to load the logical-physical address mapping table 222: data cache space 400: form BLK: block S302...S314: Step

Figure 1 illustrates the structure of a block BLK; Figure 2 is a block diagram illustrating the data storage device 200 implemented according to an embodiment of the present case; Figure 3 is a flowchart of the method for judging the entity address category in this case; Figure 4 illustrates the setting of the first value and the second value in the method of judging the entity address category in this case.

200: Data storage device

202: flash memory

204: Memory Controller

206: Temporary memory

208: Host

210: System Information Block Pool

212: Idle Block Pool

214: active block

216: data block pool

218: Physical-Logical Address Mapping Table

220: Space, used to load the logical-physical address mapping table

222: data cache space

Claims (12)

A data storage device includes: a non-volatile memory; and a memory controller, and a temporary memory, wherein: the memory controller accesses the non-volatile memory according to a request from a host; the memory The volume controller plans a data cache space on the temporary memory; the memory controller dynamically maintains mapping information on the temporary memory, and displays the physical space information of the logical address mapping identified by the host; the memory The volume controller uses the first bit to the Nth bit of the physical space information to indicate the physical space of the non-volatile memory or the address in the temporary cache space, where N is a value greater than 1; and The memory controller does not plan a specific bit in the physical space information to distinguish whether the physical space information points to the non-volatile memory or the data cache space, which is a value composed of the first bit to the Nth bit The value in the physical space of the non-volatile memory does not correspond to the value of the physical space, distinguishing that the physical space information points to the non-volatile memory or the data cache space; and the memory controller processes the physical space information with a mask. The obtained value identifies whether the physical space information points to the non-volatile memory or the data cache space. According to the data storage device described in item 1 of the patent application, the memory controller further uses the mask to process the value obtained by processing the physical space information to identify whether the physical space information is dummy data. Such as the data storage device described in item 2 of the scope of patent application, in which: When the memory controller processes the physical space information with the mask to obtain a first value, it determines that the physical space information is dummy data, and when the physical space information is processed with the mask to obtain a second value, it is determined The physical space information points to the data cache space, and when the physical space information is processed with the mask to obtain neither the first value nor the second value, it is determined that the physical space information points to the non-volatile memory. For example, the data storage device described in item 3 of the scope of patent application, wherein: the memory controller uses the mask to perform logic and operations on the physical space information. For the data storage device described in item 4 of the scope of patent application, wherein: the non-volatile memory is a flash memory; the blocks of the flash memory are distinguished by a block bit number BlkBits; each The plural units in the block are distinguished by the number of unit bits UnitBits; and the memory controller performs operations: Mask=(((1<<BlkBits)-1)*(1<<UnitBits)), where Mask For the mask. For the data storage device described in item 5 of the scope of patent application, the memory controller further performs operations: DummySrc=Mask; and DRAMSrc=(((1<<BlkBits)-2)*(1<<UnitBits)) , Where DummySrc is the first value, and DRAMSrc is the second value. A non-volatile memory control method includes: accessing a non-volatile memory according to a request of a host; Plan a data cache space on a temporary memory; dynamically maintain mapping information on the temporary memory to display the physical space information mapped by the logical address identified by the host; use the first bit of the physical space information The Nth bit indicates the physical space of the non-volatile memory, or indicates the address in the data cache space, and N is a value greater than 1, where no specific bit is planned in the physical space information to distinguish the physical space The information refers to the non-volatile memory or the data cache space, but the value composed of the first bit to the Nth bit, which does not correspond to the value of the physical space of the non-volatile memory, distinguishes the The physical space information points to the non-volatile memory or the data cache space; and the value obtained by processing the physical space information with a mask identifies that the physical space information points to the non-volatile memory or the data cache space. For example, the non-volatile memory control method described in item 7 of the scope of patent application further includes: using the mask to process the value obtained by processing the physical space information to identify whether the physical space information is dummy data. For example, the non-volatile memory control method described in item 8 of the scope of patent application further includes: when the physical space information is processed with the mask to obtain a first value, the physical space information is determined to be dummy data, and the When the mask processes the physical space information to obtain a second value, it is determined that the physical space information points to the data cache space, and the physical space information is processed with the mask to obtain neither the first value nor the second value. When numerical, it is determined that the physical space information points to the non-volatile memory. For example, the non-volatile memory control method described in item 9 of the scope of patent application further includes: using the mask to perform logic and operations on the physical space information. The non-volatile memory control method described in item 10 of the scope of patent application, wherein: the non-volatile memory is a flash memory; the plurality of blocks of the flash memory is a block bit number The difference between BlkBits; the plural units in each block are distinguished by the number of unit bits UnitBits; and the method further performs the operation Mask=(((1<<BlkBits)-1)*(1<<UnitBits)), Where Mask is the mask. For example, the non-volatile memory control method described in item 11 of the scope of patent application is further calculated: DummySrc=Mask; and DRAMSrc=(((1<<BlkBits)-2)*(1<<UnitBits)), where , DummySrc is the first value, and DRAMSrc is the second value.

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