TWI691839B - Method for data management - Google Patents

Abstract

A method for data management, which maintains a first mapping table and a second mapping table. The first mapping table records a mapping relationship between a logical address of data and a first physical address of a first storage device. The second mapping table records a mapping relationship between the logical address and a second physical address of a second storage device. According to the method for data management, a read request is answered based on the first mapping table.

Description

Data management methods

The invention relates to a data storage device, in particular to a hybrid data storage technology.

There are many forms of non-volatile memory used in data storage devices-for example, flash memory, magnetoresistive random access memory (Magnetoresistive RAM), ferroelectric random access memory (Ferroelectric RAM) , Resistive RAM (Resistive RAM), etc., used for long-term data storage. However, the operating efficiency of data storage devices is limited by the physical operating characteristics of non-volatile memory. How to improve the operation efficiency of the data storage device is an important issue in the technical field.

A data management method implemented according to an embodiment of the present invention includes: maintaining a first mapping table for recording a mapping relationship between a logical address of a data and a first physical address of a first storage element Maintaining a second mapping table for recording the mapping relationship between the logical address of the data and a second physical address of a second storage element; and responding to a read request according to the first mapping table.

When the read request cannot be answered according to the first mapping table, the data management method can respond to the read request according to the second mapping table. The second storage element can store the data non-volatilely.

In one embodiment, the logical address is placed in a logical address range. The logical address range may be fixed, or the logical address range may be continuous.

In one embodiment, the data is read from the second storage element and then stored in the first storage element.

A data management method implemented according to another embodiment of the present invention includes: maintaining a first mapping table to record a mapping relationship between a first logical address and a first physical address of a first storage element; maintaining a second The mapping table is used to record the mapping relationship between the second logical address and the second physical address of the second storage element; if the third logical address required for reading is the same as the first logical address, the reading is stored in the first The first data at a physical address, if the third logical address required for reading is the same as the second logical address, then the second data stored at the second physical address is read, where the first data and The second data are confidential and non-confidential data, and the first physical address and the second physical address are placed in random access memory and non-volatile memory, respectively.

The following describes the embodiments in detail and the accompanying drawings to explain the content of the present invention in detail.

100‧‧‧Flash memory

300‧‧‧Data storage device

304‧‧‧Control unit

306‧‧‧Host

310‧‧‧ Online burning block pool

312‧‧‧System Information Block Pool

314‧‧‧Idle block pool

316‧‧‧ active block

318‧‧‧Data block pool

320‧‧‧Microcontroller

322‧‧‧random access memory space

324‧‧‧Read-only memory

330‧‧‧Dynamic Random Access Memory

332‧‧‧Dynamic use of temporary storage area

334‧‧‧Special use temporary storage area

BLK#1, BLK#2, BLK#Z‧‧‧Physical block

B#‧‧‧Physical block number

DRAM_Addr‧‧‧Dynamic random access memory address

DRAM_Tab‧‧‧ mapping table

Flash_Tab‧‧‧ mapping table

LBA#‧‧‧Logical block address

S502…S512, S602…S610‧‧‧Step

U#‧‧‧Unit number

Figure 1 illustrates the storage space plan of a flash memory 100; Figures 2A, 2B, and 2C show different plans for a specific use temporary storage area on the dynamic random access memory; Figure 3 is a block diagram Illustrate a data storage device 300 implemented according to the embodiment of this case; FIG. 4 illustrates the mapping information that the data storage device 300 needs to maintain; FIG. 5 is a flowchart illustrating the operation of the data storage device 300 according to an embodiment of the case; and FIG. 6 is a flowchart illustrating the operation of the data storage device 300 according to another embodiment of the present case.

The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention and is not intended to limit the content of the present invention. The actual scope of invention shall be defined in accordance with the scope of patent application.

Non-volatile memory can be flash memory, magnetoresistive RAM, ferroelectric RAM, and resistive RAM. ), spin transfer torque random access memory (Spin Transfer Torque-RAM, STT-RAM and other memory devices with long-term data storage, the following particularly takes flash memory (flash memory) as an example for discussion, but It is not intended to be limited. Figure 1 illustrates a flash memory (flash memory) 100 storage space plan is divided into a plurality of physical blocks (physical blocks) BLK#1, BLK#2...BLK#Z, etc., Z It is a positive integer. Each physical block includes a plurality of physical pages (physical pages), for example: 256 physical pages. Each physical page can store data of a preset length, for example: 16KB of data.

Today's data storage devices often use flash memory 100 as a storage medium, and are often used to implement products such as memory cards, universal serial bus flash devices (USB flash devices), solid state drives (SSDs), etc. One application is to use a multi-chip package to package the flash memory 100 and its controller—called an embedded flash memory module (such as eMMC).

The data update of the flash memory 100 does not overwrite the same storage space, but stores the updated data in a free space; the content of the original storage space becomes invalid. Frequent write operations can easily cause the storage space to be filled with invalid storage contents, resulting in a low efficiency of the storage contents of the flash memory 100. The reading and writing speed of the flash memory 100 will also be dragged down. This involves the read/write performance of the flash memory 100.

In addition, for the physical blocks filled with invalid physical pages, the flash memory 100 has a garbage collection (Garbage Collection) design. The valid physical pages of the physical block to be sorted will be copied to other physical blocks, so that the physical blocks are left empty and invalid physical pages can be freed by erase operations. However, the number of erasures allowed for each physical block is limited. Frequent write operations can cause serious data retention problems due to excessive erasure of physical blocks. This is the erase endurance of the physical block of the flash memory.

Flash memory has more read disturbance issues. During the read operation, the peripheral word line of the target word line (WL) must be applied with a high voltage, which will cause disturbance to the contents of the memory cells controlled by the peripheral word line. The reliability of the flash memory is therefore reduced.

In response to at least the operating bottleneck of flash memory, this case proposes a hybrid data storage device. In addition to realizing the non-volatile storage of data by the flash memory 100, the data storage device also plans to connect the control unit of the data storage device to a volatile memory. The volatile memory provides a specific temporary storage area to share the storage function of the flash memory. After the data storage device is powered on, the write request faced by the data storage device will be partially changed to the specific use temporary storage area as a target to avoid frequent writing of data to the flash memory. In addition, the data of the specific use temporary storage area will be directly used to respond to the read request, avoiding frequent reading of the flash memory. In this way, the above-mentioned read/write performance problems, physical block erasure restrictions, and read disturbance issues occurring in the flash memory 100 can be effectively resolved. The volatile memory may be a dynamic random access memory (DRAM).

FIG. 2A is a plan for the dynamic random access memory to provide the space for the initial configuration of the flash memory corresponding to the specific use temporary storage area. For example, for the 8GB flash memory, the 128MB system file at the front end corresponds to the above-mentioned specific use temporary storage area which is also 128MB. In still other embodiments, the dynamic random access memory is planned to provide the specific use temporary storage area corresponding to other fixed use sections of the flash memory.

In another embodiment, the dynamic random access memory provides a 128 MB specific use temporary storage area as a temporary storage area for data in a specific logical block address (LBA) number range. For example, the temporary storage area for LBA#0~#262,143 data, or the first temporary storage area for 262,144 LBA data. The data of the first LBA created may be an operating system file or an application file, and the frequency of data access is relatively high. The technology in this case uploads the operating system file or application program file to the specific temporary storage area planned in the dynamic random access memory to facilitate timely response to the access request. In this way, the efficiency of data access can be significantly improved, and it also overcomes the physical block erasure limit of flash memory and the problem of read disturbance.

Figure 2B shows another plan for the dynamic random access memory to provide the above-mentioned temporary storage area. Compared with FIG. 2A, FIG. 2B does not make the dynamic random access memory provide the specific use temporary storage area corresponding to the fixed use section of the flash memory, but corresponds to the dynamic allocation of specific files in the flash memory. storage space. For example, a 128MB specific use temporary storage area that provides dynamic random access memory as a temporary storage area for specific files of a data storage device. For example, the above-mentioned temporary storage area provided by the dynamic random access memory can be used as a storage for a game log file. The frequent reading and writing behavior of game log files is applied to dynamic random access memory, not flash memory. Therefore, the read and write efficiency of game log files can be significantly improved, and flash memory is not involved. Physical block erasure restrictions and read disturbance issues.

Figure 2C shows another plan for the above-mentioned temporary storage area of dynamic random access memory, which is related to a printer application. A data storage device can be installed on a printer, in which the flash memory is used to store the printing information of the connected user and to be printed. The data storage device is as described above, its control unit uses a dynamic random access memory, and the dynamic random access memory is planned to have a special use temporary storage area. According to the concept of Figure 2C, the confidential printing information is stored in the special-purpose temporary storage area for the printer. In particular, confidential printing information is not stored in the flash memory, but is limited to the special-use temporary storage area of the dynamic random access memory. In addition, the confidential printing information is preferably stored through data The device performs encryption processing. Only non-confidential print information will be stored in the flash memory. Once the printer is turned off or powered off, the confidential printing information will be permanently destroyed when the dynamic random access memory is powered off to achieve the purpose of keeping information confidential. Compared to dynamic random access memory, the information on the flash memory remains on the flash memory even if the power is turned off or even marked as invalid. If confidential information is stored on the flash memory, there will be a certain risk in the confidentiality of the information.

FIG. 3 is a block diagram illustrating a data storage device 300 implemented according to the above concept, which includes a flash memory 100 and a control unit 304. The control unit 304 is coupled between a host 306 and the flash memory 100, and includes operating the flash memory 100 according to commands issued by the host 306.

The preferred storage space plan of the flash memory 100 includes: an online burning block pool 310, a system information block pool 312, an idle block pool 314, an active block 316, and a data block pool 318. The blocks of the online programming block pool 310 store in-system programming (ISP) programs. The block of system information block pool 312 stores system information-for example, a mapping table. The active block 316 is supplied by the idle block pool 314 and is responsible for receiving the data from the host 306 and pushing it into the data block pool 318 after the data storage is completed.

The control unit 304 includes a microcontroller 320, a random access memory space 322, and a read-only memory 324. The random access memory space 322 can be divided into internal and external random access memory. The internal random access memory is placed in the same die as the microcontroller 320. The external random access memory is not placed in the same die as the microcontroller 320. The random access memory space 322 may be implemented by dynamic random access memory (DRAM) or/and static random access memory (SRAM). The read-only memory 324 stores a read-only program code (eg, ROM code). The microcontroller 320 executes the read-only program code contained in the read-only memory 324 or/and the online programming program contained in the online programming block pool 310 of the flash memory 100 for operation.

In this case, a dynamic random access memory 330 (not limited to the above-mentioned internal or external random access memory) belonging to the random access memory space 322 is provided with a dynamic use temporary storage area 332, and a specific use temporary storage is also planned Area 334. The dynamic use temporary storage area 332 can be used as a temporary storage of a mapping table or operation information. The temporary storage of the computing information includes implementing a cache function for implementing instruction prediction or data prefetching, etc. The specific use temporary storage area 334 shares the storage function of the flash memory 100 to avoid that the operation performance of the data storage device 300 is excessively limited by the physical operation characteristics of the flash memory 100. The use of the specific use temporary storage area 334 can refer to the descriptions in FIGS. 2A, 2B, and 2C. For example, the specific use temporary storage area 334 can be used to share the storage of operating system files or application files (Figure 2A), or the storage of game log files (Figure 2B), or even independent of the flash memory 100 is used to store the confidential information of the lister (Figure 2C).

FIG. 3 further shows that there may be interaction between the control unit 304 and the flash memory 100 to meet the non-volatile storage requirements of the specific use temporary storage area 334. When the data storage device 300 is powered on, the microcontroller 320 uploads the specific data of the flash memory 100 to the specific use temporary storage area 334 and changes the specific use temporary storage area 334 as a target to respond to data read/write requests That is, it is not necessary to synchronize the written data from the specific use temporary storage area 334 to the flash memory 100 in real time, and to respond to the read request with the content of the specific use temporary storage area 334 without accessing the flash memory 100. Regarding the data changed in the specific use temporary storage area 334 due to the write request, the user can set the synchronization conditions of the flash memory 100 by himself. For example, every time a time limit is reached, the updated data of the specific use temporary storage area 334 is synchronized to the flash memory 100 in response to an unexpected power-down/power-off event. Before the data storage device 300 is turned off, the updated data of the specific use temporary storage area 334 needs to be synchronized to the flash memory 100 to ensure that the flash memory 100 maintains the latest version of the data after power-off/power-off.

FIG. 4 illustrates the mapping information that the data storage device 300 needs to maintain. The mapping table DRAM_Tab shows the logical address of the host 306 end mapped by the specific use temporary storage area 334 of the dynamic random access memory 330. The legend uses the dynamic random access memory address DRAM_Addr as an index to show the logical block address LBA# corresponding to the address unit of 334 in the specific temporary storage area. The mapping table Flash_Tab shows the location of the flash memory mapped by the logical address on the host 306 side. The legend shows that each logical block address LBA# corresponds to a unit U# of a certain physical block B# of the flash memory 100 (usually a physical page is divided into four unit numbers U0~U3). In another embodiment, the mapping table DRAM_Tab is not indexed by the dynamic random access memory address DRAM_Addr, but is indexed by the logical block address LBA#. The mapping table Flash_Tab can also be replaced with another table sufficient to represent the logical-physical mapping relationship between the host 306 and the flash memory 100.

When the host 306 wants to access a specific logical block address LBA#, the control unit 304 can know whether it corresponds to the dynamic random access memory address DRAM_Addr according to the mapping table DRAM_Tab. When the dynamic random access memory address DRAM_Addr is found, the access to the specific logical block address LBA# is directed to the found dynamic random access memory address DRAM_Addr. On the contrary, the access of the specific logical block address LBA# refers to the mapping table Flash_Tab, and the flash memory 100 is targeted.

Regarding the non-volatile storage requirements of the specific use temporary storage area 334, in addition to its mapping to the specific use storage area 334 in the mapping table DRAM_Tab, there is also mapping information that needs to be maintained in the mapping table Flash_Tab. The microcontroller 320 can use the temporary storage area 332 to dynamically maintain the mapping information (including the mapping tables DRAM_Tab and Flash_Tab). The microcontroller 320 further includes updating the mapping information from the dynamic use temporary storage area 332 to the flash memory 100 for non-volatile storage.

FIG. 5 is a flowchart illustrating one embodiment of the operation of the data storage device 300. After the data storage device 300 is powered on, according to step S502, the microcontroller 320 uploads the mapping tables DRAM_Tab and Flash_Tab from the flash memory 100 to the dynamic use temporary storage area 332, and based on the mapping tables DRAM_Tab and Flash_Tab, the specific use temporary storage area The content corresponding to 334 is uploaded from the flash memory 100 to the temporary storage area 334. If it is determined in step S504 that a data access request (write/read) has occurred, the process proceeds to step S506, checks the mapping table DRAM_Tab, and checks whether the data access request points to the specific use temporary storage area 334, in order to use the specific use station storage area 334 is specific data of the access target. If not, according to step S508, the microcontroller 330 queries the mapping table Flash_Tab and accesses with the flash memory 100 as the target. On the contrary, the microcontroller 330 proceeds to step S510, based on the mapping table DRAM_Tab, using the specific use temporary storage area 334 as the access target. The frequent access of the flash memory 100 is effectively shared by the specific use temporary storage area 334. Step S512 further determines whether the synchronization condition between the specific use temporary storage area 334 and the flash memory 100 is satisfied. If satisfied, the microcontroller 330 proceeds to step S514, synchronizes the update of the specific use temporary storage area 334 to the flash memory 100, and updates the mapping table Flash_Tab. The access request monitoring in step S504 may continue until the power is turned off.

FIG. 6 is a flowchart illustrating another embodiment of the operation of the data storage device 300, in order to ensure that the data is not lost, the flash memory 100 is synchronized with the specific use temporary storage area 334 in real time, as for the specific use temporary storage area 334 The concept of sharing the frequent read operations of the flash memory 100 continues with the content of FIG. 5. For simplicity, Figure 6 only describes the write operation. After the data storage device 300 is powered on, according to step S602, the microcontroller 320 uploads the mapping tables DRAM_Tab and Flash_Tab from the flash memory 100 to the dynamic use temporary storage area 332, and based on the mapping tables DRAM_Tab and Flash_Tab, the specific use temporary storage area The content corresponding to 334 is uploaded from the flash memory 100 to the temporary storage area 334. If it is determined in step S604 that a data writing request has occurred, the process proceeds to step S606, and the microcontroller 320 writes the data to the flash memory 100 in real time, and updates the mapping table Flash_Tab accordingly. According to step S608, the microcontroller 320 further checks the mapping table DRAM_Tab to check whether the data writing request is to write specific data, and a backup is needed in the specific use temporary storage area 334 to share the frequent reading of the flash memory 100 Operation, to solve the reading disturbance of the flash memory 100. If yes, the microcontroller 320 proceeds to step S610 to update the specific use temporary storage area 334 so that the content of the specific use temporary storage area 334 synchronizes with the flash memory 100. The writing request in step S604 can continue until the power is turned off.

Other technologies that use the above concept to complete the hybrid data storage are all within the scope of protection in this case. Based on the above technical content, this case further relates to the operation method of the data storage device.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can do some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined in the scope of the attached patent application.

100‧‧‧Flash memory

300‧‧‧Data storage device

304‧‧‧Control unit

306‧‧‧Host

310‧‧‧ Online burning block pool

312‧‧‧System Information Block Pool

314‧‧‧Idle block pool

316‧‧‧ active block

318‧‧‧Data block pool

320‧‧‧Microcontroller

322‧‧‧random access memory space

324‧‧‧Read-only memory

330‧‧‧Dynamic Random Access Memory

332‧‧‧Dynamic use of temporary storage area

334‧‧‧Special use temporary storage area

Claims (16)

A data management method includes: maintaining a first mapping table for recording a mapping relationship between a preset logical address range and a first storage element, including a data entry that falls within the preset logical address range The mapping relationship between the logical address and a first physical address of the first storage element; maintain a second mapping table for recording the logical address of the data and a second physical address of a second storage element Mapping relationship; and responding to a read request according to the first mapping table. The method as described in item 1 of the patent application scope further includes: when the read request cannot be answered according to the first mapping table, the read request should be returned according to the second mapping table. The method as described in item 1 of the patent application scope, wherein the second storage element stores the data non-volatilely. The method as described in item 1 of the patent application scope, wherein the predetermined logical address range is fixed. The method as described in item 1 of the patent application scope, wherein the predetermined logical address range is continuous. The method as described in item 1 of the patent application scope, wherein the read request comes from a host. The method as described in item 1 of the patent application scope, wherein the response to the read request is to read the data from the first physical address or the second physical address and provide it. The method as described in item 1 of the patent application scope, in which the information is from the second The storage element is stored in the first storage element after being read. The method as described in item 1 of the patent application scope, further comprising: when the power is turned off, storing the second mapping table to the second storage element. The method as described in item 1 of the patent application scope, further comprising: when powered on, reading the second mapping table from the second storage element and storing it in the first storage element. A data management method includes: maintaining a first mapping table for recording a mapping relationship between a predetermined logical address range and a first storage element, including a first logic falling within the predetermined logical address range The mapping relationship between the address and a first physical address of the first storage element; maintaining a second mapping table to record a second logical address and a second logical address that do not fall within the preset logical address range A mapping relationship of a second physical address of the storage element; and if a target logical address requested by a read is the same as the first logical address, the first physical address is accessed according to the first mapping table If the target logical address is the same as the second logical address, a second data on the second physical address is accessed according to the second mapping table. The method as described in item 11 of the patent application scope, wherein the data types of the first data and the second data are different. The method as described in item 11 of the patent application scope, wherein the first information and the second information are confidential and non-confidential information, respectively. The method as described in item 11 of the patent application scope, wherein the first physical position The address and the second physical address are placed on different data storage media. The method according to item 11 of the patent application scope, wherein the first physical address and the second physical address are placed in a volatile and a non-volatile memory, respectively. The method according to item 11 of the patent application scope, wherein, when a power-off event occurs, the second mapping table is stored to the second storage element, but the first mapping table is not stored non-volatilely.

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