JP4774999B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor package by which peeling on the interface between a first semiconductor chip and a die bonding agent can be suppressed. <P>SOLUTION: A first silicon wafer substrate 1 wherein first semiconductor chips 2 are formed is adhered to a dicing tape 4 containing no plasticizer, and it is diced into the first semiconductor chips. Then, a second semiconductor chip 6 is arranged on the first semiconductor chip 2, and they are heated to melt a bump 3 on the first chip and a bump 7 of the second chip together, thereby electrically connecting the first and second chips with each other and mounting it to a mounting substrate. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device. Specifically, the present invention relates to a method for manufacturing a semiconductor device including two semiconductor chips electrically connected by protruding electrodes.

  Currently, with the miniaturization and high performance of various electrical appliances, the density of semiconductor packages used in the interiors has increased, and high-density packaging technology for mounting semiconductor chips at high density in semiconductor packages has been increasing. Progressing. As one of them, a second semiconductor chip is electrically connected directly face-down on the first semiconductor chip by using a flip-chip mounting technique (for example, see Patent Document 1). There is a technique for mounting a connected first semiconductor chip and a second semiconductor chip on a circuit board (mounting board).

  Hereinafter, a manufacturing method of a semiconductor package including two semiconductor chips electrically connected by a flip chip method will be described with reference to the drawings. That is, a conventional method for manufacturing a semiconductor package will be described.

  In the conventional method of manufacturing a semiconductor package, first, a plurality of first semiconductor chips 102 are formed on a first silicon wafer substrate 101, and an electrode (not shown) of each first semiconductor chip is mainly composed of solder. A bump electrode 103 (hereinafter referred to as a first chip-side bump) generally referred to as a bump is formed (see FIG. 2A).

  Next, after the back grinding process of the first silicon wafer substrate is performed to reduce the thickness of the first silicon wafer substrate (see FIG. 2B), the polishing process on the back surface of the first silicon wafer substrate is performed. To reduce the roughness of the back surface of the first silicon wafer substrate to 10 nm or less.

  Subsequently, the first silicon wafer substrate is bonded to the dicing tape 104 in which the surface of the tape base material 104a mainly composed of vinyl chloride is coated with the adhesive 104b mainly composed of the acrylic adhesive, and the dicing process is performed. In parallel, the first silicon wafer substrate is separated into pieces for each first semiconductor chip (see FIG. 2C).

  In addition to the formation of the first semiconductor chip, a plurality of second semiconductor chips 106 are formed on the second silicon wafer substrate 105, and solder is mainly applied to the electrodes (not shown) of each second semiconductor chip. A bump electrode 107 (hereinafter referred to as a second chip-side bump) is formed as a component (see FIG. 2D).

  Next, after the back grinding process of the second silicon wafer substrate is performed to reduce the thickness of the second silicon wafer substrate (see FIG. 2E), the polishing process of the back surface of the second silicon wafer substrate is performed. To make the back surface roughness 10 nm or less.

  Subsequently, a second silicon wafer substrate is bonded to a dicing tape 104 in which a pressure-sensitive adhesive mainly composed of an acrylic adhesive is applied to the surface of a tape base material mainly composed of vinyl chloride, and a dicing process is performed. The second silicon wafer substrate is separated into pieces for each second semiconductor chip (see FIG. 2F).

  Next, the second semiconductor chip is arranged on the first semiconductor chip so that the first chip-side bump and the second chip-side bump are in contact with each other (see FIG. 2G). The entire semiconductor chip 1 and the second semiconductor chip are heated to melt the first chip-side bump and the second chip-side bump, and the first chip-side bump and the second chip-side bump are integrated. Thus, the first semiconductor chip and the second semiconductor chip are electrically connected (see FIG. 2H).

  Subsequently, after filling the gap between the first semiconductor chip and the second semiconductor chip with the underfill material 108, the first semiconductor chip is mounted on the mounting substrate 110 via the die bond agent 109, and the first semiconductor chip is mounted on the mounting substrate 110. The semiconductor chip and the mounting substrate are electrically connected by the bonding wire 111. Thereafter, the mounting substrate is loaded into a mold (not shown) composed of an upper mold and a lower mold, and a mold resin 112 mainly composed of an epoxy resin and an inorganic oxide filler is placed in the mold. By implanting, a semiconductor package as shown in FIG. 2 (i) can be obtained.

JP-A-6-112402

  However, in the semiconductor package obtained by the above-described conventional semiconductor package manufacturing method, peeling may occur at the interface between the back surface of the first semiconductor chip and the die bond agent in the reflow process of mounting on the motherboard. Hereinafter, this point will be described in detail.

That is, the tape base material containing vinyl chloride as a main component contains a plasticizer such as phthalates, and the first silicon wafer substrate is bonded to the dicing tape to bond the first silicon wafer substrate. A plasticizer will adhere to the back surface (the back surface of the first semiconductor chip).
Then, by the heat treatment for melting the first chip side bump and the second chip side bump, the plasticizer attached to the back surface of the first semiconductor chip is heated at a high temperature and melted. The melted plasticizer spreads over the entire back surface of the first semiconductor chip, and the back surface of the first semiconductor chip is covered with the plasticizer.
In this way, the plasticizer film formed on the back surface of the first semiconductor chip reduces the adhesion between the first semiconductor chip and the die bond agent. Peeling occurs at the interface.

Note that for the peeling that occurs at the interface between the back surface of the first semiconductor chip and the die bond agent, the plasticizer attached to the back surface of the first semiconductor chip melts to form a film on the back surface of the first semiconductor chip. Is considered to be the main cause. Therefore, if the first semiconductor chip is not subjected to heat treatment before mounting on the mounting substrate, peeling at the interface between the back surface of the first semiconductor chip and the die bond agent is rarely a problem.
For example, when a single semiconductor chip is mounted on a mounting substrate, even if the plasticizer contained in the dicing tape adheres to the back surface of the semiconductor chip, it is mounted on the mounting substrate without being heated. The plasticizer attached to the back surface of the semiconductor chip does not melt to form a film on the back surface of the semiconductor chip, and peeling at the interface between the back surface of the semiconductor chip and the die bond agent is rarely a problem.
Therefore, peeling at the interface between the back surface of the semiconductor chip and the die bonding agent is a problem when heat treatment is performed before the semiconductor chip is mounted on the mounting substrate (for example, the first chip-side bump is formed by heat treatment). And the second semiconductor chip are mounted on the mounting substrate after the first semiconductor chip and the second semiconductor chip are electrically connected by melting the second chip side bump.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress peeling at the interface between a semiconductor chip and a die bond agent.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of first semiconductor chips on a wafer substrate, and forming a first protruding electrode on the first semiconductor chip. Bonding the wafer substrate to a dicing tape, dividing the wafer substrate into pieces for each first semiconductor chip, and forming a second protruding electrode on the first semiconductor chip. A step of arranging a second semiconductor chip so that the first protruding electrode and the second protruding electrode are in contact with each other, and melting the first protruding electrode and the second protruding electrode by heat treatment; A step of integrating and electrically connecting the first semiconductor chip and the second semiconductor chip, and the first semiconductor chip electrically connected to the second semiconductor chip via a die bond agent. On the board Mounting to the method of manufacturing a semiconductor device and a step of sealing the first semiconductor chip and the second semiconductor chip, the dicing tape, the back surface of the wafer substrate before the images stuck to the dicing tape The back surface roughness of the first semiconductor chip after peeling the dicing tape and the roughness is substantially the same, the back surface roughness of the first semiconductor chip is 1.0 nm or less, The step of electrically connecting the first semiconductor chip and the second semiconductor chip is performed such that a temperature at which the first protruding electrode and the second protruding electrode are electrically connected is 300 ° C. Apply processing .

  Here, the dicing tape is configured so that the back surface roughness of the wafer substrate before being bonded to the dicing tape and the back surface roughness of the first semiconductor chip after peeling the dicing tape are substantially the same. That is, since the dicing tape is configured so as not to contain the plasticizer, the plasticizer does not adhere to the back surface of the first semiconductor chip, and the back surface of the first semiconductor chip is also plasticized by heat treatment. It is not covered with.

  “The dicing tape is configured so that the roughness of the back surface of the wafer substrate before being bonded to the dicing tape is substantially the same as the roughness of the back surface of the first semiconductor chip after peeling the dicing tape.” This means that “the dicing tape is configured not to contain a plasticizer”. That is, when a plasticizer is included in the dicing tape, the plasticizer adheres to the back surface of the wafer substrate (the back surface of the first semiconductor chip) when the wafer substrate is bonded to the dicing tape. Compared with the back surface of the wafer substrate before being bonded to the tape, the back surface roughness of the first semiconductor chip after peeling the dicing tape is increased (the back surface of the first semiconductor chip becomes rough due to adhesion of the plasticizer. ). Therefore, when the back surface roughness of the first semiconductor chip after peeling the dicing tape is not so increased compared to the back surface of the wafer substrate before being bonded to the dicing tape, that is, before being bonded to the dicing tape. When the roughness of the back surface of the wafer substrate and the roughness of the back surface of the first semiconductor chip after peeling the dicing tape are substantially the same, the plasticizer is attached to the back surface of the wafer substrate (first semiconductor chip). This means that no plasticizer is contained in the dicing tape.

Also, cracks that occur in the wafer substrate and the first semiconductor chip can be generated by performing a back surface polishing process in which the back surface roughness of the wafer substrate is equal to or higher than a predetermined flatness, that is, by making the back surface of the wafer substrate smooth. It becomes possible to suppress.
That is, when the back surface of the wafer substrate (the back surface of the first semiconductor chip) is rough as the first semiconductor chip is thinned, that is, the back surface of the wafer substrate (the first semiconductor chip) is uneven. In this case, it is conceivable that a crack is generated due to the unevenness on the back surface of the wafer substrate (first semiconductor chip). Therefore, by performing a back surface polishing process in which the back surface roughness of the wafer substrate is equal to or higher than a predetermined flatness, and reducing the unevenness on the back surface of the wafer substrate, cracks generated in the wafer substrate and the first semiconductor chip can be suppressed. It is.

  In the semiconductor device manufacturing method of the present invention, the plasticizer does not adhere to the back surface of the first semiconductor chip, and the back surface of the first semiconductor chip is not covered with the plasticizer even by heat treatment. Further, peeling at the interface between the first semiconductor chip and the die bond agent can be suppressed, and a highly reliable semiconductor device can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to provide an understanding of the present invention.
FIG. 1 is a schematic view for explaining a semiconductor package manufacturing method as an example of a semiconductor device manufacturing method to which the present invention is applied. In the semiconductor package manufacturing method to which the present invention is applied, first, a first silicon A plurality of first semiconductor chips 2 (lower chips) are formed on the wafer substrate 1, and first chip-side bumps 3 mainly composed of solder are formed on the electrodes (not shown) of the respective first semiconductor chips. (See FIG. 1A.)

  Next, after the back grinding process of the first silicon wafer substrate is performed to reduce the thickness of the first silicon wafer substrate (see FIG. 1B), the polishing process of the back surface of the first silicon wafer substrate is performed. To reduce the roughness of the back surface of the first silicon wafer substrate to 10 nm or less. Specifically, the roughness Ra (1) of the back surface of the first silicon wafer substrate is set to 1.0 nm. The polishing process is an example of a back surface polishing process.

  Here, the polishing of the back surface of the first silicon wafer substrate to reduce the roughness of the back surface of the first silicon wafer substrate (first semiconductor chip) to 10 nm or less is the first silicon wafer substrate ( This is for suppressing the occurrence of cracks in the first semiconductor chip). That is, when the back surface of the first semiconductor chip is rough as the first semiconductor chip is thinned, cracks may be generated due to the unevenness of the back surface of the first semiconductor chip. Therefore, polishing is performed on the back surface of the first silicon wafer substrate so that the roughness of the back surface of the first silicon wafer substrate (first semiconductor chip) is 10 nm or less, and unevenness on the back surface of the first silicon wafer substrate is formed. By reducing, the crack which generate | occur | produces in a 1st silicon wafer substrate (1st semiconductor chip) is suppressed.

  Even if the back grinding process is still performed on the first silicon wafer substrate (the back surface of the first semiconductor chip is rough), the first silicon wafer substrate (first semiconductor chip) is cracked. When the first silicon wafer substrate (first semiconductor chip) is thick enough to prevent the occurrence of the occurrence of polishing, it is preferable not to polish the back surface of the first silicon wafer substrate. That is, by keeping the back surface of the first semiconductor chip rough without performing the polishing process, it is possible to suppress peeling at the interface between the back surface of the first semiconductor chip and the die bond agent by a so-called anchor effect. it can. Therefore, when the silicon wafer substrate has a thickness that does not cause cracks without performing the polishing process, it is preferable not to perform the polishing process.

  Subsequently, the adhesive force obtained by applying the adhesive 4b mainly composed of an acrylic adhesive to the surface of the tape substrate 4a mainly composed of polyolefin (polyethylene, polypropylene, polybutene, polybutadiene, polymethylpentene, etc.) is 41 kPa. The first silicon wafer substrate is bonded to the dicing tape 4 and a dicing process is performed to separate the first silicon wafer substrate for each first semiconductor chip (see FIG. 1C).

  Here, the dicing tape for dicing the first silicon wafer substrate is one in which the plasticizer does not adhere to the back surface of the first semiconductor chip when peeling from the first semiconductor chip after the dicing process. That is, as long as the dicing tape does not contain a plasticizer, the surface of the tape base material containing polyolefin as a main component does not necessarily have to be applied with an adhesive containing an acrylic adhesive as a main component. For example, tape base materials mainly composed of polyester (polyethylene terephthalate, polyethylene naphthalate, polybutylene terephthalate, polybutylene naphthalate, etc.), ester copolymers (ethylene / vinyl acetate copolymer, ethylene / (meth)) Acrylic acid copolymer, ethylene / (meth) acrylic acid ester copolymer, etc. Tape base material mainly containing polyurethane, tape base material mainly containing polyurethane, tape base material mainly containing ionomer resin, tape base material mainly containing polystyrene, tape base material mainly containing polycarbonate A dicing tape in which an adhesive mainly composed of an acrylic adhesive is applied to the surface of a tape base material mainly composed of a material or a fluororesin may be used.

  Separately from the formation of the first semiconductor chip, a plurality of second semiconductor chips 6 (upper chips) are formed on the second silicon wafer substrate 5, and electrodes (not shown) of the respective second semiconductor chips. A second chip-side bump 7 containing solder as a main component is formed (see FIG. 1D).

  Next, after the back grinding process of the second silicon wafer substrate is performed to reduce the thickness of the second silicon wafer substrate (see FIG. 1E), the polishing process of the back surface of the second silicon wafer substrate is performed. To reduce the roughness of the back surface of the second silicon wafer substrate to 10 nm or less.

  Here, the polishing of the back surface of the second silicon wafer substrate to reduce the roughness of the back surface of the second silicon wafer substrate (second semiconductor chip) to 10 nm or less means that the second silicon wafer substrate ( This is for suppressing the occurrence of cracks in the second semiconductor chip). That is, when the back surface of the second semiconductor chip is rough as the thickness of the second semiconductor chip is reduced, cracks may occur due to unevenness on the back surface of the second semiconductor chip. Accordingly, polishing is performed on the back surface of the second silicon wafer substrate so that the roughness of the back surface of the second silicon wafer substrate (second semiconductor chip) is 10 nm or less, and unevenness on the back surface of the second silicon wafer substrate is formed. By reducing, the crack which generate | occur | produces in a 2nd silicon wafer substrate (2nd semiconductor chip) is suppressed.

  Subsequently, an acrylic adhesive is the main component on the surface of the tape substrate 8a that has the same polyolefin (polyethylene, polypropylene, polybutene, polybutadiene, polymethylpentene, etc.) as that used in the first semiconductor chip. The second silicon wafer substrate is bonded to the dicing tape 8 to which the adhesive 8b is applied, and a dicing process is performed to separate the second silicon wafer substrate into pieces for each second semiconductor chip (FIG. 1 (f)). reference.).

Since the back surface of the second semiconductor chip is not a mounting surface on the mounting substrate, the adhesion of the plasticizer to the back surface of the second semiconductor chip is not regarded as a problem. That is, since the back surface of the first semiconductor chip is mounted on the mounting substrate via the die bond agent, the back surface of the first semiconductor chip and the die bond are caused by adhesion of the plasticizer to the back surface of the first semiconductor chip. Although peeling occurs at the interface with the agent, the back surface of the second semiconductor chip is not the surface on the side mounted on the mounting substrate. Therefore, the adhesion of the plasticizer to the back surface of the second semiconductor chip is regarded as a problem. There is nothing.
Accordingly, a dicing tape for dicing the second silicon wafer substrate includes a plasticizer in the dicing tape (for example, an acrylic adhesive is mainly applied to the surface of a tape base material mainly composed of vinyl chloride. A dicing tape coated with a pressure-sensitive adhesive as a component), or a dicing tape that does not contain a plasticizer (for example, an acrylic pressure-sensitive adhesive mainly on the surface of a tape base material mainly composed of polyolefin). It may be a dicing tape coated with an adhesive as a component.

  Next, the second semiconductor chip is arranged on the first semiconductor chip so that the first chip-side bump and the second chip-side bump are in contact with each other (see FIG. 1G). Heat treatment is performed on the entire semiconductor chip 1 and the second semiconductor chip (heat treatment is performed so that the temperature T at which the first chip-side bump and the second chip-side bump are electrically connected is 300 ° C.) The first chip side bump and the second chip side bump are melted, and the first chip side bump and the second chip side bump are integrated to form a first semiconductor chip and a second semiconductor chip. Are electrically connected to each other (see FIG. 1H).

Here, since the plasticizer is not included in the dicing tape for performing the dicing process of the first silicon wafer substrate, the plasticizer does not adhere to the back surface of the first semiconductor chip. This is because the roughness Ra (2) of the back surface of the first semiconductor chip after chip sorting is 1.1, the roughness of the back surface of the first silicon wafer substrate before bonding to the dicing tape, and after chip sorting. It is also clear from the fact that the roughness of the back surface of the first semiconductor chip is substantially the same (R = {Ra (2) −Ra (1)} / Ra (1) = 0.1).
And since the plasticizer does not adhere to the back surface of the first semiconductor chip, even if the first semiconductor chip and the second semiconductor chip are all heated, the back surface of the first semiconductor chip is The plasticizer is not covered.

  Subsequently, after filling the gap between the first semiconductor chip and the second semiconductor chip with the underfill material 9, the first semiconductor chip is mounted on the mounting substrate 11 via the die bond agent 10, The semiconductor chip and the mounting substrate are electrically connected by the bonding wire 12. Thereafter, the mounting substrate is loaded into a molding die (not shown) composed of an upper die and a lower die, and a molding resin 13 mainly composed of an epoxy resin and an inorganic oxide filler is injected into the molding die. As a result, a semiconductor package as shown in FIG. 1I can be obtained.

  When the moisture absorption reflow test was performed on the 20 semiconductor packages obtained as described above, no peeling occurred at the interface between the back surface of the first semiconductor chip and the die bond agent (in Table 1). See Example 1).

  Table 1 shows the results of manufacturing a semiconductor package and performing a moisture absorption reflow test in the same manner as in Example 1 described above. In Table 1, Example 2 is a case where a dicing tape having an adhesive force of 43 kPa is used for dicing the first silicon wafer substrate, and in Table 1, Example 3 is the case of the first silicon wafer substrate. This is a case where a dicing tape having an adhesive strength of 46 kPa was used to perform the dicing process, and Example 4 in Table 1 used a dicing tape having an adhesive force of 49 kPa for performing the dicing process on the first silicon wafer substrate. Example 5 in Table 1 is a case where a dicing tape having an adhesive strength of 50 kPa is used to perform the dicing process on the first silicon wafer substrate. In Table 1, Comparative Example 1 is a case where a tape base material mainly composed of polyvinyl chloride is used as a dicing tape for dicing the first silicon wafer substrate. This is a case where the polishing process after the back grinding process is not performed.

From Comparative Example 1 in Table 1 above, when a dicing tape containing a plasticizer is used for dicing the first silicon wafer substrate (in the case of a conventional semiconductor package manufacturing method), 20 pieces are used. It can be seen that peeling occurred in two of the semiconductor packages. In contrast, from Examples 1 to 5 in Table 1, when using a dicing tape that does not contain a plasticizer for dicing the first silicon wafer substrate (for the semiconductor package to which the present invention is applied). In the case of the manufacturing method), it can be seen that none of the 20 semiconductor packages peeled off.
That is, by using a dicing tape that does not contain a plasticizer as a dicing tape used for dicing the first silicon wafer substrate, peeling at the interface between the back surface of the first semiconductor chip and the die bond agent is suppressed. I can see that
In Examples 1 to 5, R = 0.1, the roughness of the back surface of the first silicon wafer substrate before bonding to the dicing tape and the roughness of the back surface of the first semiconductor chip after chip sorting. It can also be seen that the substantially same length means that no plasticizer is attached to the back surface of the first semiconductor chip.

In Comparative Example 2, although a dicing tape containing a plasticizer is used as the dicing tape used for dicing the first silicon wafer substrate, the polishing process is not performed. Then, no peeling occurred. As a result, peeling occurs at the interface between the back surface of the first semiconductor chip and the die bond agent due to the polishing process performed to suppress cracks associated with the thinning of the first semiconductor chip. I understand.
In Comparative Example 2, since the polishing process was not performed, peeling at the interface between the back surface of the first semiconductor chip and the die bond agent did not occur, but the polishing process was not performed. ) = 400 nm and Ra (2) = 450, the roughness of the back surface of the first semiconductor chip is rough, and there is a risk of cracks occurring in the first semiconductor chip.

It is a schematic diagram for demonstrating the manufacturing method of the semiconductor package to which this invention is applied. It is a schematic diagram for demonstrating the manufacturing method of the conventional semiconductor package.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st silicon wafer board | substrate 2 1st semiconductor chip 3 1st chip side bump 4 Dicing tape 4a Tape base material 4b Adhesive 5 2nd silicon wafer board 6 2nd semiconductor chip 7 2nd chip side bump 8 Dicing tape 8a Tape base material 8b Adhesive 9 Underfill material 10 Die bond agent 11 Mounting substrate 12 Bonding wire 13 Mold resin

Claims (3)

Forming a plurality of first semiconductor chips on a wafer substrate;
Forming a first protruding electrode on the first semiconductor chip;
Bonding the wafer substrate to a dicing tape, and dividing the wafer substrate into pieces for each of the first semiconductor chips;
Disposing a second semiconductor chip having a second protruding electrode formed on the first semiconductor chip such that the first protruding electrode and the second protruding electrode are in contact with each other;
Melting and integrating the first protruding electrode and the second protruding electrode by heat treatment, and electrically connecting the first semiconductor chip and the second semiconductor chip;
Mounting the first semiconductor chip electrically connected to the second semiconductor chip on a substrate via a die bond agent, and sealing the first semiconductor chip and the second semiconductor chip; In a method for manufacturing a semiconductor device comprising:
The dicing tape is configured such that the rear surface roughness of the first semiconductor chip after peeling the back surface roughness and the dicing tape of the wafer substrate before the images stuck to the dicing tape is substantially the same,
The back surface roughness of the first semiconductor chip is 1.0 nm or less;
The step of electrically connecting the first semiconductor chip and the second semiconductor chip is such that the temperature at which the first protruding electrode and the second protruding electrode are electrically connected is 300 ° C. A method for manufacturing a semiconductor device, wherein heat treatment is performed . The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing a back surface polishing process in which the back surface roughness of the wafer substrate is equal to or higher than a predetermined flatness. The dicing tape comprises a dicing tape base material and an adhesive applied to the surface of the dicing tape base material, and the dicing tape base material is polyolefin, polyester, ethylene copolymer, polyurethane, ionomer resin, polystyrene, polycarbonate or 2. The method of manufacturing a semiconductor device according to claim 1, wherein any one of fluororesins is a main component.

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