TWI240392B - Process for packaging and stacking multiple chips with the same size - Google Patents

Abstract

A process for packaging and stacking multiple chips with the same size is disclosed. A partially-cured resin is coated on a wafer, and then the wafer is cut to form a plurality of chips. The partially-cured resin under one of the chips is bonded to a substrate or an active surface of another lower chip. A plurality of bonding wires electrically connect the chip with the substrate. Each bonding wire has a ball end bonded on the substrate and a wiring end bonded on the active surface of the chip. During chip-to-chip stacking, the partially-cured resin between the two chips is melted under heat to seal the wiring ends, so that the wiring ends breaking will not easily occur during molding. Moreover, more chips with the same size can be stacked in a limited package thickness.

Description

1240392 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a multi-chip stacking and sealing process including wafer dicing, and particularly relates to a packaging process of stacking wafers with the same size. [Prior art] The conventional multi-chip stacked package is a method of stacking a plurality of semiconductor wafers of the same size on a substrate one by one, and the main surface of the semiconductor wafers is facing up to facilitate wiring, and soldering formed by wiring The wire system electrically connects the wafers to the substrate, such as the technique disclosed in U.S. Patent No. 5, 3,23,006. &Quot; f 'In order to prevent the bonding wires from being pressed by the stacked wafers above, A spacer should be provided between the sheets. The height f of the spacer material should be higher than the arc height of the same layer of welding wire. This spacer material can be conventionally known as polyimide tape (PI tape), Virtual chip (dummy chip): Metal sticker: 151 ^ 1 ^ 2, etc., the spacer material is pre-adhered to the ΪΠ: active surface before wiring, but the size of this spacer material must be the small active surface. The solder exposed on the wafer below can only make the ===, which causes the spacer material to support the wire bonding around it. Therefore, the thickness of the ± 4 crystals is sufficient. It is also not possible to use thin materials as a necessary technical means. The number of spacer wafers varies. u You can stack within the thickness of the seal. Please refer to Figure 1, currently made! In-predetermined thickness of the seal :: use package :; 〇a ΰ ^ One of the first day of the first day of the 4th day of the 10th film 12 series stick to the 1240392

V. Description of the invention (2) The upper surface 31 of one of the substrates 30, and a plurality of bonding pads 13 are formed around the -active surface n of the -wafer 10, as in the case of _ u u ㈤η η 逯 is the first The active surface of the sheet 10 is "the sheet / spacer material 50 is attached to the auxiliary surface 11 without covering the solder pads 13 and then 3". The bonding pad 23 connecting the first wafer 10 to the substrate two spacer material 50 is a wire arc that is higher than the bonding wires 4: 4 people 20 pieces. In addition, each i line 40 has a -knot y, ^, And it is known that the nodular ends 41 are formed on the first crystal chip 13 'these wire tail ends 42 are formed on the substrate 30: Tan 2 the spacer material 50 has a considerable thickness to make it It is higher than f; two: ㈣of f two "One of the back surface 22 of the second wafer 20 is adhered to the :, it is known that a plurality of pads 23 of the second wafer 20 are formed on the first 6 0 1 The periphery of the active surface 2 丨 and a plurality of bonding wires = 塾 23 to the upper surface 31 of the substrate 30. Due to the formation area of the second crystal bonding pad 23, it is not possible to obtain two of the spacer material 50. ^ ^ ^ Therefore, the second wafer 20 has a considerable thickness to avoid J ^ causing the second wafer 20 to break when forming the bonding wires 60 to prevent the problem of connection failure, the first After the wafer 10 and the second wafer 20 are electrically connected to each other, they are conventionally sealed with a gel 30, so the number of wafers that can be stacked within a predetermined package thickness is limited. China's Patent Bulletin No. 563 900 "The chip stack of the universal chip specification is dead, revealing another conventional multi-chip stacked package structure, which is stacked on a substrate with ^ eight charges and bonded with a wire. Connected, a spacer layer covers the active surface of the first chip to fix one end of the bonding wire (knot ball)

1240392 V. Description of the invention (3) end) In order to reduce the occurrence of punching lines, it is known that the ball end of the welding wire has a strong bonding strength. It is still possible that the ball end of the welding wire covered with the spacer layer is covered by the welding Punching occurs at the end of the line. In addition, since the spacer layer needs to be repeatedly formed by printing or coating after each sticking and wire bonding, it increases the lamination step and the flatness of the spacer layer. And thickness cannot be controlled uniformly

And the spacer layer does not have adhesiveness after curing, an additional tape must be pasted on the upper surface of the spacer layer for a second wafer to be stacked; when more wafers are stacked, the position and level of the bonding pads for wire bonding The more difficult it is to be controlled, in addition, to form a spacer layer by printing or coating on the active surface of the finished wafer. The jigs (such as stencils) that form the spacer layer must avoid the soldering. Line, and it is difficult and unavailable to form a spacer layer of the appropriate area on the active surface of the wafer. [Summary of the invention] The main purpose of the present invention is the packaging process. On the back of the semi-cured tree wafer, an active surface of the semi-cured surface is formed, and a bonding pad is used to lower and cover the bonding wire surfaces to replace Known materials, so in order to seal the sheet, and to promote the end of the first and the plurality of bonding wire arcs of a wafer cutting resin according to the present invention, multiple wafers of the same thickness with some bonding wires in the thickness are required. It is formed in a plurality of wafers. After the wafer is cut into a plurality of wafers, a wafer is bonded to a substrate or a wire end of the wire is connected to the high, and the semi-cured resin is formed on the first wafer process before it can be formed. The large thickness simplifies the steps of stacking more wire end fixing forces. Packaging process for size stacking. The size of the round stack size is one of the second wafers. The number of active spacers that are melted by the wafer mainly includes 1240392. 5. Description of the invention (4) Yes: Provide half of the surface, and the active surface forms half. Solidify to form the back grease of a wafer of the same size; then, connect the first wafer end and a wire tail end from the back to a substrate; the wire tail end is set on the semi-cured active surface of the wafer, wherein the wire tail end; The substrate, the ends, the balls are heated on the second wafer to melt the half and the second wafer, which has a polycrystalline effect. [Embodiment] Referring to the attached FIG. 2A of the present document, first, a wafer region of a conductor wafer has resin on at least one of the first and second crystals and the top surface of the first wafer; and the substrate, the The balls are bonded to the first wafer resin and bonded to the semi-cured tree. Then, each of the first ends is fixed to the solder-cured resins to form a stack, which fixes the inner circle of the wafer. The back of a wafer chip is semi-fixed, wherein each of the second crystalline lipids is supported on several first-crocodile wire substrates, and later, a multi-wafer fixed wire system has an active A surface and a plurality of bonding pads; a surface; and then forming a resin bond with at least one side respectively, cutting the first wafer to form the half-connected first with a plurality of first bonding wires and a first bonding wire having above The surface is on the substrate pad; the backside of the sheet is hot-melted and the two-bond wire electrical system has an upper surface, and the end of the wire with a colloid of the same size is repeatedly applied, and then the first cover is connected to the Knot ends and the line ends The first package and the second package are stacked and sealed. Then, the wafer, and the first cured tree wafer are electrically connected with a ball, and the first soldering of the second wafer and the second line end of the second wafer are provided with the wafer and • The U-chip structure, the crystal step pattern, the present invention will list a number of wafers with the same size, and provide a semiconductor crystal to illustrate the following examples. Stacked packaging process, please refer to Round 110 ’This wafer 11〇 has

1240392 V. Description of the invention (5): active surface 111 and a back surface 丨 2; a plurality of integrated circuit elements (not shown) and a plurality of solder pads 113 are formed in the chip area of the active surface i U The active side 111 of the 5 xuan wafer 110 is placed on a wafer carrier 210, facing down, as shown in FIG. 2B. A wafer back grinding tool 220 is used to polish the back surface 1 1 2 of the wafer 1 1 2 to make the crystal The thickness of the circle 丨 丨 〇 reaches, for example, 6 to 5 m 1 (mil, 1 to ni 1 is approximately equal to 25.4 micrometers). Next, refer to the 2C and 2D drawings to form a semi-cured resin. 22 is formed on the back surface of the edge wafer 110. 12 First, spin coating or printing is used to apply a glue tool 2 3 0. Uncured resin 121 ′, such as B-St age resin, is applied to the back surface 112 of the wafer 110 in a liquid or gel state. Please refer to FIG. 2D again, under the action of a baking device 240 or an irradiation device. The uncured resin 1 2 1 is partially polymerized into a semi-cured resin 丨 2 2. The semi-cured resin 1 22 will exhibit a semi-solid film and a thick paste at different temperatures. The thickness of the semi-cured resin 1 2 2 is based on Between 3 ~ 8 mi 1 is better. Next, please refer to FIG. 2E. On the back surface 11 2 of the wafer 11 〇, a dicing tape 2 50 is used to stick the semi-cured resin 1 2 2, and then the wafer 110 is cut. A cutting tool 260 cuts the wafer 110 to form at least one first wafer 1 j 4 and at least one second wafer 1 1 5 ′ in the same size. In this embodiment, the wafer 1 10 is cut into one wafer. Examples of the first wafer 114, a second wafer 1 15, a third wafer 1 16 and a fourth wafer 117, and the back of each wafer (including the back of the first wafer ii 4 ji) 2a and the back surface 11 2 b of the second wafer 11 5 are respectively formed with the semi-cured resins 122 a and 12 2b, and the active surface of each wafer (including the active surface 111 a of the first wafer 114 and the second wafer 115 The active surfaces (lllb) are respectively formed with complex

Page 11 1240392 V. Description of the invention (6) Several pads 1 1 3 a and 1 1 3 b. Of course, in different embodiments, a first wafer 1 4 and a second wafer 1 15 can also be divided from two different wafers, and the semi-cured resin is formed on the back surface of each wafer. Among them, the size of the first wafer 1 1 4 and the second wafer 1 15 are approximately the same, or the first wafer j j 4 is slightly larger (smaller) than the second wafer 1 1 5. Next, referring to FIG. 2G, the semi-cured resin 1 2 2 a below the first wafer 丨 4 is bonded to the back surface 11 2 a of the first wafer 11 4 to the upper surface 1 31 of a substrate 130, The substrate 130 may be a circuit board made of ceramic, glass fiber reinforced resin, or polyurethane. In this embodiment, the substrate 130 is a ball grid array package substrate. On the substrate 130, the surface 131 and A connection pad 132 and a ball-receiving pad (not shown) are formed on the lower surface, respectively. In addition, conventional adhesive or tape may be used to adhere the first chip i 丨 4 to the substrate 130. Next, make a wire connection between the first chip Π4 and the substrate 3 (). In this embodiment, before the wire is formed to form a plurality of first bonding wires 14, please refer to FIG. 2H. A plurality of stud bumps 143 (stud bumps) are formed on the welding pads 113 & of the film 114 to facilitate the bonding of the wire ends 142 of the first welding pads 140; then, refer to FIG. 21 to The first solder pads 140 are electrically connected to the first chip 114 and the substrate 13.

=, 140 has a knot end i4i formed at the beginning of a hit line and a tail end 142 formed at the start of the hit ^. These knot ends 141 are provided on the upper surface of the base plate 1 31, and the end ends of these strands 14 2 is provided on the first wafer 11 4 j, and some of the first-bonding wires 140 are formed on the first wafer 3 3a, and have lower foxes.

Page 12 1240392 V. Description of the invention (7)

Next, referring to FIG. 2J, the semi-cured resin 1 22b below the second wafer 115 is used to adhere the back surface 11 2b of the second wafer 115 to the active surface 1 1 ia of the first wafer 114, where The semi-cured resin 22b is heated and melted to cover the wire ends 1 42 of the first bonding wires 1 40. In this embodiment, the temperature of the semi-cured resin 122b is about 11 °. ~ 150 ° c, so in a single stacking step, only the appropriate heating is needed. The semi-cured resin 1 2 2 b will adhere to the active surface 111 a of the first wafer 114 and cover the end of the first bonding wires 140. The end 1 4 2 omits the conventional spacer material forming step after wafer stacking and wire bonding. In addition, the semi-cured resin 1 22b covers the pads H3a of the first wafer 114 and can completely cover the first wafer. The active surface 111a of 114 provides good wire support for the second chip 115, so the first chip 115 can have a thinner thickness (for example, it can be as thin as 6 to 15 m1). Preferably, the semi-cured resin 1 22b may also be relatively thin. In this embodiment, at least some of the first bonding wires 1 40 may contact the back surface 112b of the second wafer 115. Next, referring to FIG. 2K, the second chip " 5 and the substrate 130 are electrically connected by a plurality of-鋥 蝮 ho, and a plurality of nodular bumps can also be formed in the pad 11 3b of the same. In order to facilitate the bonding of the wire ends 152 of the second bonding wires 150, and the ball end 151 of the second bonding wires 150 are also formed on the upper surface 131 of the substrate 130; please refer to FIG. After grounding, stacking the wafers and heating and melting the semi-cured resins 122a and 122b, the third wafer 116 can be quickly stacked again with the package thickness of this embodiment, and the third wafer 116 can be connected with the third bonding wire 160. And the substrate 130, and a fourth wafer 117 can be stacked on the substrate 130, the fourth wafer 117 and the substrate 130 are connected by a fourth bonding wire 170, and finally, a piece of gel

Page 13 1240392 V. Description of the invention (8) I 8 0 seals the first wafer 11 4, the second wafer 1 1 5, the third wafer II 6, the fourth wafer 1 1 7 and the first solder Wire 1 4 0, the second bonding wires 1 50, the third bonding wires 1 6 0 and the fourth fresh wires 1 7 0, and the semi-cured resins 1 2 2 a, 1 2 2 b Simultaneous curing into individual fully cured resins 1 2 3 to form a multi-chip stacked package structure of the same size, to achieve the effect of stacking a large number of wafers, fixing the end of the wire and reducing the step of stacking. 0 In addition, this Invention of the first bonding wire 1 40 for connecting the first chip 丨 4 and the substrate 丨 3 〇, which can use the aforementioned reverse wire method, can also use

Kulicke & Soffa's previous folding wire bonding process (Forwar (j Folded Loop Bonding Process; F2 bonding process). In this wire bonding method, the bonding wire is:-the bonding point is located on the wafer pad, and the second bonding point is located on the base 2 at: The t-type wire bonding process has the advantage of low arc height (10W 100), and is applicable to the multi-chip stacking packaging process of the present invention. In order to make any changes and modifications made within the scope defined by the back wall, Belong to the present invention

1240392 on page 14 Brief description of the drawings [Simplified illustration of the drawings] Figure 1: A cross-sectional view of a conventional multi-chip stacking structure with the same size; Figures 2A to 2K: A multi-chip stacking process with the same size according to the present invention. A schematic cross-sectional view of a wafer or a diced wafer during the manufacturing process; and FIG. 3 is a schematic cross-sectional view of the packaging structure of a multi-chip stacked stack of the same size according to the multi-chip stacked stack packaging process of the present invention. Brief description of component symbols: 1 Multi-chip stacked package structure of the same size 10 First chip 11 Active surface 12 Back surface 13 Welding pads 20 First --- wafer 21 Active surface 22 Back surface 23 Welding pads 30 Substrate 31 Upper surface 40 Welding wire 41 Ball end 42 Line tail 50 Spacer material 51 Adhesive layer 60 Welding wire 70 Sealant 110 Wafer 111 Active face 111a Active face of first wafer 111b Active face of wafer 112 Back side 112a Active face of first wafer 112b Second wafer Back surface 113 pad 113a pad of the first wafer

Page 15 1240392_ Brief description of the diagram 113b Pad for the second wafer

Page 16 114 First wafer 115 Second wafer 116 Second wafer 117 Fourth wafer 121 Uncured resin 122 Semi-cured resin 122a Semi-cured resin under the first wafer 122b Semi-cured resin under the second wafer 123 Fully cured resin 130 Base plate 131 Upper surface 132 Connection pad 140 First fresh line 141 Ball end 142 Line end 143 Ball end bump 150 Second wire 151 Ball end 152 Line end 153 Ball end bump 160 Third wire 170 Fourth wire 180 Sealant 210 Wafer stage 220 Grinding tool 230 Gluing tool 240 Baking device 250 Cutting tape 260 Cutting tool

Claims (1)

1240392 [Scope of patent application] 1. Two kinds of multi-chip stacked packaging process including: providing a semiconductor wafer, the wafer has an active surface and a back surface, and a plurality of wafers are formed in the area of the active surface Forming a half-cured resin on the back surface of the wafer; cutting the wafer to form at least one first wafer and at least one second wafer; a side surface of the wafer and a back surface of the second wafer are formed respectively Having the semi-cured resin; adhering the first wafer to an upper surface of a substrate; and electrically connecting the first wafer and the substrate with a plurality of first bonding wires, wherein ， and a fresh wire have a knot end and A wire tail end, the nodule ends δ are on the upper surface of the substrate, and the wire tail ends are provided on the pads of the first wafer; the semi-cured resin of the second wafer is used to bond the second wafer The back surface to the active surface of the first chip, wherein the semi-cured resin is heat-melted to cover the wire ends of the first bonding wires; and-electrically connecting the second chip and the substrate. 2. "Packaging and packaging of multiple wafers of the same size as described in item 1 of the scope of patent application" wherein the first wafer is adhered to the substrate with a semi-cured resin on its back. 3. The packaging process of multi-wafer stacking of the same size as described in item 2 of the scope of the patent application, further comprising: simultaneously curing the semi-cured resin under the back surface of the first wafer and the semi-cured resin under the back surface of the second wafer. 4 'Seal with multiple wafers stacked in the same size as described in item 1 of the patent application scope Page 12 1240392 6. Scope of the application for patent Application: One step of electrically connecting the second chip and the substrate is to connect the second chip to the substrate. The first fresh wire is a bonding pad that connects the substrate to the second chip. Yishen; =: = 1 The multi-chip stacking of the same size as the first item is sealed. Before the electrical connection step of the first θ ′, the first bonding wire, bump) to bond the wires of the first bonding wire. Tail end. Two: d; the multi-chips described in item 1 or 5 are stacked on the back of the same size, and at least one of the first bonding wires is in contact with the second chip. The multi-chip stacking seals of the same size include: grinding the back surface of the semiconductor wafer to reduce the thickness of the first wafer and the second wafer.飒 ^ The manufacturing process of the multi-chip stack with the same size as described in item 1 of the patent application range, wherein the thickness of the semi-cured resin is 3 to 8 mils. According to the multi-chip and same-size packaging process described in item 丨 of the patent application scope, the temperature at which the semi-cured resin is melted by heating is 150 ° c. Meaning τ, ... 10. The packaging process of multi-chip stacking with the same size as described in item i of the patent application, which further includes: forming a colloid to seal the first wafer and the second wafer. 11. A multi-chip stacked packaging process, comprising: providing a first semiconductor wafer and a second semiconductor wafer, the wafers respectively having an active surface and a back surface, and the wafer area of the active surface is Forming a plurality of fresh pads; r Page 18 1240392 6. The scope of the patent application forms half of the cured resin on the back of these wafers; a semiconductor wafer to form a plurality of first wafers, and a conductor wafer 'to form a pole number of second wafers, etc. The semi-cured resin is formed on the crystal; the upper surface of the substrate; the ball end and a wire tail end of the first wafer and the substrate are sexually connected, and the ball end and the wire tail end are arranged on the first wafer; The back side of the first cut second half piece is respectively adhered with the first plurality of wafers to the first bonding wire. Each of the first bonding wires is provided on the substrate pad; the second active surface, wherein The electrical end of the line; electrical connection, such as the application of the 12th process board, 13 procedures, such as the application, which also contains grease and the second crystal 14, such as application for the special process, in which the first fresh wire is connected to 15, such as Apply for a special trip, in which the semi-cured tree on the top surface, the back of the wafer, and the second wafer are in the profit range 1 1 The first wafer is in the profit range 1 2 Yes, the profit range under the back of the solid wafer is at the same time 1 1 Connect this The substrate is connected to a first range of interest of the plurality of first solder 11 The grease of the semi-cured resin adhered to the first wafer is melted by heat to cover the first solder and the substrate. The package of the multi-chip stack described in the item The back-cured resin of the multi-chip stack described in the item is bonded to the semi-cured resin of the first wafer under the package of the multi-chip stack described in the item. The step of packaging the t-chip and the substrate as described in the multi-chip stack of the item, a plurality of second-chip bonding pads. Before the step of electrically connecting the packaging lines of the multi-chip stack described in item 1, on page 19, 1240392 VI. Patent application scope, a plurality of stud bumps are formed on the pads of a chip, In order to facilitate joining the tail ends of the first bonding wires. 16. The packaging process of multi-chip stacking as described in the scope of the patent application, wherein at least one first bonding wire is in contact with the back surface of the second chip. 17. According to the multi-wafer stacking method described in item 丨 丨 of the patent application scope, it further includes: grinding the back surfaces of the semiconductor wafers to reduce the thickness of the first wafer and the second wafer. 18. The packaging process of multi-chip stacking as described in item 丨 丨 of the scope of patent application, wherein the thickness of the semi-cured resin is 3 to 8 m. 19. The multi-chip stacking package as described in item 丨 丨 of the scope of patent application, wherein the temperature of the semi-cured resin being melted by heat is between 1 10 and 150 ° C. 20. The multi-chip stack packaging system described in item 丨 丨 of the patent application scope, further comprising: forming a colloid to seal the first chip and the 21, a multi-chip stack packaging process, Contains:-j, a first wafer and a second wafer, the wafers have an active surface and the active surface of the wafer is provided with a plurality of welding pads, and the back of these wafers is provided with half of the cured resin; A semi-cured resin on the back surface of the first wafer is used to adhere the first wafer to the upper surface of a substrate; the forward folding wire bonding process (Forward Folded Loop Bonding Process) electrically connects the plurality of first bonding wires to the first wafer. The pads and the upper surface of the substrate; 1240392 6. The scope of the patent application is based on the second active surface, one of which; and 22 if the electrical connection is for a special trip, it also includes: providing a first circle system having a plurality of lines forming the above-mentioned cut, the second cut, and the second half The back side is respectively 2 3. If applying for a special trip, it also includes: providing a half plane 'the active side forms a half cut the crystal. The second crystal mentioned above is formed with the 24, if applying for a special trip', it further contains a fat and the second crystal. 1 = The semi-cured resin on the surface is connected to the semi-cured tree of the first wafer. The purpose of the semi-cured tree is to make the hot-melt and cover the first bonding wires, the second wafer, and the substrate. The two-semiconductor wafer and one second semiconductor wafer of the multi-chip stack package described in Item ^, the active side and a back side of the wafer factory, a pad on the active area of the wafer area; semi-cured resin On the back of the wafers; and a semiconductor wafer to form the first wafer described above, and a conductor wafer to form the second wafer described above, the crystals are formed with the semi-cured resin. The multi-chip-stacked packaged conductor wafer described in Item 21, the wafer is a wafer area having an active side and a back side, and a plurality of bonding pads are formed in the wafer area; the cured resin is formed on the semiconductor wafer. A back surface; and a circle to form at least one of the above-mentioned first wafer and at least one sheet, and the back surface of the first wafer and the back surface of the second wafer are semi-cured resin. The multi-chip stack packaging system described in the benefit range item 21 includes: simultaneously curing the semi-cured resin under the back of the first wafer and the semi-cured resin under the back of the wafer. Page 12 1240392 25. = Please refer to the multi-chip stacking process described in item 21 of the patent scope, wherein the second crystal wire and the second bonding wire are electrically connected to the substrate to the second crystal;; In the multi-chip stack packaging process described in the multiple patents W21, the first bonding wire is in contact with the back surface of the second chip. Second, the thickness of the sealed wafer and the second wafer of the multi-wafer stack described in the 211th member of the scope; to reduce the multi-wafer stack described in the 21st item of the 21st patent scope In the package system, the thickness of the semi-cured resin is 3 to 8 m. 2. The multi-chip stacked packaging system described in item 21 of the patent application scope, wherein the temperature of the semi-cured resin is heated and melted between 丨 丨 ～ 150 〇c. The described multi-chip stack packaging process further includes: forming a gel to seal the first chip and the second chip.