JP4298079B2 - Synchronization holding circuit - Google Patents

Description

により算出する。ここで、変数n は0, 1, 2,・・・, (k-1)の符号番号で、変数N は任意の自然数である。
【００４２】
なお、サンプリング系列r[t]は、受信系列14A の値R[t]の確率的な表現で、この値は２値に限定されない。
【００４３】
次に相関長 kΔの関係について説明する。説明を簡単化するため、それぞれ、サンプリング系列r[-aΔ] から r[(k-1-a)Δ] 、r[+aΔ] から r[(k-1+a)Δ] 、同期系列において相関長毎に繰り返される符号をS[0]からS[k-1]を用いて相関を求める。すなわち、処理開始するオフセット分を表す変数N をゼロに設定する。これにより、式(1) および式(2) は
【００４４】
【数２】

と簡略化することができる。相関値C₁, C₂はそれぞれ、 k個のサンプリング系列と受信系列の乗算結果の総和として算出される。
【００４５】
ここで、相関長 kΔ毎に符号が繰り返されることから、任意の時刻t における符号を符号番号n で表すことができる（剰余として、 n＝mod(N, kΔ) ）。これにより、受信系列R[n]、同期系列S[n]は、k 個で表すこともできる。
【００４６】
相関値C₁から相関値C₂を減算すると、式(3) および式(4) を用いて、式(5)
【００４７】
【数３】

により相関長 kΔ分の相関値の差C_Dが得られる。この相関値の差C_Dから同期タイミングの補正について説明する。相関値の差C_Dが一致しているとき、図５の受信系列14A の符号境界を同期タイミング位置S_t（矢印A ）にとっている。この関係を相対的に時間に対する相関値で模式的に表すと、同期タイミングは図６(a) に示す位置S_tに設定することが判る。
【００４８】
ところで、同期保持のモードでは算出した相関値の差C_Dがゼロでない値をとる場合がある（図６(b) を参照）。時間に対する相関値の曲線60は実線で示すように実際、平行移動はしない。しかしながら、受信系列と同期系列の同期関係に着目して見ると、破線で示す相関値の曲線62で同期をとった場合に相当している。このときの同期タイミングは位置S_fになる。同期に関して先の一致した位置S_tと位置S_fの差が同期のずれΔ_s である。図６(b) の場合、受信系列14A に対して同期系列の同期が遅れたタイミングにあることを示している。同期のずれΔ_s は、たとえば同期のずれ方向を正負の符号で表すことができる。本実施例では制御値算出部204 において供給される相関値の差C_Dから同期のずれΔ_s を換算するとともに、同期のずれΔ_s を補正するように制御値を生成する。また、同期のずれ方向を戻すように一定の制御値を出力するようにしてもよい。発振器16は、供給される制御値に応じて発振周波数を変化させる。符号発生器18は、前述したように発振器16からの信号をタイミングにして符号発生するので、受信系列と同期系列との同期を保持するように動作することになる。
【００４９】
次により具体的な同期保持回路20c の第１の実施例について図７を用いて説明する。本実施例は、同期保持回路20c のうち、相関値計算部202 の特徴を説明する。相関値計算部202 には、セレクタ202a、系列カウント制御部202b、乗算器202cおよび累算部202dが備えられている。
【００５０】
セレクタ202aは、２入力１出力を切替信号に応じて切り替えるスイッチである。本実施例でセレクタ202aは、符号発生器18からの同期系列18A とこの同期系列18A を遅延反転させた同期系列18B が供給される。セレクタ202aは、乗算器202cに選択を出力する。系列カウンタ制御部202bは、同期系列カウンタを含む。図２に図示していないが系列カウンタ制御部202bには、同期系列カウンタの初期値20A とともにクロックが供給される。初期値20A は開始時の符号の系列番号n である。系列番号n は相関長 kΔ内（ k個）のいずれか一つが該当する。系列カウンタ制御部202bは、セレクタ202aに供給する切替信号を出力する。切替信号は、 1/2Δ毎に選択対象を切り替える。
【００５１】
乗算器202cは、２入力の信号に乗算を施す演算回路である。２入力は、それぞれ受信系列14A と同期系列18A, 18Bのいずれか一方の選択された同期系列である。乗算器202cは、このように乗算することで相関値C₁, -C₂ を交互に累算部202dに出力する。累算部202dは、加算器2020および累算器2022を含む。特に、累算器2022は、累算結果を一時保持し、乗算器202cからの出力が加算器2020の一端202A側に供給された際に同期して保持した累算結果を加算器2020の他端202B側に出力する。累算器2022は、あらかじめ設定した累算回数を終了すると、相関値の差の総和が得られる。これらを含む相関値計算部202 は、この算出した相関値の差C_Dを制御値算出部204 に出力する。
【００５２】
前述した原理で相関値の差C_Dは、乗算結果の総和で表される相関値C₁, C₂をそれぞれ、求めた後、相関値C₁, C₂の差を演算する手順を説明した（式(5) を参照）。しかしながら、演算の手順は、この方法に限定されるものでなく、交互に得られる相関値C₁, C₂を算出し、相関値C₁, C₂の所定の回数の累算結果から、相関値C₁, C₂の差を求めても同じ結果が得られる。この後者の関係は式(6)
【００５３】
【数４】

で表される。式(6) は、前述した式(5) を整理した形式である。ここで、変数m は系列カウント制御部202bの切替信号に対応し、セレクタ202aの出力選択を行っている。本実施例において、符号周期は 1Δで２倍のオーバーサンプリングを行っていることから、相関演算は、Δ/2以内に行うとよい。
【００５４】
セレクタ202aから供給される同期系列と受信系列14A を乗算器202cで乗算すると、個々の対の相関値を算出することになる。累算部202dでこの相関値に付された符号を考慮して加算し、累算すると、相関値の差C_Dが一つの相関値計算部202 で得られる。これにより、回路構成の冗長性を改善することができる。さらに、回路規模の縮小により、消費電力も抑えることができるようになる。
【００５５】
次に同期保持回路20c の第２の実施例について図８を参照しながら説明する。先の実施例の構成要素と共通する部分には、同じ参照符号を付して説明を省略する。同期保持回路20c の特徴である本実施例の相関値計算部202 には、セレクタ202a、系列カウント制御部202b、乗算器202cおよび累算部202dの他に、倍数器202e、セレクタ202f、固定値出力部202g、セレクタ202h、および比較回路202iが備えられている。
【００５６】
倍数器202eは、入力を２倍にする演算器である。入力信号が符号系列のようにディジタル信号の場合、倍数器202eにはシフトレジスタが用いられる。特に、２値符号に適用するとき、シフトレジスタは桁を上位の桁に１つシフトさせるだけで容易に出力を２倍のデータにする。倍数器202eには、受信系列14A が供給される。倍数器202eは、出力端とセレクタ202fの入力端を接続している。
【００５７】
セレクタ202f, 202hは、ともに２入力１出力の切替スイッチである。セレクタ202hについては後段でさらに説明する。セレクタ202fは、受信系列14A を入力端の一方の側に入力し、他方の側の入力端が倍数器202eと接続関係にある。セレクタ202fは、セレクタ202aと同様に系列カウント制御部202bからの切替信号に応じて切り替えを行うように構成されている。ただし、図８に示すように系列カウント制御部202bが、たとえば、カウント値をセレクタ202a, 202fに出力するだけのような場合、セレクタ202fは、単なる切替スイッチではなく、カウント値に応じて出力を選択する機能を有していることは言うまでもない。セレクタ202fは、出力端と乗算器202cの一端20C 側とをつないでいる。固定値出力部202gは、あらかじめ設定した値だけを出力する回路である。設定する値としては、「0 」である。
【００５８】
セレクタ202hは、セレクタ202hの一方の入力端20D と乗算器202cの出力端を接続し、セレクタ202hの他方の入力端20E と固定値出力部202gの出力端を接続している。セレクタ202hは、この入力した乗算器202cの出力と固定値出力部202gの出力を比較回路202iからの切替信号に応じて切り替えて、累算部202dに出力する。
【００５９】
比較回路202iは、２つの信号を比較し、比較結果が等しいかどうかに対応した信号を出力する回路である。本実施例では、比較回路202iには、同期系列18A, 18Bが供給される。比較回路202iは、同期系列18A, 18Bの符号をΔ/2毎に比較し、比較結果に応じた信号をセレクタ202hの切替信号としてセレクタ202hに出力する。
【００６０】
本実施例における相関値計算部202 の動作を説明する。受信系列14A は倍数器202eとセレクタ202fに供給される。倍数器202eで２倍にした受信系列14B がセレクタ202fに供給される。系列カウント制御部202bに供給される初期値20A に応じて切替信号を生成する。初期値20A がたとえば、系列番号n において、 n＝0 （初項）または n＝k-1 （終項）のとき、受信系列14A をそのまま出力するように系列カウント制御部202bで切替信号が生成される。系列番号 n≠0 ≠k-1 のとき、倍数器202eからの受信系列14B を出力するように系列カウント制御部202bで切替信号が生成される。
【００６１】
この切替信号は、セレクタ202aにも供給されている。セレクタ202aは供給される切替信号に応じて同期系列18A, 18Bのいずれかを選択する。同期系列18A, 18Bの互いの周期の差を 1Δとする場合、２倍のサンプリングしているのでサンプリング間隔a はΔ/2になる。したがって、 1Δを2aΔで表すことができる。この関係を用いれば、[(n+1-a)Δ] ＝[(n+2a-a) Δ] ＝[(n+a)Δ] と整理される。サンプリング値r[t]は、これにより、
【００６２】
【数５】

になる。
【００６３】
この関係にあるとき、図５の各系列のタイミング関係を見ると、一致している区間と一致していない区間とがある。それぞれの区間での相関値を算出し、この相関値の差C_Dを求めると、式(8)
【００６４】
【数６】

という式になる。サンプリング系列と同期系列18A の相関において、第１項は初項の相関、第２項は、符号の系列番号 n＝1 〜(k-1) までの和により相関値C₁を表している。また、第３項および第４項はそれぞれ、サンプリング系列と同期系列18B の相関における系列番号 n＝0 〜(k-2) までの(k-1) 個の相関と終項(k-1) の相関を表している。したがって、相関値の差C_Dは、第１および第２項の和と第３および第４項の和との差で表される。
【００６５】
式(8) の第２項を第３項の総和の範囲に合わせると、相関値の差C_Dは、
【００６６】
【数７】

と変形した第３項を含む式(9) が得られる。この式(9) に前述した式(7) の関係を適用すると、式(9) は、
【００６７】
【数８】

にまとめることができる。式(10)の第３項に着目して、サンプリング系列と同期系列18A, 18B、それぞれの相関が等しいとき、第３項の相前後する符号S[n+1], S[n]の差はゼロになる（S[n+1]-S[n] ＝0 ）。また、この相前後する相関が異なるとき、第３項の相前後する符号S[n+1], S[n]の差を1 にする（S[n+1]-S[n] ≠0 ）。この関係をまとめると、式(11)
【００６８】
【数９】

で表される。
この関係式(11)を式(10)に適用すると、式(12)
【００６９】
【数１０】

が得られる。
【００７０】
式(12)を実現するように、セレクタ202fは供給される式(12)の第１項および第２項に対応した受信系列14A と、第３項に対応した受信系列14B とを選択して乗算器202cに出力する。受信系列14A はサンプリング系列に相当している。乗算器202cには、セレクタ202aにより選択した同期系列が供給される。供給される各系列の乗算を行うとともに、式(12)の第３項のδに対応する処理を比較回路202iで行う。比較回路202iではこの比較に同期系列18A, 18Bを用いている。この比較回路202iでは、相前後する符号の値の比較結果がセレクタ202hに供給される際に、セレクタ202hでは相関値が同じになる場合、固定値出力部202gの出力「0 」が選択され、それ以外のとき乗算器202cの出力が選択される。累算部202dでの累算により相関値の差C_Dが得られる。この構成では、先の実施例における2k回 /Δの演算に比べて式(12)から明らかなように(k+1) 回/ Δで済ませることができる。これにより、消費電力の削減が可能になる。
【００７１】
この第２の実施例の変形例について図９を参照して説明する。この変形例の相関値計算部202 は、図９に示すように第２の実施例の構成のうち、セレクタ202a, 202fが省略された構成である。参照符号は同じものを用いている。相関値計算部202 において乗算器202cには、受信系列14A に倍数演算が施された符号系列と同期系列18A とが供給される。乗算器202cの乗算結果がセレクタ202hに供給される。セレクタ202hには、この他に、受信系列14A および固定値出力部202gから「0 」が供給されている。
【００７２】
この３入力は比較回路202iの切替信号に応じて行われる。比較回路202iではこの３入力の選択に対応するため３値の切替信号を生成する。３値の分類条件は、式(12)の３項に対応している。すなわち、第１項の系列番号が初項、第２項の系列番号が終項で、それぞれ系列番号の値を「0 」、「1 」と異なる値に固定する。式(12)の第１項または第２項が0 になる。このように固定することにより、拡散符号系列の平衡が保たれる。比較結果が初項を示している場合、比較回路202iで切替信号がセレクタ202hでの選択を固定値出力部202gからの信号、すなわち「0 」を選択するように生成される。また、比較結果が終項を示す場合、比較回路202iで切替信号がセレクタ202hでの選択を受信系列14A をそのまま出力するように生成される。これ以外の場合、第３項に対応し個々の演算結果を出力するように切替信号を生成する。この切替信号に応じて入力を切り替えて累算部202dに供給することにより相関値の差C_Dが得られる。
【００７３】
このように構成しても、相関値の差C_Dの得られることが判った。この構成は、第２の実施例の構成よりも構成要素を少なくできるので、相関値計算部202 の構成の簡素化に寄与する。回路規模をさらに小さくでき、消費電力の改善に寄与できる。
【００７４】
次に同期保持回路20c の第３の実施例について図10の相関値計算部202 を参照しながら説明する。これまでの実施例で用いたと同じ構成要素には同じ参照符号を付して説明を省略する。本実施例では、第２の実施例の変形例と同様に一つのセレクタ202hで供給される信号の選択に対応する。そして、新たに反転器202j, 202kを構成に含めている。また、比較回路202iの代わりに、制御系列生成部202mを用いている。さらに各要素を説明する。反転器202j, 202kは、入力した符号の数値の正負を反転させる回路を有する。ここで用いる反転器は、たとえば、レジスタを含んでいてもよい。一旦、２値符号で表した値をこのレジスタに取り込んだ後、ビット毎に反転させる。
【００７５】
制御系列生成部202mは、同期系列18A, 18Bの２つの符号系列の差を算出し、この算出結果を制御系列として生成する演算回路である。具体的に示すと、制御系列生成部202mは同期系列18A の値S_-、同期系列18B の値S₊として(S_- −S₊) の演算を行う回路を有する。この演算結果は、この場合も正負、0 の３値形式になる。また、演算を行わず、あらかじめ同期系列の２入力に応じて演算結果を、たとえばROM に書き込んでおくようにしてもよい。この場合、逐次計算を行わずに済むので消費電力を抑えることができる。
【００７６】
ところで、セレクタ202hは５つの信号を供給する信号ラインと接続している。この５つの信号を選択するように制御系列生成部202mは切替信号を３ビットで表し、セレクタ202hに供給する。
【００７７】
このような構成・接続を行っている相関値計算部202 の動作を説明する。本実施例で用いる制御系列は、制御系列生成部202mで生成される。差(S_- −S₊) は、前述したように３値で、式(12)の第３項に対応している。この他、式(12)の第１項および第２項に対応した入力をも選択することになる。この２項の対応には、系列カウント制御部202aからの制御信号としてカウント値が供給されるようにしてもよい。また、この２項（初項、終項）の対応関係を示す情報でもよい。
【００７８】
ここで、さらに制御系列について説明する。制御系列は、各同期系列の値およびその差を{S_-, S₊, (S_-−S₊)}で表す。制御系列には、次の４種類がある。２進数で表すと、{0, 0, 00}, {0, 1, 11}, {1, 0, 01}, {1, 1, 00}という関係が得られる。差を10進数で表すと、「00」＝0,「11」＝-1, 「01」＝+1を示す。このような制御系列および前述した２項の選択も加味して、切替信号は３ビットで表す。セレクタ202hにおける切替信号と出力選択との関係は、初項を示す情報が供給されたとき、制御系列の値にかかわらず、受信系列14A をそのまま出力する選択、終項を示す情報が供給されたとき、制御系列の値にかかわらず、受信系列14A をそのまま出力する選択、制御系列の値が正のとき、倍数器202eの出力の選択、制御系列の値が負のとき、反転器202kの出力の選択および制御系列の値が0 のとき、固定値出力部202gの出力の選択を、それぞれ行う。
【００７９】
このようにセレクタ202hで出力選択した値を累算部202dに供給すると、式(12)で表した相関値の差C_Dが得られる。本実施例は、このように構成するとともに、同期系列が十分に短い場合、制御系列生成部202mに演算結果を記憶させておくことが可能になる。この制御系列生成部202mは、先の第２の実施例に用いた比較回路202iに比べて小さい実装面積で済ませることができる。これにより回路規模をより小さくすることができる。
【００８０】
次に第３の実施例の変形例について図11を参照して説明する。この変形例の相関値計算部202 は、図11に示すように第３の実施例の構成のうち、反転器202jが省略された構成である。参照符号は同じものを用いている。固定値出力部202gからは「0 」が供給されている。
【００８１】
相関値計算部202 の動作を説明する。また、相関をとる区間の拡散符号系列は、初項を0,終項を1 に設定する。この場合、相関検出区間は、同期系列の１周期に対応する。これにより、同期系列S[0]＝0,終項 S[k-1] ＝1 に固定される。固定する初項、終項の関係は、この逆でもよい。
【００８２】
ところで、これまで同期系列として[0,1] の２値をとる場合を説明してきたが、本実施例では、同期系列に[-1,1]の２値をとるものとする。同期系列に[-1,1]の２値をとる場合、式(12)における第１項および第２項の演算は、サンプリング系列r[t]の値に-1または+1を乗算することに相当する。この処理は、以下の切替信号を生成することで代用している。すなわち、制御系列生成部202mにおいて、たとえば供給されるカウント値が0 、かつ同期系列18A が初項の入力タイミングでは、セレクタ202hを介して受信系列14A が制御系列にかかわらず選択されるように切替信号が生成される。また、たとえば、供給されるカウント値が(k-1) 、かつ同期系列18A が終項の入力タイミングでは、セレクタ202hを介して固定値出力部202gからの出力が制御系列にかかわらず選択されるように切替信号が生成される。
【００８３】
そして、式(12)の第３項に対応する演算は、同期系列の値S_-, S₊が+1, -1のとき、サンプリング系列の値r[t]を２倍した、倍数器202eからの出力を選択することに相当する。また、この演算は、同期系列の値S_-, S₊が-1, +1のとき、サンプリング系列の値r[t]を-2倍した、反転器202kからの出力を選択することに相当する。そして、第３項の演算においてこれら２つの場合以外の演算は、固定値出力部202gからの出力を選択することになる。この演算は、２つの同期系列の値が等しいときに相当する。これは、同期系列18A が終項の入力時の切替信号と同じである。これにより、切替信号は役割を共用できる。したがって、制御系列生成部202mは、第３の実施例に比べてこの変形例では５値から４値でセレクタ202hを切替制御できるようになる。切替信号のビットも３ビットから２ビットと少なくて済む。
【００８４】
このように変形した構成にして、反転器を一つ減らすとともに、切替信号のビットも一つ削減することにより、回路の実装面積を2/3 にすることができる。
【００８５】
以上のように携帯電話10を構成することにより、同期系列18A と遅延反転部200 を介した同期系列18B を相関値計算部202 に供給するとともに、受信系列14A と同期系列18A, 18Bとの相関値をそれぞれ算出し、相関値計算部202 だけで相関値の差までも算出し、この算出した出力を補正量として制御値算出部204 に供給することができ、制御値算出部204 で制御量を出力する。この制御により、発振器16、符号発生器18が制御されて、受信系列14A との符号同期を維持するように制御される。この制御のデータである相関値の差を一つだけで済ませることから、回路の実装面積を大幅に削減することができる。また、回路規模の低下にともなって回路の消費電力も少なくすることができるので、搭載した機器のバッテリ寿命を長くすることもできるようになる。
【００８６】
なお、本発明で行う符号同期は、受信系列の同期タイミングの位置が同期系列の中央位置になっているので、復調時にこの分の受信系列の位相を考慮しておくとよい。
【００８７】
【発明の効果】
このように本発明のスペクトラム拡散方式受信装置および同期保持回路によれば、補正制御手段において符号発生手段が出力する符号系列の第２の信号と遅延反転手段を介した第３の信号を演算手段に供給するとともに、第１の信号と第２の信号, 第３の信号との相関値をそれぞれ算出し、この演算手段だけで相関値の差までも算出し、この算出した出力を補正量としてタイミング制御手段に供給することができ、タイミング制御手段で制御量を出力する。この制御により、発振手段、符号発生手段が制御されて、第１の信号との符号同期を維持するように制御される。この制御のデータである相関値の差を一つだけで済ませることから、回路の実装面積を大幅に削減することができる。また、回路規模の低下にともなって回路の消費電力も少なくすることができるので、搭載した機器のバッテリ寿命を長くすることもできる。
【００８８】
また、本発明の同期保持方法によれば、第１の信号の符号位相と第２の信号の符号位相との位相差を検出し、検出した位相差を補正して前記タイミングの供給を制御する際に、第２の信号の符号位相を遅延させ、この第２の信号の反転した第３の信号を生成して、第１の信号と第２の信号に対する相関処理により得られる第１の相関値と、第３の信号と第２の信号に対する相関処理により得られる第２の相関値とを算出する際に、第１の相関値と第２の相関値の算出する符号区間を符号区間の最初の符号、最後の符号およびこの最初の符号とこの最後の符号との間の符号の３つに分けて演算することにより、演算回数を改善して処理の簡素化を図り、得られた第１の相関値と第２の相関値を用いてこれら相関値の差を算出している。この演算回数の改善により、ハードウェアの回路構成も改善する。これは、回路の実装面積を大幅に削減するとともに、回路による消費電力も少なくすることができるので、搭載した機器のバッテリ寿命を長くすることもできる。
【図面の簡単な説明】
【図１】本発明に係るスペクトラム拡散方式受信装置を携帯電話に適用した際の概略的な構成を示すブロック図である。
【図２】図１に用いた同期保持回路および遅延同期ループの基本構成を示すブロック図である。
【図３】図２の比較に用いた従来の同期保持回路および遅延同期ループの基本構成を示すブロック図である。
【図４】図３の相関値計算部の概略的な構成を示すブロック図である。
【図５】図１の携帯電話に供給される受信系列と生成した同期系列との関係を示すタイミングチャートである。
【図６】図５のタイミング関係において、符号の同期と同期ずれの関係を模式的に示す図である。
【図７】図２の同期保持回路に適用する相関値計算部の第１の実施例における構成を示すブロック図である。
【図８】図２の同期保持回路に適用する相関値計算部の第２の実施例における構成を示すブロック図である。
【図９】図８の相関値計算部における第２の実施例の変形例の構成を示すブロック図である。
【図１０】図２の同期保持回路に適用する相関値計算部の第３の実施例における構成を示すブロック図である。
【図１１】図10の相関値計算部における第３の実施例の変形例の構成を示すブロック図である。
【符号の説明】
10 携帯電話
12 空中線
14 仮復調部
16 発振器
18 符号発生器
20 同期調整部
22 復調部
20c 同期保持回路
202 相関値計算部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a spread spectrum receiver, a synchronization holding circuit, and a synchronization holding method, and in particular, to capture a spreading code in a signal generated with respect to a code phase of a spreading code in a received signal, that is, a code phase of a synchronizing code. This is suitable for application to, for example, a CDMA receiver that maintains the synchronization of the captured code after synchronization is established.
[0002]
[Prior art]
In recent years, as one of mobile communication systems, a power spread per unit frequency has been reduced, and a spread spectrum communication system that is strong against interference and interference has attracted attention. Among these methods, the Code Division Multiple Access (CDMA) method is currently in the spotlight. In general, an apparatus using this method digitizes information to be communicated, for example, performs PSK (Phase Shift Keying) modulation, and uses the modulated data as a pseudo random noise code (hereinafter referred to as PN code). The signal is transmitted in a wide band using a spread code such as a radio frequency signal. Also, in this system reception, the received signal is despread using the same code as the spreading code used in transmission, and the digital demodulation for the above-mentioned modulation is performed to reproduce the communication information. .
[0003]
In this type of system, when performing communication, not only the synchronization signal of the receiving apparatus and the carrier wave of the received signal are tuned, but also the communication is performed according to the above-described procedure, so that the transmission side spread code (ie, reception sequence) and The code acquisition with the spreading code (that is, the synchronization sequence) on the receiving side is also performed for the acquisition of synchronization within a predetermined range. For synchronization acquisition, various methods have been proposed as described in, for example, Japanese Patent Laid-Open Nos. 8-32547 and 9-55716. In the case where synchronization is acquired, synchronization tracking of both code sequences is performed so as to maintain the synchronization of the acquired code (synchronization holding mode). This synchronous tracking is to correct a chip phase shift caused by generating a PN code using a signal oscillated independently by an oscillator provided on the transmission side and the reception side for timing. In addition to this, the cause of synchronization tracking may be caused by fading, multipath, or the like. When this occurs, the reception state appears as an unstable state.
[0004]
In order to perform more stable reception, the receiving apparatus may correct the phase shift by changing the chip phase of the synchronization sequence with sufficiently high accuracy as compared with one chip of the reception sequence as described above. Actually, the receiving apparatus applies, for example, a matched filter or a delay locked loop (hereinafter referred to as DLL) as a component for correction.
[0005]
The DLL circuit calculates each correlation value between the two synchronization sequences generated by shifting each other by one chip phase and the reception sequence using a correlator, and calculates the difference between the obtained correlation values between the code phase of the synchronization sequence and the reception sequence. This is detected as the amount of deviation. The DLL circuit controls the oscillator that takes charge of the generation timing of the PN code based on the detected deviation amount. As can be seen from this control, the DLL circuit is configured to sequentially calculate the correlation value between the received sequence and the synchronous sequence, so the circuit configuration is smaller than the matched filter. be able to. The DLL circuit is also suitable for integration.
[0006]
[Problems to be solved by the invention]
By the way, in the mobile terminal, in response to user requests such as low cost, portability, and long battery life, the number of parts is further reduced (high integration), small size and light weight, and Power saving is desired. Various functions have been added to mobile terminals in order to bring out the characteristics of individual products.
[0007]
However, in such a situation, it is becoming difficult for mobile terminals to satisfy the requirements even if, for example, the above-described DLL circuit is simply integrated.
[0008]
  The present invention eliminates such drawbacks of the prior art, and makes it possible to make the code phase shift detected during synchronization tracking and the shift correction smaller than in the conventional configuration.Synchronization holding circuitThe purpose is to provide.
[0012]
[Means for Solving the Problems]
  In order to solve the above-mentioned problem, the present invention receives a signal obtained by performing spread spectrum modulation on an original signal including information using a predetermined spreading code sequence, obtains a first signal as a reception sequence, and supplies a built-in timing. Code generating means for outputting a code sequence generated in the same manner as the spreading code sequence based on the timing of the signal obtained from the timing supplying means, and the code sequence output from the code generating means as the second signal, In a synchronization holding circuit that synchronizes the phase of the spread code sequence of the signal and the second signal, the phase difference between the code phase of the first signal and the code phase of the second signal is detected, and the detected phase difference is corrected. Correction control means for controlling the timing supply means, the correction control means delaying the sign phase of the second signal and inverting the second signal, and the first signal. And the first correlation value obtained by the correlation processing on the second signal and the first correlation value obtained by the correlation processing on the third signal and the second signal when the output from the delay inversion means is the third signal. Calculating means for calculating a difference between the two correlation values, and a timing control means for performing a control for correcting the phase difference based on the difference between the correlation values output from the calculating means on the timing supply means,The computing means includes a multiplying means for doubling the value of the code sequence of the first signal, a first selecting means for switching and selecting the second signal and the third signal, and a plurality of input signals. A second selection means for selecting one input signal, and a second selection means for controlling the switching selection of the first selection means and the second selection means in response to the code phase of the second signal and the code phase of the third signal. One switching control means, a multiplication means for performing a correlation operation based on signals supplied from the first and second selection means, a fixed value output means for outputting a predetermined value, and a plurality of input signals. A third selection means for selecting one input signal; a second switching control means for performing a switching selection of the third selection means by comparing and judging the values of the second signal and the third signal; The selection result of the selection means and the value held immediately before this selection result are added, and this addition result is accumulated. The second selection means supplies the output of the multiplication means and the first signal, and the third selection means receives the signals from the fixed value output means and the multiplication means, respectively. SupplyDo.
[0013]
  Also,A synchronization holding circuit according to another aspect of the present invention for solving the above-described problem is provided with a first signal which receives a signal obtained by performing spread spectrum modulation on an original signal including information using a predetermined spreading code sequence and sets it as a reception sequence. Code generation means for outputting a code sequence generated in the same manner as the spread code sequence based on the timing of the signal obtained from the timing supply means for supplying the built-in timing, and the code sequence output by the code generation means is In a synchronization holding circuit that synchronizes the phases of the spreading code sequences of the first signal and the second signal, the phase difference between the code phase of the first signal and the code phase of the second signal is detected. Correction control means for correcting the detected phase difference and controlling the timing supply means. The correction control means delays the sign phase of the second signal and inverts the second signal. The delay inversion means, the first correlation value obtained by the correlation processing for the first signal and the second signal, and the third signal when the output from the delay inversion means is the third signal. Timing for calculating the difference between the second correlation value obtained by the correlation processing for the two signals and a control for correcting the phase difference based on the difference between the correlation values output from the calculation means. Control means,The arithmetic means controls to generate a control sequence represented using a plurality of values when a range obtained by subtracting using the second signal and the third signal covers a plurality of values. Sequence generating means, control means for controlling the control sequence generating means in response to the code phase and the third code phase of the second signal, second inversion means for inverting the sign of the first signal, A multiplication means for doubling the value of the code sequence of the first signal; a third inversion means for inverting the output of the multiplication means; a fixed value output means for outputting a predetermined value; and a plurality of input signals A fourth selecting means for selecting one input signal from the inside; an accumulating means for adding the selection result of the fourth selecting means and the value held immediately before the selection result and accumulating the addition result; And the fourth selection means includes the first signal, the output of the second inversion means, the output of the multiplication means, 3 supplies the output of the output and the fixed value output means of the inverting means, selected in response to the control sequence of the control sequence generation unitDo.
[0014]
  In addition, a synchronization holding circuit according to another aspect of the present invention for solving the above-described problem is a first circuit that receives a signal obtained by performing spread spectrum modulation on an original signal including information using a predetermined spreading code sequence and sets the received signal as a received sequence. A code sequence that outputs a code sequence generated in the same manner as a spread code sequence based on the timing of a signal obtained from a timing supply unit that obtains a signal and supplies a built-in timing, and that is output by the code generation unit In the synchronization maintaining circuit that synchronizes the phases of the spreading code sequences of the first signal and the second signal, the phase difference between the code phase of the first signal and the code phase of the second signal is And a correction control unit that detects and corrects the detected phase difference to control the timing supply unit. The correction control unit delays the code phase of the second signal and outputs the second signal. The delay inversion means for inverting, the first correlation value obtained by the correlation processing for the first signal and the second signal, and the third signal when the output from the delay inversion means is the third signal, Computation means for computing the difference between the second correlation value obtained by the correlation processing for the second signal and control for correcting the phase difference based on the difference between the correlation values output from the computation means are applied to the timing supply means. Timing control means,The arithmetic means controls to generate a control sequence represented using a plurality of values when a range obtained by subtracting using the second signal and the third signal covers a plurality of values. Sequence generation means, control means for controlling the control sequence generation means in response to the code phase and third code phase of the second signal, and multiplication means for doubling the value of the code sequence of the first signal A third inversion means for inverting the output of the multiplication means, a fixed value output means for outputting a predetermined value, a fourth selection means for selecting one input signal from a plurality of input signals, The fourth selection means includes an addition means for adding the selection result of the fourth selection means and the value held immediately before the selection result, and accumulating the addition result. The fourth selection means includes a first signal Supply the output of the multiplication means, the output of the third inversion means and the output of the fixed value output means, Selected in response to the control sequence from meansDo.
[0015]
  further,A synchronization holding circuit according to another aspect of the present invention for solving the above-described problem is provided with a first signal which receives a signal obtained by performing spread spectrum modulation on an original signal including information using a predetermined spreading code sequence and sets it as a reception sequence. Code generation means for outputting a code sequence generated in the same manner as the spread code sequence based on the timing of the signal obtained from the timing supply means for supplying the built-in timing, and the code sequence output by the code generation means is In a synchronization holding circuit that synchronizes the phases of the spreading code sequences of the first signal and the second signal, the phase difference between the code phase of the first signal and the code phase of the second signal is detected. Correction control means for correcting the detected phase difference and controlling the timing supply means. The correction control means delays the sign phase of the second signal and inverts the second signal. The delay inversion means, the first correlation value obtained by the correlation processing for the first signal and the second signal, and the third signal when the output from the delay inversion means is the third signal. Timing for calculating the difference between the second correlation value obtained by the correlation processing for the two signals and a control for correcting the phase difference based on the difference between the correlation values output from the calculation means. Control means,The computing means is a second switching control means for performing switching control by comparing and judging the values of the second signal and the third signal, and the second means in response to the code phase and the third code phase of the second signal. Control means for controlling the switching control means, multiplication means for doubling the value of the code sequence of the first signal, multiplication means for performing a correlation operation based on the output of the multiplication means and the second signal, A fixed value output means for outputting a predetermined value, a fourth selection means for selecting one input signal from a plurality of input signals, a selection result of the fourth selection means, and a previous one of the selection result Adding a held value and accumulating the addition result, and supplying the first signal, the output of the multiplication means, and the output of the fixed value output means to the fourth selection means, Select in response to the switching signal from the second switching control meansDo.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a spread spectrum receiver according to the present invention will be described in detail with reference to the accompanying drawings.
[0019]
The spread spectrum receiver of the present invention supplies a reception sequence (first signal), a synchronization sequence (second signal), and a delay inversion sequence obtained by delay-inverting the synchronization sequence to one arithmetic unit of the synchronization holding unit. The difference between the first correlation value indicating the correlation between the reception sequence and the synchronization sequence and the second correlation value indicating the correlation between the reception sequence and the delay inversion sequence is calculated. This calculation result reflects a code phase shift between the first signal and the second signal. The timing control means controls the operation of the timing supply means by outputting a control signal to the timing supply means using the supplied calculation result. As a result, since the code generation means generates a predetermined spreading code sequence based on the output signal of the timing supply means, the code phase of the second signal can be made to follow the code phase of the first signal. .
[0020]
The configuration and operation of a receiving unit of a CDMA mobile phone 10 according to an embodiment to which the present invention is applied will be described with reference to FIGS. The CDMA mobile phone 10 of the embodiment is provided with a transmission unit (not shown). In the present embodiment, since the receiving unit in the CDMA mobile phone has the main configuration and operation, the following description will be made focusing on the receiving unit in order to simplify the description. As shown in FIG. 1, the mobile phone 10 includes an antenna (antenna) 12, a temporary demodulator 14, an oscillator 16, a code generator 18, a synchronization adjuster 20, and a demodulator 22.
[0021]
The antenna 12 is an antenna that receives radio waves transmitted via a transmitter of a caller and a base station. The reception signal on the antenna 12 includes transmission information subjected to primary and secondary modulation. The antenna 12 is connected to the temporary demodulator 14.
[0022]
The temporary demodulation unit 14 includes a high frequency amplifier 14a, a frequency conversion unit 14b, a primary demodulator 14c, and a matching unit 14d. The temporary demodulator 14 has a function of demodulating the primary modulated signal except for the carrier wave of the modulated received signal. The high frequency amplifier 14a is an amplifier that amplifies the reception signal supplied via the antenna 12 to a signal level suitable for subsequent processing. The high frequency amplifier 14a outputs the amplified received signal to the frequency conversion unit 14b.
[0023]
The frequency conversion unit 14b has a function of converting the frequency of the received signal to baseband. The frequency converter 14b supplies the baseband received signal to the primary demodulator 14c. The primary demodulator 14c is a demodulator that demodulates the primary modulation performed on the transmission side. As the primary demodulator 14c, for example, a PSK demodulator or the like is used corresponding to the primary modulation format. The primary demodulator 14c outputs the primary demodulated signal to the matching unit 14d. The matching unit 14d has a signal input / output matching function for converting the supplied primary demodulated signal into a reception sequence used by the synchronization adjusting unit 20 and the demodulating unit 22. Although not shown, the matching unit 14d includes a sampling unit that samples an input signal at a predetermined timing, and an A / D conversion unit that quantizes the sampled value (that is, the chip level). The matching unit 14d converts the received primary demodulated signal into a numerical value with a predetermined code length by this chip-level quantization. This is the reception sequence 14A. The matching unit 14d supplies the received sequence 14A to the synchronization adjusting unit 20 and the demodulating unit 22, respectively.
[0024]
As the oscillator 16, for example, a voltage-controlled oscillator (VCO) is used. The VCO generally changes the oscillation frequency according to the applied voltage. The oscillator 16 is a control target of a synchronization holding circuit 20c described later. The oscillator 16 has such an accuracy that the phase of the code output from the code generator 18 can be controlled.
[0025]
The code generator 18 generates the same code sequence as the spreading code sequence used at the time of transmission as the synchronization sequence 18A. The code generator 18 includes a calculator that generates, for example, a pseudo noise code (PN code) as a spread code sequence by a predetermined calculation. For the arithmetic unit, for example, a linear feedback shift register is used. An initial value other than 0 is given to the linear feedback shift register to generate a so-called M-sequence, which is one of PN codes, as a spreading code. The code generator 18 also includes a memory for storing the generated spreading code. The code generator 18 supplies, for example, a PN code to the synchronization adjustment unit 20 and the demodulation unit 22 according to the timing of the signal supplied from the oscillator 16.
[0026]
The synchronization adjustment unit 20 includes a changeover switch 20a, a synchronization acquisition circuit 20b, a synchronization holding circuit 20c, and an oscillator 20d. The changeover switch 20a is supplied with the reception sequence 14A from the temporary demodulator 14 at the terminal a. A changeover signal 22A, which will be described later, is also supplied to the changeover switch 20a. The changeover switch 20a switches the switch according to the changeover signal 22A. The terminal b of the changeover switch 20a is connected to the synchronization acquisition circuit 20b. The terminal c of the changeover switch 20a is connected to the synchronization holding circuit 20c.
[0027]
The synchronization acquisition circuit 20b uses a correlator to determine whether the code synchronization between the reception sequence 14A supplied via the changeover switch 20a and the synchronization sequence 18A from the code generator 18 is within a predetermined synchronization control range. . An example of this correlator is a sliding correlator. The synchronization acquisition circuit 20b outputs the code half period to the code generator 18 in the minimum unit until the code synchronization acquisition of the correlator is obtained. At this time, the code generator 18 uses the output from the synchronization acquisition circuit 20b as a control signal, and outputs a PN code shifted by the minimum unit by this control. The synchronization acquisition circuit 20b acquires the minimum unit shift timing from the oscillator 20d at the time of this output.
[0028]
As shown in FIG. 2, the synchronization holding circuit 20c includes a delay inversion unit 200, a correlation value calculation unit 202, and a control value calculation unit 204. The delay inversion unit 200 includes a circuit that delays the phase of the supplied signal by a predetermined amount. Although not shown, the delay inverting unit 200 uses a time of one code of the synchronization sequence 18A supplied from the code generator 18 in the present embodiment as a code period, and delays this code period, and this delayed synchronization sequence 18A And an inverter for inverting the sign. This inverter is a circuit that handles supplied signals and bit data, and inverts the level of input data or the sign of the sign (the polarity of the sign value). This inverter is configured to perform level reversal in the application example in which the synchronization sequence 18A takes a binary value of 0 and 1, and to invert the polarity in an application example that takes the binary value of -1 and +1. Is done. The delay inversion unit 200 delays and inverts the synchronization sequence 18A, and sends the output to the correlation value calculation unit 202 as the synchronization sequence 18B. Note that the delay inversion unit 200 may have a function of outputting the delay amount as, for example, a voltage or quantized information. Although not shown, the delay inversion unit 200 may output this information to the control value calculation unit 204.
[0029]
The correlation value calculation unit 202 includes a configuration having the characteristics of the present invention. Correlation value calculation section 202 is supplied with sync sequence 18A and delay-inverted sync sequence 18B, as well as received sequence 14A. The correlation value calculation unit 202 uses a configuration that accumulates the reception sequence 14A and the synchronization sequence 18A, the reception sequence 14A and the synchronization sequence 18B, and the difference between the correlation values. Correlation value calculation section 202 may perform the calculation sequentially for each code, or may perform the calculation for each predetermined code section. A more specific configuration will be described in detail later. Correlation value calculation section 202 outputs the accumulated correlation value difference to control value calculation section 204.
[0030]
The control value calculation unit 204 has a function of generating a control value to be supplied to the oscillator 16 by correcting a difference between accumulated correlation values (not shown). The control principle will be described in detail later. First, the true synchronization timing position corresponds to a position shifted by the half width of the code period, which is the difference between the synchronization sequence 18A and the synchronization sequence 18B, when the reception sequence 14A and the synchronization sequence 18A match. Since the half value of the difference between the accumulated correlation values is shifted between the reception sequence 14A and the synchronization sequence 18A, the position of the synchronization timing is also shifted. Basically, the difference between the half value of the accumulated correlation value difference and the half value of the code period is the amount of synchronization timing position deviation caused by the reception sequence 14A and the synchronization sequence 18A. This difference corresponds to the control amount. In order to realize this principle, the control value calculation unit 204 includes, for example, a subtractor that calculates the difference between the accumulated correlation value difference and the code period, and a multiplication that multiplies the calculated value by 1/2. And a converter for converting the output of the multiplier into a voltage or a control value. The control value calculation unit 204 outputs the calculated control value to the oscillator 16. As a result, a loop is formed by the oscillator 16, the code generator 18, and the synchronization holding circuit 20c. Note that the value of the delay period from the delay inverting unit 200 may be used as the code period described above.
[0031]
Returning to FIG. 1, the demodulation unit 22 includes a despreading unit 22a, an interface circuit 22b, and a speech decoding unit (D / A) 22c. The despreading unit 22a has a despreading circuit (not shown) that performs despreading on the reception sequence 14A from the temporary demodulation unit 14. The despreading unit 22a is supplied with the synchronization sequence 18A from the code generator 18. The despreading circuit uses the synchronization sequence 18A when performing the despreading process on the reception sequence 18A. The despreading unit 22a compares both sequences, reproduces the communication information, and outputs it to the interface circuit 22b and the speech decoding unit 22c. The output format in the despreading section 22a is normally the transmission bit format in the transmitting apparatus. Although not shown in detail, the despreading unit 22 may include a threshold value determination unit 220. The threshold determination unit 220 compares the phases of the spread codes of the reception sequence 14A and the synchronization sequence 18A, for example, and expresses the phase difference as a signal level. Further, the threshold determination unit 220 includes a determination circuit that determines whether or not the signal level is within the synchronization acquisition range by comparing with a preset threshold level. The determination circuit outputs a switching signal 22A corresponding to the determination to the changeover switch 20a. As a result, the synchronization acquisition mode and the synchronization holding mode are switched.
[0032]
The interface circuit 22b is a circuit that outputs a digital signal. The interface circuit 22b is provided with a processing circuit that converts the transmission bit string obtained from the despreading unit 22a into a predetermined information bit string. As described above, the transmission bit string has the same format as the code used in the transmission apparatus. This format includes, for example, convolutional codes and Reed-Solomon codes that make information bits redundant. Further, an error correction processing circuit may be provided in the interface circuit 22b by utilizing such a transmission bit string being supplied. The interface circuit 22b is suitable for data communication or the like.
[0033]
The audio decoding unit 22c is a circuit that decodes the transmission bit string and outputs the decoded data as an analog signal. The speech decoding unit 22c has a decoding circuit for decoding the transmission bit string obtained from the despreading unit 22a. The voice decoding unit 22c is provided with a D / A conversion circuit that converts the decoded data into an analog signal. The format of the analog signal is not limited to an audio signal. The demodulator 22 demodulates as described above and outputs various corresponding decoded signals from the interface circuit 22b and the audio decoder 22c.
[0034]
A comparison of the configuration with respect to the synchronization holding circuit 20c of this embodiment will be made with reference to FIGS. The synchronization holding circuit 30 of FIG. 3 shows a conventional configuration. The oscillator 16 and the code generator 18 have the same configuration as in this embodiment. Further, the input signal supplied to the synchronization holding circuit 30 is the same signal as in this embodiment, and is denoted by the same reference numeral. The synchronization holding circuit 30 includes a delay device 300, correlation value calculation units 302 and 304, and a control value calculation unit 306. The delay device 300 is a circuit that delays the phase of the code by one phase in the synchronization sequence 18A from the code generator 18, and is the same as the delay device 200. The delay device 300 delays the supplied synchronization sequence 18A and sends it to the correlation value calculation unit 304 as a synchronization sequence 18B.
[0035]
Correlation value calculation sections 302 and 304 use the configuration shown in FIG. 4 so as to calculate the correlation values of reception sequence 14A and synchronization sequence 18A, and reception sequence 14A and synchronization sequence 18B, respectively. Since the correlation value calculation units 302 and 304 have the same configuration, the configuration of the correlation value calculation unit 302 will be schematically described. The correlation value calculation unit 302 includes a multiplier 302a, an adder 302b, and an accumulator 302c. The multiplier 302 has a configuration for multiplying two inputs of the received reception sequence 14A and the synchronization sequence 18A. The adder 302b has a circuit that adds the output from the multiplier 302a at one end and the output from the accumulator 302c at the other end. The adder 302b outputs this addition result to the accumulator 302c. The adder 302c is configured to accumulate the addition result to a held value and to output the accumulation result to the adder 302b in accordance with the output timing of the multiplier 302a. As shown in FIG. 4, the adder 302b and the accumulator 302c form a feedback loop. The accumulator 302c may output the accumulated result every time it is calculated, but it is preferable to output the accumulated result over a predetermined period as a correlation value.
[0036]
The control value calculation unit 306 includes a circuit that calculates a difference between the two supplied correlation values and converts the calculated difference into a signal that can be used as a control value.
[0037]
A comparison from the configurations of FIGS. 2 and 3 will be briefly described. The conventional synchronization holding circuit 30 uses two correlation value calculation units 302 and 304 to calculate the correlation values of the reception sequence 14A and the synchronization sequence 18A, and the reception sequence 14A and the synchronization sequence 18B, respectively. On the other hand, in addition to the reception sequence 14A, both of the synchronization sequences 18A and 18B to be correlated are supplied to the correlation value calculation unit 202 in the synchronization holding circuit 20c of the present embodiment. Then, the correlation value calculation unit 202 not only calculates the correlation values of the correlation value calculation units 302 and 304, but also calculates the difference between them. As is clear from this comparison, the synchronization holding circuit 20c has half the correlation value calculation unit compared to the conventional synchronization holding circuit 30. In this embodiment, by using this configuration, the redundancy of the configuration is improved, and the synchronization holding circuit can be implemented with a smaller mounting area than the conventional one. In addition, since the synchronization holding circuit 20c of the present embodiment performs correlation calculation in one block, when having a plurality of correlators as in the conventional configuration, the adjustment / output signal of the correlator is strictly aligned. Complicated operations such as linearity can be eliminated. A more specific configuration will be described later.
[0038]
Before showing a specific configuration, the operation principle of the synchronization holding circuit 20c of this embodiment will be described with reference to the code phase and synchronization relationship of FIG. 5 and the schematic diagram of FIG. As described above, the reception sequence 14A and the synchronization sequences 18A and 18B are the same spreading code sequence. This spreading code sequence is represented by k code periods Δ shown in FIG. Correlation between code sequences is performed using k iterations. From this, it can be said that the correlation length is kΔ. The spread code sequence uses a code number n to distinguish individual codes. R [n] of the reception sequence 14A and S [n] of the synchronization sequences 18A and 18B are values at individual code numbers n. The relative sampling interval size of these spreading code sequences is represented by a. Further, the sampling of the reception sequence 14A in FIG. 5 indicates that a = 1/2, that is, double oversampling is performed in half the period of the spreading code. In this embodiment, in particular, a sequence obtained by sampling the reception sequence 14A is represented by a sampling sequence r [t]. The symbol t indicates time. Therefore, the time t expressed based on sampling is also expressed as aΔ.
[0039]
In order to detect a shift in the code phase between the reception sequence 14A and the synchronization sequence generated by the mobile phone 10, two synchronization sequences having a code phase amount shifted by | aΔ | from the reception sequence 14A are generated. That is, the synchronization phase 18A corresponding to the case where the code phase is −aΔ with respect to the reception sequence 14A is generated by the code generator 18, for example. Then, the other synchronization sequence 18B delays the synchronization sequence 18A by the delay amount Δ by the delay inversion unit 200. As a result, the synchronization sequence 18B becomes a code sequence whose code phase is delayed by + aΔ with respect to the reception sequence 14A.
[0040]
Since the sampling for the reception sequence 14A shown in FIG. 5 is twice oversampling, the code phase shift amount in this case is a = 1/2. A correlation value with the reception sequence 14A is calculated using the synchronization sequences 18A and 18B. Correlation value between received sequence 14A and synchronous sequence 18A is C₁The correlation value between the received sequence 14A and the synchronous sequence 18B is C₂Then the correlation value C₁, C₂Are the sum of the multiplication results of the sampling sequence r [t] and the reception sequence S [n], respectively, as shown in Equations (1) and (2)
[0041]
[Expression 1]

Calculated by Here, the variable n is a code number of 0, 1, 2,..., (K−1), and the variable N is an arbitrary natural number.
[0042]
The sampling sequence r [t] is a probabilistic expression of the value R [t] of the reception sequence 14A, and this value is not limited to binary.
[0043]
Next, the relationship of the correlation length kΔ will be described. To simplify the explanation, the sampling sequences r [-aΔ] to r [(k-1-a) Δ], r [+ aΔ] to r [(k-1 + a) Δ] Correlation is obtained using S [0] to S [k-1] as codes repeated for each correlation length. That is, the variable N representing the offset for starting processing is set to zero. As a result, Equation (1) and Equation (2) become
[0044]
[Expression 2]

And can be simplified. Correlation value C₁, C₂Is calculated as the sum of multiplication results of k sampling sequences and received sequences.
[0045]
Here, since the code is repeated for each correlation length kΔ, the code at an arbitrary time t 1 can be represented by the code number n (the remainder is n = mod (N, kΔ)). As a result, the reception sequence R [n] and the synchronization sequence S [n] can be represented by k pieces.
[0046]
Correlation value C₁To correlation value C₂Is subtracted from Equation (5) using Equation (3) and Equation (4).
[0047]
[Equation 3]

Correlation value difference C for correlation length kΔ_DIs obtained. This correlation value difference C_DNext, the correction of the synchronization timing will be described. Correlation value difference C_DAre coincident with each other, the code boundary of the reception sequence 14A in FIG._t(Arrow A) When this relationship is schematically represented by a correlation value with respect to time, the synchronization timing is represented by a position S shown in FIG._tIt turns out to set to.
[0048]
By the way, in the synchronization holding mode, the calculated correlation value difference C_DMay take a non-zero value (see FIG. 6 (b)). The correlation value curve 60 with respect to time does not actually translate as shown by the solid line. However, when focusing attention on the synchronization relationship between the reception sequence and the synchronization sequence, this corresponds to the case where synchronization is obtained by the curve 62 of the correlation value indicated by the broken line. The synchronization timing at this time is position S_fbecome. Previous matched position S with respect to synchronization_tAnd position S_fIs the difference in synchronization Δ_s It is. In the case of FIG. 6B, it is shown that the synchronization of the synchronization sequence is delayed with respect to the reception sequence 14A. Synchronous deviation Δ_s For example, the direction of synchronization shift can be represented by a positive or negative sign. In the present embodiment, the difference C between the correlation values supplied by the control value calculation unit 204._DOf synchronization Δ_s Conversion and synchronization deviation Δ_s A control value is generated so as to correct. Further, a constant control value may be output so as to return the synchronization shift direction. The oscillator 16 changes the oscillation frequency according to the supplied control value. Since the code generator 18 generates a code at the timing of the signal from the oscillator 16 as described above, the code generator 18 operates so as to maintain the synchronization between the reception sequence and the synchronization sequence.
[0049]
Next, a more specific first embodiment of the synchronization holding circuit 20c will be described with reference to FIG. In the present embodiment, the feature of the correlation value calculation unit 202 in the synchronization holding circuit 20c will be described. The correlation value calculation unit 202 includes a selector 202a, a sequence count control unit 202b, a multiplier 202c, and an accumulation unit 202d.
[0050]
The selector 202a is a switch that switches between two inputs and one output according to a switching signal. In this embodiment, the selector 202a is supplied with a synchronization sequence 18A from the code generator 18 and a synchronization sequence 18B obtained by delay-inverting the synchronization sequence 18A. The selector 202a outputs the selection to the multiplier 202c. Sequence counter control section 202b includes a synchronous sequence counter. Although not shown in FIG. 2, a clock is supplied to the sequence counter control unit 202b together with the initial value 20A of the synchronization sequence counter. The initial value 20A is the sequence number n of the code at the start. The sequence number n corresponds to any one of the correlation lengths kΔ (k). The series counter control unit 202b outputs a switching signal to be supplied to the selector 202a. The switching signal switches the selection target every 1 / 2Δ.
[0051]
The multiplier 202c is an arithmetic circuit that multiplies a 2-input signal. The two inputs are the selected synchronization sequence of the reception sequence 14A and the synchronization sequence 18A, 18B, respectively. The multiplier 202c multiplies the correlation value C by multiplying in this way.₁, -C₂ Are alternately output to the accumulating unit 202d. Accumulation unit 202d includes an adder 2020 and an accumulator 2022. In particular, the accumulator 2022 temporarily holds the accumulated result, and the accumulated result held in synchronization with the output from the multiplier 202c supplied to the one end 202A side of the adder 2020 is added to the other of the adder 2020. Output to the end 202B side. When the accumulator 2022 finishes the preset number of accumulations, the sum of the correlation value differences is obtained. The correlation value calculation unit 202 including these is calculated by calculating the difference C between the calculated correlation values._DIs output to the control value calculation unit 204.
[0052]
Correlation value difference C based on the principle described above_DIs the correlation value C expressed as the sum of the multiplication results₁, C₂After obtaining the correlation value C,₁, C₂Explained the procedure to calculate the difference (see equation (5)). However, the calculation procedure is not limited to this method, and the correlation value C obtained alternately.₁, C₂And the correlation value C₁, C₂Correlation value C₁, C₂The same result can be obtained even if the difference is obtained. This latter relationship is given by equation (6)
[0053]
[Expression 4]

It is represented by Expression (6) is a form in which Expression (5) described above is arranged. Here, the variable m corresponds to the switching signal of the sequence count control unit 202b and selects the output of the selector 202a. In this embodiment, since the code period is 1Δ and double oversampling is performed, the correlation calculation is preferably performed within Δ / 2.
[0054]
When the synchronization sequence supplied from the selector 202a and the reception sequence 14A are multiplied by the multiplier 202c, the correlation value of each pair is calculated. When the accumulating unit 202d adds and considers the sign attached to the correlation value, and accumulates, the difference C of the correlation value_DIs obtained by one correlation value calculation unit 202. Thereby, the redundancy of the circuit configuration can be improved. Furthermore, power consumption can be suppressed by reducing the circuit scale.
[0055]
Next, a second embodiment of the synchronization holding circuit 20c will be described with reference to FIG. Portions common to the constituent elements of the previous embodiment are denoted by the same reference numerals, and description thereof is omitted. The correlation value calculation unit 202 of this embodiment, which is a feature of the synchronization holding circuit 20c, includes a multiplier 202e, a selector 202f, a fixed value, in addition to the selector 202a, the sequence count control unit 202b, the multiplier 202c, and the accumulation unit 202d. An output unit 202g, a selector 202h, and a comparison circuit 202i are provided.
[0056]
The multiplier 202e is an arithmetic unit that doubles the input. When the input signal is a digital signal such as a code sequence, a shift register is used for the multiplier 202e. In particular, when applied to a binary code, the shift register easily doubles the output by simply shifting the digit to the upper digit. The multiplier 202e is supplied with the reception sequence 14A. The multiplier 202e connects the output terminal and the input terminal of the selector 202f.
[0057]
The selectors 202f and 202h are both 2-input / 1-output selector switches. The selector 202h will be further described later. The selector 202f inputs the reception sequence 14A to one side of the input end, and the input end on the other side is connected to the multiplier 202e. The selector 202f is configured to perform switching according to a switching signal from the sequence count control unit 202b, similarly to the selector 202a. However, as shown in FIG. 8, when the series count control unit 202b only outputs the count value to the selectors 202a and 202f, for example, the selector 202f is not a simple changeover switch but outputs according to the count value. It goes without saying that it has a function to select. The selector 202f connects the output terminal and the one end 20C side of the multiplier 202c. The fixed value output unit 202g is a circuit that outputs only a preset value. The value to be set is “0”.
[0058]
The selector 202h connects one input terminal 20D of the selector 202h and the output terminal of the multiplier 202c, and connects the other input terminal 20E of the selector 202h and the output terminal of the fixed value output unit 202g. The selector 202h switches the input output of the multiplier 202c and the output of the fixed value output unit 202g according to the switching signal from the comparison circuit 202i, and outputs it to the accumulating unit 202d.
[0059]
The comparison circuit 202i is a circuit that compares two signals and outputs a signal corresponding to whether the comparison results are equal. In this embodiment, the comparison circuits 202i are supplied with the synchronization sequences 18A and 18B. The comparison circuit 202i compares the signs of the synchronization sequences 18A and 18B for every Δ / 2, and outputs a signal corresponding to the comparison result to the selector 202h as a switching signal for the selector 202h.
[0060]
The operation of the correlation value calculation unit 202 in this embodiment will be described. The reception sequence 14A is supplied to a multiplier 202e and a selector 202f. The reception sequence 14B doubled by the multiplier 202e is supplied to the selector 202f. A switching signal is generated according to the initial value 20A supplied to the sequence count control unit 202b. For example, when sequence number n is n = 0 (first term) or n = k−1 (final term), initial value 20A is generated by sequence count control section 202b so that reception sequence 14A is output as it is. Is done. When sequence number n ≠ 0 ≠ k−1, a switching signal is generated by sequence count control section 202b so as to output reception sequence 14B from multiplier 202e.
[0061]
This switching signal is also supplied to the selector 202a. The selector 202a selects one of the synchronization sequences 18A and 18B according to the supplied switching signal. When the difference between the periods of the synchronization sequences 18A and 18B is 1Δ, the sampling interval a is Δ / 2 since sampling is performed twice. Therefore, 1Δ can be expressed as 2aΔ. If this relationship is used, [(n + 1−a) Δ] = [(n + 2a−a) Δ] = [(n + a) Δ] is arranged. The sampling value r [t] is
[0062]
[Equation 5]

become.
[0063]
In this relationship, when the timing relationship of each series in FIG. 5 is seen, there are sections that match and sections that do not match. Calculate the correlation value for each interval, and then calculate the difference C_DIs given by Equation (8)
[0064]
[Formula 6]

It becomes the expression. In the correlation between the sampling sequence and the synchronization sequence 18A, the first term is the correlation of the first term, and the second term is the correlation value C by the sum of the code sequence numbers n = 1 to (k-1).₁Represents. The third term and the fourth term are (k-1) correlations and final term (k-1) of sequence numbers n = 0 to (k-2) in the correlation between the sampling sequence and the synchronization sequence 18B, respectively. Represents the correlation. Therefore, the correlation value difference C_DIs represented by the difference between the sum of the first and second terms and the sum of the third and fourth terms.
[0065]
When the second term of equation (8) is matched to the total sum of the third term, the correlation value difference C_DIs
[0066]
[Expression 7]

Equation (9) including the modified third term is obtained. Applying the relationship of equation (7) described above to equation (9), equation (9) becomes
[0067]
[Equation 8]

Can be summarized. Focusing on the third term of equation (10), when the sampling sequence and the synchronization sequences 18A and 18B have the same correlation, the difference between the codes S [n + 1] and S [n] that precede and follow the third term Becomes zero (S [n + 1] -S [n] = 0). Also, when the phase correlations are different, the difference between the phase Ssn + 1] and S [n] in the third term is set to 1 (S [n + 1] -S [n] ≠ 0 ). To summarize this relationship, the equation (11)
[0068]
[Equation 9]

It is represented by
When this relational expression (11) is applied to the expression (10), the expression (12)
[0069]
[Expression 10]

Is obtained.
[0070]
In order to realize the equation (12), the selector 202f selects the received sequence 14A corresponding to the first term and the second term of the supplied equation (12) and the received sequence 14B corresponding to the third term. Output to the multiplier 202c. The reception sequence 14A corresponds to a sampling sequence. The multiplier 202c is supplied with the synchronization sequence selected by the selector 202a. In addition to performing multiplication of each supplied sequence, processing corresponding to δ in the third term of equation (12) is performed by the comparison circuit 202i. The comparison circuit 202i uses the synchronization sequences 18A and 18B for this comparison. In this comparison circuit 202i, when the comparison result of the value of the code that follows is supplied to the selector 202h, if the correlation value is the same in the selector 202h, the output `` 0 '' of the fixed value output unit 202g is selected, At other times, the output of the multiplier 202c is selected. Correlation value difference C by accumulation in accumulation section 202d_DIs obtained. With this configuration, as compared with the calculation of 2k times / Δ in the previous embodiment, it is possible to finish with (k + 1) times / Δ as is apparent from the equation (12). Thereby, power consumption can be reduced.
[0071]
A modification of the second embodiment will be described with reference to FIG. The correlation value calculation unit 202 of this modification has a configuration in which the selectors 202a and 202f are omitted from the configuration of the second embodiment as shown in FIG. The same reference numerals are used. In correlation value calculation section 202, multiplier 202c is supplied with a code sequence obtained by multiplying received sequence 14A and a synchronization sequence 18A. The multiplication result of the multiplier 202c is supplied to the selector 202h. In addition, “0” is supplied to the selector 202h from the reception sequence 14A and the fixed value output unit 202g.
[0072]
These three inputs are performed according to the switching signal of the comparison circuit 202i. The comparison circuit 202i generates a ternary switching signal to cope with the selection of the three inputs. The ternary classification condition corresponds to the three terms of Equation (12). That is, the sequence number of the first term is the first term, the sequence number of the second term is the last term, and the values of the sequence numbers are fixed to values different from “0” and “1”, respectively. The first or second term of equation (12) becomes zero. By fixing in this way, the balance of the spread code sequence is maintained. When the comparison result indicates the first term, the switching signal is generated by the comparison circuit 202i so as to select the signal from the fixed value output unit 202g, that is, “0” for selection by the selector 202h. When the comparison result indicates the final term, the switching signal is generated by the comparison circuit 202i so that the selection by the selector 202h is output as it is in the reception sequence 14A. In other cases, the switching signal is generated so as to output individual calculation results corresponding to the third term. By switching the input in accordance with this switching signal and supplying it to the accumulating unit 202d, the difference C_DIs obtained.
[0073]
Even with this configuration, the correlation value difference C_DIt was found that Since this configuration can reduce the number of components compared to the configuration of the second embodiment, it contributes to the simplification of the configuration of the correlation value calculation unit 202. The circuit scale can be further reduced, which can contribute to improvement of power consumption.
[0074]
Next, a third embodiment of the synchronization holding circuit 20c will be described with reference to the correlation value calculation unit 202 of FIG. The same components as those used in the above embodiments are denoted by the same reference numerals, and the description thereof is omitted. This embodiment corresponds to selection of a signal supplied by one selector 202h as in the modification of the second embodiment. In addition, inverters 202j and 202k are newly included in the configuration. Further, a control sequence generation unit 202m is used instead of the comparison circuit 202i. Further, each element will be described. The inverters 202j and 202k have a circuit that inverts the sign of the input sign. The inverter used here may include a register, for example. Once a value represented by a binary code is taken into this register, it is inverted bit by bit.
[0075]
The control sequence generation unit 202m is an arithmetic circuit that calculates the difference between the two code sequences of the synchronization sequences 18A and 18B and generates the calculation result as a control sequence. Specifically, the control sequence generation unit 202m uses the value S of the synchronization sequence 18A._-, Value S of synchronous sequence 18B₊As (S_- −S₊). In this case, the result of this calculation is also a ternary format of positive / negative and 0. Further, the calculation result may be written in advance in, for example, a ROM in accordance with the two inputs of the synchronization sequence without performing the calculation. In this case, since it is not necessary to perform sequential calculation, power consumption can be suppressed.
[0076]
Incidentally, the selector 202h is connected to a signal line for supplying five signals. The control sequence generation unit 202m represents the switching signal with 3 bits so as to select these five signals, and supplies the switching signal to the selector 202h.
[0077]
The operation of the correlation value calculation unit 202 having such a configuration / connection will be described. The control sequence used in this embodiment is generated by the control sequence generation unit 202m. Difference (S_- −S₊) Is a ternary value as described above and corresponds to the third term of equation (12). In addition, the input corresponding to the first term and the second term of Expression (12) is also selected. To cope with these two terms, a count value may be supplied as a control signal from the sequence count control unit 202a. Moreover, the information which shows the correspondence of these 2 terms (first term, last term) may be sufficient.
[0078]
Here, the control sequence will be further described. The control sequence uses the value of each synchronization sequence and its difference {S_-, S₊, (S_-−S₊)}. There are the following four types of control sequences. When expressed in binary, the relationship {0, 0, 00}, {0, 1, 11}, {1, 0, 01}, {1, 1, 00} is obtained. When the difference is represented by a decimal number, “00” = 0, “11” =-1, “01” = + 1. In consideration of such a control sequence and the selection of the two items described above, the switching signal is represented by 3 bits. The relationship between the switching signal and the output selection in the selector 202h is that when the information indicating the first term is supplied, the selection indicating that the received sequence 14A is output as it is regardless of the value of the control sequence, the information indicating the final term is supplied. When the control sequence value is positive, the selection of the output of the multiplier 202e is selected regardless of the control sequence value, the output of the inverter 202k is output when the control sequence value is negative And the value of the control sequence is 0, the output of the fixed value output unit 202g is selected.
[0079]
When the value selected by the selector 202h is supplied to the accumulating unit 202d in this way, the correlation value difference C expressed by Equation (12)_DIs obtained. The present embodiment is configured as described above, and when the synchronization sequence is sufficiently short, the calculation result can be stored in the control sequence generation unit 202m. This control sequence generation unit 202m can be completed with a smaller mounting area than the comparison circuit 202i used in the second embodiment. Thereby, the circuit scale can be further reduced.
[0080]
Next, a modification of the third embodiment will be described with reference to FIG. The correlation value calculation unit 202 of this modification has a configuration in which the inverter 202j is omitted from the configuration of the third embodiment as shown in FIG. The same reference numerals are used. “0” is supplied from the fixed value output unit 202g.
[0081]
The operation of the correlation value calculation unit 202 will be described. In addition, the spreading code sequence of the section to be correlated is set to 0 for the first term and 1 for the last term. In this case, the correlation detection section corresponds to one cycle of the synchronization sequence. As a result, the synchronization sequence S [0] = 0 and the final term S [k−1] = 1 are fixed. The relationship between the first term and the last term to be fixed may be reversed.
[0082]
By the way, although the case where the binary value of [0, 1] is taken as the synchronization sequence has been described so far, in this embodiment, the binary value of [-1, 1] is assumed as the synchronization sequence. When the binary value of [-1,1] is taken as the synchronous sequence, the calculation of the first term and the second term in the equation (12) is to multiply the value of the sampling sequence r [t] by -1 or +1. It corresponds to. This processing is substituted by generating the following switching signal. That is, in the control sequence generator 202m, for example, when the supplied count value is 0 and the input timing of the synchronization sequence 18A is the first term, switching is performed so that the received sequence 14A is selected regardless of the control sequence via the selector 202h. A signal is generated. Also, for example, when the supplied count value is (k−1) and the synchronization sequence 18A is the last input timing, the output from the fixed value output unit 202g is selected via the selector 202h regardless of the control sequence. Thus, a switching signal is generated.
[0083]
And the calculation corresponding to the third term of equation (12) is the value S of the synchronization sequence._-, S₊Is +1, −1, which corresponds to selecting the output from the multiplier 202e, which is twice the sampling sequence value r [t]. In addition, this calculation uses the value S of the synchronization sequence._-, S₊When −1 is −1, +1, this corresponds to selecting the output from the inverter 202k, which is obtained by multiplying the sampling sequence value r [t] by −2. In the calculation of the third term, the calculation other than these two cases selects the output from the fixed value output unit 202g. This calculation corresponds to the case where the values of the two synchronization sequences are equal. This is the same as the switching signal when the synchronization sequence 18A is the last input. Thereby, the switching signal can share the role. Therefore, the control sequence generation unit 202m can control to switch the selector 202h with five to four values in this modification as compared with the third embodiment. The number of bits of the switching signal can be reduced from 3 bits to 2 bits.
[0084]
With such a modified configuration, the number of inverters is reduced by one, and the bit of the switching signal is also reduced, so that the circuit mounting area can be reduced to 2/3.
[0085]
By configuring the mobile phone 10 as described above, the synchronization sequence 18A and the synchronization sequence 18B via the delay inversion unit 200 are supplied to the correlation value calculation unit 202, and the correlation between the reception sequence 14A and the synchronization sequences 18A and 18B Each value is calculated, and even the correlation value difference is calculated only by the correlation value calculation unit 202, and the calculated output can be supplied as a correction amount to the control value calculation unit 204. The control value calculation unit 204 Is output. By this control, the oscillator 16 and the code generator 18 are controlled so that the code synchronization with the reception sequence 14A is maintained. Since only one difference in correlation value, which is the control data, is required, the circuit mounting area can be greatly reduced. Further, since the power consumption of the circuit can be reduced as the circuit scale is reduced, the battery life of the mounted device can be extended.
[0086]
In the code synchronization performed in the present invention, since the position of the synchronization timing of the reception sequence is the center position of the synchronization sequence, it is preferable to consider the phase of this reception sequence at the time of demodulation.
[0087]
【The invention's effect】
As described above, according to the spread spectrum receiver and the synchronization holding circuit of the present invention, the correction control means calculates the second signal of the code sequence output from the code generation means and the third signal via the delay inversion means. And calculating the correlation value between the first signal, the second signal, and the third signal, calculating the difference between the correlation values only by this computing means, and using the calculated output as a correction amount. It can be supplied to the timing control means, and the control amount is output by the timing control means. By this control, the oscillating means and the code generating means are controlled so that the code synchronization with the first signal is maintained. Since only one difference in correlation value, which is the control data, is required, the circuit mounting area can be greatly reduced. In addition, since the power consumption of the circuit can be reduced as the circuit scale decreases, the battery life of the mounted device can be extended.
[0088]
Further, according to the synchronization maintaining method of the present invention, the phase difference between the code phase of the first signal and the code phase of the second signal is detected, and the supply of the timing is controlled by correcting the detected phase difference. In this case, the first correlation obtained by delaying the code phase of the second signal, generating the inverted third signal of the second signal, and correlating the first signal with the second signal When calculating the value and the second correlation value obtained by the correlation processing on the third signal and the second signal, the code interval in which the first correlation value and the second correlation value are calculated is the code interval The first code, the last code, and the code between the first code and the last code are divided into three operations, thereby improving the number of operations and simplifying the process. The difference between these correlation values is calculated using the correlation value of 1 and the second correlation value. By improving the number of operations, the hardware circuit configuration is also improved. This greatly reduces the circuit mounting area and also reduces power consumption by the circuit, so that the battery life of the mounted device can be extended.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration when a spread spectrum receiving apparatus according to the present invention is applied to a mobile phone.
2 is a block diagram showing a basic configuration of a synchronization holding circuit and a delay locked loop used in FIG. 1;
FIG. 3 is a block diagram showing a basic configuration of a conventional synchronization holding circuit and delay locked loop used for the comparison of FIG. 2;
4 is a block diagram showing a schematic configuration of a correlation value calculation unit in FIG. 3;
5 is a timing chart showing the relationship between a reception sequence supplied to the mobile phone of FIG. 1 and a generated synchronization sequence.
6 is a diagram schematically illustrating the relationship between code synchronization and synchronization shift in the timing relationship of FIG. 5. FIG.
7 is a block diagram showing a configuration in a first embodiment of a correlation value calculation unit applied to the synchronization holding circuit of FIG. 2; FIG.
FIG. 8 is a block diagram showing a configuration in a second embodiment of a correlation value calculation unit applied to the synchronization holding circuit of FIG. 2;
FIG. 9 is a block diagram showing a configuration of a modification of the second embodiment in the correlation value calculation unit of FIG. 8;
10 is a block diagram showing a configuration of a third embodiment of a correlation value calculation unit applied to the synchronization holding circuit of FIG. 2; FIG.
11 is a block diagram showing a configuration of a modified example of the third embodiment in the correlation value calculation unit of FIG.
[Explanation of symbols]
10 Mobile phone
12 Antenna
14 Temporary demodulation unit
16 Oscillator
18 Code generator
20 Synchronization adjustment section
22 Demodulator
20c Sync hold circuit
202 Correlation value calculator

Claims (5)

A first signal is obtained as a reception sequence by receiving a signal obtained by performing spread spectrum modulation on an original signal including information with a predetermined spread code sequence, and based on the timing of a signal obtained from a timing supply means for supplying a built-in timing. And a code generation means for outputting a code sequence generated in the same manner as the spreading code sequence, the code sequence output by the code generation means is a second signal, and the spreading code of the first signal and the second signal In a synchronization holding circuit that synchronizes the phase of a sequence, the circuit includes:
A correction control unit that detects a phase difference between the code phase of the first signal and the code phase of the second signal, corrects the detected phase difference, and controls the timing supply unit;
The correction control means delays the code phase of the second signal and delay inversion means for inverting the second signal;
When the first correlation value obtained by the correlation processing on the first signal and the second signal and the output from the delay inversion means is the third signal, the third signal and the second signal Computing means for computing a difference from a second correlation value obtained by correlation processing on the signal;
Timing control means for performing control for correcting the phase difference on the basis of the correlation value output from the calculation means, on the timing supply means,
The computing means is
Multiplication means for doubling the value of the code sequence of the first signal;
First selection means for switching and selecting between the second signal and the third signal;
Second selection means for selecting one input signal from a plurality of input signals;
First switching control means for controlling switching selection of the first selection means and the second selection means in response to the code phase of the second signal and the code phase of the third signal;
Multiplication means for performing a correlation operation based on the signals respectively supplied from the first and second selection means;
Fixed value output means for outputting a predetermined value;
Third selection means for selecting one input signal from a plurality of input signals;
Second switching control means for performing switching selection of the third selection means by comparing and judging the values of the second signal and the third signal;
Adding a selection result of the third selection means and a value held immediately before the selection result, and accumulating means for accumulating the addition result;
The second selection means is supplied with the output of the multiplication means and the first signal,
A synchronization holding circuit, wherein the third selection means is supplied with signals from the fixed value output means and the multiplication means, respectively. A first signal is obtained as a reception sequence by receiving a signal obtained by performing spread spectrum modulation on an original signal including information with a predetermined spread code sequence, and based on the timing of a signal obtained from a timing supply means for supplying a built-in timing. And a code generation means for outputting a code sequence generated in the same manner as the spreading code sequence, the code sequence output by the code generation means is a second signal, and the spreading code of the first signal and the second signal In a synchronization holding circuit that synchronizes the phase of a sequence, the circuit includes:
A correction control unit that detects a phase difference between the code phase of the first signal and the code phase of the second signal, corrects the detected phase difference, and controls the timing supply unit;
The correction control means delays the code phase of the second signal and delay inversion means for inverting the second signal;
When the first correlation value obtained by the correlation processing on the first signal and the second signal and the output from the delay inversion means is the third signal, the third signal and the second signal Computing means for computing a difference from a second correlation value obtained by correlation processing on the signal;
Timing control means for performing control for correcting the phase difference on the basis of the correlation value output from the calculation means, on the timing supply means,
The arithmetic means calculates a control sequence represented by using a plurality of values when a range of values obtained by subtraction using the second signal and the third signal covers a plurality of values. Control sequence generation means for generating;
Control means for controlling the control sequence generating means in response to the code phase of the second signal and the third code phase;
Second inversion means for inverting the sign of the first signal;
Multiplication means for doubling the value of the code sequence of the first signal;
Third inversion means for inverting the output of the multiplication means;
Fixed value output means for outputting a predetermined value;
Fourth selecting means for selecting one input signal from a plurality of input signals;
Adding a selection result of the fourth selection means and a value held immediately before the selection result, and accumulating means for accumulating the addition result;
The fourth selection means is supplied with the first signal, the output of the second inversion means, the output of the multiplication means, the output of the third inversion means, and the output of the fixed value output means, A synchronization holding circuit, wherein the selection is performed in response to a control sequence from the control sequence generation means. A first signal is obtained as a reception sequence by receiving a signal obtained by performing spread spectrum modulation on an original signal including information with a predetermined spread code sequence, and based on the timing of a signal obtained from a timing supply means for supplying a built-in timing. And a code generation means for outputting a code sequence generated in the same manner as the spreading code sequence, the code sequence output by the code generation means is a second signal, and the spreading code of the first signal and the second signal In a synchronization holding circuit that synchronizes the phase of a sequence, the circuit includes:
A correction control unit that detects a phase difference between the code phase of the first signal and the code phase of the second signal, corrects the detected phase difference, and controls the timing supply unit;
The correction control means delays the code phase of the second signal and delay inversion means for inverting the second signal;
When the first correlation value obtained by the correlation processing on the first signal and the second signal and the output from the delay inversion means is the third signal, the third signal and the second signal Computing means for computing a difference from a second correlation value obtained by correlation processing on the signal;
Timing control means for performing control for correcting the phase difference on the basis of the correlation value output from the calculation means, on the timing supply means,
The computing means is
Control sequence generation for generating a control sequence represented using a plurality of values when a range obtained by subtraction using the second signal and the third signal covers a plurality of values Means,
Control means for controlling the control sequence generating means in response to the code phase of the second signal and the third code phase;
Multiplication means for doubling the value of the code sequence of the first signal;
Third inversion means for inverting the output of the multiplication means;
Fixed value output means for outputting a predetermined value;
Fourth selecting means for selecting one input signal from a plurality of input signals;
Adding a selection result of the fourth selection means and a value held immediately before the selection result, and accumulating means for accumulating the addition result;
The fourth selection means is supplied with the first signal, the output of the multiplication means, the output of the third inversion means and the output of the fixed value output means, and a control sequence from the control sequence generation means A synchronization holding circuit characterized by selecting in response to A first signal is obtained as a reception sequence by receiving a signal obtained by performing spread spectrum modulation on an original signal including information with a predetermined spread code sequence, and based on the timing of a signal obtained from a timing supply means for supplying a built-in timing. And a code generation means for outputting a code sequence generated in the same manner as the spreading code sequence, the code sequence output by the code generation means is a second signal, and the spreading code of the first signal and the second signal In a synchronization holding circuit that synchronizes the phase of a sequence, the circuit includes:
A correction control unit that detects a phase difference between the code phase of the first signal and the code phase of the second signal, corrects the detected phase difference, and controls the timing supply unit;
The correction control means delays the code phase of the second signal and delay inversion means for inverting the second signal;
When the first correlation value obtained by the correlation processing on the first signal and the second signal and the output from the delay inversion means is the third signal, the third signal and the second signal Computing means for computing a difference from a second correlation value obtained by correlation processing on the signal;
Timing control means for performing control for correcting the phase difference on the basis of the correlation value output from the calculation means, on the timing supply means,
The computing means is
Second switching control means for performing switching control by comparing and determining the values of the second signal and the third signal;
Control means for controlling the second switching control means in response to the code phase of the second signal and the third code phase;
Multiplication means for doubling the value of the code sequence of the first signal;
Multiplication means for performing a correlation operation based on the output of the multiplication means and the second signal;
Fixed value output means for outputting a predetermined value;
Fourth selecting means for selecting one input signal from a plurality of input signals;
Adding a selection result of the fourth selection means and a value held immediately before the selection result, and accumulating means for accumulating the addition result;
The fourth selection means is supplied with the first signal, the output of the multiplication means, and the output of the fixed value output means, and is selected in response to a switching signal from the second switching control means. A synchronization holding circuit.   The communication apparatus which has a synchronous holding circuit of any one of Claims 1 thru | or 4.

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