JP2000216703A - Error estimate device for direct spread reception data and direct spread receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error estimate device for direct spread reception data that can simply estimate a bit error rate from received data, and to provide a direct spread receiver. SOLUTION: A 1st stage interference canceller 51 generates a replica of an interference signal included in a direct spread signal on the basis of an output of a Rake reception section 3. The direct spread signal from which the effect of an interference signal is reduced is generated by subtracting the replica from the direct spread signal passing through a delay section 4, inverse spread processing is applied to the direct spread signal and received data are outputted. An error output section 7 outputs the rate of dissidence between an input data value to and an output data value from a 2nd stage interference canceller 52.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a DS-CDMA.
(Direct Sequence-Code Division Multiple Acces
s) The present invention relates to a direct spread receiving apparatus used in a system or the like and an error estimating apparatus for direct spread received data.

[0002]

2. Description of the Related Art As a DS-CDMA system, a CDMA cellular telephone system (TIA) standardized in North America.
IS95). In this system, in a downlink, a pilot symbol is inserted into a pilot channel and transmitted, and a receiving side detects a carrier phase based on a received signal of the pilot channel and performs synchronous detection. FIG. 9 is a diagram illustrating a configuration of a downlink in the DS-CDMA system. 101 is a base station, 1
02 is a slave station. The downlink is a link from the base station 101 to the slave station 102. FIG. 10 is a schematic configuration diagram of a transmission device of a base station in a DS-CDMA system.
In the code multiplexing unit 103, the data of the communication channel from data 1 to data N (N is an integer of 1 or more) and the data set to all 1s for the pilot channel are:
The orthogonal codes generated by the orthogonal code generator 107 are respectively assigned and code-multiplexed, and are directly spread by being multiplied by the PN signal from the PN generator 108 in the multiplier 104. 109 is multiplied (modulated) by a reference frequency signal (carrier) 109, and is put on the carrier to transmit the signal.
Sent from

FIG. 11 is a schematic configuration diagram of a receiving device of a slave station in a DS-CDMA system. Receiving antenna 1
The signal received by 10 is multiplied by a sine wave reference frequency signal of reference frequency oscillator 112 in multiplier 111 to be converted into a baseband reception signal. DS-C
As a feature of the demodulator of the DMA system, a Rake reception method is adopted. Since the signal transmitted from the base station reaches the receiving antenna 110 through a plurality of paths,
The received signal is obtained by combining a plurality of signals having different amplitudes, carrier phases, and delay times. In the Rake reception method, a baseband reception signal is despread, separated into reception signals of paths 1 to K and subjected to maximum ratio combination (Rake combination), thereby forming one impulse response to obtain a reception signal. Improve C / N characteristics.

[0004] A baseband received signal is output to a rake receiving section 121 and a searcher section 122. The baseband received signal is input to _K fingers 118 _{1 to} 118 K in Rake receiving section 121.
Each of the fingers 118 _{1 to} 118 _K is a demodulator for the _{first to K-} th paths, respectively. In the illustrated example, signals of up to K paths can be received. Each finger 118 _{1 -1}
18 _K have the same configuration. The baseband received signal is multiplied by the PN code output from the PN generator 114 in the multiplier 113 to obtain PN synchronization, and the slave station output from the orthogonal code generator 117 in the multiplier 115. The signal is multiplied by the orthogonal code of the communication channel of the user (hereinafter, referred to as “user”), and is despread by the integrator 116 by integrating the received signal of the communication channel of the user over one symbol period. From the fingers 118 _{1 to} 118 _K , despread received signals of the user's communication channel on the corresponding paths _{1 to K} are output to the combining circuit 119.

Here, a timing signal for each of the paths 1 to K is supplied to the PN generator 114 and the orthogonal code generator 117 from a control unit 129 in the searcher unit 122 for estimating an impulse response. As a result, the PN generator 114 and the orthogonal code generator 117 output the PN code and the orthogonal code synchronized with the PN code and the orthogonal code of the corresponding paths 1 to K, respectively.

[0006] In the searcher section 122, the baseband received signal is supplied to a multiplier 123 by a PN generator 12.
4 is multiplied by the PN code output from the P.4, and is multiplied by the orthogonal code of the pilot channel output from the orthogonal code generator 126 in the multiplier 125 to separate the pilot channel received signal. Next, the integrator 127
Represents a received signal amplitude of a baseband of a pilot channel in a certain path k and a phase (carrier phase) with respect to a reference frequency signal through a filter 128 which integrates one symbol and further performs averaging for a plurality of symbols. The reference signal W (k) is generated and the control unit 12
9 is output. W (k) is a complex number, and k = 1 to K. As paths 1 to K, the path with the larger power is K
Are selected.

In the control unit 129, the PN generator 12
The timing of the PN generator 124 is controlled so that the PN code 4 is code-synchronized with the received signal, and the timing of the orthogonal code generator 126 is controlled so that the orthogonal code of the orthogonal code generator 126 is code-synchronized with the received signal. Control unit 12
Reference numeral 9 divides the time to generate K reference signals W (k) for K fingers. Also, by dividing the time, Rak
PN of K fingers 118 ₁ - 118 _K of e receiver 121
A timing signal is output to generator 114 and orthogonal code generator 117.

In the synthesizing circuit 119, each finger 1
18 ₁ signal communication channels of a user from - 118 _K on the basis of the reference signal W (k) obtained from the received signal of the pilot channel of each path 1 to K, a communication channel of the user in the respective paths 1 to K Synchronous detection is performed by removing the phase offset of the received signal.
e Combined. The rake-combined received signal is decoded by the decoding unit 120, and desired data of the communication channel of the own station is output.

As described above, by estimating the impulse response of each path k by using the despread received signal of the pilot channel on which known data is transmitted, the phase offset of the received signal of each path k can be calculated. Has been removed. Although not shown, the two multipliers 111 shown in FIG.
Are also multiplied by a quadrature reference frequency signal that is orthogonal to the reference frequency signal to become two series of baseband reception signals (usually represented by complex numbers) that are in-phase and orthogonal to the reference frequency signal. The subsequent processes are individually performed on the two sequences, and the combining circuit 119 synchronously detects the two sequences as an in-phase component and a quadrature component with respect to the phase of the reference frequency signal (carrier).

Generally, DS-CDMA is used for high-speed data transmission.
If the system is to be used, the chip rate naturally increases due to the increase in the data rate. As the chip rate increases, the amount of interference due to multipath increases. When the number of multipaths increases, deterioration of transmission performance can no longer be prevented by the Rake reception method. Time delayed path 1
When the arrival wave of the path K is received and the arrival wave of a certain path k is despread, the arrival wave of another time-delayed path becomes an interference signal. Therefore, an impulse response of one path k includes an interference wave component generated by a cross-correlation with an incoming wave of another path. Therefore, if the impulse responses of the paths 1 to K are rake-combined, the transmission performance deteriorates.

As a technique for eliminating such multipath interference, there is an interference canceller technique. For example, Wada et al., “A study of a multi-user multi-stage interference canceller in a B5-140 DS-CDMA system”, IEICE Society Conference (19
98.9). Such an interference canceller is disclosed in Japanese Patent Application No. Hei 10-236777.
No. has been filed.

In brief, an accurate impulse response is estimated using a pilot channel or the like. K paths having a large amplitude are selected, and the value is set to Wk. The path P having the maximum amplitude value is selected. The rake reception data or output data of the preceding stage interference canceller is input to the interference canceller. Further, an interference replica for each user is generated using a spreading code and Wk for each path other than the maximum amplitude path P. By subtracting interference replicas of all users from the received signal, despreading is performed on path P, and data for all users is detected. That is, Wk is estimated in advance, and information of radio wave propagation is fixed after the estimation.

As a method for canceling an interference signal by a different method, Sawahashi et al., "Channel estimation successive update type DS-CD using pilot and data symbols"
MA Coherent Multistage Interference Canceller, ”IEICE Technical Report 96 (354), IEICE (1996-
11) RCS96-100, p. Also known as 9-16.

In brief, a DS-CDMA system having a pilot symbol periodically in a frame, and cancels one user at a time from a user having a large power. In the user k, the interference replica at the i-stage for the user having a higher power than the user k and the interference replica at the i-1 stage for the other user having the lower power are removed. , Respectively, removes interference replicas other than each path, estimates the impulse response in each path using pilot symbols, and performs despreading based on the value. The signals despread in each path are rake-combined. After the combining, an interference replica is generated based on the decoded data and the estimated impulse response.

In the above-described interference canceller technology for removing interference due to multipath, a multistage type in which interference cancellers are cascaded in multiple stages is effective in order to improve the characteristics of the interference canceller. However, when the interference canceller is connected and operated in many stages, there is a problem that processing delay time and power consumption increase. Also, the reception quality information may be transmitted to the base station by estimating the bit error rate at the slave station. In such a case, however, there is a problem that the bit error rate cannot be easily estimated from the received data. there were.

Here, a first example of the above-described interference canceller technique, which is a technique described in the prior application (hereinafter referred to as the prior art) for estimating an impulse response and canceling interference of a path except for at least a path P having a maximum power. , Called prior art)
, The function of the interference canceller will be specifically described. FIG. 12 is a basic block configuration diagram of the prior art. This is a case where a code-multiplexed channel sharing one PN code consists of one communication channel (one user) and one pilot channel. On the other hand, FIG. 11 has a slightly different premise because there are a plurality of code-multiplexed communication channels (users) sharing one PN code, but the Rake unit will be described with reference to FIG. I do.

In this basic configuration, the impulse response is estimated, the reference signal W (k) representing the impulse response is fixed, and the rake receiving section 121 detects the output data DR. In addition, the power maximum path detector 131
Selects the path P having the maximum power based on the reference signal W (k). In the interference canceller 133, R
Using the data output from the ake receiving unit 121 as initial data, in paths other than the path P having the maximum power,
A signal before the synchronous detection and the despreading is generated, and a signal of the pilot channel before the despreading is generated based on the known data of the pilot channel in a path other than the path P having the maximum power. Then, the interference replica is subtracted from the received signal, and the data is detected again by performing despreading and synchronous detection again on the path P having the largest power. In this manner, the bit error rate is improved by removing the interference that is a cause of the deterioration of the received signal quality.

In searcher section 122 shown in FIG. 11, K paths with large power obtained by despreading the pilot channel received signal are selected, and reference signal W is used as the value of the impulse response of each of paths 1 to K. (K) (k
= 1 to K). The power maximum path detector 131 is
From the reference signal W (k), the path P with the maximum power is selected, and the value of P is output to the interference canceller 133.

FIG. 15 is a diagram for explaining the operation of the interference canceller 133. The signal transmitted from the base station 1 passes through a plurality of paths and is received as a combination of signals having different delay times. The upper diagram shows an impulse response by multipath. A path P having the maximum power is selected, and a baseband received signal before performing synchronous detection and despreading in another path is virtually generated based on the detection data and pilot channel data, and is subtracted. The received signal is subjected to despreading in the path P having the maximum power, and data in which an interference signal is canceled as shown in the lower part is detected.

The path P having the maximum power has a small ratio including an interference signal, and the paths other than the path P are estimated to be mainly interference signals. Then, the Rake receiving unit 12
The data DR that is likely to be output from the communication channel 1 of one user is used as an initial value, and a signal before the synchronous detection and despreading is generated from the signal DR by performing reverse signal processing. At the same time, it generates a previous signal of the pilot channel to be despread based on a known data D _p of the pilot channel. In this way, interference replicas in paths 1 to K excluding path P are generated.
Then, when all the interference replicas of the paths 1 to K excluding the path P are subtracted from the baseband reception signal, the baseband reception signal is almost only the path P.

Therefore, the interference canceller 133 has
Using output data DR of one communication channel output from ake receiving section 121 and known data D _p of the pilot channel, K−1 excluding path P having the maximum power.
Generate interference replicas for the paths. Then, despreading is performed again on the path P for the baseband reception signal obtained by removing the interference replica from the baseband reception signal. In this way, it is possible to perform despreading on a baseband received signal substantially the same as when it is assumed that only an incoming wave of a single path P has been received. As a result, the received data DC of the communication channel from which the interference signal due to the cross-correlation of the path is removed is obtained. The delay unit 132 compensates for a processing delay required for Rake reception in the Rake reception unit 121.

FIG. 13 is an internal configuration diagram of the interference canceller 133 shown in FIG. The interference replica generation unit 135 for one user generates interference replicas for K-1 paths excluding the path P for the only communication channel used by only one user. Further, the pilot channel interference replica generating unit 135 _p generates interference replicas for the K−1 paths excluding the path P for the pilot channel.

FIGS. 14A and 14B show the interference replica generators 135 and 135 shown in FIG. 13, respectively.
It is an internal block diagram of p. Regarding the interference replica generation unit 141 ₁ for the path 1, the data DR output from the Rake receiving unit 121
Is multiplied by the reference signal W ₁ (1)
The carrier phase and amplitude of the path 1 are returned to the signal before the synchronous detection, which has the signal point phase and amplitude added. Next, in multiplier 139, P
The despreading has a time delay of path 1 by being multiplied by the N code PN ₁ (1) and the orthogonal code WS ₁ (1) for one user's path 1 in the multiplier 140 and spread. The interference signal is returned to the baseband reception signal before the transmission, and an interference replica of path 1 is generated. Same configuration as that of the interference replica generation unit 141 ₁ for the path 1 is located 1 K-piece with the exception of the path P, these K-1 pieces of signals are added by the adder 142, the output signal path P Excluded are the output signals of the interference replicas of paths 1 to K.

Here, W ₁ (k) (k = _{1 to} K, k = P
Is a reference signal output by the control unit 129 shown in FIG. 11, and PN ₁ (k) (except k = _{1 to} K, k = P).
Is the PN generator 1 of the finger 118 _k shown in FIG.
14, the PN code and the orthogonal code WS ₁ (k) (k =
1 to K, k = P) are based on the orthogonal code of one user output from the orthogonal code generator 117 of the finger 118 _k shown in FIG. However, as in the case where the baseband reception signal in FIG. 12 is delayed by the delay unit 132, a time delay is provided to compensate for the processing delay in the Rake reception unit 121. The time delay is adjusted in consideration of the processing delay. W ₁ (k), PN ₁ (k), and WS ₁ (k) correspond to the control unit 129, the PN generator 114, and the orthogonal code generator 1 described above.
Each of the seventeen outputs can be made by providing a delay unit similar to the delay unit 132.

[0025] shown in FIG. 14 (b), the interference replica generation unit 135 _p for the pilot channel, known data D _p of the pilot channel, a multiplier 13
At 8, the signal is multiplied by the reference signal W ₁ (1) for path 1 to become a signal having the signal point phase and amplitude given the carrier phase and amplitude of path 1.
Next, PN ₁ (1) which is a PN code for path 1 in multiplier 139, and orthogonal code WS for pilot channel path 1 in multiplier 140
_By being multiplied by ₁ (p, 1) and spreading, respectively, the baseband reception signal having the time delay of path 1 before being despread is returned to generate an interference replica of path 1. Figure 14 similarly to (a), the same configuration as the interference replica generation unit 141 ₁ for the path 1 is located 1 K-piece with the exception of path P, these K-1 pieces of signal adders 1
42, the output signal becomes the output signal of the interference replica of the paths 1 to K excluding the path P.

Here, W ₁ (k) (k = _{1 to} K, k = P
Is a reference signal output from the control unit 129 shown in FIG. 11, and PN ₁ (k) (except k = _{1 to} K, k = P) is a PN generator 124 of the searcher unit 122 shown in FIG. PN code (PN generator 1 with finger 118 _k )
14), and the orthogonal code WS ₁
(P, k) (except k = 1 to K, k = P) is based on the orthogonal code of the pilot channel output from the orthogonal code generator 126 of the searcher unit 122 shown in FIG. However, a time delay is provided to compensate for the processing delay in the Rake receiving unit 121, and the time delay is adjusted in consideration of the processing delay inside the interference canceller 133. W ₁ (k), PN ₁ (k), WS ₁ (p, k)
Can be produced by providing a delay unit similar to the delay unit 132 in each of the outputs of the control unit 129, the PN generator 124, and the orthogonal code generator 126 described above.

Returning to FIG. 13, the description will be continued. In the adder 136, the output signal of the interference replica 135 is subtracted from the delayed baseband reception signal, and the result is input to the despreading unit 137 for the path P. The despreading unit 137 for this path P has the same configuration as the finger part of the path P in the finger parts 118 _{1 to} 118 _K shown in FIG. That is, the reference signal W for the path P
₁ (P), a PN code for the path P, PN ₁ (P),
And one user's orthogonal code WS for path P
_{Using 1} (P), the baseband received signal from which the interference replica has been deleted is subjected to despreading for the path P to detect data. This output data is data of one user whose transmission performance is improved by eliminating interference due to cross-correlation. The above-described reference signal W ₁ (P), PN code P
N ₁ (P) and one user's orthogonal code WS ₁ (P)
Is the reference signal W of the path excluding the path P described above.
_{Like the 1} (k), the PN code PN ₁ (k), and the orthogonal code WS ₁ (k) of one user, a time delay is provided for compensating for a processing delay in the Rake receiving unit 121 and interference is caused. The time delay is adjusted in consideration of the processing delay inside the canceller 133.

FIG. 16 shows a case where a code-multiplexed channel sharing one PN code is composed of N communication channels of N users and one pilot channel. Then, the interference cancellers corresponding to a plurality of users are the interference cancellers 151 _{1 to} 151 _{M of the 1st to} Mth stages.
Are connected in cascade. In this specific example, a plurality of interference cancellers are operated on paths of a plurality of users 1 to N to remove interference, and furthermore, a plurality of stages of interference cancellers are operated. Is done. First-stage interference canceller 151
₁ is the data DR output from the Rake receiving unit 146
(1) to DR (N) are input as probable data, and the known data of the pilot channel is input, and the more probable data DC (1,1) to DC (1, N) in which the interference signal is cancelled. ) Is output.

In the second and subsequent stages, the interference capacitors of the preceding stage are used.
The output data from the canceller is input to the next stage interference canceller.
Force data and the pilot channel is known.
Is also input. Any stage interference canceller 1
51₁~ 151_MAlso output from the maximum power path detector 131
Is selected as the maximum power path. What
Note that, among the interference cancellers at each stage, the first to (M-1) th stages
Interference canceller 151 ₁~ 151_M-1About your own station
Data of users 1 to N including data of (user 1)
Need to output. That is, the first to (M-1) th stages
Interference canceller 151₁~ 151_M-1About the user
A despreading unit for users 1 to N is required.

[0030]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to easily estimate a bit error rate from received data. Provided are an error estimating apparatus for direct-spread received data and a direct-spread receiving apparatus, which can reduce processing delay time and power consumption by adaptively controlling the number of operation stages of a multi-stage interference canceller using the same. The purpose is to do so.

[0031]

According to a first aspect of the present invention, there is provided an apparatus for estimating error of direct spread reception data, comprising the steps of: An interference canceller that generates a replica of the interference signal included in, based on a signal obtained by subtracting the replica from the direct spread signal, and outputs received data with reduced influence of the interference signal, and
An error information output means for comparing the value of the input data and the value of the output data of the interference canceller and outputting error information based on the mismatch rate. Since there is a predetermined relationship between the above-described mismatch rate and the bit error rate, a bit error can be estimated with a simple configuration.

According to a second aspect of the present invention, there is provided an error estimating apparatus for directly-spread received data, wherein an initial data receiving section for receiving a directly-spread signal and outputting received data, and a receiving section previously obtained from the direct-spread signal. Based on the data, a plurality of stages of generating a replica of the interference signal included in the direct spread signal, based on a signal obtained by subtracting the replica from the direct spread signal, and outputting received data with reduced influence of the interference signal. An interference canceller, an input of an output of the initial data receiving unit being input to a first stage of the interference canceller, an interference canceling unit in which the plurality of stages of interference cancellers operate in cascade, and each stage of the interference canceller And outputs the ratio of mismatch by comparing the value of input data and the value of output data of each stage of the interference canceller. It has a number of comparison unit and has an error information output unit that outputs the error information based on the output of the comparison unit. Therefore, a bit error can be accurately estimated with a simple configuration based on the ratio of mismatch at each stage of the interference canceller.

According to a third aspect of the present invention, in the error estimating apparatus for direct spread reception data according to the first or second aspect, there is provided a transmission means for transmitting reception quality information based on the error information. . Therefore, the base station or the like can receive the reception quality information and use this information for transmission power control or the like.

According to a fourth aspect of the present invention, in the direct spreading receiving apparatus, an initial data receiving unit for receiving a direct spreading signal and outputting received data, based on received data obtained in advance from the direct spreading signal, A replica of the interference signal included in the direct spread signal is generated, and based on a signal obtained by subtracting the replica from the direct spread signal, a multi-stage interference canceller that outputs received data with reduced influence of the interference signal is provided. In addition, the output of the initial data receiving unit is input to the first stage of the interference canceller, and the interference cancellers in which the plurality of stages of interference cancellers operate in cascade correspond to each stage of the interference canceller, and A plurality of comparators for comparing the input data value and the output data value of each stage of the canceller and outputting a mismatch ratio; An error information output unit that outputs error information based on the output of the comparison unit, and according to the error information with the cascade operation of the plurality of stages of interference cancellers, while stopping the operation of the interference cancellation unit halfway. And control means for using the output of the interference canceling unit as output data of a receiving apparatus. Therefore, the number of operation stages of the interference cancellation unit can be adaptively determined according to the error information, so that processing delay time and power consumption can be reduced. Further, based on the ratio of mismatch of each stage of the interference canceller, with a simple configuration,
Bit errors can be accurately estimated.

According to a fifth aspect of the present invention, in the direct spread receiving apparatus, an initial data receiving unit for receiving a direct spread signal and outputting received data, based on received data obtained in advance from the direct spread signal, A replica of the interference signal included in the direct spread signal is generated, and based on a signal obtained by subtracting the replica from the direct spread signal, a multi-stage interference canceller that outputs received data with reduced influence of the interference signal is provided. In addition, the first stage of the interference canceller inputs the output of the initial data receiving unit, and the plurality of stages of interference cancellers operate in cascade, corresponding to a predetermined stage of the interference canceller, A comparison unit that compares a value of input data and a value of output data of a predetermined stage of the interference canceller and outputs a ratio of mismatch; An error information output unit that outputs error information based on the output of the comparison unit, and with the cascade operation of the plurality of interference cancellers, the number of stages for cascading the plurality of interference cancellers according to the error information. And a control unit that determines the output of the interference canceling unit and uses the output of the interference canceling unit as output data of a receiving device. Therefore, the number of operation stages of the interference cancellation unit can be adaptively determined according to the error information, so that processing delay time and power consumption can be reduced.

According to a sixth aspect of the present invention, in the direct spread receiving apparatus according to the fourth or fifth aspect, the initial data receiving section is a Rake receiving section that receives a direct spread signal. Therefore, reliable initial reception data can be obtained using the existing Rake reception unit.

According to a seventh aspect of the present invention, in the direct spreading receiver according to any one of the fourth to sixth aspects, there is provided a transmitting means for transmitting reception quality information based on the error information. is there. Therefore, the base station or the like can receive the reception quality information and use this information for transmission power control or the like.

[0038]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an apparatus for estimating an error of direct-spread reception data according to the present invention; FIG. 1 is a block diagram illustrating a first embodiment of an error estimating apparatus for direct-sequence received data and a direct-sequence receiving apparatus according to the present invention. In the figure, 1
Is a receiving antenna, 2 is a baseband converter, 3 is Rak
e receiving unit, 4 is a delay unit, 5 ₁ and 5 ₂ are interference cancellers, 6
₁ is a delay unit, 7 is an error output unit. The direct spread signal received by the receiving antenna 1 is multiplied by a reference frequency signal in a baseband converter 2 to be converted into a baseband signal, and is input to a Rake receiver 3. In the Rake receiving unit, the direct spread signal is despread and synchronously detected, and the received data is output after maximum ratio combining. Rak
The e-receiving unit provides initial data that is necessary for the interference canceling operation and is somewhat certain. Instead, initial data that is likely to some extent may be detected by another method. For example, in the case of the above-described prior art, the baseband received signal is despread for the path P having the maximum power, and its output is decoded to be initial data.

The first stage of the interference canceller 5 _1, Rake
Based on the output of the receiving unit 3, a replica of the interference signal included in the direct spread signal is generated. By subtracting the replica from the direct spread signal that has passed through the delay unit 4 for compensating the processing delay time of the Rake receiving unit 3, a direct spread signal with reduced influence of the interference signal is generated, and the influence of the interference signal is reduced. The received data is output by despreading and decoding the reduced direct spread signal.

Second stage interference canceller 5_TwoIs the first stage
It is similar to the interference canceller. However, to some extent
First stage interference canceller 5 as new received data₁of
Use the output. The baseband direct spread signal is
4 to delay unit 6₁Interference canceller 5 through_TwoEnter
Is forced. Delay unit 6₁Is the first-stage interference canceller 5 ₁To
Compensate for processing delays. First-stage interference canceller 5
₁Is output from the Rake receiver 3
Received signal with less influence of interference than received data
The second stage interference canceller 5_TwoIs the first stage
Interference canceller 5₁Is better than the incoming data
Perform interference cancellation using a reliable input signal.
Output more likely received data.

The error output unit 7, and the value of the second-stage interference canceller 5 and _second input signals (1 stage receiving data output from the interference canceller 5 _1), the interference signal which is the output data of the interference canceller 5 ₂ Is compared with the value of the received data in which the influence of the data is reduced, and a ratio at which the respective values become inconsistent is output, thereby outputting a bit error rate difference estimated value as described later. The interference canceller and error output unit at each stage can be realized by hardware, or can be realized by software by a CPU that executes a program.

FIG. 2 is a schematic block diagram of the error output section shown in FIG. In the figure, reference numeral 11 denotes an exclusive OR (XO
R) and 12 are counters, 13 is a division unit, and 14 is a calibration unit. The input data and output data to the interference canceller 5 ₂ are compared in exclusive OR (XOR) 11. This operation outputs 1 if the values of the two data (bits in the case of binary) are different, and outputs 0 if the values of the two data are the same. Therefore, the interference canceller 5 _2, the result of the interference cancellation, when the erroneous received data is changed to correct the received data, output becomes 1 exclusive OR (XOR) 11, the received data to the interference canceller 5 ₂ It is presumed that there was an error.

Incidentally, in the exclusive OR 11, the received data input to the interference canceller 5 _2, and data of a certain bit position, the influence of the interference signal data in the interference canceller 5 ₂ of this bit position is reduced Needs to be compared with the data that is output again as received data. Therefore, although not shown, the input data 11, either through a delay circuit only delaying processing delay time in the interference canceller 5 _2, and stored in the memory,
The data is read out in synchronization with the output bit position.

The counter 12 has an exclusive OR (XOR).
The number of 1s output by 11 is counted. In dividing unit 13 the output, divided by the total input data rate, the second-stage interference canceller 5 ₂ bit error rate of the output of a reference (assumed to zero), the relative bit error of the input data You can get an estimate of the rate. Another point of view, the difference value of the bit error rate between the input and output data of the interference canceller 5 _second stage (difference estimate of bit error rate) is estimated.

[0045] If the assumed error by the second-stage interference canceller 5 ₂ is sufficiently corrected, the output of the division unit 13, rather than as a difference estimate of the error rate, as it is,
It can also be estimated to be an absolute bit error rate.
However, in order to improve the accuracy of the estimated value of the bit error rate, the calibration unit 14 creates a correlation between the difference value of the bit error rate and the value of the absolute bit error rate in advance as a calibration database. In addition, the absolute bit error rate can be more accurately estimated using the database. When the calibration unit 14 is operated,
The output of the calibration unit 14 is output as an estimated value of the error rate.

FIG. 3 is a diagram showing the error rate characteristics of the received data output from the cascade-connected interference canceller. In the figure, the horizontal axis represents the signal power per bit as Eb, 1 Hz.
Average Eb / No when the noise power per unit is No
No. The vertical axis represents the average bit error rate in logarithmic scale, E ₁ is the first-stage interference canceller 5 ₁ average bit error rate, E ₂ is the average bit error rate of the interference canceller 5 ₂ in the second stage. Absolute average bit error rate E ₁ and E ₂ itself shown, can be determined by simulation, it is not easy to actually measured. However, the ratio obtained by the error output unit shown in FIG. 2, the value of the input data of the interference canceller 5 ₂ and the value of the output data are different, the difference value of the average bit error rate (E ₂ -E ₁₎ Estimation You are doing.

The difference value of the average bit error rate (E ₂ −E ₁ )
Becomes smaller as the value a of Eb / No becomes larger. Therefore, if the average bit error rates E ₁ and E ₂ as shown in the figure are obtained in advance by simulation or actual measurement and a calibration database is created, the difference value (E ₂ From the estimate of -E ₁ ), the average bit error rates E ₁ and E ₂ themselves can be estimated. Further, the value a of Eb / No at that time can also be estimated.

As a method of estimating the absolute average bit error rates E ₁ and E ₂ themselves by actual measurement, data of a certain fixed bit string is actually transmitted, the reception side decodes a reception signal, and A method of estimating the bit error rate by comparing the decoded data with the data of the transmitted bit string can be considered. Of course, FIG.
Instead of the error output section shown in ( ₁₎ , it is also possible to always estimate the average bit error rates E ₁ and E ₂ themselves by such a method. However, not only is a communication control procedure for transmitting and receiving such a bit string necessary, but if it is performed during normal data communication, the transmission rate of user data is reduced due to the transmission of the determined data string. Become.

The error rate itself is estimated by actual measurement using the technique of the invention filed as Japanese Patent Application No. 5-045837 according to the present inventor instead of the error output section 7 shown in FIG. There are ways. This method is a method of estimating the error rate itself based on the difference between the bit error rates at the optimal sample timing and the slightly shifted sample timing at the time of digital demodulation.
However, there are disadvantages in that it is difficult to realize a circuit configuration due to the need for high-speed processing, and the power consumption of the circuit increases as the speed increases.

FIG. 4 is a block diagram for explaining an error estimating apparatus and an apparatus for directly spreading received data according to a second embodiment of the present invention. In this embodiment, up to N interference cancellers are connected in cascade. Insert the error output unit 7 ₀ between the input and output of the first stage interference canceller 5 _1, also interference canceller 5 ₂ to 5 _N of each stage was added to the error output unit 7 ₁ to _7-N-1. Error output unit 7
The internal configuration of ₀ , 7 _{1 to} 7 _N−1 is the same as that of the error output unit 7 of FIG. 6 _N-1 is the (N-1) th stage delay unit. The error output unit 7 _0, and outputs an error information corresponding to a difference between the bit error rate of the Rake receiver 3 and the first-stage interference canceller 5 ₁ bit error rate.

[0051] received at the error output unit _{7 0, 7 1 ~7 N-} 1 for each stage, and the received data input to the interference canceller 5 ₁ to 5 _N at the respective stages, output is canceled interference Ratio of different data values (estimated difference of bit error rate)
Is output as error information. Alternatively, the calibration unit 14 at each stage can estimate the absolute bit error rate from the bit error rate difference estimated value and output this as error information. Based on the error information of the error output unit for each stage, it is possible to accurately estimate the bit error rate of the final reception data in which the influence of the interference signal is reduced by the interference canceller.

After the pre-stage processing is completed, the multi-stage interference cancellers 5 _{1 to} 5 _N can use the pre-stage processing results (received data with reduced influence of interference) to perform post-stage processing. Cascade operation. Therefore, if it is only necessary to determine whether the bit error rate is lower than the predetermined threshold value Eth, the difference value of the bit error rate when the bit error rate of the output data of this stage becomes lower than the predetermined threshold value Eth Is stored, and when the difference value of the bit error rate becomes the stored value, the cascade operation of the subsequent stages can be stopped, thereby reducing the processing time, the power consumption, and the software. In addition, hardware resources can be reduced.

FIG. 5 is a block diagram for explaining a third embodiment of the apparatus for estimating an error of direct-spread reception data and the direct-spread reception apparatus according to the present invention. 21 is a judgment selection circuit, and 22 is an output data selection switch.

In this embodiment, FIG.
As in the second embodiment, the interference canceller 5₁, 5_Two~
5_NAre cascaded. At the same time,
Pull out the data selection terminal from the output of the canceller, and
Data selection switch 22 to select one and receive it.
Output as received data as a transceiver. This output data
The determination selection circuit 21 that controls the data selection switch 22
Stage interference canceller 5 ₁~ 5_NBit at the output of each stage
When the error rate becomes a bit error rate that satisfies the predetermined quality
Error output section 7 of each stage₀~ 7_N-1Detected in
The threshold of the difference estimated value of the set error rate is stored.

The decision selecting circuit 21 is connected to the error output section 7 of each stage.
₀~ 7_N-1Difference estimate of bit error rate detected at
Has fallen below the threshold value of the difference estimation value described above.
When it comes out, the interference canceller 5 performing the cascade operation₁~
5_N, And the error output unit 7 ₀~ 7_NStop the operation of
As well as the final operation stage that performed the interference cancellation operation.
The output of the interference canceller is set to an output data selection switch 22.
To select. As a result, the difference estimate of the bit error rate is
From the middle stage of the interference canceller that satisfies the reference threshold
Will also stop subsequent operations. Subsequent circuits
Since the operation or calculation need not be performed, the received data
The delay time until the
Power consumption can also be reduced.

FIG. 6 is a block diagram for explaining a fourth embodiment of the apparatus for estimating an error of direct-spread reception data and the apparatus for direct-spread reception according to the present invention. This embodiment has a configuration substantially similar to that of FIG.
Tsutoshi, in this example, corresponding to the interference canceller 5 of the _first stage, is provided with the error output unit 7 _0, may be provided on other stages.

[0057] can estimate the absolute bit error rate from the difference the estimated value of the bit error rate that is output from the error output unit 7 _0. From this absolute bit error rate, it is possible to identify at which stage of the output of the cascade-connected interference canceller the bit error rate satisfies the predetermined quality. Therefore, the number of stages of the interference canceller that satisfies the bit error rate that satisfies the predetermined quality is determined, the interference canceller is operated so that this stage becomes the final stage, and the received data as the receiving device is output from the final stage interference canceller. . However, the detection accuracy of the bit error rate is lower than that of the embodiment shown in FIG.

FIG. 7 is a block diagram for explaining a fifth embodiment of the direct spread reception data error estimating apparatus and the direct spreading reception apparatus according to the present invention. In this embodiment, the direct spreading receiver has a function of inserting error information into transmission data and transmitting the error data to another station.
This is used, for example, for optimal transmission power control or the like by transmitting, to a base station, quality information of received data finally output from the mobile terminal. As the quality information of the received data, for example, a difference estimated value of the bit error rate or an estimated value of the absolute bit error rate created by the calibration unit may be used. The receiving device only needs to output one estimated value of the absolute bit error rate. Therefore, when there are a plurality of error output units, the calibration unit of one of the error output units may be operated. In addition to the use in the receiving device, the error estimation device for the direct spread reception data may similarly transmit the quality information of the received signal to another station. Further, in this embodiment, the apparatus shown in FIG. 1 is premised, but the present invention can be similarly applied to apparatuses in other embodiments.

FIG. 8 is a diagram showing the result of computer simulation of the direct spread receiver according to the present invention. This is applied to the interference canceller described as the prior art. That is, a signal receiving apparatus in a DS-CDMA system, which receives a received signal and estimates an impulse response for K paths, and a path having a maximum power from an output of the impulse response estimating means. Path selecting means to select, despreading means for despreading at least the user channel of the own station in the K paths for the received signal, by performing synchronous detection on the output signal of the despreading means, Initial data output means for outputting at least the initial data of the user channel of the own station, multiple-stage interference replica generation means, and multiple-stage data output means, the first-stage interference replica generation means, On the basis of the initial data, a path excluding at least the path where the power is maximum Generating a signal before performing the synchronous detection and the despreading, thereby virtually generating at least the reception signal of the user channel of the own station in a path excluding at least a path where the power is maximum. The interference replica generation means of the second and subsequent stages, based on output data of the data output unit of the previous stage of the stage, the synchronous detection and the By generating a signal before performing despreading, in the path except at least the path where the power is maximum, at least the reception signal of at least the user channel of the own station is virtually generated, and the data output unit is , The power is maximized for a signal obtained by subtracting the output signal of the interference replica generation means of the stage from the received signal. De-spreading again for at least the user channel of the own station in the base station, and performing the synchronous detection again on at least the user channel of the own station for the signal subjected to the de-spreading again. The data of the user channel is output.

In particular, the received signal includes a plurality of user channels, and the despreading means despreads the received signal with respect to the plurality of user channels in the K paths, and outputs the initial data. Outputs the initial data of the plurality of user channels, and the first-stage interference replica generation unit and the second-stage and subsequent interference replica generation units output at least a path excluding a path at which the power becomes maximum. The data output means excluding the last stage virtually generates the reception signals of the plurality of user channels, performs the despreading again on the plurality of user channels in the path where the power is maximum, and performs the despreading again. By performing the synchronous detection on the plurality of user channels for the despread signal, Data of the user channel is output, and the data output means at the final stage performs the despreading again on the plurality of user channels in the path where the power is maximum, and for the signal on which the despreading is performed again, By performing the synchronous detection on at least the user channel of the own station, data of at least the user channel of the own station is output.

The chip rate of the computer simulation is 1 Mcps, the fading environment is equal power Rayleigh fading of 4 waves (100 Hz), the number of users (the number of code multiplexing) is 24, the number of fingers K for Rake reception is 4, and the filter in the searcher unit 168 A moving average filter 128 has eight symbols in the average section. Although the description is omitted in the description of the prior art, the carrier phase accuracy is improved by correcting the phase error of the searcher unit 168 in FIG. 11 and estimating Wk. The horizontal axis is 1
This is the average Eb / No when the signal power per bit is Eb and the noise power per Hz is No. The vertical axis is the average bit error rate.

In FIG. 5, bit error rate estimated value QI
(I) compares the output data of the i-th interference canceller with the output data of the (i + 1) -th interference canceller, and calculates the ratio of the number of mismatched data to the total number of data. That is, the bit error rate estimated value QI (i) is a bit error rate difference estimated value output from the division unit 13 without using the calibration unit 14 shown in FIG. However, this is shown as an absolute bit error rate estimate as it is. Also, QI (0) is the difference estimate of bit error rate by interference canceller 5 ₁ between the Rake receiver 3 first stage.

[0063] As is apparent from this diagram, the bit error rate of the output data of the Rake receiver 3 to the bit error rate estimate QI in the error output unit 7 ₀ (0) (open circles) (black circles), the error output section 7 bit error rate estimates QI in ₁
(1) for the bit error rate of the output data of the interference canceller 5 ₁ of the first stage for the (open triangles) (closed triangles), and the bit error rate estimate QI in the error output section ₇₁ (2) (open squares) the two-stage interference canceller 5 ₂ bit error rate of the output data (closed squares), respectively, it can be seen that almost coincide. From this result, it is also effective to estimate the absolute bit error rate using the bit error rate difference estimated value.

Of course, by storing the correspondence between the bit error rate difference estimated value and the bit error rate in advance by the calibration unit, the absolute bit error rate can be more accurately estimated. The bit error rate estimation value QI (i) is regarded as an absolute bit error rate,
In addition, when this value falls below a predetermined threshold, a simple estimation of the bit error rate that outputs the final received data from the output of the i-th stage interference canceller is performed. Rate data can be output. However, i + 1 of the next stage that has already completed the operation
If the received data is extracted from the interference canceller at the stage, the received data with a lower bit error rate can be output.

It should be noted that even if the absolute bit error rate estimated value described with reference to FIG. 3 is directly measured, the cascade connection is adaptively performed according to the absolute error rate. The number of operating stages of the plurality of interference cancellers can be determined.

The above description has been made on the assumption that the canceller cancels the interference signal of the direct spread reception signal. However, the present invention is not limited to the interference canceller as long as a signal that causes a reduction in the bit error rate of a general received signal including a direct spread received signal is removed from the received signal. By cascade-connecting such cancellers in multiple stages, it is possible to output a more reliable reception signal by repeatedly removing a signal that causes a reduction in the bit error rate a plurality of times. Even in such a case, the difference estimated value of the bit error rate can be output with a simple configuration, and the bit error rate can be estimated from the difference estimated value. Further, by calculating the difference estimated value of the bit error rate or the estimated value of the bit error rate, it is possible to determine how many stages the canceller is operated to satisfy the quality required for the received data.

[0067]

As is clear from the above description, the present invention has an effect that the bit error rate can be easily estimated with a simple configuration if an interference canceller is provided. Furthermore, using the estimation result of the bit error rate determined by comparing the output data of each stage of the multi-stage interference canceller, the number of stages of the interference canceller is adaptively changed to shorten the average processing time and reduce power consumption. It is also possible to plan.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of an error estimating apparatus for direct-sequence received data and a direct-sequence receiving apparatus according to the present invention.

FIG. 2 is a schematic block diagram of an error output unit shown in FIG. 1;

FIG. 3 is a diagram showing an error rate characteristic of received data output from a cascade-connected interference canceller.

FIG. 4 is a block diagram illustrating a second embodiment of an error estimating apparatus for direct-sequence received data and a direct-sequence receiving apparatus according to the present invention;

FIG. 5 is a block diagram illustrating a third embodiment of a direct spread reception data error estimating apparatus and a direct spreading reception apparatus according to the present invention.

FIG. 6 is a block diagram illustrating a fourth embodiment of an apparatus for estimating an error of direct-spread reception data and a direct-spread reception apparatus according to the present invention;

FIG. 7 is a block diagram illustrating a fifth embodiment of an apparatus for estimating an error of direct-sequence reception data and a direct-sequence reception apparatus according to the present invention;

FIG. 8 is a diagram showing a computer simulation result of the direct spread receiving apparatus of the present invention.

FIG. 9 is a diagram illustrating a configuration of a downlink in a DS-CDMA system.

FIG. 10 is a schematic configuration diagram of a transmission device of a base station in a DS-CDMA system.

FIG. 11 is a schematic configuration diagram of a receiving device of a slave station in the DS-CDMA system.

FIG. 12 is a basic block configuration diagram of a prior art.

FIG. 13 is an internal configuration diagram of the interference canceller shown in FIG.

14 is an internal configuration diagram of the interference replica generation unit shown in FIG.

15 is an explanatory diagram of the operation of the interference canceller shown in FIG.

FIG. 16 is a block diagram of the prior art.

[Explanation of symbols]

1 receiving antenna, 2 baseband converter, 3 Ra
ke receiving unit, 4 delay unit, 5 _{1 to} 5 _N interference canceller,
6 _{1 to} 6 _N-1 delay section, 7 error output section, 11 exclusive OR (XOR), 12 counter, 13 division section, 14
Calibration unit, 21 judgment selection circuit, 22 output data selection switch.

Continued on the front page F term (reference) 5K014 AA01 EA08 FA09 GA02 HA10 5K022 EE02 EE32 EE35 5K052 AA01 BB08 DD04 EE24 FF32 GG20 GG42

Claims (7)

[Claims] 1. A replica of an interference signal included in the direct spread signal is generated based on reception data obtained in advance from the direct spread signal, and an interference signal is generated based on a signal obtained by subtracting the replica from the direct spread signal. An interference canceller that outputs received data in which the influence of the interference canceller is reduced, and error information output means that compares the value of input data and the value of output data of the interference canceller and outputs error information based on a mismatch ratio. An error estimating apparatus for directly-spread received data, comprising: 2. An initial data receiving unit that receives a direct spread signal and outputs received data, based on received data obtained in advance from the direct spread signal, generates a replica of an interference signal included in the direct spread signal. A multi-stage interference canceller that outputs received data with reduced influence of an interference signal based on a signal obtained by subtracting the replica from the direct spread signal, and the first data in the first stage of the interference canceller. An interference canceling unit that receives an output of a receiving unit and in which the plurality of stages of interference cancellers operate in cascade, and corresponding to each stage of the interference canceller, the input data value and output data of each stage of the interference canceller And a plurality of comparison units for comparing the values of the error information and outputting the ratio of mismatch, and outputting error information based on the output of the comparison unit. Parts, the error estimating apparatus of the direct spread received data and having a. 3. The apparatus according to claim 1, further comprising a transmitting unit configured to transmit reception quality information based on the error information. 4. An initial data receiving unit that receives a direct spread signal and outputs received data, based on received data obtained in advance from the direct spread signal, generates a replica of an interference signal included in the direct spread signal. A multi-stage interference canceller that outputs received data with reduced influence of an interference signal based on a signal obtained by subtracting the replica from the direct spread signal, and the first data in the first stage of the interference canceller. An input of a receiving unit, an interference canceling unit in which the plurality of stages of interference cancellers operate in cascade, a value of input data and an output data value of each stage of the interference canceller corresponding to each stage of the interference canceller Error information output for outputting error information based on the outputs of the plurality of comparison units, the plurality of comparison units outputting the ratio of mismatch by comparing And control means for stopping the operation of the interference canceling unit in the middle according to the error information in conjunction with the cascade operation of the plurality of stages of interference cancellers, and using the output of the interference canceling unit as output data of a receiving device. A direct spread receiving apparatus comprising: 5. An initial data receiving unit that receives a direct spread signal and outputs received data, based on received data obtained in advance from the direct spread signal, generates a replica of an interference signal included in the direct spread signal. A multi-stage interference canceller that outputs received data with reduced influence of an interference signal based on a signal obtained by subtracting the replica from the direct spread signal, and the first data in the first stage of the interference canceller. An interference canceling unit that receives an output of a receiving unit and in which the plurality of stages of interference cancellers operate in cascade, corresponding to a predetermined stage of the interference canceller, and input data values and output data of the predetermined stage of the interference canceller An error information output unit that has a comparison unit that compares the values of and outputs a ratio of mismatch, and outputs error information based on an output of the comparison unit. With the cascade operation of the plurality of interference cancellers, the number of stages for cascade operation of the plurality of interference cancellers is determined according to the error information, and the output of the interference cancellation unit is used as output data of a receiving device. A direct spread receiver, comprising: control means. 6. The direct spread receiving apparatus according to claim 4, wherein the initial data receiving section is a rake receiving section that receives a direct spread signal. 7. The direct spread receiving apparatus according to claim 4, further comprising a transmitting unit that transmits reception quality information based on the error information.