KR100354164B1 - Signal Demodulation Apparatus in CDMA - Google Patents

Abstract

In the CDMA communication system, the present invention relates to a signal demodulation device for realizing high integration and low power of an application specific integrated circuit (hereinafter, referred to as an ASIC) for signal demodulation. A despreader which despreads differently sampled I and Q channel signals and pseudonoise codes PN different in phase by 1/4 chips for each I and Q channels, and multiplexes and outputs the signals during one PN chip period; Performs pilot filtering for phase and frequency synchronization of the signal of each channel, accumulation processing for timing synchronization, and symbol unit accumulation of the signal for each channel while circulating during the corresponding PN chip period by using the output of the despreader. The present invention relates to a signal demodulation device configured in one integrated circuit including an accumulator bank, which can realize miniaturization and low cost of an ASIC for signal demodulation.

Description

Signal Demodulation Apparatus {Signal Demodulation Apparatus in CDMA}

The present invention relates to a CDMA communication system, and more particularly, to a signal demodulation device for realizing high integration and low power of an ASIC for signal demodulation.

According to the existing IS-95 standard, a forward link demodulation method of a CDMA communication system uses a coherent method of extracting phase information using a pilot signal of a forward link.

The pilot signal received by the CDMA signal demodulator includes information on the signal phase and signal strength of each path by the multipath, and therefore the pilot signal is used as a reference signal for timing synchronization.

In order to extract phase information from the received pilot signal, a module called a pilot filter is statistically averaged for the I channel and the Q channel, and processed. Magnitude is the signal strength, and the angle on the polar coordination of the output vector is the signal phase.

In addition, since the error of the reception frequency is proportional to the phase change rate, the signal phase of each path by the multiple paths is also used to estimate the frequency error of the reception signal.

In addition, the demodulation device requires a device for timing synchronization, which is divided into initial acquisition and time tracking. Once the initial synchronization is performed by a module called a searcher, a correct signal reception is performed. In order to achieve this, the timing synchronization must be maintained continuously. For this purpose, a reception method called Early / Late is generally used.

An early receiver is a receiver that receives signals at an earlier timing than on-time, and a late receiver is a receiver that receives signals at a later timing than the original timing.

The early / late sync circuit detects the timing error of the received signal by using the energy difference between the two receivers, and uses the detected timing error to close the closed loop control scheme such as a phase locked loop (PLL). Correct the timing error by -loop control.

1 is a block diagram showing a partial configuration of a CDMA signal demodulation device according to the prior art.

Referring to FIG. 1, the CDMA signal demodulation apparatus may be broadly divided into a part of processing a PN chip unit and a part of processing a plurality of PN chips in an accumulated symbol unit from the viewpoint of CDMA signal processing.

The illustrated configuration shows a portion to be processed in units of PN chips, which are pilot filters 11 and 12, Walsh symbol accumulators 13 and 14, early chip accumulators 21 and 22, and late chips. Signal processing is performed by separating the accumulators 31 and 32.

The pilot filters 11 and 12 are modules for averaging the received pilot signals for the I and Q channels, and the result y (n) of the pilot filters 11 and 12 is expressed by the following equation. Is calculated.

Equation 1 above is summarized as Equation 2, where y (n-1) is the previous result of the pilot filters 11 and 12, and x (n) is the new input of the pilot filters 11 and 12. .

Is the result of right shifting the previous result of the pilot filters 11 and 12 by K bits.

The pilot filters 11 and 12 have a structure of an infinite impulse response filter, and provide information on frequency synchronization, phase synchronization, and signal strength of the despread signal in synchronization with on-time. The signal is output to the symbol rate processor 40.

In this case, the I-channel and Q-channel vector amplitudes of the output signals of the pilot filters 11 and 12 are signal strengths, and the angles of the polar coordination of the I-channel and Q-channel vectors are different from each other. do. This signal phase is also used to estimate the error of the receive frequency.

The Walsh symbol accumulators 13 and 14 accumulate the despread signal in symbol units in synchronization with the on-time using information of the pilot filters 11 and 12.

In addition, the CDMA signal demodulator must maintain timing synchronization for correct signal reception after initial synchronization is performed by a module called a searcher. For this purpose, an early receiver and a late receiver are used.

Figure 1 shows the correlation processing part in the early receiver and the late receiver.

The correlation processing portion of the early receiver is the second despreader 20 and the early chip accumulators 21 and 22, and the correlation processing portion of the late receiver is the third despreader 30 and the late chip accumulator 31, 32).

For reference, an early receiver is a receiver that receives a signal earlier than a signal synchronized on-time, and a late receiver is a receiver that receives a signal later than a signal synchronized with on-time. to be.

It detects the timing error of the received signal by using the error between the correlation processing part of each early receiver and the correlation processing part of the late receiver, and corrects the timing error by using the detected timing error. The timing error is corrected by using a closed-loop control method such as a phase locked loop.

2 is a diagram illustrating an internal configuration of a despreader used in a CDMA signal demodulation device according to the prior art.

In FIG. 2, a complex quadrature phase shift keying despreader (Complex QPSK Despreader) is used as the despreaders 10, 20, and 30 of the conventional CDMA signal demodulator.

The despreaders 10, 20, and 30 use the accumulators 13, 14, 21, 22, 31, and 32 shown in FIG. Correlation is also performed.

As described above, the conventional CDMA signal demodulation device is implemented as an ASIC for signal demodulation, and it is necessary to further minimize the configuration of an internal digital circuit for high integration and low power of the ASIC for signal demodulation.

However, there is a problem in that a conventional CDMA signal demodulator requires a lot of internal digital circuits in order to implement a portion processed in units of PN chips, and thus has a complicated structure.

An object of the present invention is to provide a signal demodulation device suitable for minimizing the configuration of an internal digital circuit by sharing a plurality of digital circuits processed in units of PN chips in a CDMA signal demodulation device. There is this.

A feature of the signal demodulation device according to the present invention for achieving the above object is an I and Q channel signal sampled out of phase in 1/2 chip units and a pseudo noise code whose phase is different by 1/4 chip for each I and Q channel. A despreader that demultiplexes (PN) and time-multiplexes the output for 1 PN chip period, and circulates during the corresponding PN chip period by using the output of the despreader for phase and frequency synchronization of the signal for each channel. And an accumulation bank including a pilot filtering process, an accumulation process for timing synchronization, and an accumulation bank for performing symbol unit accumulation processing of the signals for each channel. Preferably, the accumulation bank is an I-channel accumulation bank. And a Q-channel accumulating bank, wherein the I-channel accumulating bank and the Q-channel accumulating bank each have a predetermined bit output when the output of the despreading unit is input in units of chips. A subtractor for subtracting an input from the despreader in the previous result after the shifted feedback; And a circular register bank for storing the output of the subtractor and shifting the stored value by a predetermined bit when there is an input from the subtractor.

In addition, the I-channel accumulating bank performs the pilot filtering process and the accumulating process for the timing synchronization sequentially after performing the accumulating processing in units of symbols, and the Q-channel accumulating bank performs the pilot filtering process after performing the pilot filtering process. Accumulation processing in symbol units and accumulation processing for timing synchronization are sequentially performed.

1 is a block diagram showing a partial configuration of a CDMA signal demodulation device according to the prior art;

2 is a diagram showing an internal configuration of a despreading unit used in a CDMA signal demodulation device according to the prior art.

3 is a diagram illustrating a detailed configuration of a signal demodulation device for signal processing in units of PN chips according to the present invention.

4 is an internal timing diagram of a signal demodulation device for signal processing in units of PN chips according to the present invention;

* Description of the symbols for the main parts of the drawings *

100: decimator 200: despreading unit

300: I-channel accumulation bank 310: N-bit add / drop section

320: cyclic register bank 340: latch portion

350: K bit trunk gate 400: Q channel accumulation bank

500: symbol rate processing unit 600: Walsh code generation unit

700: pilot PN code generation unit 800: timing control unit

Hereinafter, a preferred embodiment of a signal demodulation device according to the present invention will be described with reference to the accompanying drawings.

The present invention proposes to minimize the digital circuit configuration of the portion of the signal demodulation unit to be processed in units of PN chips, and performs the same signal processing as the conventional CDMA signal demodulation device.

3 is a diagram illustrating a detailed configuration of a signal demodulation device for signal processing on a PN chip basis according to the present invention.

Referring to FIG. 3, the decimator 100 includes 1/2 chip latches 110 and 120 configured as flip-flops to respectively include I channel data Rx I data and Q channel data Rx Q data. After sampling in units of 1/2 chip, each sampled data is output to the despreader 200 in units of 1/2 chip by synchronous timing provided from the timing controller 800.

The despreader 200 operating in a time-multiplexed format shares the respective despreaders for on-time reception, early reception, and late reception in a time-multiplexed format. The signals sampled in units of 1/2 chips are arranged and output so as to differ by 1/4 chips from the PN codes for each channel generated in synchronization with the pilot PN code generator 700.

By doing so, a signal for on-time correlation processing and one signal for early correlation processing and late correlation processing for one PN chip period can be calculated in a time-multiplexed format.

The signals arranged and output in a time-multiplexed format by the despreader 200 are input to the I-channel accumulating bank 300 and the Q-channel accumulating bank 400, and these accumulating banks 300 and 400 are despread. Information about the frequency synchronization, phase synchronization, timing synchronization, and signal strength of the received signal is provided to the symbol rate processor 500.

In each of the accumulation banks 300 and 400, the N-bit adder 310 and the circular register bank 320 serve as an accumulator. That is, pilot filtering using an infinite impulse response filter (IIR Filter) structure is performed while circulating for one PN chip period, and accumulation processing of Walsh symbols, early reception signal, and late reception signal are performed.

FIG. 4 is an internal timing diagram of a signal demodulation device for signal processing on a PN chip basis according to the present invention. Referring to FIG. 4, pilot filtering and accumulation processing are performed on a signal despread in a time-multiplexed format. Describe the procedure in more detail.

Some of the half-chip on-time correlation processing of despread signals in time-multiplexed format is used for pilot filtering such as frequency synchronization, phase synchronization, and signal strength measurements. The remainder of one except PN chip period is used for Walsh symbol accumulation processing using the Walsh code sequence generated by the Walsh code generator 600.

In particular, in the QPSK spreading CDMA method using QPSK Modulation, such as IMT2000, a noncoherent method is used to perform signal demodulation, so that an I-channel signal and a Q-channel signal are crossed or added or subtracted. Will be needed.

To this end, the despreader 200 according to the present invention alternately processes the I-channel signal and the Q-channel signal by a time-multiplexed format, so that the I-channel accumulator bank 300 or the Q-channel accumulator bank 400 is performed. ) Is accumulated by using one N-bit subtractor and a rotating register bank.

In the illustrated timing diagram, "W" is a Walsh symbol accumulation processing section, and "1", "2", and "3" are pilot filtering processing sections such as frequency synchronization, phase synchronization, and signal strength measurement.

The symbols shown in these sections indicate the operation mode of the N-bit add / drop unit 310, and the section of the "-" sign shown indicates that the N-bit add / drop unit 310 operates as "B-A".

As described above, according to the signal demodulation apparatus of the present invention, a digital circuit having a minimum configuration is used to perform the same operation as the conventional one by efficiently sharing a portion processed in units of PN chips.

Accordingly, miniaturization and low price of the ASIC for signal demodulation can be realized, and power consumption can be reduced due to high integration. It can be particularly useful for mobile terminals.

Claims (4)

I and Q channel signals sampled out of phase in 1/2 chip units and pseudonoise codes (PNs) that are out of phase by 1/4 chip for each I and Q channel are despread and multiplexed for 1 PN chip period. An output despreading unit; Pilot filtering processing for phase and frequency synchronization of the signal of each channel, accumulation processing for timing synchronization, and symbol unit accumulation processing of the signal for each channel are performed while circulating during the corresponding PN chip period by using the output of the despreader. Signal demodulation device, characterized in that configured in one integrated circuit including an accumulating bank. 2. The accumulating bank of claim 1, wherein the accumulating bank comprises an I-channel accumulating bank and a Q-channel accumulating bank, wherein the I-channel accumulating bank and the Q-channel accumulating bank are respectively. An adder or subtractor which adds or subtracts an input from the despreader from a previous result when the output of the despreader is input by a chip unit and the output of the despreader is shifted by a predetermined bit; And a cyclic register bank for storing the output of the subtractor and shifting the stored value by a predetermined bit when there is an input from the subtractor. 3. The method of claim 2, wherein the I-channel accumulating bank sequentially performs the pilot filtering process and the accumulating process for timing synchronization after performing the accumulating processing in units of symbols, and the Q-channel accumulating bank performs the pilot filtering process. And performing the accumulating processing for the symbol unit and the accumulating processing for the timing synchronization sequentially. The PN code of claim 1, wherein the PN code having a phase different from each other by a quarter chip includes a PN code generator that generates a PN code having a phase that is faster or slower by a quarter chip according to a timing control signal than a reference PN code. Signal demodulation device, characterized in that.