JP3567733B2 - Signal decoding method, signal decoding circuit, information transmission communication device using the same, and information storage / reproduction device - Google Patents

Description

上記の更新処理は、選択された状態遷移パスに応じてＰｉ（ｋ−１）、またはＰｊ（ｋ−１）を選択し、この時間的な記憶位置を一時刻ずつ過去に移動させて、最も過去の記憶内容 （（Ｄ＋２）番目の要素）をビタビ復号の結果として取り出した後、最新時刻の記憶位置に新たな遷移状態Ｓｎ（ｋ）を追加したものをＰｎ（ｋ）の記憶内容として、転記する操作を意味する。公知技術において、これは、各時刻毎に記憶内容を順次シフトさせるシフトレジスタのような記憶回路によって一般的に構成され（シフトレジスタ交換法）、また、様々な記憶回路を用いた構成方法が開示されている。さらに、多くの場合、パス系列履歴Ｐｋ（ｎ）への記憶内容としては、選択された遷移状態の情報（状態番号）そのものを記憶する代わりに、選択された遷移状態へのパスブランチに対する送信符号を記憶する。例えば、時刻ｋにおける状態Ｓｎ（ｋ）に対して、状態Ｓｉ（ｋ−１）からの遷移パスが生き残りパスとして選択された場合、これに対する生き残りパス履歴への記録内容としては、状態Ｓｉ（ｋ−１）からＳｎ（ｋ）へのパスブランチに対応する送信符号Ｘ（ｉ，ｎ）の値を用いることができる。これにより、記憶されたパス履歴情報を参照した場合に、直ちに、生き残りパスが示す送信符号系列｛Ｘ（ｎ）｝を復号符号結果として得ることができる。
【００２５】
また、上記（３）の生き残りパス系列履歴情報の更新処理の記述では、状態Ｓｎ（ｋ）に至る生き残りパス系列履歴Ｐｎ（ｋ）内の時刻ｋに対する記憶情報（最新時刻に対するパス履歴情報）は、時刻ｋ−１からのパス選択の状態によらず、状態Ｓｎ（ｋ）で一定である。したがって、実際に、このパス情報自身は、物理的に格納される必要はなく、この状態Ｓｎ（ｋ）に連接する時刻ｋ−１以前の生き残りパス系列履歴情報のみが記憶回路内に物理的に記録されればよい。時刻ｋに対するパス履歴記憶情報Ｓｎ（ｋ）は、このパス履歴情報が状態Ｓｎ（ｋ） に至る生き残りパス系列履歴Ｐｎ（ｋ）として記憶されている事実（記憶位置情報）により表すことができ、次時刻ｋ＋１の処理において、この生き残りパス系列履歴Ｐｎ（ｋ）の記憶内容を参照する際に、この時刻ｋに対するパス履歴記憶情報Ｓｎ（ｋ）を補って参照すればよい。
【００２６】
上述のように、生き残りパス履歴への記録内容として、選択されたパスブランチに対応する送信符号Ｘ（ｉ，ｎ）の値を記憶する場合にも、これは、同様であり、各々の生き残りパス系列履歴Ｐｎ（ｋ）において、状態Ｓｎ（ｋ）へ至るパス遷移であることによって固定される時刻ｋから所定時刻以前までの履歴情報（ＥＰＲ４チャネルの場合は、時刻ｋから時刻ｋ−２までの３ビット送信符号の履歴）は、生き残りパス系列履歴Ｐｎ（ｋ）として記憶されているという記憶位置情報そのものにより示すことで省略し、参照時にこの情報を補うことで、記憶装置のハードウエア量を節約することができる。
【００２７】
以上（１）（２）（３）の一連のビタビ復号処理が、各時刻の受信信号値Ｙ（ｋ）が入力される毎に、繰り返し処理される。これを実施するための具体的構成要素は図６（ａ）の如く示される。
【００２８】
（１）のブランチメトリックＢＭ（ｉ，ｎ）（ｋ）及びＢＭ（ｊ，ｎ）（ｋ）の計算は、自乗誤差演算回路２０１により行う。状態Ｓｉ（ｋ−１）及びＳｊ（ｋ−１）に対する生き残りパスのパスメトリックＭｉ（ｋ−１）及びＭｊ（ｋ−１）は、メトリック記憶回路２０２ａ及び２０２ｂに保持されており、メトリック累積加算回路２０３により（２）におけるパスメトリックＰＭ（ｉ，ｎ）（ｋ）及びＰＭ（ｊ，ｎ）（ｋ）の計算、比較器２０４によりこれらパスメトリック値の比較演算を行う。比較結果は選択信号２０５に出力され、メトリック選択回路２０６は、この選択信号２０５に従って、パスメトリックＰＭ（ｉ，ｎ）（ｋ）またはＰＭ（ｊ，ｎ）（ｋ）の何れかを選択し、これを用いて、状態Ｓｎ（ｋ）への生き残りパスメトリックＭｎ（ｋ）を保持するメトリック記憶回路２０２ｃの内容を更新記憶する。一方、状態Ｓｉ（ｋ−１） 及びＳｊ（ｋ−１）に至る生き残りパス履歴Ｐｉ（ｋ−１）およびＰｊ（ｋ−１）は、パス履歴記憶回路２０７ａ及び２０７ｂに記憶されており、（３）における状態Ｓｎ（ｋ） への生き残りパス履歴Ｐｎ（ｋ）の内容更新処理は、選択信号２０５により指示されたパス履歴記憶回路２０７ａまたは２０７ｂの内容のいずれかをパス履歴選択回路２０８により選択して参照し、この内容の記憶位置を一時刻分シフトさせて、Ｐｎ（ｋ）を保持するパス履歴記憶回路２０７ｃの内容として新たに更新記憶する。このとき、パス履歴記憶回路２０７ａまたは２０７ｂの末尾の記憶位置から選択された生き残りパス履歴情報が、復号結果（復号符号系列Ｚ（ｋ）１０９）として出力される。
【００２９】
実際のビタビ復号では、最尤系列推定の対象となるトレリス線図の全ての状態に対して、各時刻の受信信号Ｙ（ｋ）に対する上記（１）〜（３）の処理が、それぞれ独立に行なわれる必要がある。従って、 実際のビタビ復号器の実施構成では、図６（ａ）に示した状態Ｓｎ（ｋ）に対する処理の実施構成要素を、同一構成において状態数分だけ並列に設ける。例えば、図５（ｄ）のトレリス線図に対しては、図６（ｂ）のビタビ・アルゴリズムによる最尤復号器の構成に示すように、８つの状態 Ｓ０（ｋ）〜Ｓ７（ｋ）の各々に対して割り当てた図６（ａ）の実施構成要素を、計８系列並列にして設ける。このとき、生き残りパスメトリックＭ０（ｋ）〜Ｍ７（ｋ）を記憶するメトリック記憶回路２０２ａ〜２０２ｈ、および、生き残りパス系列履歴Ｐ０（ｋ）〜Ｐ７（ｋ）を記憶するパス履歴記憶回路２０７ａ〜２０７ｈは 、各々の状態Ｓ０（ｋ）〜Ｓ７（ｋ）に対して、それぞれ１つずつ割り当てられ、これらの参照先は、各状態のトレリス線図上の次段接続状態に従って複数箇所に接続される。例えば、状態Ｓｉ（ｋ）と状態Ｓｊ（ｋ＋１） （ｉ，ｊ＝０，１，〜７）との間にトレリス線図のパス接続関係が存在するならば、状態Ｓｉ（ｋ） に割り当てられたメトリック記憶回路２０２の参照先の一つは、状態Ｓｊ（ｋ） に割り当てられたメトリック累積加算器２０３のうち、ブランチメトリックＢＭ（ｉ，ｊ）（ｋ）との加算を行うものの他方入力となり、また、状態Ｓｉ（ｋ） に割り当てられたパス履歴記憶回路２０７の参照先の１つは、状態Ｓｊ（ｋ） に割り当てられたパス履歴選択回路２０８の入力となる。
【００３０】
また、実際のトレリス線図上の受信信号期待値Ｅ（ｉ，ｊ）の値は、いくつかのパスブランチで共通であることが多いため、このブランチメトリックに対して演算を行う自乗誤差演算回路２０１も共通化されて、該当する複数のメトリック累積加算器２０３に入力される構成が実際的に用いられることが多い。以上、図６（ｂ）にまとめられるように、ビタビ復号器構成は、受信信号Ｙ（ｋ）を入力して（１）処理を行うブランチメトリック演算部（ＢＭＵ）２００ａ、このブランチメトリック出力を用いて（２）処理を実行し、各状態への生き残りパスを選択するパスメトリック比較選択部（ＡＣＳ演算部）２００ｂ、さらに、この選択出力を受けて、（３）処理による生き残りパス履歴を記憶更新を行い、復号結果を絞り込み決定するパスメモリ部（ＰＭＵ）２００ｃに大別される。以上が、ビタビ・アルゴリズムによる最尤シーケンス復号処理の実施方法および構成方法である。
【００３１】
次に、本発明の実施の原理を明らかにするため、図５（ｄ）の該ＥＰＲ４チャネル上におけるトレリス線図上の状態遷移例を図１２に示し、これを用いて、上述の従来ビタビの復号処理における生き残りパス選択から復号結果の確定までの過程を説明する。上述の従来ビタビ復号の実施方法及び構成方法により、各時刻における受信（復号入力）信号系列｛Ｙ（ｋ）｝１０７を用いて、トレリス線図上の各時刻・各状態への状態遷移パス（パスブランチ）１１２ａは、常に一本ずつに選択される。こうして、生き残りパス系列１１３の選択が繰り返して進められることにより、各時刻に生き残ったパス系列は、さらに次第に絞りこまれる。
【００３２】
例えば、図７における生き残りパス系列１１３の履歴が示すように、時刻ｋおいて各状態へ選択された、各状態への８つの生き残りパス系列は、その後のパス選択により、次第に棄却され、最終的に時刻（ｋ＋１０）での選択処理の終了時に、連接する生き残りパス系列（太線矢印系列）は一本に収束する、このとき、時刻（ｋ−１）〜（ｋ＋８）までの収束した生き残りパス系列が確定最尤パス系列１１４としてが決定され、これにより、時刻ｋにおける復号符号Ｚ（ｋ）は、確定最尤パス系列１１４上に生き残る唯一の状態遷移パス（パスブランチ）１１２ｂに割り当てられる送信符号Ｘ（ｉ，ｊ）を参照することで決定される。この生き残りパス系列の絞り込み操作（パス棄却）は、前述の復号処理（３）において、選択されたパス履歴Ｐｊ（ｋ−１）またはＰｊ（ｋ−１）の内容を一時刻ずつ過去に移動させながら、新たなＰｋ（ｎ）の記憶内容として、転記する操作に他ならない。
【００３３】
そして、図１１（ｂ）において、生き残りパス系列履歴Ｐ０（ｋ）〜Ｐ７（ｋ）を記憶するパス履歴記憶回路２０７ａ〜２０７ｈが十分な記憶長さを有するならば、このパス履歴記憶回路の選択参照と転記を繰り返すことによって、各記憶回路２０７ａ〜２０７ｈの末尾の記憶位置（最も過去の時刻のパスブランチ選択履歴）の内容は、全て同一の記憶内容に収束一致し、この内容の何れかを参照して復号結果とすることができる。以上のように、最尤シーケンス復号における最尤パス確定の操作は、各時刻において、確定最尤パス系列１１４上の各状態に至る生き残りパス候補の棄却・選択を繰り返すことによって行われる。最終的に収束し、復号結果として得られる確定最尤パス系列１１４は、このパス系列上の全時刻での状態遷移パス選択において、より高い尤度を有し、棄却されることなく唯一残った生き残りパス系列である。
【００３４】
本発明は、ここまでに示した、従来の最尤シーケンス復号処理における復号誤り事象を改善し、より高い信頼性を有する復号処理方法を提供することを目的とする。図８（ａ）の第２のトレリス遷移図例は、図７と同様、２進符号送信系列ＥＰＲ４伝送路チャネルにおける生き残りパス系列１１３の例を示しており、最尤復号処理過程において、雑音などの不確定性により生ずる復号誤りパス系列と正規パス系列との関係を説明するためのものである。この図において、状態遷移系列Ｓ６（ｋ−１）→Ｓ５（ｋ）→Ｓ３（ｋ＋１）→Ｓ６（ｋ＋２）→Ｓ４（ｋ＋３）→Ｓ０（ｋ＋４）→Ｓ０（ｋ＋５）→Ｓ１（ｋ＋６）→Ｓ３（ｋ＋７） のパス遷移で表される正規パス系列１１５に対して、復号誤り事象（復号誤り系列）を含む確定最尤パス系列１１４が、状態遷移系列Ｓ６（ｋ−１）→Ｓ５（ｋ）→Ｓ３（ｋ＋１）→Ｓ６（ｋ＋２）→Ｓ５（ｋ＋３）→Ｓ２（ｋ＋４）→Ｓ４（ｋ＋５）→Ｓ１（ｋ＋６）→Ｓ３（ｋ＋７）のパス遷移で確定されたとき、この復号誤り事象（復号誤り系列）は、確定最尤パス系列１１４上、時刻（ｋ＋６）の状態Ｓ１（ｋ＋６）に流入する２つの生き残りパスブランチ候補に対して、誤りパス選択１１７が生ずることにより起こったものである。
【００３５】
即ち、正規パス系列１１７上の時刻（ｋ＋２）における状態Ｓ６（ｋ＋２） から派生分岐し、時刻（ｋ＋６）の状態Ｓ１（ｋ＋６）に流入する２本の生き残りパスブランチ候補の間において比較選択を誤ることによって、該生き残りパスブランチ候補の一方である正規パス系列１１５上の部分パス系列Ｓ６（ｋ＋２）→Ｓ４（ｋ＋３）→Ｓ０（ｋ＋４）→Ｓ０（ｋ＋５）→Ｓ１（ｋ＋６） （太点線矢印パス系列）が、該生き残りパスブランチ候補の他方のパス系列Ｓ６（ｋ＋２）→Ｓ５（ｋ＋３）→Ｓ２（ｋ＋４）→Ｓ４（ｋ＋５）→Ｓ１（ｋ＋６）によって置き換えられて、復号誤りが符号シーケンスの誤りとして発生したものである。復号回路における処理としては、時刻（ｋ＋６）での状態Ｓ１（ｋ＋６）に対する前述の復号処理（２）において、生き残りパスメトリックＰＭ（０，１）（ｋ＋６）とＰＭ（４，１）（ｋ＋６）の大小判定：
Ｍ１（ｋ）＝Ｍｉｎ［ＰＭ（０，１）（ｋ＋６） ， ＰＭ（４，１）（ｋ＋６）］
を誤ることによって、ＰＭ（０，１）（ｋ＋６）の代わりにＰＭ（４，１）（ｋ＋６）が選択される。これにより、状態遷移Ｓ０（ｋ＋５）→Ｓ１（ｋ＋６）の側の生き残りパス系列の代わりに状態遷移Ｓ４（ｋ＋５）→Ｓ１（ｋ＋６）の側の生き残りパス系列が選択判定され、生き残りパス系列履歴を更新記憶する復号処理（３）において、
Ｐ１（ｋ＋６）＝｛Ｓ１（ｋ＋６），Ｐ４（ｋ＋５）｝
なるパス履歴置換処理が実行されることにより、シーケンス誤りが生ずる。これにより、時刻（ｋ＋５）状態Ｓ０（ｋ＋５）までの正規パス系列１１５を有する生き残りパス系列履歴Ｐ０（ｋ＋５）の内容が棄却され、誤りパス系列１１６を有する生き残りパス系列履歴Ｐ４（ｋ＋５）の内容が、生き残りパス系列として選択され、更新されたパス履歴記憶回路に残存する。雑音状況下において、この生き残りパスブランチ候補の選択誤りは、確定最尤パス系列１１４上の各状態において、一様の確率頻度で発生するものではなく、各状態に流入する当該２つの生き残りパス系列候補が有する受信信号期待値の差の累積総和（信号系列間距離、あるいは、パスメトリック差）が小さいほど、最尤復号処理（２）における比較演算処理の誤りの可能性と頻度は高まる。すなわち、２つの生き残りパス系列間のパスメトリック尤度の比較・選択において、パスメトリック間の識別差（尤度差）の期待値が小さく、雑音に対する比較判定の識別余裕が狭まるほど、上述のランダム雑音による復号誤り事象は、より発生しやすくなる。
【００３６】
図８（ａ）の正規パス系列１１５および誤りパス系列１１６の受信信号系列の期待値は、時刻（ｋ＋３）から時刻（ｋ＊６）までの４ビット時刻において、各々｛−４，−２，０，＋２｝及び｛−２，０，−２，０｝の識別の差を生じることから、その自乗誤差の累積総和（信号系列間距離）は、１６となる。この自乗誤差の累積総和１６は、２進符号送信系列ＥＰＲ４伝送路チャネル上での全ての受信信号系列間で保証される最小の自乗誤差累積量（最小自乗ユークリッド距離、最小自由距離）に等しい。また、雑音下における伝送チャネルの復号信頼度（復号誤り率）を決定するのは、主にこのような最小自乗ユークリッド距離を有する送信符号系列間での誤り事象によるものであることは、伝送・通信理論上よく知られる事実である。
【００３７】
図８（ａ）の例では、状態Ｓ１（ｋ＋６）におけるこのパスメトリック尤度の比較・選択の誤りによって、生き残りパス履歴Ｐ１（ｋ＋６）における時刻（ｋ＋３）から（ｋ＋６）までの４ビットの内容が、誤りパス系列１１６の内容で置換される。このような最尤復号における誤り事象の発生過程から、確定最尤パス系列１１４の各時刻の遷移状態の中で、上記の尤度比較誤り事象とパス選択誤り事象が発生している可能性の高い箇所を推定し、かつ、このパス選択誤り事象による生き残りパス履歴記憶回路の誤り置換の内容を推定することができれば、確定最尤パス系列１１４に対して、次善に高い復号信頼度の復号符号系列を得ることができる。さらに、これを他の符号誤り判定手段を用いて、確定最尤パス系列１１４と比較し、送信符号系列としての妥当性を検査して、選択的に最終の復号符号系列として用いるようにすれば、復号符号の信頼性を効率良く高めることが可能である。したがって、本発明の必要構成要件は、選択誤り事象の発生箇所を推定する処理、（ｂ）生き残りパス履歴において、（ａ）の誤り事象によって置換された誤りパス系列の内容（（ａ）確定最尤パス系列１１４上において、尤度比較およびパス符号誤りパターン）を推定する処理、（ｃ）（ａ）により得た誤り事象の位置情報と、（ｂ）により得た符号誤りパターン情報、および確定最尤パス系列１１４に対応する最尤復号系列の情報を用いて、復数の次善復号符号系列の候補を生成する処理、（ｄ）（ｃ）で生成された復数の復号符号系列候補の中から、送信符号系列として妥当性なものを検査し、最終的な復号符号系列として選択出力する処理、の４つの処理ステップからなる。この各ステップについて、実施の原理と概略を以下に説明する。
【００３８】
処理（ａ）の実施の方法：確定最尤パス系列１１４上の各時刻における生き残りパス選択において、尤度比較およびパス選択における誤り事象発生の可能性は、比較されるパスメトリック尤度差の大きさ（絶対値）により判断することができる。
【００３９】
実用的な雑音状況下では、状態Ｓｎ（ｋ）に至る生き残りパスメトリック：
Ｍｎ（ｋ）＝Ｍｉｎ［ＰＭ（ｉ，ｎ）（ｋ） ， ＰＭ（ｊ，ｎ）（ｋ）］
の選択において、
各生き残りパスメトリック尤度間の差の絶対値を、状態Ｓｎ（ｋ）におけるパス選択信頼度情報：
Ｒｎ（ｋ）＝ＡＢＳ［ＰＭ（ｉ，ｎ）（ｋ）−ＰＭ（ｊ，ｎ）（ｋ）］，
ＡＢＳ［・］は絶対値をとる演算
として用いることができる。これは、パスメトリック尤度の比較演算における大小関係が雑音により逆転した場合、このパスメトリック尤度の差は、一般に曖昧であり、小さな値であること、また、大小関係が逆転し、かつ、パスメトリック尤度差がより大きな値となる確率は、上記の比較演算誤りの確率に比して、極めて小さな確率となることに基づいている。これにより、上記のパス選択信頼度情報Ｒｎ（ｋ）の大きさは、各状態Ｓｎ（ｋ）におけるパス選択の確率的誤りの低さ、すなわち、パス選択信頼度の高さとみなして評価することができる。各状態において、流入する３本以上のパスメトリックから選択が行われる場合には、各２本ずつのパスメトリック尤度差絶対値が評価され、この２本の生き残りパスの間での選択誤りの可能性が判断される。確定された最尤パス系列１１４上の各状態Ｓｎ（ｋ）に対し、このパス選択信頼度情報Ｒｎ（ｋ）を評価し、これが、一定の基準値以下である状態の相当箇所、あるいは、ある有限長の系列区間で最小の値、乃至、小さいほうから所定個数内の値をとる状態の相当箇所をパス選択誤り事象発生の可能性の高い箇所と推定することができ、この箇所にフラグ情報をたてることができる。パス選択信頼度情報Ｒｎ（ｋ）の評価値から誤り事象の発生の有無（誤り事象の位置）を判断する方法は、誤り事象の平均的な発生確率に応じ、上記のような様々な方法から選択して用いられる。
【００４０】
処理（ｂ）および（ｃ）の実施の方法：パス選択誤りにより、生き残りパス履歴において置換される誤りパス系列の内容、すなわち、誤り符号パターン系列（誤りシンドローム）は、前述のように最尤シーケンス復号におけるパス系列選択誤りが、正規パス系列と誤りパス系列の受信信号系列間のユークリッド距離に依存した生起確率で発生することを利用して、簡易に推定できる。すなわち、変調処理や意図的な符号処理により、送信符号系列に付加された拘束条件と最尤シーケンス復号処理の対象トレリス遷移図とによって、受信信号系列間の距離構造が予め規定されたならば、多くの場合、最小自乗ユークリッド距離を有する限定された信号系列の対に着目することによって、この系列間の選択誤りにより生ずる発生頻度の高い誤り符号パターン系列（誤りシンドローム）を予め限定し予測することが可能である。そして、この発生頻度の高い誤り符号パターン系列（誤りシンドローム）の事象から、順次、誤り事象を改善することによって、次に良い復号誤り率（信頼度）を得ることができる。
【００４１】
例えば、図８（ａ）の生き残りパス系列１１３において、正規パス系列１１５と誤りパス系列１１６は、パス系列上および受信（復号入力）信号系列１０７上、時刻（ｋ＋３）〜時刻（ｋ＋６）の４ビット時刻間で異なる系列をとる。先に述べたように、この２つの系列対は、このトレリス遷移図上で最小自乗ユークリッド距離を有する系列対であり、この系列間での誤り事象は、最頻の復号誤り事象、最もしばしば発生する復号の誤り符号パターン系列（誤りシンドローム）の一つである。すなわち、送信符号系列、あるいは、復号符号系列１０９上において、これら正規パス系列１１５と誤りパス系列１１６は、時刻（ｋ＋３）において１ビットのみ反転相異なる符号系列を互いに有し、この２つの符号系列間の差系列を復号誤りパターン系列１１８と定義して誤り事象、すなわち、誤り符号パターン系列（誤りシンドローム）を記述すると、１ビット符号誤りパターン１１９ａの如く表すことができる。（ここで、復号誤りパターン系列１１８において、０は符号誤りなし、＋１は符号“１”を“０”に誤るビット位置、−１は符号“０”を“１”に誤るビット位置を各々示す。即ち、２進符号系列上では、復号誤りパターン系列上の非ゼロ位置のみが誤り発生箇所の意味を持ち、反転ビット誤りの符号位置を示すポインタとなる。）生き残りパス系列上１１３では、同時刻において、異なる送信（復号）符号を示す２本のパスに分岐した後、同送信（復号）符号系列を示す３ビット長の異なるパス系列を経て、同一の状態Ｓ１（ｋ＋６）に合流する。これは、過去３ビット符号履歴によりチャネル状態が決定されるトレリス線図の定義から自明であり、これが最小自乗ユークリッド距離を有するパス系列対の一つの形態となる。
【００４２】
以上のように、２進送信符号によるＥＰＲ４伝送系チャネルにおいては、４ビット長の誤りパス系列の置換が、いずれのトレリス線図状態からも高い頻度で生じ、（ａ）の処理によって判定されたパス選択誤り事象発生のビット時刻（図８（ａ）の誤りパス系列例では、時刻（ｋ＋６）の誤りパス選択検出位置１１９）を基準として、相対的に３ビット前の復号位置（図８（ａ）の誤りパス系列例では、時刻（ｋ＋３）の位置）の正規符号が１ビット反転誤りを起こす誤りシンドロームの誤り事象、すなわち、復号誤り符号パターン（１ビット符号誤りパターン系列１１９ａ）が、発生頻度の高い誤りパターン系列の一つであると事前に予測できる。このように、対象となるトレリス遷移図から、頻出の誤り符号パターン系列（誤りシンドローム）が予め決定されれば、これに従い、（ａ）で判定されたパス選択誤り位置を基準として、相対的に決まった位置の最尤復号系列上の符号を反転置換処理することにより、次善に高い信頼度の復号系列を得ることができる。
【００４３】
また、図８（ｂ）は、図８（ａ）と同様の２進送信符号によるＥＰＲ４伝送系チャネル上の最尤シーケンス検出における正規パス系列１１５と誤りパス系列１１６の関係の別の具体例を示したものである。本具体例における誤りパス系列１１６の発生は、確定最尤パス系列１１４上の時刻（ｋ＋５）の状態Ｓ３（ｋ＋５）に対する生き残りパス選択処理において、誤りパス選択１１７が発生したことによるもので、時刻ｋから時刻（ｋ＋５）までの６ビット長のシーケンス誤りとして生ずる。受信（復号入力）信号系列１０７上の正規パス系列１１５と誤りパス系列１１６は、最小自乗ユークリッド距離１６をとり、図８（ａ）における誤り事象と同様に、高い発生頻度で生ずる誤り事象の一つとみなすことができる。この正規パス系列１１５と誤りパス系列１１６の関係を復号符号系列１０９上で比較すると、復号誤りパターン系列１１８としては、誤り事象発生のビット時刻である時刻（ｋ＋５） の誤りパス選択検出位置１１９を基準として、図８（ａ）同様に相対的に３ビット前の時刻（ｋ＋２） の復号位置までの連続３ビット符号位置（時刻ｋ〜（ｋ＋２））の正規符号が反転誤りを起こす誤りシンドロームの復号誤り事象とみることができ、このような、３ビット符号誤りパターン１１９ｂを、該チャネルの頻出復号誤り事象と事前に予測することができる。
【００４４】
上記図８（ａ）の１ビット符号誤りパターン１１９ａの復号誤り事象は、対象となるトレリス遷移図上のいずれの状態からも生起し、送信符号系列に依存せず、トレリス遷移図の構造のみで決定される確率的発生頻度の高い復号誤りパターン系列の一つである。一方で、２進送信符号によるＥＰＲ４伝送系チャネルでは、特定の送信符号系列に依存し、最小自乗ユークリッド距離をとる信号系列対が存在する。図８（ｂ）は、この例として、３ビット符号誤りパターン１１９ｂを示している。このような符号誤りパターンは、送信符号系列上の符号ビットが交互に３ビット以上連続反転するような“…０１０１０…”あるいは“…１０１０１…”なる送信符号系列が、該伝送路チャネルを伝送される場合である。この２つの送信（受信）符号系列のいずれか一方が伝送された場合、送信符号ビットの交互反転が繰り返される符号列部分において、最終ビット位置からｎ（ｎは２以上の整数）ビットまでの連続符号ビットが全て反転する復号誤りパターンが高い頻度で発生しうる。
【００４５】
例えば、送信符号系列“…００１００００…”が伝送されるとき、”０１０”の３ビット符号列部分が上記の符号パターンに合致し、この符号列の当該各ビットを反転させた”…０１０１０００…”が最小ユークリッド距離をとる信号系列対となる。すなわち、復号誤りパターン系列１１８は、”…０ −１ ＋１ −１ ０ ０ ０ …”となり、３ビットの連続反転誤りを起こす誤りシンドロームの誤りパターン系列（３ビット符号誤りパターン１１９ｂ）となる。また、送信符号系列“…００１０１００００…”が伝送されるとき、”０１０１０”の５ビット符号列部分が上記の符号パターンに合致し、この符号列の後ろから３ビット（ｎ＝２のとき）、４ビット（ｎ＝３のとき）、５ビット（ｎ＝４のとき）の当該各ビットを反転させた”…００１１０１０００…”、”…０００１０１０００…”、”…０１０１０１０００…”の３つの系列が最小ユークリッド距離をとる信号系列対となる。すなわち、復号誤りパターン系列は、”…０００ −１ ＋１ −１ ０００…”、”…００＋１ −１ ＋１ −１ ０００…”、”…０−１ ＋１ −１ ＋１ −１ ０００…”となり、３〜５ビットの連続反転誤りを起こす誤りシンドロームの符号誤りパターン（３〜５ビット符号誤りパターン系列）となる。このように、伝送される送信符号列が連続符号反転パターンを有するとき、その部分列が連続反転ビット誤りとなる誤りパターン事象もまた、最小ユークリッド距離の関係から、１ビット符号誤りパターン１１９ａと同等に確率的発生頻度の高い復号符号誤りパターン系列（誤りシンドローム）となる。
【００４６】
したがって、（ａ）の処理によって判定されたパス選択誤り事象発生のビット時刻ｋから相対的に３ビット前の復号位置（ｋ−３）から、ｉビット前（整数ｉ＞１）の時刻（ｋ−ｉ−３）までの復号符号系列１０９が、交互に連続反転するような上記のパターンに相当する場合、時刻（ｋ−５）〜（ｋ−３）までの連続３ビット、または、時刻（ｋ−６）〜（ｋ−３）までの連続４ビット、または、時刻（ｋ−ｉ−３）〜（ｋ−３）までの連続（ｉ＋１）ビットの各符号ビット位置を反転させた符号列を各々することにより、次善信頼度の復号系列候補を得ることができる。このように、（ａ）で判定された誤りパス選択位置（誤りパス選択検出位置１１９）を基準として、相対的に決まった位置の最尤復号系列上の符号を参照し、これに基づいて選択的に、所定の長さの符号列部分を所定の誤りシンドロームに従って反転置換処理することにより、次善に高い信頼度の復号系列を得ることができる。この場合、処理を簡易化するために、復号符号系列１０９を参照することなく、誤りパス選択検出位置１１９を基準として、相対的に決まった位置の復号符号系列１０９上の符号列部分を所定の誤りシンドロームに従って反転置換処理することにより、次善信頼度の復号系列候補を生成することもありうる。また、３ビットから所定の連続ビット数（送信符号系列の拘束条件できまる所定数以下のビット数）まで、全ての符号誤りパターン（誤りシンドローム）に従い、それぞれ反転置換処理して、次善尤度の復号符号系列を得る場合の他、ある特定のビット長・パターンの符号誤りパターン（誤りシンドローム）を制限あるいは選択して行う場合もあり得る。
【００４７】
また、上記のように、（ａ）で判定された誤りパス選択位置１１９を基準として、符号誤りパターン（誤りシンドローム）による反転置換処理の可能性が生じた場合、この誤りパス選択検出位置１１９の状態における生き残りパス履歴記憶回路２０７の内容を参照して、棄却パス系列の長さを検査することにより、起こりうる復号誤り系列（符号誤りパターン、誤りシンドローム）の長さを判断し、当該の長さの符号誤りパターン（誤りシンドローム）のみを選択して反転置換処理を施すことができる。これにより、次善復号信頼度の復号系列候補の数を限定することが可能である。例えば、先に述べた１ビット符号誤りパターン１１９ａは、この誤りパス選択検出位置１１９で棄却されたパス系列の長さ（選択された生き残りパス系列と棄却されたパス系列の間の異なる状態遷移系列の長さ）が４ビットであるという事実によって、棄却パス長が６ビットである３ビット符号誤りパターン１１９ｂやその他誤りパターン発生の可能性とは、予め区別して処理することができる。
【００４８】
図９は、図８（ａ）と同様の生き残りパス系列１１３において、確定最尤パス系列１１４に対して、時刻ｋ〜（ｋ＋８）の各時刻の処理に対して棄却されたパス系列（棄却パス系列ａ〜ｈ）と各棄却パス系列の長さから推定される復号符号系列１０９上における符号反転置換位置（表中斜線部符号位置）の関係を一例として示している。時刻（ｋ＋３）における棄却パス系列ｄは、長さ４ビットであることから、該棄却パスに対する処理が誤り選択である可能性が判断された場合、１ビット符号誤りパターン１１９ａが推定され、棄却時刻（ｋ＋３）から３ビット前時刻ｋにおける確定最尤パス系列１１４上の符号が、１ビット反転置換処理される。時刻（ｋ＋４）〜（ｋ＋６）における棄却パス系列ｅ〜ｇに対しても、同様に４ビットパス長であることから、１ビット符号誤りパターン１１９ａが推定され、棄却時刻（ｋ＋４）〜（ｋ＋６）から３ビット前の各時刻（ｋ＋１）〜（ｋ＋３）における確定最尤パス系列１１４上の符号が、１ビット反転置換処理の対象となる。また、時刻（ｋ＋７）における棄却パス系列ｈは、６ビットパス長であることから、３ビット符号誤りパターン１１９ｂが推定され、棄却時刻（ｋ＋７）から３ビット前までの連続３ビット符号、時刻（ｋ＋２）〜（ｋ＋４）における確定最尤パス系列１１４上の符号が、３ビット反転置換処理の対象と判断することができる。このように、処理（ａ）において、誤りパス選択検出位置１１９と同時に、棄却パス系列の長さを判定することによって、反転置換処理において参照する符号誤りパターン（誤りシンドローム）を長さによって選択することができ、最尤復号系列上の反転置換処理による次善復号系列候補の数を限定して、回路資源の利用効率を向上させることができる。
【００４９】
本発明における処理（ｂ）および（ｃ）の実施では、対象となる伝送チャネルに応じ、受信信号期待値系列間の距離によって、発生頻度の高い復号誤りパターン系列を予め設定し、これに基づいて、処理（ａ）で判定した誤りパス選択検出位置１１９を基準とした復号符号系列１０９上の部分列を反転置換処理して、次善信頼度の復号系列候補を生成する。したがって、この復号誤りパターン系列の設定は、対象となる伝送チャネルの特性や、符号化・変調処理などにより送信符号系列に付加される拘束条件によって異なる。前述の磁気記録再生系チャネル等に用いられる２進送信符号系列ＥＰＲ４チャネルを含め、一般に、パーシャルレスポンス特性多項式 Ｇ（Ｄ）＝（１−Ｄ）（１＋Ｄ）Ｆ（Ｄ）（Ｆ（Ｄ）は、任意の特性多項式）は、しばしば、多くの実用に具せられる伝送チャネルの形態である。この形態の伝送チャネルは、２進送信符号系列の周波数成分の内、ＤＣ成分（同符号の連続系列）と最高伝送周波数成分（連続反転符号系列）に対して零応答を示す伝送特性上の特徴を有し、上述のＥＰＲ４伝送チャネルの例に代表して示されるように、その共通したチャネル状態遷移の構造から、受信信号系列間の最小自乗ユークリッド距離を規定する最頻の復号誤りパターン系列は、１ビット以上の連続反転符号誤り系列である点、かつ、該チャネルを伝送される送信符号系列上の連続反転符号系列の部分に対し、この連続反転符号誤りが最頻の確率で発生する点が共通した特徴となる。
【００５０】
したがって、上述のＥＰＲ４伝送チャネルにおける処理（ｂ）（ｃ）の実施方法を一般化し、該チャネルメモリ長を整数ｎ（ＥＰＲ４チャネルの場合ｎ＝３）とした時、復号符号系列および、処理（ａ）により判定されたパス選択誤り位置に対応する時刻ｋを基準として、復号符号位置の時刻（ｋ−ｎ）から時刻（ｋ−ｎ−ｉ＋１）（ｉ＝１〜最大反転長ｍ迄の各値）迄の連続の復号符号系列を反転置換することにより、次善尤度の復号符号系列を各々生成できる。このとき、複数の反転置換処理を、当該の復号符号系列が連続反転符号系列であることを参照した上で実施するか、無条件に実施するか、あるいは、棄却生き残りパス系列の長さに応じて選択的に行うかは、ＥＰＲ４チャネルの場合と同様、実施の形態に応じて、任意に取捨選択することができる。
【００５１】
また、置換処理の最大符号長である最大反転長ｍは、送信符号系列上の拘束条件により制限された最大連続符号反転長さ以下の所定値であり、復号信頼度の性能を維持する上で実用上優位な所定の長さを設定することができ、同様に、実現性能と実施規模の観点から、１〜ｍビットまでのｍ通りの該符号反転置換処理のうち、実施形態に合わせて任意の反転置換処理を省略することもあり得る。また、これまでの実施例は、送信符号系列１００がそのままの形態でチャネル伝送され、最尤シーケンス復号器から出力される復号符号系列もまた、送信符号系列に等しい符号系列に復号出力される場合について記述されたが、様々な実施形態の伝送チャネルにおいては、伝送チャネル入力前、あるいは、最尤シーケンス復号器内あるいは出力直後の復号系列に対し、プリコード処理、あるいは、ポストコード処理を始めとする様々な符号変換処理・信号処理操作が施される場合が多い。この場合、伝送チャネル上の符号系列と異なる復号符号系列に対する、誤りパス選択検出位置１１９と符号置換処理の箇所との相対的位置関係や、符号誤りパターン系列（誤りシンドローム）の誤り符号位置は、復号系列上の誤りシーケンスに対して、情報符号と同様の該符号変換処理・信号処理操作により、処理符号位置を写像変換することによって求めることができる。例えば、チャネル上の伝送符号系列に対して、ポストコード処理（１＋Ｄ^２）（２進符号に対し、＋は２を法とする加算）を施した系列を復号符号系列として出力する場合、伝送符号系列に対して有意な符号誤りパターン系列（誤りシンドローム）”…０＋１−１＋１−１＋１００…”は、同様のポストコード処理を施し、”…０＋１−１０００−１＋１…”なる変換をして、該復号符号系列に対する反転置換処理の復号符号誤りパターン系列（誤りシンドローム）として同等の処理を施せばよい。情報伝送系における符号変換処理は、符号再現性を保証するから、変換の前後において、符号誤りパターン系列（誤りシンドローム）や符号系列位置の一対一対応は可能である。従って、伝送符号系列に対する上記実施例処理と等価な処理を、様々な符号処理を施された復号符号系列の上で実行することが可能である。
【００５２】
処理（ｄ）実施の方法：処理（ｄ）の具体的流れを説明するため本発明の特徴となる符号処理の流れを図９を用いて説明する。 図１の情報伝送系１０１に供給される送信符号系列１００（情報符号列）は、伝送チャネル１０４に供給されるために伝送・記録の形態に応じて、所定の処理を施され、伝送記録符号系列１２０（情報符号列）として与えられる。（本実施例においては、伝送記録符号系列１２０は送信符号系列１００と同義と考えても実施上の問題はない。）（ｃ）で生成された復数の復号符号系列候補の中から、送信符号系列として妥当性なものを検査し、最終的な復号符号系列として選択するためには、伝送記録符号系列１２０を所定長さの伝送記録情報符号ブロック１２０ａ，１２０ｂ，１２０ｃ…に分割し、これに（ｂ）（ｃ）で設定された復号符号誤りパターン（誤りシンドローム）の符号誤り事象が、当該の伝送記録情報符号ブロック内で発生したことを検出するための誤り検査符号列１２２ａ，１２２ｂ，１２２ｃ…を付加し、これを伝送符号ブロック１２１ａ，１２１ｂ，１２１ｃ…とする。そして、再び、これを元の送信符号ブロック伝送記録情報符号ブロック１２０ａ，１２０ｂ，１２０ｃ…の時系列順に、一つのチャネル伝送符号系列１２１とみなして処理し、該伝送チャネル上に伝送する。
【００５３】
この処理において伝送記録符号系列１２０に付加される誤り検査符号列１２２ａ，１２２ｂ，１２２ｃ…は、パリティ検査符号や巡回冗長符号（ＣＲＣ：Ｃｙｃｌｅ Ｒｅｄｕｎｄａｎｃｙ Ｃｈｅｃｋ）等、公知の誤り検出符号・誤り訂正符号の構成技術により構成することができる。例えば、パーシャルレスポンス特性多項式 Ｇ（Ｄ）＝（１−Ｄ）（１＋Ｄ）Ｆ（Ｄ）で表される前出の伝送チャネルにおいて、頻出する１〜ｎビット（ｎは所定の整数）の連続反転符号誤りパターン（長さｎビットまでのバースト誤り）を検出するためには、次数ｎの生成多項式によリ生成される巡回冗長符号が適用できる。特定の符号誤りパターンに対し、低冗長度・高検出能力を有する誤り検出符号の構成方法を提供することは、本発明の範疇を越えるものであるためここでは言及しないが、伝送チャネル上での符号誤りパターン（誤りシンドローム）の特徴から、（ｂ）（ｃ）の処理で予め設定された、限定された個数の符号誤りパターン（誤りシンドローム）の存在のみを検出する誤り検出符号を構成することにより、低冗長度かつ簡易な構成の誤り検出符号を用いて、伝送情報の信頼度を上げ得る点が本発明の利点となる。
【００５４】
復号処理側では、最尤シーケンス復号器の出力である復号符号系列１０９と、これに対応して、処理（ｂ）（ｃ）において生成される次善最尤の復号符号系列とが、該伝送符号ブロック１２１ａ，１２１ｂ，１２１ｃ…に対応する単位で処理される。すなわち、復号符号系列１０９が最尤シーケンス復号器から得られるとともに、処理（ａ）（ｂ）（ｃ）により該復号符号系列１０９上の符号反転置換位置が決定されて、この位置を指示する符号置換ポインタ系列１２４が生成されると、復号符号系列１０９は、当該の伝送符号ブロック単位で、逐次、復号符号候補ブロック１２５ａ，１２５ｂ，１２５ｃ…に分割され、最尤復号系列から生成された復号符号候補ブロック系列１２６ａが生成される。さらに、各々の復号符号候補ブロック１２５ａ，１２５ｂ，１２５ｃ…の符号単位において、符号置換ポインタ系列１２４が指示する復号符号系列１０９上の当該復号符号候補ブロック内の符号箇所を、全て一カ所乃至複数箇所組み合わせで独立に、あるいは、一カ所乃至複数箇所組み合わせを所定の様式で選択するなどして、反転置換する処理が施される。これにより、次善尤度の復号符号系列である復号符号候補ブロック系列１２６ｂ、１２６ｃ…が生成され、各々の伝送符号ブロック１２１ａ，１２１ｂ，１２１ｃ…に対応する各復号符号候補ブロック１２５ａ，１２５ｂ，１２５ｃ…の符号単位に対しては、復号符号候補ブロック系列１２６ａ、１２６ｂ、１２６ｃ…に属する複数の復号符号候補ブロックが展開され、復号符号候補ブロックリスト１２５が構成される。各々の伝送符号ブロック１２１ａ，１２１ｂ，１２１ｃ…に対応する復号符号候補ブロック１２５ａ，１２５ｂ，１２５ｃ…の各符号単位に対し、複数個存在する復号符号候補ブロック（復号符号候補ブロック系列１２６ａ、１２６ｂ、１２６ｃ…に属する）の中からは、伝送時に付加された誤り検査符号列１２２ａ，１２２ｂ，１２２ｃ…を用いて、誤りの無い復号符号候補ブロックが一つ検査選択され、該誤り検査符号列を排除した上で、各々の伝送符号ブロック１２１ａ，１２１ｂ，１２１ｃ…に対応する確定復号符号ブロック１２７ａ，１２７ｂ，１２７ｃ…が選択出力される。 このように、本発明では、最尤符号系列と次善最尤符号系列からなる復数符号系列のリストが形成され、復数の復号符号候補ブロック系列１２６ａ、１２６ｂ、１２６ｃ…からは、当該の伝送符号ブロック単位で、正規符号ブロック（確定復号符号ブロック１２７ａ，１２７ｂ，１２７ｃ…）が検査選択されて、最終的な確定復号符号系列１２７が決定される。
【００５５】
伝送符号ブロックの符号長と付加される誤り検出符号列の符号長および誤り検出能力は、本発明が実施される雑音環境と復号誤り確率によって設定される。本発明を適用する最尤シーケンス復号器１０８の出力における復号誤り確率を考えたとき、設定された伝送符号ブロック１２１ａ、１２１ｂ、１２１ｃ…の符号長から、この符号ブロック内に発生する復号誤り事象の平均的な個数を推定し、この誤り事象を全て検出できる誤り検出符号列１２２ａ，１２２ｂ，１２２ｃ…を構成して付加する。このように、本発明では、雑音要素に起因するランダム復号誤り事象が、ある符号箇所に集中して発生する確率は、極めて希となることに着目して、実用的な復号誤り確率を達成する上で十分となるよう、所定の長さの伝送符号ブロック（復号符号候補ブロック）内で救済できる復号誤り事象の数に制限を与える。これによって、付加する誤り検出符号の構成を比較的簡易なものとし、誤り検出符号列の符号長（冗長性）を低く抑えて、復号誤り率改善を果たすことができる。例えば、最尤シーケンス復号の誤り確率が１．０Ｅ−３であるならば、伝送符号ブロック（復号符号候補ブロック）長を逆数オーダーの１０００ビット程度とすることで、この中に発生する復号誤り事象の数を平均的に１個程度とすることができる。したがって、伝送符号ブロック長を１０００ビット以下に設定し、単一の誤り事象を検出し得る誤り検出符号列１２２ａ，１２２ｂ，１２２ｃ…を付加することによって、誤り事象の救済と復号誤り率の改善を実施することができる。一般に、ある復号誤り率の復号系のもと、伝送符号ブロック長を大に設定するほど、付加する誤り検出符号の検出能力を高め、誤り検出符号列の符号長を大とする必要があり、伝送符号ブロック長および誤り検出符号列構成と長さは、実施形態により各々最適な長さが選択される。
【００５６】
一方、各伝送符号ブロック１２１ａ，１２１ｂ，１２１ｃ…に付加される誤り検出符号列１２２ａ，１２２ｂ，１２２ｃ…の検出能力及び該伝送符号ブロックに対応する復号符号候補ブロック内での誤り事象の検出可能最大数が設定されると、処理（ａ）において検出される各復号符号候補ブロック内での誤りパス選択事象の最大数、すなわち、処理（ｂ）（ｃ）における各復号符号候補ブロック内の符号反転置換処理箇所の最大数（置換処理数）は、この誤り事象の検出可能最大数以下となるように設定される。
【００５７】
このように設定された符号反転置換処理の置換処理数に従い、復号符号系列１０９上、処理（ａ）（ｂ）（ｃ）によって判断された全ての誤り符号処理箇所の一部または全部の組み合わせを符号反転置換処理することによって、伝送符号ブロック１２１ａ，１２１ｂ，１２１ｃ…を単位として復号符号候補ブロックを複数生成し、復号符号候補ブロックリスト１２５を生成した後、この中から、当該伝送符号ブロックに対する復号符号ブロックが誤り検査され、選択出力される。以上が本発明の実施方法と原理に関する説明である。
【００５８】
図１は、上記方法により本発明を実施するための情報伝送・記録再生系の基本的構成を説明する図である。符号化過程において、伝送・記録のオリジナルな情報データ系列である送信／記録情報符号系列３００に対しては、一般的に、符号化回路３０１により、誤り訂正符号化処理や符号化変調処理など、実施形態に応じた所定の符号処理が、公知の技術に施されて、伝送記録符号系列１２０への変換がなされる。
【００５９】
本発明では、前述の処理（ｄ）による復号符号誤りの検出処理を行うため、この伝送記録符号系列１２０を所定の長さの伝送記録情報符号ブロック１２０ａ、１２０ｂ、１２０ｃ…に分割し、該伝送記録情報符号ブロックの各々に対して、誤り検出符号列１２２ａ、１２２ｂ、１２２ｃ…を生成し、これを付加する処理が施される。これを行う検査符号付加回路３０２は、検査符号生成回路３０３ａおよび検査符号挿入回路３０３ｂから構成される。検査符号付加回路３０２は、シーケンシャルな符号時系列である伝送記録符号系列１２０（情報符号系列）を、逐次、所定の符号長の伝送記録情報符号ブロック１２０ａ、１２０ｂ、１２０ｃ…のブロック単位ごとの系列とみなし、各ブロックに対する誤り検出符号列１２２ａ、１２２ｂ、１２２ｃ…を生成する誤り検出符号器によって構成される。前出の処理（ｄ）において説明したように、ここで生成される誤り検出符号列は、該伝送記録系における最尤シーケンス復号回路３０８の出力である復号符号系列１０９上において、高頻度で発生する所定の復号符号誤りパターン（誤りシンドローム）の存在を検出するように構成され、このような予め設定された特定有限個の所定の符号誤りパターン（誤りシンドローム）のみをを所定の有限個数まで検出することが可能な低い冗長度のものが生成される。これを行う符号化回路が検査符号生成回路３０３ａである。また、検査符号挿入回路３０３ｂは、検査符号生成回路３０３ａで生成された誤り検出符号列１２２ａ、１２２ｂ、１２２ｃ…を、伝送記録符号系列１２０（情報符号系列）内ので、当該伝送記録符号ブロックの直後、あるいは、所定の対応する符号位置に挿入付加する。この検査符号挿入回路３０３ｂによって、伝送記録符号系列１２０は、伝送記録符号ブロック１２０ａ、１２０ｂ、１２０ｃ…の符号ブロック単位毎に誤り検査符号列１２２ａ、１２２ｂ、１２２ｃ…が挿入付加され、伝送符号ブロック１２１ａ、１２１ｂ、１２１ｃ…の符号ブロック系列であるチャネル伝送符号系列１２１が生成される（図９実施例参照）。この後、該チャネル伝送符号系列１２１は、元の伝送記録符号系列１２０（情報符号系列）の符号時系列と同様、伝送符号ブロックのストリームからなる一本の符号時系列と見なされ、処理されて、符号伝送過程に入力される。伝送・記録再生信号伝送系３０４は、このチャネル伝送符号系列１２１を、伝送・記録再生チャネル３０６を介して伝達可能となるようなアナログまたはデジタルの信号形式に変換する送信・記録符号信号処理系３０５と、伝送・記録再生情報伝達の担い手である伝送・記録再生チャネル３０６からなる。送信・記録符号信号処理系３０５では、チャネル伝送符号系列１２１に対して、プリコード等の所定の符号処理を施す符号処理回路３０５ａ、この出力であるチャネル伝送符号系列を伝送可能な信号形態に変換する符号信号変換回路（変調）３０５ｂ、変換された伝送信号に信号補正や増幅処理などの所定の信号処理を施す送信・記録信号処理回路３０５ｃなどが必要に応じて設けられ、いずれも、公知の技術により構成される。本発明の実施は、この伝送・記録再生信号伝送系３０４の構成要素に依存するものではない。伝送・記録再生チャネル３０６は、伝送または記録媒体およびトランスデューサ・センサなどから構成される情報伝送媒体であり、特に情報記憶再生装置においては、記録ヘッド・情報記憶媒体・再生ヘッドを含む記録再生系に相当する。以上が送信・記録側における本発明実施の基本的構成である。
【００６０】
次に受信・再生側における基本的実施構成を述べる。伝送・記録再生チャネル３０６から出力される受信・再生信号系列には、増幅処理をはじめ利得・位相制御処理、雑音除去処理、等化処理など、所定の信号処理操作が、受信・再生信号処理回路３０７を通じてなされる。この処理の後、受信信号系列１０７は、最尤シーケンス復号回路３０８に入力され、前述した最尤シーケンス推定処理（最尤復号）により、復号符号系列１０９が復号出力される。本発明では、処理（ａ）に基づき、この最尤シーケンス復号回路３０８において、復号符号系列１０９を推定する際の誤りパス系列選択事象の発生の可能性（低信頼度の生き残りパス選択処理、誤りパス選択検出位置１１９）を判定する機能が設けられる。また、この低信頼度パス系列の符号位置（誤りパス選択検出位置１１９）を出力指示する復号信頼度フラグ１２３を生成し、復号符号系列１０９の各符号に同期して出力する機能が設けられる。さらに、必要に応じて、この復号信頼度フラグ１２３により指示された低信頼度の生き残りパス系列選択（誤りパス選択検出位置１１９におけるパス選択）において、棄却された生き残りパス系列の長さ（または、該生き残りパス系列の長さによって推定される符号反転置換処理を行う符号列長さ）に関する情報を、復号信頼度フラグ１２３に付与して、これを同時に送出する機能を設ける場合もある。このような機能を有する最尤シーケンス復号回路３０８の具体的構成および実施例は、後に詳述される。
【００６１】
上記の最尤シーケンス復号回路３０８からの出力情報である、復号符号系列１０９と復号信頼度フラグ１２３が示す情報に基づき、復号符号候補ブロックリスト生成回路３０９では、復号信頼度フラグ１２３が示す復号符号系列１０９上の低信頼度復号箇所に、処理（ｂ）（ｃ）に基づく、符号反転置換処理を行って、伝送符号ブロックの符号ブロック単位に対応する復号符号候補ブロック１２１ａ、１２１ｂ、１２１ｃ…の符号ブロック単位ごとに復数の復号符号候補ブロック３１０（１），３１０（２），３１０（３）…３１０（ｍ）（ｍは所定の自然数）を生成して、復号符号候補ブロックリスト１２５を形成する。復号符号候補ブロックリスト生成回路３０９において、復号符号処理回路３０９ａは、復号符号系列１０９に対して、必要に応じ、ポストコード処理などの所定の符号処理を施した後、この符号系列を該伝送符号ブロックと同様の長さとタイミングでブロック分割する処理を行う。また、符号置換ポインタ生成回路３０９ｂは、復号信頼度フラグ１２３の情報と、予め設定した復号誤りパターン系列（誤りシンドロームパターン）の情報に基づき、復号信頼度フラグ１２３が示す基準符号位置（例えば、誤りパス選択検出位置１１９）から、復号符号系列１０９上、所定の相対的位置にある１つ乃至複数の符号位置に対して、該符号位置にある復号符号が反転置換処理の対象にあることを示すポインタ情報（符号置換ポインタ系列１２４）を送出する。この符号置換ポインタ系列１２４は、符号ブロック内の複数の反転置換処理の箇所に対し、個々に、あるいは、複数箇所の組み合わせに、選択的に置換処理を指示する場合もあり、また、各反転置換処理の箇所に対して、楠数の異なる符号反転パターンによる置換反転処理が、それぞれに行われる場合もある。この場合生ずる、複数の符号反転置換処理組み合わせに対しては、各符号処理の反転符号位置を指示する複数の符号置換ポインタ系列１２４が生成される。処理（ｂ）（ｃ）の実施方法に述べたように、、生き残りパス選択での棄却パス系列の長さ（反転置換符号系列の長さ）に関する情報が復号信頼度フラグ１２１に付加されて供給されるとき、これを基づき行う置換反転処理の復号符号誤りパターン系列（誤りシンドロームパターン）を限定・選択する処理は、この符号置換ポインタ生成回路３０９ｂにおける符号置換ポインタ系列１２４の生成を制限することによって行う。また、反転置換部分の復号符号系列１０９上パターンにより、反転置換処理の有無や復号誤り符号パターン系列（誤りシンドロームパターン）を限定・選択する場合も、復号符号系列１０９を参照しながら、同様に、符号置換ポインタ生成回路３０９ｂにおいて符号置換ポインタ系列１２４の生成を制限することによって行う。復号符号候補ブロック生成回路３０９ｃは、ブロック分割された復号符号系列１０９に対し、これに対応する符号置換ポインタ系列１２４を受け、該符号置換ポインタ系列１２４の指示する符号反転処理を復号符号系列１０９に施して、最尤復号符号ブロックと次善最尤復号符号ブロックによる複数の復号符号候補ブロック３１０（１）、３１０（２）、３１０（３）、…、３１０（ｍ）を生成し、復号符号候補ブロックリスト１２５が形成される。以上の復号符号候補ブロックリストの構成操作をまとめた一実施例が図２である。最尤シーケンス復号回路３０８出力情報１２８である復号信頼度フラグ１２３が指示する符号位置を基準として、符号置換ポインタ生成回路３０９ｂでは、（ｂ）（ｃ）で述べた原理によって、相対的な符号反転置換位置を指示する符号置換開始位置ポインタ１２３ｂが生成される。さらに、この符号置換開始位置ポインタ１２３ｂを基準として、所定の符号誤りパターン（誤りシンドローム）に応じて、符号反転位置を直接指示する符号置換ポインタ系列１２４が生成される。復号符号候補ブロック生成回路３０９ｃでは、復号符号系列１０９上の符号ブロック単位ごとに、該符号置換ポインタ系列１２４が指示する符号置換処理の各々の箇所、または、複数の箇所の組み合わせに対して、その全て、または、一部を選択して、復号符号系列１０９上の符号に反転置換処理を施し、反転置換を行わない元の復号符号系列１０９のままの符号ブロックを含めた複数の復号符号候補ブロック３１０（１）、３１０（２）、３１０（３）、…、３１０（ｍ）からなる復号符号候補ブロックリスト１２５が構成される。（このとき、符号置換ポインタ１２４は、各符号ブロックに対する複数の符号置換処理ごとに、複数生成される場合もある。）以上の復号符号候補ブロックリストの生成は、一般的な論理演算回路とバッファ記憶回路とによって、容易に実現することが可能である。
【００６２】
図１において、復号符号候補ブロックリスト１２５を構成する複数の復号符号候補ブロック３１０（１）、３１０（２）、３１０（３）、…、３１０（ｍ）は、各々、復号符号候補ブロック系列１２６として符号誤り検査回路３１１に入力され、検査符号付加回路３０２において付加された各伝送符号ブロックの誤り検査符号列を用いて、各復号符号候補ブロックにおける符号誤りの有無を検査する。この結果を、復号符号候補ブロック選択信号３１２ａを通じて復号符号候補ブロック選択回路３１３に指示し、符号誤りのない正規の復号符号候補ブロックを、付加された誤り検出符号列を削除した上で、確定復号符号ブロックとして出力する。この確定復号符号ブロックの時系列が確定復号符号系列１２７として出力され、これが伝送記録符号系列１２０に対する情報再生符号系列となる。該符号誤り検査回路３１１において、同時入力されたいずれの復号符号候補ブロックにも誤りが存在し、正規の復号符号候補ブロックが選択できない場合は、当該の復号符号系列上に符号誤りが存在することを指示するために、復号結果である確定復号符号系列１２７に同期して、誤り復号ブロックフラグ３１２ｂを送出し、後段の符号処理あるいは伝送・記録再生系制御処理において活用することができる。符号復調回路３１４は、入力された復号結果である確定復号符号系列１２７に対して、符号化回路３０１で行われた符号処理に対する逆変換あるいは適切な所定の処理を施して、もとの送信／記録情報符号系列３００に対応する受信／再生情報符号系列３１５を得る。
【００６３】
上記の復号符号候補ブロックリスト生成回路３０９における反転置換ポインタ系列１２４の複数生成処理、および、置換処理による復号符号候補ブロック３１０（１），３１０（２）…の復数生成処理と符号誤り検査回路３１１における各復号符号候補ブロックに対する誤り検出処理は、処理遅延を短縮するよう、復数の復号符号候補ブロックに対して並列に設けた回路資源により処理を行う実施形態を記述している。一方で、これら、符号置換ポインタ系列１２４の生成、符号置換処理および誤り検出処理の一連の処理を、各復号符号候補ブロックごとに同一の回路資源を時分割で用いて、逐次、繰り返して行うことにより、処理時間遅延の拡大を許容しながら、実施回路規模を縮小する実施形態をとることも可能である。さらに、実施例では、説明上、各符号ブロック単位を、各符号系列から物理的に分離分割して処理する如く記述しているが、これは、実現回路構成上は、論理的にブロック単位で分割処理されるものであり、復号符号候補ブロックリスト生成回路入力から、符号誤り検査回路３１１および復号符号候補ブロック選択回路３１３までの一連の処理は、連続したシーケンショルな符号処理の流れとして、例えば、シフトレジスタ構成のバッファ記憶装置と論理演算素子を用いて、実現することができる。
【００６４】
また、本発明では、実施形態や伝送・記録再生チャネル３０５の状態に従い、符号ブロックの長さや付加される誤り検出符号の構成と符号長、復号ブロック内における符号反転置換処理の個数や符号誤りパターン系列の数、および、復号符号候補ブロックリスト１２５内のブロック数ｍは、所望の復号信頼度と実施規模のもとで最適な値を設定されることがしばしば要求されるが、これらのパラメータを可変とし、実施の状況に応じて変更可能とすることは容易である。最も簡易な実施形態としては、本発明を実施する情報伝送・記録再生システムの伝送単位（伝送フレームなど）や記録再生単位（ディスク装置におけるセクタ単位など）に、本発明の伝送符号ブロック１１１の長さを一致させる形態がある。さらに、復号信頼度を向上させるためには、前述したように、伝送チャネルと所望の復号誤り率に基づき、上記の情報伝送・記録再生システムの伝送単位を、所定の長さの複数の伝送記録符号ブロックに分割して、この各々に誤り検出符号を付加し、上記の実施例に基づく処理を施すことができる。
【００６５】
図３（ａ）は、復号信頼度フラグ１２３を同時出力するための各遷移状態に対するビタビ復号処理の第１の実施例を示したものである。本実施例では、図６（ａ）の従来ビタビ復号器構成に対して、フラグ生成部２１０ａとフラグメモリ部２１０ｂが設けられ、処理（ａ）に基づき、復号信頼度フラグ１２３が復号符号系列１０９に同期し、同時出力される。フラグ生成部２１０ａでは、処理（ａ）に基づき、生き残りパスメトリック尤度ＰＭ（ｉ，ｎ）（ｋ）とＰＭ（ｊ，ｎ）（ｋ）の間の差の絶対値を計算し、これを生き残りパス選択信頼度情報として用いる。このため、ＡＣＳ演算部２００ｂからパスメトリック尤度ＰＭ（ｉ，ｎ）（ｋ）とＰＭ（ｊ，ｎ）（ｋ）を参照し、絶対値演算回路２１１では、これらを用いてパスメトリック尤度の間の差メトリック絶対値２１７を計算する。そして、この差メトリック絶対値２１７が、予め設定された信頼度フラグ判定しきい値Ｄ２１２より小か否かを比較器２１３にて判定し、小である場合には、ＡＣＳ演算部２００ｂからの選択信号２０５が指示する該パスメトリックの選択判定の信頼度が低下していることを示す信頼度フラグ２１４を同時に出力する。フラグメモリ部２１０ｂは、パスメモリ部２００ｃと同一の構成をとり、パスメモリ部２００ｃのパス履歴記憶回路２０７ａ〜２０７ｈの各々に対応するフラグ履歴記憶回路２１５ａ〜２１５ｈと、パス履歴選択回路２０８ａ〜２０８ｈの各々に対応するフラグ履歴選択回路２１６ａ〜２１６ｈが設けられる。このフラグメモリ部２１０ｂは、パスメモリ部２００ｃと同一の選択信号２０５と同一周期の同期動作信号を受けて、同様の記憶更新処理動作を繰り返す。そして、動作タイミング毎に、上記の信頼度フラグ２１４の内容を、対応する遷移状態のフラグ履歴記録回路２１５ｃの左端記憶要素へ初期値として保持し、復号符号がパスメモリ部２００ｃにおいて、淘汰選択される過程と全く同様の選択更新処理を経て、復号信頼度フラグ１２３として出力する。これにより、復号符号系列１０９上の各復号符号と同期して、該復号符号位置でのに生き残りパス選択の信頼度の高低（誤りパス選択検出位置１１９）を示すフラグ情報が復号信頼度フラグ１２３として出力される。この復号信頼度フラグ１２３は、復号符号候補ブロックリスト生成回路３０９における符号反転置換処理の基準位置を示す情報を提供する。
【００６６】
図３（ｂ）は、復号信頼度フラグ１２３を同時出力するための各遷移状態に対するビタビ復号処理の第２の実施例を示している。本実施例は、復号符号系列１０９上の所定の区間（復号符号候補ブロックに対応する区間）ごとに、最も信頼度の低い生き残りパス選択処理の符号位置に対するフラグ情報を得るための具体的手段を示している。この場合も、図３（ｂ）の実施例と同様に、図６（ａ）の従来ビタビ復号器構成に対して、各状態遷移パス選択処理系ごとに、フラグ生成部２１０ａとフラグメモリ部２１０ｂが設けられ、処理（ａ）に基づいて、各状態遷移における生き残りパス選択の際の差メトリック絶対値２１７に基づいて処理が行われる。本実施例では、フラグメモリ部２１０ｂは、図３（ａ）実施例と同様とし、フラグ生成部２１０ａに、過去の復号履歴における最も小さな差メトリック絶対値２１７の値を保持するための差メトリック記憶回路２１９と、この内容と各復号動作タイミングで得られる差メトリック絶対値２１７との大小関係を検査する比較器２１３とを設ける。そして、各復号動作タイミングでの当該遷移パス選択における差メトリック絶対値２１７が差メトリック記憶回路２１９の内容以下あるいは未満の値である場合には、ＡＣＳ演算部２００ｂからの選択信号２０５が指示する該パスメトリックの選択判定が低信頼度であることを示す信頼度フラグ２１４を、図３（ａ）の実施例と同様に出力するとともに、差メトリック選択回路２１８を介して、このときの差メトリック絶対値２１７の値を差メトリック記憶回路２１９の内容として選択入力し、最小の差メトリック絶対値２１７の値を常に更新保持する。このようなフラグ生成部２１０ａを設けることにより、所定の復号タイミング（例えば、前述の復号符号候補ブロックの開始符号位置に相当するタイミング）毎に、差メトリック絶対値２１７が取りうる最大値を、差メトリック記憶回路２１９に保持する記憶回路初期値２２０として設定することにより、この初期値２２０設定タイミングの間隔で決まる復号区間ごとに最小の差メトリック絶対値２１７を判定することができる。すなわち、この初期値２２０設定間隔の復号符号区間内（例えば、前述の復号符号候補ブロックに対応する復号符号区間）の復号信頼度フラグ１２３において、最後に出力された低信頼度パス選択（誤りパス選択検出位置１１９）のフラグ位置を最低信頼度の復号パス選択の符号位置情報として扱うことができる。一般に最低信頼度から第ｎ番目に低い信頼度（ｎは所定の整数）までの符号位置に対するフラグ情報を得るためには、同様の原理と構成に基づいて、図３（ｃ）の実施例のようにフラグ生成部２１０ａとフラグメモリ部２１０ｂをｎ段（本実施例では、ｎ＝２）にわたり縦続に接続する構成をとることにより、容易にこれを実現することができる。（本実施例では、ブランチメトリック演算部２００ａ、ＡＣＳ演算部２００ｂ、パスメモリ部２００ｃは、図３（ｂ）と同様であるため省略）本実施例構成により、各々の復号信頼度フラグ１２３（ｎ）の出力から、所定の復号区間において第ｎ番目まで低い信頼度パス選択復号（誤りパス選択検出位置１１９）の符号位置のフラグ情報を、図３（ｂ）実施例と同様に、得ることができる。
【００６７】
図３（ｄ）は、ビタビ復号器から復号信頼度フラグ情報とともに、低信頼度パス選択における棄却パス長の情報を同時出力する場合の復号器構成の実施例を示す。本実施例は、図３（ａ）に基づいて、信頼度フラグ判定しきい値２１２と差メトリック絶対値２１７の比較による信頼度判定の実施例に基づいて示される。本実施例では、パス選択における棄却パス長を検査するため、パスメモリ部２００ｃにおいて、各状態遷移先に対応するパス履歴記憶回路（本実施例では、２０７ｃ）に対して、一致検出回路２２２およびパス履歴収束位置検出回路２２３を設ける。これらは、当該のパス履歴記憶回路２０７ｃに対して、パス履歴選択回路２０８を介し、該パス履歴記憶回路の内容を更新する際に参照先となりうるパス履歴記憶回路（本実施例では、２０７ａおよび２０７ｂ）を参照して、これらのパス履歴内容の一致を検査する。このため、一致検出回路２２２は、パス履歴記憶回路２０７ａと２０７ｂにおいて、各々対応する時刻位置の記憶要素の内容の一致を検査し、パス履歴収束位置検出回路２２３は、この結果を受けて、両パス履歴記憶回路２０７ａおよび２０７ｂの間の記憶要素の内、終段（パス履歴記憶回路中の最右端位置）の記憶要素からどの位置までの記憶要素が収束一致しているか、換言すると、２つのパス履歴記憶回路２０７ａおよび２０７ｂが保持するパス履歴情報の内、初段（パス履歴記憶回路中の最左端位置）の記憶要素からの未収束部分の長さを検出し、これを各復号動作タイミング毎に収束位置情報２２４として出力する。一致検出回路２２２は、排他的論理和演算を用いて、また、パス履歴収束位置検出回路２２３も公知の論理演算回路を用いて、容易に実現しうる。上記の収束位置情報２２４は、信頼度フラグ２１４から低信頼度復号のフラグ情報が出力された場合、対応するパス遷移状態のフラグ履歴記憶回路２１５ｃの初段（最左端位置記憶要素）の初期値として入力される。また、信頼度フラグ２１４が高い信頼度復号のフラグ情報を出力した場合には、パス収束位置情報２２４として意味を持たない、いわゆる、ｎｕｌｌ値が入力される。フラグ選択回路２２５は、この信頼度フラグ２１４に応じたフラグ履歴記憶回路２１５ｃ初段への初期値選択を行う。これにより、復号信頼度フラグ１２３は、単なる復号パス選択の信頼性の有無を示すものではなく、同時に、該符号位置での棄却生き残りパス系列の長さの情報が出力されることになる。この棄却パス長の情報を用いて、後段の復号符号候補ブロックリスト生成回路３０９では、符号反転置換処理のための復号符号誤りパターン（誤りシンドロームパターン）を符号長によって選択し、処理を限定することができる。本実施例は、図３（ａ）実施例に基づき示されたが、図３（ｂ）および図３（ｃ）実施例にも同様に適用することができる。
【００６８】
本発明は、図１に示した一般的実施形態を通じて、伝送通信系や記録再生系など、最尤シーケンス復号器が使用されるさまざまな情報伝達系に適用することができ、その復号信頼度を向上させることができる。本発明による伝送通信系での復号信頼度向上は、受信復号装置の性能を改善するとともに、送信装置における送信電力の低減を許容し、かつ、装置の省電力化や小型化を促進することを可能にする。また、記録再生系への本発明適用は、再生信号の雑音および信号対雑音比品質の低下を許容することができ、これにより、記録媒体への情報記憶密度を高める、あるいは、記録再生信号帯域や記録再生動作周波数の拡大を許容するなどの新たな効果を生み出すことができる。
【００６９】
図４は、情報記録再生系への適用例として、磁気ディスク装置への本発明適用の実施例を示している。本実施例の記録側では、記録情報である記録符号４００は、符号／変調回路４０１により、ランレングス制限などの拘束条件を付加された後、図１に述べたような検査符号付加回路３０２により、符号ブロック単位で誤り検出符号列が付加される。高密度磁気記録再生系では、伝達多項式（１−Ｄ）（１＋Ｄ）Ｆ（Ｄ）（Ｆ（Ｄ）は任意多項式）で特徴づけられるパーシャルレスポンスチャネルがしばしば用いられ、この記録再生系における符号間干渉による畳み込み処理を利用し、最尤シーケンス復号回路を用いて復号処理が行われる。前述のように、このような情報伝達系では、１ビット以上の連続反転符号誤りが復号誤りにおける支配的な復号符号誤りパターン（誤りシンドロームパターン）となる。したがって、１ビット、乃至、所定の長さの連続反転符号誤りを検出するための誤り検出符号列を生成し、符号／変調回路４０１出力の記録符号の系列に対して、検査符号付加回路３０２を介してこれを付加する。このとき、前述（図９）のように、最尤シーケンス復号の復号誤り率と、所望の復号誤り率によって、符号／変調回路４０１出力の記録符号は、複数の伝送記録符号ブロックに分割され、各々の符号ブロックに所定の誤り検出符号列が挿入付加された後、改めて、符号処理回路４０５に一連の記録符号系列として逐次入力される。最尤シーケンス復号の復号誤り率が比較的良好である場合、読みだし単位であるセクタ内での平均的な誤り個数が比較的少ない場合には、これを検出できる誤り検査符号列をセクタに付加し、セクタをより細分化された記録符号ブロックに分割することなく、セクタ全体をひとつの符号ブロックとみなして処理する場合もあり得る。該、検査符号付加回路３０２出力の記録情報符号系列に対して、符号処理回路４０５ではパーシャルレスポンスチャネルに対するプリコードなどの記録前の所定の符号処理を施し、該記録情報符号は、記録電流変換回路４０４において、記録電流に変換された後、記録アンプ４０５を介して、電磁変換系である記録再生チャネル４０９に供給される。記録ヘッド４０６・再生ヘッド４０７および記録媒体４０８の電磁変換系からなる記録再生チャネル４０９では、記録情報符号は、磁気的に蓄積記憶される。再生側では、読みだし要求に応じて、この記憶された記録情報符号を記録再生チャネル４０９からの電気的信号出力として読み出す。再生信号処理回路４１０は、この読み出した電気信号に対して、再生アンプ４１１による増幅処理、可変利得アンプ４１２による利得制御、アナログ／デジタル変換器４１４による離散化処理、等化器４１５による等化処理などを施した後、出力である再生信号系列を最尤シーケンス復号回路３０８に供給する。（タイミング抽出／利得制御回路４１６は、再生信号系列からサンプルタイミング信号４１６ａや利得制御信号４１６ｂを生成する。符号処理回路４０３入力から再生信号処理回路４１０出力までの一連の処理は、記録再生系に応じて様々な形態がとられ、公知の技術により実現される。）最尤シーケンス復号回路３０８は、前述の実施例に基づき構成され、この出力には、復号符号系列１０９と同時に、これと同期して、各復号符号位置に対応する復号信頼度フラグ１２３が出力される。図１および図２の実施例において述べたように、この復号符号系列１０９と復号信頼度フラグ１２３を用いて、復号符号候補ブロックリスト生成回路３０９では、検査符号付加回路３０３において誤り検査符号列を付加した符号ブロックを単位として、復号符号候補ブロックのリストを生成する。復号符号処理回路３０９ａでは、ポストコード処理などの所定の後符号処理を復号符号系列１０９に施す。また、符号置換ポインタ生成回路３０９ｂでは、復号信頼度フラグ１２３と所定の復号符号誤りパターン（復号誤りシンドロームパターン）に基づいて、符号反転置換処理を施す復号符号位置を指示するポインタ信号系列を所定の数だけ出力する。これを受けて復号候補ブロック生成回路３０９ｃは、所定の個数の復号符号候補ブロックを符号置換ポインタ系列１２４が示すポインタ位置の符号反転置換処理により生成し、符号誤り検査回路３１１では、検査符号付加回路３０３において符号ブロック単位で付加された誤り検出符号列を用いて、正規の復号符号候補ブロックが検査され、選択される。復号符号候補ブロック選択回路３１３は、この検査選択の結果を示す復号符号候補ブロック選択信号３１２ａを受けて、正規の復号符号ブロックのみを選択出力し、確定復号符号系列１２７を復調器４１８に供給する。復調器４１８は、符号／変調回路４０１の逆変換処理を確定復号符号系列に施す。これにより、記録符号４００に対して、忠実にこれを再現する再生符号４１９を再生側に得ることができる。符号誤り検査回路３１３では、いずれの復号符号候補ブロックからも復号符号誤りが検出された場合には、誤り復号ブロックフラグ３１２ｂを出力し、当該符号ブロックの再生符号４１９には、本発明により救済できなかった復号誤り事象が含まれることを示すフラグ情報を後段の処理に伝えることができる。後段の誤り訂正処理では、この情報を用いて、さらに効率の良い誤り訂正処理を実行することができる他、再読み出し動作（リトライ）を実行して復号誤りを回復することができる。また、本実施例では、符号／変調器４０１の後に検査符号付加回路３０３ａを設けて、符号ブロックの分割処理や誤り検査符号列の挿入付加を行うこととしているが、これは、再生側での復号符号誤りパターンが復調器４１８での逆変換処理によって、伸長されることにより、誤り検査符号列の構成が複雑かつ冗長になることを避けるためである。しかしながら、符号／変調器４０１や復調器４１８での処理によっては、これは、回避でき問題とはならない場合もあり、本実施例における符号／変調器４０１と検査符号付加回路３０３、および、復調器４１８と符号誤り検査回路３１３（復号符号候補ブロック選択回路４１４）の処理の順序は、本発明の実施形態に応じて、効果的な形態で入れ替えることができる。本実施例は、磁気ディスク装置の記録再生系への適用を例にとり示されたが、他の磁気記録再生装置あるいは、光記録・光磁気記録再生装置などの多くの情報記録再生装置は、最尤シーケンス復号を用いた再生系が適用でき同様の実施形態を適用することが可能である。本発明により、記録再生チャネル４０９からの出力再生信号の信号対雑音比品質が低下しても、これによる復号符号系列の信頼度の低下を救済することができ、記録再生系の記録媒体４０８上への情報記録密度が高まる、あるいは、記録再生周波数が高まることにより、高記録密度かつ高速な情報記録再生装置を提供することができる。
【００７０】
また、本発明は、既存のデジタル信号処理回路によって、容易に構成し、これを実施することが可能であり、これにより、上記のような情報伝送系や情報記録再生系を提供する集積回路上に搭載することが可能である。本発明で必要となる復号符号候補ブロックリスト生成回路３１１などの論理回路は、わずかな論理素子とバッファ記憶回路により容易に構成できるため、高速・高集積度の集積回路への搭載に好適な回路資源によって構成される。本発明を集積回路に搭載し実現することにより、本発明のもたらす効果により省電力・高速化された情報伝送系や高記録密度・高速化された情報記録再生系を用いた機器を、より小型化して実現することが可能となる。
【図面の簡単な説明】
【図１】本発明の基本的構成を示す実施例を示す図である。
【図２】復号符号候補ブロックリストの構成方法を説明するための図である。
【図３ａ】復号信頼度フラグを同時出力するビタビ復号処理構成の第１の実施例を示す図である。
【図３ｂ】復号信頼度フラグを同時出力するビタビ復号処理構成の第２の実施例を示す図である。
【図３ｃ】復号信頼度フラグを同時出力するビタビ復号処理構成の第３の実施例を示す図である。
【図３ｄ】復号信頼度フラグを同時出力するビタビ復号処理構成の第４の実施例を示す図である。
【図４】本発明の記録再生装置への適用実施例を示す図である。
【図５ａ】情報伝送系または記録再生系における情報系列の流れを示す図である。
【図５ｂ】ＥＰＲ４パーシャルレスポンス伝走路チャネルモデルを示す図である。
【図５ｃ】状態遷移図（２進符号送信系列ＥＰＲ４伝送路チャネル）である。
【図５ｄ】時刻ｋにおけるトレリス遷移を示す図（２進符号送信系列ＥＰＲ４伝送路チャネル）である。
【図５ｅ】時刻ｋにおける各状態へのパス遷移を示す図（２進符号送信系列ＥＰＲ４伝送路チャネル）である。
【図５ｆ】時刻ｋ〜ｋ＋４における状態遷移パス例を示す図 （２進符号送信系列ＥＰＲ４伝送路チャネル）である。
【図６ａ】ビタビ復号処理を実施する具体的構成要素を説明するための図である。
【図６ｂ】ビタビ・アルゴリズムによる最尤復号器（最尤シーケンス復号器、ビタビ復号器）の構成を示す図である。
【図７】生き残りパス系列選択による最尤復号処理過程を説明するためのトレリス線図（２進符号送信系列ＥＰＲ４伝送路チャネル）である。
【図８ａ】最尤復号処理過程における正規パス系列と誤りパス系列の関係を説明するための第１のトレリス線図（２進符号送信系列ＥＰＲ４伝送路チャネル）である。
【図８ｂ】最尤復号処理過程における正規パス系列と誤りパス系列の関係を説明するための第２のトレリス線図（２進符号送信系列ＥＰＲ４伝送路チャネル）である。
【図８ｃ】最尤復号処理過程における正規パス系列と誤りパス系列の関係を説明するための第３のトレリス線図（２進符号送信系列ＥＰＲ４伝送路チャネル）である。
【図９】本発明における符号処理の流れを説明するための図である。
【符号の説明】
１００…送信符号系列、１０１…情報伝送系、１０２…符号器、１０３…変調器、１０４…チャネル、１０５…付加雑音、１０６…受信信号処理回路、１０７…受信（復号入力）信号系列、１０８…最尤シーケンス復号器、１０９…復号符号系列、１１０ａ，１１０ｂ，１１０ｃ…１ビット遅延記憶要素、１１１ａ，１１１ｂ，１１１ｃ…加減演算要素、１１２…パス系列、１１２ａ，１１２ｂ…状態遷移パス（パスブランチ）、１１３…生き残りパス系列、１１４…確定最尤パス系列、１１５…正規パス系列、１１６…誤りパス系列、１１７…誤りパス選択、１１８…復号誤りパターン系列、１１９ａ…１ビット符号誤りパターン、１１９ｂ…３ビット符号誤りパターン、１１９…誤りパス選択検出位置、１２０…伝送記録符号系列（情報符号系列）、１２０ａ〜１２０ｃ…伝送記録情報符号ブロック（情報符号ブロック）、１２１…チャネル伝送符号系列、１２１ａ〜１２１ｃ…伝送符号ブロック、１２２ａ〜１２２ｃ…誤り検査符号列、１２３，１２３（１），１２３（２）…復号信頼度フラグ、１２３ａ…符号置換基準位置ポインタ、１２３ｂ…符号置換開始位置ポインタ、１２４…符号置換ポインタ系列、１２５…復号符号候補ブロックリスト、１２５ａ〜１２５ｃ…復号符号候補ブロック、１２６、１６ａ〜１２６ｃ…復号符号候補ブロック系列、１２７…確定復号符号系列、１２７ａ〜１２７ｃ…確定復号符号ブロック、１２８…最尤シーケンス復号回路出力情報、２００ａ…ブランチメトリック演算部、２００ｂ…ＡＣＳ演算部、２００ｃ…パスメモリ部、２０１…自乗誤差演算回路、２０２ａ〜２０２ｈ…メトリック記憶回路、２０３…メトリック累積加算回路、２０４…比較器、２０５…選択信号、２０６…メトリック選択回路、２０７ａ〜２０７ｈ…パス履歴記憶回路、２０８，２０８ａ〜２０８ｈ…パス履歴選択回路、２１０ａ，２１０ａ（１），２１０ａ（２）…フラグ生成部、２１０ｂ，２１０ｂ（１），２１０ｂ（２）…フラグメモリ部、２１１…絶対値演算回路、２１２：信頼度フラグ判定しきい値、２１３…比較器、２１４，２１４（１），２１４（２）…信頼度フラグ、２１５ａ〜２１５ｃ…フラグ履歴記憶回路、２１６，２１６（ａ），２１６（ｂ）…フラグ履歴選択回路、２１７…差メトリック絶対値、２１８，２１８（ａ），２１８（ｂ）…差メトリック選択回路、２１９…差メトリック選択回路、２２０…記憶回路初期値、２２１…フラグ判定論理素子、２２２…一致検出回路、２２３…パス履歴収束位置検出回路、２２４…収束位置情報、２２５…フラグ選択回路、３００…送信／記録情報符号系列、３０１…符号化回路、３０２…検査符号付加回路、３０３ａ…検査符号生成回路、３０３ｂ…検査符号挿入回路、３０４…伝送・記録再生信号伝送系、３０５…送信・記録符号信号処理系、３０５ａ…符号処理回路、３０５ｂ…符号信号変換回路（変調）、３０５ｃ…送信・記録信号処理回路、３０６…伝送・記録再生チャネル、３０７…受信・再生信号処理回路、３０８…最尤シーケンス復号回路、３０９…復号符号候補ブロックリスト生成回路、３０９ａ…復号符号処理回路、３０９ｂ…符号置換ポインタ生成回路、３０９ｃ…復号符号候補ブロック生成回路、３１０（１）〜（ｎ）…復号符号候補ブロック、３１１…符号誤り検査回路、３１２ａ…復号符号候補ブロック選択信号、３１２ｂ…誤り復号ブロックフラグ、３１３…復号符号候補ブロック選択回路、３１４…符号復調回路、３１５…受信／再生情報符号系列、４００…記録符号、４０１…符号／変調回路、４０３…符号処理回路、４０４…記録電流変換回路、４０５…記録アンプ、４０６…記録ヘッド、４０７…再生ヘッド、４０８…記録媒体、４０９…記録再生チャネル、４１０…再生信号処理回路、４１１…再生アンプ、４１２…可変利得アンプ、４１３…低域通過フィルタ、４１４…アナログ／デジタル変換器、４１５…等化器、４１６…タイミング抽出／利得制御回路、４１６ａ…サンプルタイミング信号、４１６ｂ…利得制御信号、４１８…復調器、４１９…再生符号。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal decoding method, and to a signal decoding circuit to which the method is applied, an information transmission communication device using the same, and an information storage / reproduction device.
[0002]
[Prior art]
In a high-speed information communication system or a high-density information recording / reproducing system, data using maximum-likelihood sequence detection (MLSD) is used to improve the reliability of data reproduction from low-quality transmission or recording / reproducing signals. Error correction and demodulation techniques based on decoding techniques, convolutional coding, and the like are widely used.
[0003]
This maximum likelihood sequence detection is a technique for minimizing the error occurrence probability in the decoded code sequence by estimating the decoded code sequence in a time-series manner using the memory property or correlation of the decoded data. When a sequence {Y (n)} (n is an integer indicating a discrete signal generation order and time) is given to a decoding input, from among all possible transmission information (code) sequences {X (n)}, A sequence (maximum likelihood sequence) having the highest probability (likelihood) of receiving Y (n)} is selected, and this is output as a decoded information (code) sequence {Z (n)}. That is, given the entire sequence of a certain received signal sequence {Y (n)}, the received signal sequence {Y (n)} is received under the condition that a certain transmitted sequence {X (n)} is assumed. The transmission sequence {X (n)} is selected such that the posterior prior probability P [{Y (n)} / {X (n)}] is maximized, and the maximum likelihood of the decoded sequence {Z (n)} is selected. Perform sequence estimation. At this time, the transmission sequence {X (n)} is not estimated independently of each other, but in the context. Such maximum likelihood sequence detection is performed under the condition that all possible transmission sequences {X (n)} are transmitted with equal probability, in other words, information on the transmission probability of each transmission sequence {X (n)} is decoded. Under conditions that are not given at all, the correct decoding probability P [{X (n)} & {Z (n)}] (the transmission sequence {X (n)} matches the decoded sequence {Z (n)}. Probability) is maximized to provide decoding of the best decoding error probability.
[0004]
This maximum likelihood sequence detection is efficiently realized using a Viterbi algorithm or the like in a dynamic programming format. As a paper on maximum likelihood sequence detection and Viterbi algorithm, Day. Forney, "The Viterbi Algorithm", Procedures of the IE (GD Forney, "The Viterbi Algorithm", Proceedings of the IEEE), Vol. 61, No. 3, March 1973, 268- 278, and G. Angabock, "Adaptive Maximum-Liquid Receiver for Carrier Modulated Data Transmission System", I.E.E.E.E.Transactions on Communications IEEE Transactions on Communications), Vol. 22, No. 5, May 1974, pp. 624-638. These papers describe a receiving apparatus using maximum likelihood sequence detection or a basic form of a part thereof. Show. Further, practical means for realizing the Viterbi algorithm include Healing Law, "Implementing the Viterbi Algorithm", and IEIE Signal Processing Magazine (Hui-Ling Lou, "Implementing the Vitrbi Algorithm", IEEE Signal Processing Magazine, September 1995, pp. 42-52; Fetways and H. Meir, "High-Speed Parallel Viterbi Decoding: Algorithm and VSL Architecture", I.E.E.E.E. Communication Signal Magazine (G. Fettweis and H. Meyr, "High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture ", IEEE Communications Magazine, May 1991, pp. 46-55.
[0005]
Such a maximum likelihood sequence detection technique has rapidly spread and developed through applications to information communication systems and transmission systems, and has played a major role in securing the reliability of information transmission and maintaining communication quality. Further, as disclosed in U.S. Pat. No. 203413, etc., it has been widely applied to a high-density information reproducing system, and a PRML (Partial) combining a partial response transmission equalization technique and a maximum likelihood sequence detection technique. -Response Maximum-Likelihood) method is a typical known technique.
[0006]
[Problems to be solved by the invention]
In such maximum likelihood sequence detection, a sequence (maximum likelihood sequence) having the highest probability of being received (likelihood) is selected from the context of the received signal sequence, and this is output as the most likely decoded information (code) sequence. The result is the decryption result. For this reason, in many known techniques, various constraints and storage elements are added to a transmission code sequence or a transmission communication path to increase the correlation of decoded data, and the Euclidean signal between received signal sequences for all transmission code sequences is increased. By increasing the distance (likelihood difference), the margin for identifying the likelihood difference is expanded. However, in such a method, the addition of various constraints on the transmission code sequence and the transmission signal sequence causes a gain due to the expansion of the Euclidean signal distance of the reception signal sequence, while increasing the redundancy in the transmission information sequence. Invite. For this reason, there is a natural limit in improving the information transmission efficiency and ensuring the reliability of the information transmission by this kind of method, and transmission channels with a strong band limitation, especially high-speed information communication systems and high-speed -When applied to a high-density information recording / reproducing system, the band loss due to the transmission information sequence redundancy is large, so that it is not always an effective method. Furthermore, such a method often requires an excessively complicated transmission code processing circuit and an additional circuit, and a decoder based on maximum likelihood sequence detection requires an exponential function to take into account the increased correlation of decoded data. Unavoidable demands on circuit scale.
[0007]
[Means for Solving the Problems]
The present invention provides means for efficiently improving the maximum likelihood decoding error rate (decoding reliability) in signal decoding by the maximum likelihood sequence detection technique and realizing this easily. For this reason, the present invention discloses means for effectively correcting the decoding error code after the detection of the maximum likelihood sequence by utilizing the characteristics of the decoding error event in the detection of the maximum likelihood sequence. According to the present invention, a likelihood difference in the maximum likelihood determination processing for each decoded code sequence is examined in order to identify a code position where the possibility of occurrence of an error event on the decoded code sequence in the maximum likelihood sequence detection is high. When the likelihood difference is small according to a predetermined criterion, there is provided means for outputting decoding reliability flag information for indicating as a code sequence location having a high possibility of error decoding determination processing in association with the decoded code sequence. . Further, in the present invention, a decoding error in the maximum likelihood sequence detection occurs depending on a Euclidean signal distance between received signal sequences, depends on a pattern of a transmission code sequence, and has a limited specific decoding code error pattern. An error event due to (error syndrome) dominate the best non-decoding error probability, and the occurrence pattern of the decoding error utilizes the fact that a large deviation occurs in the occurrence probability frequency. For this reason, the code replacement (inversion) process is performed on the position of the possibility of an error event on the decoded code string indicated using the above-mentioned decoding reliability flag information according to a specific decoded code error pattern (error syndrome). Thus, means is provided for generating a decoded code candidate sequence of the decoded number, and selecting a normal decoded code sequence from the decoded code candidate sequence of the decoded number and the original maximum likelihood decoded code sequence. For this reason, an error detection code string for checking the presence or absence of a decoding error event according to the above specific decoding code error pattern (error syndrome) is added to the transmission code string in advance. At this time, the error detection code sequence is periodically transmitted so as to detect the random error event due to noise, while taking into consideration the interval of occurrence of the best decoding error event by the maximum likelihood decoding, so as to be able to detect it effectively. Is inserted and added. In the transmission code sequence, an error detection code sequence is inserted and added in units of a code block having a predetermined code length set from the probability of occurrence of an error event (average occurrence interval). The decoding code candidate sequence is generated by the above-described code replacement (inversion) process and the normal decoding code sequence is selected by detecting a decoding error, using the decoding code block corresponding to the unit as a unit. As described above, after removing the error detection code string from the code block of the normal decoding code string selected for inspection, by sequentially outputting this as a decoding result, a more reliable decoded code result can be obtained. Provided. As described above, according to the present invention, in the detection of the maximum likelihood sequence, an error event of a decoding code error pattern (error syndrome) that is stochastically biased occurs, and the reliability achieved by the maximum likelihood decoded sequence is relatively good. There is a property that it is extremely rare that random error events that govern the error rate are concentrated at short intervals. Accordingly, the error detection code sequence can be configured for the purpose of detecting only an average random error event according to a specific decoding code error pattern (error syndrome). It is possible to construct an error detection code string with the property. As described above, a means for easily and effectively improving the decoding reliability by the maximum likelihood sequence detection is provided.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention are closely related to the use of a maximum likelihood sequence decoder in the reproduction of digital data, and this maximum likelihood sequence decoder is generally widely realized using a Viterbi algorithm or the like. First, in order to show an embodiment of the present invention, an outline of a maximum likelihood sequence decoder based on the Viterbi algorithm will be described with reference to FIGS.
[0009]
FIG. 5A schematically shows the flow of an information sequence in an information transmission system and a recording / reproducing system. In a transmission or recording process, a transmission code sequence {X (k)} 100 (k is a natural number indicating a time on the sequence), which is transmission or recording information, is modulated by a coder 102 after a predetermined constraint condition is added thereto. The signal is converted into an analog or digital signal information sequence which can be transmitted via the channel 104 by the device 103 and output to the channel 104. The channel 104 is an information transmission medium including a transmission or recording medium, a transducer, a sensor, and the like. In an information storage / reproduction device, the channel 104 corresponds to a recording / reproduction system including a recording head / information storage medium / reproduction head. Further, the signal in the transmission process is added with additional noise 105, which makes decoding of the received (decoded input) signal sequence {Y (k)} 107 into the original information uncertain in the reception or reproduction process. . In the reception or reproduction process, a signal output from the channel 104 is subjected to predetermined processing by a reception signal processing circuit 106, and then a decoded code is obtained from a received (decoded input) signal sequence {Y (k)} 107. The decoding into the sequence {Z (k)} 109 is performed via the maximum likelihood sequence decoder 108. The maximum likelihood sequence decoder 108 estimates the most probable decoded code sequence {Z (k)} 109 corresponding to the transmitted code sequence {X (k)} 100 which is the original transmission or recording information. I do.
[0010]
For the maximum likelihood sequence decoder 108, various storage elements may exist in the information transmission system 101, which is a pre-processing step from the encoder 102 to the reception signal processing circuit 106. For example, the encoder 102 performs decoding error detection / correction using a convolutional code, a trellis code, or the like, or in order to provide a transmission code with any constraint required in a transmission process such as a run-length restriction, Redundancy may be intentionally added to the transmission code sequence {X (k)} 100 by a convolution process or a mapping process of input / output codes of the encoder 102 sequentially stored in a finite number of storage elements. In the transmission process from the modulator 103 to the reception signal processing circuit 106, there may be a storage element on the channel due to natural or intentional addition of intersymbol interference or the like. When such a storage element is present in each step of the information transmission system 101, each value of the received signal sequence {Y (k)} 107 becomes the value of the corresponding transmission code sequence {X (k)} 100 Rather than the one-to-one correspondence with the state in the storage element depending on the history of the transmission code sequence {X (k)} 100 at each time. The maximum likelihood sequence decoder 108 estimates the transition of the internal state held by the storage element on the information transmission system 101 and utilizes the memory (redundancy) of the transmission system to improve the reliability of the decoding process for noise. By improving the degree and quality, a more accurate decoded code sequence {Z (k)} 109 can be provided on the receiving / reproducing side with respect to the transmitted code sequence {X (k)} 100.
[0011]
FIG. 5C shows received signal sequence {Y (k)} 107 and transmission code sequence {X (k)} 100 in storage channel model in transmission channel model shown in FIG. FIG. 6 is an example of a Markov state transition diagram model showing a correspondence relationship with states in the block diagram. In this state transition diagram example, the information transmission system 101 can be equivalently represented by a model with three 1-bit delay storage elements 110a to 110c (D1, D2, D3) as shown in FIG. 5B. Suppose the case. Then, the value at each time k of the received signal sequence {Y (k)} 107 is the code bit at three times immediately before the transmission code sequence {X (k)} held in these 1-bit delay storage elements 110a to 110c. And the addition / subtraction operation elements 111a to 111c are determined by the following linear convolution operation.
[0012]
Y (k) = X (k) + X (k−1) −X (k−2) −X (k−3)
A binary code (X (k) = + 1 or -1) is assumed for the transmission code sequence {X (k)} 100, and the information transmission system 101 is determined by a combination of the contents of the 3-bit delay storage element. Can take a total of eight states. The information transmission system 101 modeled in this manner is called a class 4 extended partial response (EPR4: Extended Partial Response Class 4) channel, and is often used in an information transmission channel of a magnetic recording / reproducing system. This is disclosed in detail in US Patent No. 203413. Also, for the expression of the above-described convolution operation characteristic possessed by the class 4 extended partial response channel, the partial response characteristic polynomial G (D) = 1 + D−D is often used. ² -D ³ = (1-D) (1 + D) ² (D ^k Represents a k-bit delay operator), but in a magnetic recording / reproducing system or the like that realizes high-density recording, a characteristic polynomial G (D) = (1-D) (1 + D) according to various application conditions. ⁿ A partial response channel characterized by (n is an appropriate natural number) is actively applied.
[0013]
In order for the maximum likelihood sequence decoder 108 to perform maximum likelihood sequence estimation using the storage property (redundancy) of the above-described information transmission system 101, a transition of a holding state inside the storage element on the information transmission system 101 is considered. Need to be specified and described. The state transition diagram of FIG. 5C shows that each time one bit of the transmission code sequence {X (k)} is transmitted, each storage element of the class 4 extended partial response channel information transmission system 101 shown in FIG. How the holding state changes within and how the received signal sequence {Y (k)} 107 is received as the expected signal value {E (k)}, the transition process in all cases Is expressed. In this figure, eight states Sj (j = 0, 1, 2,..., 7) and one-bit delay storage elements D1, D2, and D3 on the information transmission system 101 (110a to 110c in FIG. 5B) are included. The correspondence between the held binary transmission code {X (k)} (X (k) = + 1 or -1) is as shown in the correspondence table in FIG. When an arbitrary transmission code sequence {X (k)} 100 is given, its transmission code sequence and received signal expected value sequence are indicated by a unique transition path sequence on this state transition diagram (added to a transition branch arrow sequence). ) {X (k)} and {E (k)}.
[0014]
FIG. 5D is a trellis (lattice) diagram obtained by expanding the state transition diagram of FIG. 5C in the horizontal axis and time axis directions to express the time transition of the state transition path sequence. . The transition state corresponding to each time k is expressed as Sj (k) (that is, S0 (k), S1 (k), S2 (k), ..., S7 (k)), which is transmitted at time k. The state of the code holding in the storage elements D1, D2, D3 determined by the input of the code X (k) is shown. Further, at each time k, each branch arrow (branch) indicating a transition from the state Si (k-1) to the state Sj (k) has a transmission code for causing a state transition from the state Si to the state Sj. X (i, j) (in other words, the decoded code when this transition is determined) and when this transition occurs, the expected value E (i, j) of the received signal output from the transmission channel is X (i, j). j) / E (i, j). (In the time-invariant information transmission system 101, the state transition structure is temporally constant and does not change with time k. Therefore, X (i, j) and E (i, j) also change with time k. However, the constant value is determined only by the state Si and the state Sj. Even in a time-varying case, the following discussion can be easily generalized.) From this figure, the transmission code ｛X (k )} And the corresponding relationship between the state transition path and the expected value of the received signal {E (k)}. For example, as shown in the example of FIG. 5F, a path sequence 112 represented by five state transition paths (branches) 112a connected at times k 1 to (k + 4) is a 5-bit transmission code sequence ｛+1, +1. , -1, +1, -1} and the information transmission system 101 channel state transition S0 (k-1) → S1 (k) → S3 (k + 1) → S6 (k + 2) → S5 (k + 3) → S2 (k + 4) In this case, the expected value of the received signal sequence output from the channel at this time is expressed as {+2, +4, 0, -2, 0}.
[0015]
In consideration of the state transition of the information transmission system 101, the maximum likelihood sequence estimation in the maximum likelihood sequence decoder 108 includes the reception signal sequence {Y (n)} on which the actually observed noise is superimposed and the state transition diagram. The amount of error from the received signal expected value {E (n)} in each of the above paths is evaluated, and the transition of the state transition path that minimizes the total error of the entire received signal sequence {Y (n)} is uniquely determined. Then, the transmission code sequence {X (n)} for the determined path is output as a decoded sequence {Z (n)}. This is nothing less than estimation of a signal (code) sequence using a pattern matching method based on the principle of the so-called least square method. The Viterbi algorithm is a means for efficiently realizing pattern matching on a continuous time-series signal in real time within finite hardware resources (storage elements for storing time-series signal information) and finite processing delay time. I will provide a.
[0016]
Next, means for specifically realizing the maximum likelihood sequence decoding (maximum likelihood decoding or Viterbi decoding) by the Viterbi algorithm will be described. Here, as an example of the target information transmission system 101, the EPR4 channel shown in FIG. 5B is assumed, and the state transition diagram and the diagram of the EPR4 transmission channel using the binary transmission code sequence shown in FIG. The outline and basic configuration of the Viterbi decoding process will be described with reference to the trellis diagram of FIG. In the following specification, the embodiment will be described based on the above-described example of the EPR4 transmission channel using the binary transmission code string. The Viterbi algorithm is described by a state transition model as shown in FIG. It can be applied to any problem that estimates the maximum likelihood event transition that is stochastically most likely for any event, that is, that results in maximum likelihood transition sequence estimation. Further, the following description of the embodiments does not depend on the specific properties or restrictions of the EPR4 transmission channel, but includes information described in various state transition diagrams having storage elements in various forms described above. The present invention discloses a general embodiment that can be extended to a target channel or model in a similar manner without any restrictions for a transmission system channel or model and can be easily applied.
[0017]
Here, first, attention is paid to FIG. 5D that defines the state transition process at one time k on the trellis diagram for the EPR4 channel. Viterbi decoding, in accordance with the definition of the state transition according to this specific trellis diagram, corresponds to each input of the received (decoded input) signal value Y (k) at time k, corresponding to each state transition path branch (arrow). By evaluating the error from the expected received signal value {E (i, j)}, the path branches that transition to each of the states S0 (k) to S7 (k) at each time are narrowed down one by one. Is repeated. Therefore, the history of the connected path branch sequence transitioning to each of the states S0 (k-1) to S7 (k-1) selected by repeating the same processing until the previous time (k-1) is stored in each state. On the other hand, the surviving path sequences P0 (k-1) to P7 (k-1) are stored one by one. Also, for each of the surviving path sequences P0 (k-1) to P7 (k-1) that reach the respective states S0 (k-1) to S7 (k-1), the reception indicated on each path sequence is performed. Cumulative errors (path metrics) M0 (k−1) to M7 (k−1) between the expected signal value sequence {E (k)} and the actual received signal sequence {Y (k)} are evaluated. , As a metric (likelihood) indicating the likelihood of each of the surviving path sequences. The surviving path sequences P0 (k-1) to P7 (k-1) and the path metric M0 (k-1) for each state S0 (k-1) to S7 (k-1) up to this time (k-1). The contents of .about.M7 (k-1) are obtained by the processing described below at the next time k, and new surviving path sequences P0 (k) to P7 (k) and path metrics M0 (k) to M7 (k) ), And this is repeated as a recursive process every hour.
[0018]
As shown in FIG. 5 (e), focusing on each state on the trellis diagram, as a transition process to the state Sn (k) (n = 0, 1, to 7) at time k, the state Si ( k-1) and state Sj (k-1) (i, j = 0, 1, to 7, when there is a possibility of transition), the specific processing procedure is as follows. Summarized.
[0019]
(1) For a received signal value Y (k) input at time k, a received signal expected value E (i) corresponding to each transition path from state Si (k-1) and state Sj (k-1) , N) and E (j, n), the square error values (branch metrics) BM (i, n) (k) and BM (j, n) (k) corresponding to each transition path branch are Calculate as
[0020]
Transition branch metric from state Si (k-1) to Sn (k):
BM (i, n) (k) = [Y (k) -E (i, n)] ＾ 2
Transition branch metric from state Sj (k-1) to Sn (k):
BM (j, n) (k) = [Y (k) -E (j, n)] ＾ 2
It is known that the metric based on the square error gives an optimal likelihood metric for maximum likelihood sequence estimation when the noise sequence superimposed on the received signal sequence {Y (k)} is independent white Gaussian noise. Other error evaluation values, such as an absolute value error, can be used depending on the decoding implementation conditions.
[0021]
(2) Cumulative error (path metric) PM (i) for likelihood comparison for a path sequence that transits from each of states Si (k−1) and Sj (k−1) to state Sn (k) , N) (k) and PM (j, n) (k). Therefore, the surviving paths Pi (k-1) and Pj (k-1) to the states Si (k-1) and Sj (k-1) evaluated by the processing up to the previous time (k-1) For each of the corresponding path sequence accumulated errors (path metrics) Mi (k-1) and Mj (k-1), the state transition branch metric BM (i, n) (k) calculated in (1) And BM (j, n) (k) are newly added, and the following addition operation is performed.
[0022]
Path metric from state Si (k-1) to Sn (k):
PM (i, n) (k) = Mi (k-1) + BM (i, n) (k)
Path metric from state Sj (k-1) to Sn (k):
PM (j, n) (k) = Mj (k-1) + BM (j, n) (k)
Further, the values of the path metrics PM (i, n) (k) and PM (j, n) (k) for these two path transitions are compared in magnitude and likelihood comparison is performed. The path metric, which is the accumulated error of each path sequence, selects the smaller transition path as a more reliable and more likely path sequence that leads to the state Sn (k) at time k, and rejects the other. Further, a transition is made to the state Sn (k) using the path metric value of the selected path side among the compared path metrics PM (i, n) (k) and PM (j, n) (k). The content of Mn (k) is updated as a new path metric value of the surviving path sequence.
[0023]
Surviving path metrics leading to state Sn (k):
Mn (k) = Min [PM (i, n) (k), PM (j, n) (k)]
Min [•] is an operation to select the minimum value
(3) Update the surviving path sequence history Pn (k) for the state Sn (k) at time k. In Pn (k), connection information of (D + 1) transition states on the surviving path that goes back from the current time k to the finite time D earlier is stored in time order. For example, refer to the stored content of Pn (k) = {Sn (k), Si (k-1), Sj (k-2), ..., Sl (k-D + 1), Sm (k-D)}. Thus, the state transition on the surviving path sequence leading to the state Sn (k) selected in the processing up to the time k is Sm (k−D) → S1 (k−D + 1) → Sj (k−2) → Si It is shown that they are connected and transit in the order of (k−1) → Sn (k). According to (2), whether the surviving transition path to the state Sn (k) at the time k is a transition path from Si (k-1) or a transition path from Sj (k-1) Is determined, the new surviving path sequence history Pn (k) to the state Sn (k) determined by the selection processing is the state Si (k-1) and the state Si (k-1) up to the previous time (k-1). Among the surviving path sequence histories Pi (k-1) and Pj (k-1) for Sj (k-1), the surviving path sequence history of the selected path side state is updated as follows. .
[0024]
History of surviving path sequence leading to state Sn (k):

In the above update processing, Pi (k-1) or Pj (k-1) is selected in accordance with the selected state transition path, and this temporal storage position is moved one time at a time in the past, After extracting past storage contents ((D + 2) -th element) as a result of Viterbi decoding, the storage contents of the latest time and a new transition state Sn (k) are added as storage contents of Pn (k). It means the operation of posting. In the prior art, this is generally configured by a storage circuit such as a shift register that sequentially shifts the storage content at each time (shift register exchange method), and a configuration method using various storage circuits is disclosed. Have been. Further, in many cases, instead of storing the information (state number) of the selected transition state itself, the transmission code for the path branch to the selected transition state is stored in the path sequence history Pk (n). Is stored. For example, when the transition path from the state Si (k-1) is selected as the surviving path for the state Sn (k) at the time k, the recorded contents in the surviving path history for this state are the state Si (k) The value of the transmission code X (i, n) corresponding to the path branch from -1) to Sn (k) can be used. Thereby, when the stored path history information is referred to, the transmission code sequence {X (n)} indicated by the surviving path can be immediately obtained as a decoded code result.
[0025]
Further, in the description of the update processing of the surviving path sequence history information in the above (3), the storage information (path history information for the latest time) for the time k in the surviving path sequence history Pn (k) reaching the state Sn (k) is , Regardless of the state of the path selection from time k−1, the state is constant at the state Sn (k). Therefore, actually, the path information itself does not need to be physically stored, and only the surviving path sequence history information before the time k-1 connected to this state Sn (k) is physically stored in the storage circuit. It only has to be recorded. The path history storage information Sn (k) for the time k can be represented by the fact (storage position information) in which this path history information is stored as a surviving path sequence history Pn (k) leading to the state Sn (k), In the process at the next time k + 1, when referring to the storage content of the surviving path sequence history Pn (k), the path history storage information Sn (k) for this time k may be supplemented and referred to.
[0026]
As described above, the same applies to the case where the value of the transmission code X (i, n) corresponding to the selected path branch is stored as the recorded content in the surviving path history. In the sequence history Pn (k), history information from time k fixed by being a path transition to state Sn (k) to a time before a predetermined time (in the case of an EPR4 channel, from time k to time k-2) The history of the 3-bit transmission code) is omitted by indicating the storage location information itself, which is stored as the surviving path sequence history Pn (k), and is supplemented when referred to reduce the hardware amount of the storage device. You can save.
[0027]
The above-described series of (1), (2), and (3) Viterbi decoding processes are repeated each time the received signal value Y (k) at each time is input. The specific components for implementing this are shown in FIG.
[0028]
The calculation of the branch metrics BM (i, n) (k) and BM (j, n) (k) in (1) is performed by the square error calculation circuit 201. The path metrics Mi (k-1) and Mj (k-1) of the surviving path for the states Si (k-1) and Sj (k-1) are held in the metric storage circuits 202a and 202b, and are accumulated by the metric. The circuit 203 calculates the path metrics PM (i, n) (k) and PM (j, n) (k) in (2), and the comparator 204 performs a comparison operation on these path metric values. The comparison result is output to a selection signal 205, and the metric selection circuit 206 selects one of the path metrics PM (i, n) (k) or PM (j, n) (k) according to the selection signal 205, Using this, the content of the metric storage circuit 202c that holds the surviving path metric Mn (k) to the state Sn (k) is updated and stored. On the other hand, surviving path histories Pi (k-1) and Pj (k-1) leading to states Si (k-1) and Sj (k-1) are stored in path history storage circuits 207a and 207b, respectively. In the process of updating the content of the surviving path history Pn (k) to the state Sn (k) in 3), the path history selection circuit 208 selects one of the contents of the path history storage circuit 207a or 207b specified by the selection signal 205. Then, the storage position of this content is shifted by one time, and newly updated and stored as the content of the path history storage circuit 207c that holds Pn (k). At this time, surviving path history information selected from the end storage position of the path history storage circuit 207a or 207b is output as a decoding result (decoded code sequence Z (k) 109).
[0029]
In actual Viterbi decoding, the above-described processes (1) to (3) for the received signal Y (k) at each time are independently performed for all states of the trellis diagram to be subjected to maximum likelihood sequence estimation. Needs to be done. Therefore, in the actual implementation of the Viterbi decoder, the implementation components for the processing for the state Sn (k) shown in FIG. 6A are provided in parallel in the same configuration by the number of states. For example, for the trellis diagram of FIG. 5D, as shown in the configuration of the maximum likelihood decoder based on the Viterbi algorithm of FIG. 6B, eight states S0 (k) to S7 (k) are used. The implementation components of FIG. 6A assigned to each are provided in parallel with a total of eight systems. At this time, metric storage circuits 202a to 202h for storing surviving path metrics M0 (k) to M7 (k) and path history storage circuits 207a to 207h for storing surviving path sequence histories P0 (k) to P7 (k). Is assigned to each of the states S0 (k) to S7 (k), and these reference destinations are connected to a plurality of locations according to the next stage connection state on the trellis diagram of each state. . For example, if a path connection relationship of the trellis diagram exists between the state Si (k) and the state Sj (k + 1) (i, j = 0, 1, to 7), the state is assigned to the state Si (k). One of the reference destinations of the metric storage circuit 202 is the other input of the metric accumulator 203 assigned to the state Sj (k) that performs addition with the branch metric BM (i, j) (k). One of the reference destinations of the path history storage circuit 207 assigned to the state Si (k) is an input to the path history selection circuit 208 assigned to the state Sj (k).
[0030]
In addition, the value of the expected value E (i, j) of the received signal on the actual trellis diagram is often common to some path branches, and therefore, a square error calculation circuit that performs calculation on this branch metric. 201 is also commonly used, and a configuration input to a corresponding plurality of metric accumulators 203 is often used in practice. As described above, as summarized in FIG. 6 (b), the Viterbi decoder configuration uses a branch metric operation unit (BMU) 200a that receives the received signal Y (k) and performs (1) processing, and uses this branch metric output. (2) Execute the process and select a surviving path to each state by a path metric comparison / selection unit (ACS operation unit) 200b. Further, in response to the selection output, (3) Store and update the surviving path history by the process And a path memory unit (PMU) 200c for narrowing down and determining the decoding result. The implementation method and the configuration method of the maximum likelihood sequence decoding process using the Viterbi algorithm have been described above.
[0031]
Next, in order to clarify the principle of the embodiment of the present invention, FIG. 12 shows an example of a state transition on a trellis diagram on the EPR4 channel in FIG. 5 (d). A process from selection of a surviving path to determination of a decoding result in the decoding process will be described. According to the above-described conventional Viterbi decoding implementation method and configuration method, a state transition path (each time / state) on the trellis diagram using the received (decoded input) signal sequence {Y (k)} 107 at each time. The path branches 112a are always selected one by one. By repeatedly selecting the surviving path sequence 113 in this way, the surviving path sequence at each time is further narrowed down.
[0032]
For example, as shown by the history of the surviving path sequence 113 in FIG. 7, the eight surviving path sequences for each state selected at time k at each time are gradually rejected by the subsequent path selection, and eventually are rejected. At the end of the selection process at time (k + 10), the connected surviving path sequence (thick line arrow sequence) converges to one. At this time, the converged surviving path sequence from time (k-1) to (k + 8) Is determined as the deterministic maximum likelihood path sequence 114, whereby the decoded code Z (k) at time k is the transmission code assigned to the only state transition path (path branch) 112 b that survives on the deterministic maximum likelihood path sequence 114. It is determined by referring to X (i, j). This operation of narrowing down the surviving path sequence (path rejection) is performed by moving the contents of the selected path history Pj (k-1) or Pj (k-1) one time in the past in the above-described decoding processing (3). However, the new Pk (n) is nothing more than a transcription operation.
[0033]
In FIG. 11B, if the path history storage circuits 207a to 207h for storing the surviving path sequence histories P0 (k) to P7 (k) have a sufficient storage length, this path history storage circuit is selected. By repeating the reference and the transcription, the contents of the storage positions at the end of each of the storage circuits 207a to 207h (the path branch selection history at the oldest time) all converge and match the same storage contents. The decoding result can be referred to. As described above, the operation of determining the maximum likelihood path in the maximum likelihood sequence decoding is performed by repeating the rejection / selection of the surviving path candidates that reach each state on the determined maximum likelihood path sequence 114 at each time. The final maximum likelihood path sequence 114 that finally converges and is obtained as a decoding result has a higher likelihood in state transition path selection at all times on this path sequence, and only one remains without being rejected. It is a surviving path sequence.
[0034]
An object of the present invention is to improve a decoding error event in the conventional maximum likelihood sequence decoding process described above and provide a decoding process method having higher reliability. The example of the second trellis transition diagram in FIG. 8A shows an example of the surviving path sequence 113 in the binary code transmission sequence EPR4 transmission channel as in FIG. The purpose of this is to explain the relationship between the decoding error path sequence and the normal path sequence caused by the uncertainty. In this figure, the state transition sequence S6 (k-1) → S5 (k) → S3 (k + 1) → S6 (k + 2) → S4 (k + 3) → S0 (k + 4) → S0 (k + 5) → S1 (k + 6) → S3 With respect to the normal path sequence 115 represented by the (k + 7) path transition, the determined maximum likelihood path sequence 114 including the decoding error event (decoding error sequence) is a state transition sequence S6 (k−1) → S5 (k). This decoding error event (decoding) is determined by the path transition of → S3 (k + 1) → S6 (k + 2) → S5 (k + 3) → S2 (k + 4) → S4 (k + 5) → S1 (k + 6) → S3 (k + 7) The error sequence) is caused by the occurrence of the error path selection 117 for the two surviving path branch candidates flowing into the state S1 (k + 6) at the time (k + 6) on the determined maximum likelihood path sequence 114.
[0035]
In other words, the comparison selection is incorrect between the two surviving path branch candidates that branch off from state S6 (k + 2) at time (k + 2) on normal path sequence 117 and flow into state S1 (k + 6) at time (k + 6). Thus, the partial path sequence S6 (k + 2) → S4 (k + 3) → S0 (k + 4) → S0 (k + 5) → S1 (k + 6) on the normal path sequence 115 which is one of the surviving path branch candidates ) Is replaced by the other path sequence S6 (k + 2) → S5 (k + 3) → S2 (k + 4) → S4 (k + 5) → S1 (k + 6) of the surviving path branch candidate. It occurred as. As the processing in the decoding circuit, the surviving path metrics PM (0,1) (k + 6) and PM (4,1) (k + 6) in the above-described decoding processing (2) for the state S1 (k + 6) at the time (k + 6). Judgment of size:
M1 (k) = Min [PM (0,1) (k + 6), PM (4,1) (k + 6)]
By mistake, PM (4,1) (k + 6) is selected instead of PM (0,1) (k + 6). As a result, the surviving path sequence on the side of state transition S4 (k + 5) → S1 (k + 6) is selected and determined instead of the surviving path sequence on the side of state transition S0 (k + 5) → S1 (k + 6), and the surviving path sequence history is determined. In the decryption process (3) for updating and storing,
P1 (k + 6) = {S1 (k + 6), P4 (k + 5)}
By performing the following path history replacement processing, a sequence error occurs. As a result, the contents of the surviving path sequence history P0 (k + 5) having the normal path sequence 115 up to the time (k + 5) state S0 (k + 5) are rejected, and the contents of the surviving path sequence history P4 (k + 5) having the error path sequence 116. Are selected as surviving path sequences and remain in the updated path history storage circuit. In a noise situation, the selection error of the surviving path branch candidate does not occur at a uniform probability frequency in each state on the deterministic maximum likelihood path sequence 114, but the two surviving path sequences flowing into each state. As the cumulative sum of the differences between the expected values of the received signals of the candidates (the distance between the signal sequences or the path metric difference) becomes smaller, the possibility and frequency of the error in the comparison operation processing in the maximum likelihood decoding processing (2) increase. That is, in the comparison / selection of the path metric likelihood between two surviving path sequences, the smaller the expected value of the discrimination difference (likelihood difference) between the path metrics and the narrower the discrimination margin of the comparison judgment with respect to noise, the smaller the above randomness becomes. A decoding error event due to noise is more likely to occur.
[0036]
The expected values of the received signal sequences of the normal path sequence 115 and the error path sequence 116 in FIG. 8A are ｛−4, −2, and −4 at a 4-bit time from time (k + 3) to time (k * 6), respectively. Since a difference is generated between 0, +2} and {−2, 0, −2, 0}, the cumulative sum of the square errors (distance between signal sequences) is 16. The accumulated sum 16 of the square errors is equal to the minimum accumulated square error (minimum square Euclidean distance, minimum free distance) guaranteed between all the received signal sequences on the binary code transmission sequence EPR4 channel. In addition, the fact that the decoding reliability (decoding error rate) of a transmission channel under noise is mainly determined by an error event between transmission code sequences having such a least square Euclidean distance is determined by the transmission / transmission error. This is a well-known fact in communication theory.
[0037]
In the example of FIG. 8A, the 4-bit content from time (k + 3) to (k + 6) in the surviving path history P1 (k + 6) due to an error in the comparison / selection of the path metric likelihood in the state S1 (k + 6). Is replaced with the contents of the error path sequence 116. From the occurrence process of the error event in such maximum likelihood decoding, the possibility that the above likelihood comparison error event and the path selection error event have occurred in the transition state at each time of the determined maximum likelihood path sequence 114 is considered. If a high point can be estimated and the contents of the error replacement in the surviving path history storage circuit due to this path selection error event can be estimated, the decoding with the next best decoding reliability for the definite maximum likelihood path sequence 114 can be performed. A code sequence can be obtained. Further, if this is compared with the definite maximum likelihood path sequence 114 using another code error determination means, the validity as a transmission code sequence is checked, and it is selectively used as the final decoded code sequence. In addition, it is possible to efficiently increase the reliability of the decoded code. Therefore, the necessary components of the present invention include the process of estimating the location of the occurrence of the selection error event, (b) the content of the error path sequence replaced by the error event of (a) ((a) A process of estimating likelihood comparison and a path code error pattern) on the likelihood path sequence 114; (c) position information of an error event obtained by (a); code error pattern information obtained by (b); A process of generating a candidate of a sub-optimal decoding code sequence of a decoding number using information of the maximum likelihood decoding sequence corresponding to the maximum likelihood path sequence 114, a decoding code candidate of the decoding number generated in (d) and (c) , A process of checking a transmission code sequence that is appropriate, and selecting and outputting the final decoded code sequence. The principle and outline of each step will be described below.
[0038]
Method of performing the process (a): In the surviving path selection at each time on the determined maximum likelihood path sequence 114, the likelihood comparison and the possibility of occurrence of an error event in the path selection are determined by the magnitude of the compared path metric likelihood difference. It can be determined by the magnitude (absolute value).
[0039]
Under practical noise situations, surviving path metrics leading to state Sn (k):
Mn (k) = Min [PM (i, n) (k), PM (j, n) (k)]
In the choice of
The absolute value of the difference between the surviving path metric likelihoods is calculated as the path selection reliability information in the state Sn (k):
Rn (k) = ABS [PM (i, n) (k) -PM (j, n) (k)],
ABS [•] is an operation that takes an absolute value
Can be used as This is because, when the magnitude relation in the path metric likelihood comparison operation is reversed due to noise, this difference in path metric likelihood is generally vague and a small value, and the magnitude relation is reversed, and The probability that the path metric likelihood difference becomes a larger value is based on the fact that the probability becomes extremely small as compared with the probability of the comparison operation error. Thereby, the magnitude of the path selection reliability information Rn (k) is evaluated assuming that the probability of path selection error in each state Sn (k) is low, that is, the path selection reliability is high. Can be. In each state, when selection is made from three or more incoming path metrics, two path metric likelihood difference absolute values are evaluated for each two paths, and a selection error between the two surviving paths is evaluated. The possibility is determined. For each state Sn (k) on the determined maximum likelihood path sequence 114, the path selection reliability information Rn (k) is evaluated, and this is a corresponding part of a state that is equal to or less than a certain reference value or a certain state. It is possible to estimate a portion having a minimum value in a finite-length sequence section or a value within a predetermined number from the smaller one as a portion having a high possibility of occurrence of a path selection error event. Can be made. The method of determining the presence / absence of an error event (the position of the error event) from the evaluation value of the path selection reliability information Rn (k) is based on various methods as described above according to the average occurrence probability of the error event. Used selectively.
[0040]
Method of performing processes (b) and (c): The content of the error path sequence replaced in the surviving path history due to the path selection error, that is, the error code pattern sequence (error syndrome) is the maximum likelihood sequence as described above. It can be easily estimated by utilizing the fact that a path sequence selection error in decoding occurs with an occurrence probability depending on the Euclidean distance between a received signal sequence of a normal path sequence and an error path sequence. In other words, if the constraint structure added to the transmission code sequence and the target trellis transition diagram of the maximum likelihood sequence decoding process by the modulation process or intentional coding process define the distance structure between the reception signal sequences in advance, In many cases, by focusing on a limited signal sequence pair having a least square Euclidean distance, an error code pattern sequence (error syndrome) frequently occurring due to a selection error between the sequences is limited and predicted in advance. Is possible. Then, by sequentially improving the error events from the events of the error code pattern sequence (error syndrome) having a high frequency of occurrence, it is possible to obtain the next best decoding error rate (reliability).
[0041]
For example, in the surviving path sequence 113 shown in FIG. 8A, the normal path sequence 115 and the error path sequence 116 are the four on the path sequence and the received (decoded input) signal sequence 107 from time (k + 3) to time (k + 6). Different sequences are taken between bit times. As described above, the two sequence pairs are the sequence pairs having the least square Euclidean distance on the trellis transition diagram, and the error events between the sequences are the most frequent decoding error events, most frequently occurring. This is one of error code pattern sequences (error syndromes) for decoding. That is, on the transmission code sequence or the decoding code sequence 109, the normal path sequence 115 and the error path sequence 116 have code sequences that are different from each other by only one bit at the time (k + 3) and are different from each other. If the difference sequence between them is defined as a decoded error pattern sequence 118 and an error event, that is, an error code pattern sequence (error syndrome) is described, it can be represented as a 1-bit code error pattern 119a. (Here, in the decoding error pattern sequence 118, 0 indicates no code error, +1 indicates a bit position where the code “1” is erroneously changed to “0”, and −1 indicates a bit position where the code “0” is erroneously changed to “1”. That is, on the binary code sequence, only the non-zero position on the decoded error pattern sequence has the meaning of the error occurrence position and is a pointer indicating the code position of the inverted bit error.) At the time, after branching into two paths indicating different transmission (decoding) codes, they merge into the same state S1 (k + 6) via different 3-bit length path sequences indicating the same transmission (decoding) code sequence. This is obvious from the definition of the trellis diagram in which the channel state is determined by the past 3-bit code history, and this is one form of the path sequence pair having the least square Euclidean distance.
[0042]
As described above, in the EPR4 transmission channel using the binary transmission code, the replacement of the 4-bit error path sequence occurs at a high frequency from any trellis diagram state, and is determined by the process (a). With reference to the bit time of the occurrence of the path selection error event (in the example of the error path sequence in FIG. 8A, the error path selection detection position 119 at time (k + 6)), the decoding position (FIG. In the example of the error path sequence a), an error event of an error syndrome in which the normal code at time (k + 3) causes a 1-bit inversion error, that is, a decoding error code pattern (1 bit code error pattern sequence 119a) is generated. It can be predicted in advance that it is one of the frequently occurring error pattern sequences. As described above, if the frequently occurring error code pattern sequence (error syndrome) is determined in advance from the target trellis transition diagram, the error code pattern sequence is relatively determined based on the path selection error position determined in (a). By performing the inversion substitution process on the code on the maximum likelihood decoded sequence at the determined position, it is possible to obtain a decoded sequence with the next highest reliability.
[0043]
FIG. 8B shows another specific example of the relationship between the normal path sequence 115 and the error path sequence 116 in detecting the maximum likelihood sequence on the EPR4 transmission system channel using the same binary transmission code as in FIG. 8A. It is shown. The occurrence of the error path sequence 116 in this specific example is due to the occurrence of the error path selection 117 in the surviving path selection processing for the state S3 (k + 5) at the time (k + 5) on the determined maximum likelihood path sequence 114. It occurs as a 6-bit length sequence error from k to time (k + 5). The normal path sequence 115 and the error path sequence 116 on the received (decoded input) signal sequence 107 have a least square Euclidean distance 16 and, like the error event in FIG. Can be regarded as one. Comparing the relationship between the normal path sequence 115 and the error path sequence 116 on the decoded code sequence 109, the decoded error pattern sequence 118 is obtained by detecting the error path selection detection position 119 at the time (k + 5) which is the bit time of the occurrence of the error event. As a criterion, as in FIG. 8 (a), the normal code at the continuous 3-bit code position (time k to (k + 2)) up to the decoding position at time (k + 2), which is 3 bits earlier, causes an inversion error. This can be regarded as a decoding error event, and such a 3-bit code error pattern 119b can be predicted in advance as a frequent decoding error event of the channel.
[0044]
The decoding error event of the 1-bit code error pattern 119a in FIG. 8A occurs from any state on the target trellis transition diagram, does not depend on the transmission code sequence, and is based only on the structure of the trellis transition diagram. This is one of the determined decoding error pattern sequences having a high probability of occurrence. On the other hand, in an EPR4 transmission channel using a binary transmission code, there is a signal sequence pair that has a least square Euclidean distance depending on a specific transmission code sequence. FIG. 8B shows a 3-bit code error pattern 119b as this example. In such a code error pattern, a transmission code sequence of "... 01010 ..." or "... 10101 ..." in which code bits on the transmission code sequence are alternately continuously inverted by 3 bits or more is transmitted through the transmission channel. Is the case. When either one of the two transmission (reception) code sequences is transmitted, in the code string portion where the transmission code bits are alternately inverted, the continuous from the last bit position to n (n is an integer of 2 or more) bits A decoding error pattern in which all code bits are inverted may occur at a high frequency.
[0045]
For example, the transmission code sequence “... 0 010 000 ... ”is transmitted, the 3-bit code string portion of“ 010 ”matches the above code pattern, and the respective bits of this code string are inverted“… 0 ”. 101 000... Becomes a signal sequence pair having the minimum Euclidean distance. -1 +1 -1 0 0 0... ”, And becomes an error syndrome error pattern sequence (3-bit code error pattern 119b) that causes a 3-bit continuous inversion error. 01010 000 ... ”is transmitted, the 5-bit code string portion of“ 01010 ”matches the above code pattern, and the last 3 bits (when n = 2) and 4 bits (when n = 3) 5) (when n = 4), the respective bits are inverted. 101 000 ... "," ... 00 0101 000 ... "," ... 0 10101 000... Are three signal sequence pairs having the minimum Euclidean distance. That is, the decoded error pattern sequence is ". -1 +1 -1 000 ... "," ... 00 +1 -1 +1 -1 000 ... "," ... 0 -1 +1 -1 +1 -1 000... ”, Which is a code error pattern (3-5 bit code error pattern sequence) of an error syndrome that causes a 3-5 bit continuous inversion error. When it has, an error pattern event whose subsequence becomes a continuous inversion bit error is also a decoded code error pattern sequence (error syndrome) having a high probability of occurrence as stochastically as the 1-bit code error pattern 119a from the relation of the minimum Euclidean distance. It becomes.
[0046]
Therefore, from the decoding position (k-3) three bits before the bit time k of the occurrence of the path selection error event determined by the processing of (a), the time (k) that is i bits before (the integer i> 1) In the case where the decoded code sequence 109 up to −i−3) corresponds to the above-described pattern that is alternately and continuously inverted, three consecutive bits from time (k−5) to (k−3) or time (k−5) A code string in which each code bit position of continuous 4 bits from k-6) to (k-3) or continuous (i + 1) bits from time (ki-3) to (k-3) is inverted , A decoded sequence candidate with suboptimal reliability can be obtained. As described above, with reference to the error path selection position (error path selection detection position 119) determined in (a) as a reference, the code on the maximum likelihood decoded sequence at a relatively fixed position is referred to and selected based on this. In particular, a code sequence portion having a predetermined length is subjected to inversion and replacement processing in accordance with a predetermined error syndrome, whereby a decoded sequence having the next best reliability can be obtained. In this case, in order to simplify the processing, the code string portion on the decoded code sequence 109 at a relatively fixed position based on the error path selection detection position 119 is referred to without referring to the decoded code sequence 109. By performing the inversion permutation process according to the error syndrome, a decoded sequence candidate with suboptimal reliability may be generated. In addition, from 3 bits to a predetermined number of consecutive bits (the number of bits equal to or less than a predetermined number that can be determined by the constraint condition of the transmission code sequence), inversion and permutation processing is performed in accordance with all code error patterns (error syndromes), and the next best likelihood is obtained. In addition to the case where the decoded code sequence is obtained, there may be a case where a code error pattern (error syndrome) of a specific bit length / pattern is limited or selected.
[0047]
Further, as described above, when there is a possibility that the inversion and replacement processing due to the code error pattern (error syndrome) occurs with reference to the error path selection position 119 determined in (a), the error path selection detection position 119 By checking the length of the rejected path sequence with reference to the contents of the surviving path history storage circuit 207 in the state, the length of a possible decoding error sequence (code error pattern, error syndrome) is determined, and the length is determined. In this case, only the code error pattern (error syndrome) can be selected and subjected to the inversion replacement process. By this means, it is possible to limit the number of decoding sequence candidates with suboptimal decoding reliability. For example, the 1-bit code error pattern 119a described above is the length of the path sequence rejected at the error path selection detection position 119 (a different state transition sequence between the selected surviving path sequence and the rejected path sequence). Is 4 bits, the possibility of occurrence of a 3-bit code error pattern 119b having a rejection path length of 6 bits or other error patterns can be distinguished and processed in advance.
[0048]
FIG. 9 shows a path sequence (rejection path) rejected for the processing at each time from time k to (k + 8) with respect to the determined maximum likelihood path sequence 114 in the surviving path sequence 113 similar to FIG. The relationship between the sequences a to h) and the code inversion replacement position (the hatched portion code position in the table) on the decoded code sequence 109 estimated from the length of each rejection path sequence is shown as an example. Since the rejection path sequence d at time (k + 3) has a length of 4 bits, if it is determined that the processing for the rejection path is an error selection, a 1-bit code error pattern 119a is estimated, and the rejection time The code on the determined maximum likelihood path sequence 114 at a time k three bits before (k + 3) is subjected to one-bit inversion substitution processing. Similarly, since the rejection path sequences eg at the times (k + 4) to (k + 6) also have a 4-bit path length, the 1-bit code error pattern 119a is estimated, and the rejection times (k + 4) to (k + 6) The code on the determined maximum likelihood path sequence 114 at each time (k + 1) to (k + 3) three bits before is a target of the one-bit inversion replacement process. Also, since the rejection path sequence h at time (k + 7) has a 6-bit path length, a 3-bit code error pattern 119b is estimated, and a continuous 3-bit code from the rejection time (k + 7) to 3 bits before, time (k + 2) ) To (k + 4) on the deterministic maximum likelihood path sequence 114 can be determined to be the target of the 3-bit inversion permutation processing. As described above, in the process (a), the length of the rejection path sequence is determined at the same time as the error path selection detection position 119, thereby selecting the code error pattern (error syndrome) to be referred to in the inversion and replacement process. It is possible to limit the number of sub-optimal decoding sequence candidates by the inversion permutation process on the maximum likelihood decoding sequence, thereby improving the utilization efficiency of circuit resources.
[0049]
In the processes (b) and (c) of the present invention, a decoding error pattern sequence having a high frequency of occurrence is preset according to the distance between the received signal expected value sequences in accordance with the target transmission channel, and based on this, , The subsequence on the decoded code sequence 109 based on the error path selection detection position 119 determined in the process (a) is inverted and replaced to generate a decoded sequence candidate with sub-optimal reliability. Therefore, the setting of the decoding error pattern sequence differs depending on the characteristics of the target transmission channel and the constraint conditions added to the transmission code sequence by encoding / modulation processing. In general, the partial response characteristic polynomial G (D) = (1−D) (1 + D) F (D) (F (D)) includes the binary transmission code sequence EPR4 channel used for the above-described magnetic recording / reproducing system channel and the like. , Any characteristic polynomial) is often a form of transmission channel that is implemented in many practical applications. The transmission channel of this mode has a characteristic in transmission characteristics that shows zero response to a DC component (continuous sequence of the same code) and a highest transmission frequency component (continuous inverted code sequence) among the frequency components of the binary transmission code sequence. As shown by way of example of the EPR4 transmission channel described above, from the common channel state transition structure, the most frequent decoding error pattern sequence that defines the least square Euclidean distance between received signal sequences is A point at which a continuous inversion code error sequence of one or more bits occurs, and a point at which this continuous inversion code error occurs with a most frequent probability with respect to a portion of the continuous inversion code sequence on a transmission code sequence transmitted through the channel. Is a common feature.
[0050]
Therefore, when the method of implementing the processes (b) and (c) in the EPR4 transmission channel is generalized and the channel memory length is set to an integer n (n = 3 in the case of the EPR4 channel), the decoded code sequence and the process (a ), Each value from the time (kn) to the time (kn-i + 1) (i = 1 to the maximum inversion length m) of the decoded code position with reference to the time k corresponding to the path selection error position. By inverting and replacing the continuous decoded code sequence up to the parentheses), a decoded code sequence of the next best likelihood can be generated. At this time, a plurality of inversion permutation processes are performed with reference to the fact that the decoded code sequence is a continuous inversion code sequence, performed unconditionally, or according to the length of the rejected surviving path sequence. It is possible to arbitrarily select whether to perform the selection selectively according to the embodiment, as in the case of the EPR4 channel.
[0051]
Further, the maximum inversion length m, which is the maximum code length of the replacement process, is a predetermined value equal to or less than the maximum continuous code inversion length limited by the constraint condition on the transmission code sequence, and in maintaining the performance of the decoding reliability. A practically advantageous predetermined length can be set, and similarly, from the viewpoint of realization performance and implementation scale, any one of m kinds of sign inversion permutations from 1 to m bits can be set according to the embodiment. May be omitted. Further, in the embodiments described above, the transmission code sequence 100 is channel-transmitted as it is, and the decoded code sequence output from the maximum likelihood sequence decoder is also decoded and output to a code sequence equal to the transmission code sequence. However, in the transmission channel of various embodiments, before the transmission channel input, or for the decoded sequence in the maximum likelihood sequence decoder or immediately after the output, pre-coding process, or, starting with post-code processing In many cases, various code conversion and signal processing operations are performed. In this case, for a decoded code sequence different from the code sequence on the transmission channel, the relative positional relationship between the error path selection detection position 119 and the position of the code replacement process and the error code position of the code error pattern sequence (error syndrome) are as follows: An error sequence on a decoded sequence can be obtained by performing a mapping conversion on a processing code position by the same code conversion processing and signal processing operation as the information code. For example, the post code processing (1 + D ² ) (In which a binary code is added modulo 2) is output as a decoded code sequence, a code error pattern sequence (error syndrome) significant to the transmission code sequence "... 0 + 1- 1 + 1−1 + 100... ”Are subjected to the same post-code processing, converted into“... 0 + 1-1000-1 + 1... ”, And are equivalent to the decoded code error pattern sequence (error syndrome) of the inversion permutation process for the decoded code sequence. May be performed. Since the code conversion process in the information transmission system guarantees the code reproducibility, a one-to-one correspondence between a code error pattern sequence (error syndrome) and a code sequence position before and after the conversion is possible. Therefore, it is possible to execute a process equivalent to the above-described embodiment process on the transmission code sequence on the decoded code sequence subjected to various code processes.
[0052]
Process (d) Implementation Method: The flow of the encoding process, which is a feature of the present invention, will be described with reference to FIG. 9 to describe the specific flow of the process (d). The transmission code sequence 100 (information code sequence) supplied to the information transmission system 101 in FIG. 1 is subjected to predetermined processing according to the form of transmission / recording to be supplied to the transmission channel 104, It is given as a sequence 120 (information code sequence). (In the present embodiment, there is no practical problem even if the transmission recording code sequence 120 is considered to be synonymous with the transmission code sequence 100.) From among the decoded code sequence candidates generated in (c), transmission is performed. In order to inspect a code sequence that is valid and select it as a final decoded code sequence, the transmission recording code sequence 120 is divided into transmission recording information code blocks 120a, 120b, 120c,. Error check code strings 122a, 122b, and 122b for detecting that a code error event of the decoded code error pattern (error syndrome) set in (b) and (c) has occurred in the transmission recording information code block. .. Are added, and these are referred to as transmission code blocks 121a, 121b, 121c,. Again, this is processed as one channel transmission code sequence 121 in the time sequence of the original transmission code block transmission recording information code blocks 120a, 120b, 120c... And transmitted on the transmission channel.
[0053]
The error check code strings 122a, 122b, 122c... Added to the transmission recording code sequence 120 in this process are known error check codes and error correction codes such as a parity check code and a cyclic redundancy check (CRC). It can be configured by a configuration technology. For example, in the above-mentioned transmission channel represented by the partial response characteristic polynomial G (D) = (1−D) (1 + D) F (D), continuous inversion of frequently occurring 1 to n bits (n is a predetermined integer) In order to detect a code error pattern (burst error up to n bits in length), a cyclic redundancy code generated by a generator polynomial of degree n can be applied. Providing a method of constructing an error detection code having low redundancy and high detection capability for a specific code error pattern is beyond the scope of the present invention and will not be described here. An error detection code for detecting only a limited number of code error patterns (error syndromes) set in advance in the processes (b) and (c) from characteristics of the code error patterns (error syndromes). Accordingly, an advantage of the present invention is that the reliability of transmission information can be increased using an error detection code having a low redundancy and a simple configuration.
[0054]
On the decoding processing side, the decoded code sequence 109 output from the maximum likelihood sequence decoder and, correspondingly, the next best maximum likelihood decoded code sequence generated in the processes (b) and (c) are transmitted in the transmission mode. .. Are processed in units corresponding to the code blocks 121a, 121b, 121c. That is, the decoded code sequence 109 is obtained from the maximum likelihood sequence decoder, and the code inversion replacement position on the decoded code sequence 109 is determined by the processes (a), (b), and (c), and the code indicating this position is determined. When the replacement pointer sequence 124 is generated, the decoded code sequence 109 is sequentially divided into the decoded code candidate blocks 125a, 125b, 125c,... In units of the transmission code block, and the decoded code sequence generated from the maximum likelihood decoded sequence. A candidate block sequence 126a is generated. Further, in the code unit of each of the decoded code candidate blocks 125a, 125b, 125c,..., The code positions in the decoded code candidate block on the decoded code sequence 109 indicated by the code replacement pointer sequence 124 are all one or more. Inversion is performed independently by selecting a combination or by selecting one or a plurality of combinations in a predetermined manner. .., Which are the next best likelihood decoded code sequences, are generated, and the decoded code candidate blocks 125a, 125b, 125c corresponding to the respective transmission code blocks 121a, 121b, 121c. , A plurality of decoded code candidate blocks belonging to the decoded code candidate block sequences 126a, 126b, 126c,... Are expanded to form a decoded code candidate block list 125. For each code unit of the decoded code candidate blocks 125a, 125b, 125c... Corresponding to each of the transmission code blocks 121a, 121b, 121c, etc., a plurality of decoded code candidate blocks (decoded code candidate block sequences 126a, 126b, 126c) ..), One error-free decoded code candidate block is inspected and selected using the error check code strings 122a, 122b, 122c... Added at the time of transmission, and the error check code string is excluded. The deterministic decoding code blocks 127a, 127b, 127c,... Corresponding to the respective transmission code blocks 121a, 121b, 121c,. As described above, in the present invention, a list of the decoded code sequence including the maximum likelihood code sequence and the next best likelihood code sequence is formed, and the decoded code candidate block sequences 126a, 126b, 126c,. The normal code blocks (determined decoding code blocks 127a, 127b, 127c...) Are inspected and selected for each transmission code block, and the final deterministic decoding code sequence 127 is determined.
[0055]
The code length of the transmission code block and the code length and error detection capability of the added error detection code string are set according to the noise environment and the decoding error probability in which the present invention is implemented. When considering the decoding error probability at the output of the maximum likelihood sequence decoder 108 to which the present invention is applied, the decoding error event occurring in this code block is determined from the code length of the set transmission code block 121a, 121b, 121c. The average number is estimated, and error detecting code strings 122a, 122b, 122c... Capable of detecting all of the error events are constructed and added. As described above, the present invention achieves a practical decoding error probability by focusing on the fact that the probability that random decoding error events caused by noise elements are concentrated at a certain code point is extremely rare. As described above, the number of decoding error events that can be rescued within a transmission code block (decoding code candidate block) of a predetermined length is limited. As a result, the configuration of the error detection code to be added can be made relatively simple, the code length (redundancy) of the error detection code string can be kept low, and the decoding error rate can be improved. For example, if the error probability of the maximum likelihood sequence decoding is 1.0E-3, the length of the transmission code block (decoding code candidate block) is set to about 1000 bits in the order of the reciprocal, so that the decoding error Can be reduced to about one on average. Therefore, by setting the transmission code block length to 1000 bits or less and adding error detection code strings 122a, 122b, 122c... Capable of detecting a single error event, error event rescue and a decoding error rate can be improved. Can be implemented. In general, under a decoding system with a certain decoding error rate, the larger the transmission code block length is set, the higher the ability to detect an error detection code to be added must be increased, and the code length of an error detection code string needs to be increased. For the transmission code block length and the error detection code sequence configuration and length, the optimum length is selected according to the embodiment.
[0056]
On the other hand, the detection capability of the error detection code strings 122a, 122b, 122c... Added to each of the transmission code blocks 121a, 121b, 121c, and the maximum detectable error event in the decoded code candidate block corresponding to the transmission code block. When the number is set, the maximum number of error path selection events in each decoded code candidate block detected in process (a), that is, code inversion in each decoded code candidate block in processes (b) and (c) The maximum number of replacement processing locations (the number of replacement processing) is set to be equal to or less than the maximum number of error events that can be detected.
[0057]
According to the replacement number of the code inversion and replacement processing set in this way, a part or all of the combinations of all the error code processing positions determined by the processes (a), (b), and (c) are determined on the decoded code sequence 109. By performing the code inversion permutation processing, a plurality of decoded code candidate blocks are generated in units of the transmission code blocks 121a, 121b, 121c,..., And a decoded code candidate block list 125 is generated. The code block is checked for errors and selectively output. The above is the description of the implementation method and principle of the present invention.
[0058]
FIG. 1 is a diagram for explaining a basic configuration of an information transmission / recording / reproducing system for implementing the present invention by the above method. In the encoding process, the transmission / recording information code sequence 300 which is an original information data sequence of transmission / recording is generally subjected to an error correction coding process, a coding modulation process, etc. by a coding circuit 301. A predetermined coding process according to the embodiment is performed by a known technique, and is converted into a transmission recording code sequence 120.
[0059]
In the present invention, the transmission recording code sequence 120 is divided into transmission recording information code blocks 120a, 120b, 120c... Each of the recording information code blocks is subjected to a process of generating error detection code strings 122a, 122b, 122c,... And adding them. The check code adding circuit 302 that performs this operation includes a check code generation circuit 303a and a check code insertion circuit 303b. The check code adding circuit 302 sequentially converts the transmission recording code sequence 120 (information code sequence), which is a sequential code time sequence, into a transmission recording information code block 120a, 120b, 120c... , And is configured by an error detection encoder that generates error detection code strings 122a, 122b, 122c... For each block. As described in the above process (d), the error detection code sequence generated here is generated at a high frequency on the decoded code sequence 109 output from the maximum likelihood sequence decoding circuit 308 in the transmission recording system. To detect the presence of a predetermined decoded code error pattern (error syndrome), and to detect only a predetermined finite number of predetermined code error patterns (error syndromes) up to a predetermined finite number. A low degree of redundancy is generated that can be used. An encoding circuit that performs this is the check code generation circuit 303a. The check code insertion circuit 303b converts the error detection code strings 122a, 122b, 122c,... Generated by the check code generation circuit 303a into the transmission recording code sequence 120 (information code sequence) immediately after the transmission recording code block. Alternatively, it is inserted and added at a predetermined corresponding code position. By the check code insertion circuit 303b, the transmission record code sequence 120 is added with error check code sequences 122a, 122b, 122c... For each code block unit of the transmission record code blocks 120a, 120b, 120c. , 121b, 121c... Are generated (see FIG. 9 embodiment). Thereafter, the channel transmission code sequence 121 is regarded as a single code time sequence composed of a stream of transmission code blocks and processed like the code time sequence of the original transmission recording code sequence 120 (information code sequence). , Are input to the code transmission process. A transmission / recording / reproducing signal transmission system 304 converts the channel transmission code sequence 121 into an analog or digital signal format that can be transmitted via a transmission / recording / reproducing channel 306. And a transmission / recording / reproducing channel 306 which is responsible for transmitting transmission / recording / reproducing information. In the transmission / recording code signal processing system 305, a code processing circuit 305a that performs predetermined code processing such as precoding on the channel transmission code sequence 121, and converts the output channel transmission code sequence into a transmittable signal form. And a transmission / recording signal processing circuit 305c for subjecting the converted transmission signal to predetermined signal processing such as signal correction and amplification processing, if necessary. It is composed of technology. The embodiment of the present invention does not depend on the components of the transmission / recording / reproducing signal transmission system 304. The transmission / recording / reproduction channel 306 is an information transmission medium including a transmission / recording medium and a transducer / sensor. In an information storage / reproduction device, in particular, the transmission / reproduction channel includes a recording / reproduction system including a recording head / information storage medium / reproduction head. Equivalent to. The above is the basic configuration of the present invention on the transmitting / recording side.
[0060]
Next, a basic embodiment on the receiving / reproducing side will be described. The received / reproduced signal sequence output from the transmission / recording / reproducing channel 306 is subjected to a predetermined signal processing operation such as gain / phase control processing, noise removal processing, equalization processing, etc. 307. After this process, the received signal sequence 107 is input to the maximum likelihood sequence decoding circuit 308, and the decoded code sequence 109 is decoded and output by the above-described maximum likelihood sequence estimation process (maximum likelihood decoding). According to the present invention, based on the process (a), in this maximum likelihood sequence decoding circuit 308, the possibility of occurrence of an error path sequence selection event when estimating the decoded code sequence 109 (survival path selection process with low reliability, error A function for determining the path selection detection position 119) is provided. Further, a function is provided for generating a decoding reliability flag 123 for instructing the output of the code position (error path selection detection position 119) of the low reliability path sequence and outputting the flag in synchronization with each code of the decoded code sequence 109. Further, if necessary, the length of the rejected surviving path sequence (or the length of the rejected surviving path sequence in the low-reliability surviving path sequence selection (path selection at the error path selection detection position 119) indicated by the decoding reliability flag 123). In some cases, a function may be provided in which information relating to the code string length for performing the code inversion and permutation process estimated based on the length of the surviving path sequence is added to the decoding reliability flag 123 and transmitted simultaneously. A specific configuration and an example of the maximum likelihood sequence decoding circuit 308 having such a function will be described later in detail.
[0061]
Based on the decoding code sequence 109 and the information indicated by the decoding reliability flag 123, which are output information from the maximum likelihood sequence decoding circuit 308, the decoding code candidate block list generation circuit 309 generates the decoding code indicated by the decoding reliability flag 123. The code-reversal replacement process based on the processes (b) and (c) is performed on the low-reliability decoding positions on the sequence 109, and the decoded code candidate blocks 121a, 121b, 121c,. A decoding code candidate block 310 (1), 310 (2), 310 (3)... 310 (m) (m is a predetermined natural number) is generated for each code block unit. Form. In the decoded code candidate block list generation circuit 309, the decoded code processing circuit 309a performs predetermined code processing such as post code processing on the decoded code sequence 109 as necessary, and then converts this code sequence into the transmission code. A process for dividing the block into blocks having the same length and timing as the blocks is performed. Further, the code replacement pointer generation circuit 309b, based on the information of the decoding reliability flag 123 and the information of the decoding error pattern sequence (error syndrome pattern) set in advance, sets the reference code position (for example, error code) indicated by the decoding reliability flag 123. From the path selection detection position 119), for one or a plurality of code positions at a predetermined relative position on the decoded code sequence 109, it indicates that the decoded code at the code position is the target of the inversion substitution process. The pointer information (code replacement pointer sequence 124) is transmitted. The code replacement pointer sequence 124 may selectively instruct a replacement process individually or in combination with a plurality of locations for a plurality of inversion replacement processes in a code block. In some cases, replacement inversion processing using sign inversion patterns having different numbers of numbers may be performed on processing locations. For a plurality of combinations of sign inversion permutations that occur in this case, a plurality of sign substitution pointer sequences 124 that indicate the inversion sign positions of each sign process are generated. As described in the method of performing the processes (b) and (c), information on the length of the rejected path sequence (length of the inverted permutation code sequence) in surviving path selection is added to the decoding reliability flag 121 and supplied. In this case, the process of limiting and selecting the decoded code error pattern sequence (error syndrome pattern) in the permutation inversion process performed based on this is performed by restricting the generation of the code replacement pointer sequence 124 in the code replacement pointer generation circuit 309b. Do. Also, when limiting / selecting the presence / absence of the inversion / replacement processing and the decoded error code pattern sequence (error syndrome pattern) based on the pattern on the decoded code sequence 109 of the inverted / substituted portion, similarly, referring to the decoded code sequence 109, This is performed by restricting the generation of the code replacement pointer sequence 124 in the code replacement pointer generation circuit 309b. The decoded code candidate block generation circuit 309c receives the code replacement pointer sequence 124 corresponding to the block-divided decoded code sequence 109, and performs a code inversion process indicated by the code replacement pointer sequence 124 on the decoded code sequence 109. , 310 (3),..., 310 (m) by the maximum likelihood decoding code block and the next best maximum likelihood decoding code block. A candidate block list 125 is formed. FIG. 2 shows an embodiment in which the above-described operations for constructing the decoded code candidate block list are summarized. Based on the code position indicated by the decoding reliability flag 123 which is the output information 128 of the maximum likelihood sequence decoding circuit 308, the code replacement pointer generation circuit 309b performs the relative sign inversion according to the principle described in (b) and (c). A code replacement start position pointer 123b indicating the replacement position is generated. Further, based on the code replacement start position pointer 123b, a code replacement pointer sequence 124 that directly indicates the code inversion position is generated according to a predetermined code error pattern (error syndrome). In the decoded code candidate block generation circuit 309c, for each code block unit on the decoded code sequence 109, for each position of the code replacement process indicated by the code replacement pointer sequence 124 or a combination of a plurality of positions, A plurality of decoded code candidate blocks including a code block of the original decoded code sequence 109 in which all or a part is selected and the code on the decoded code sequence 109 is subjected to inversion and permutation processing, and the inversion permutation is not performed. A decoded code candidate block list 125 including 310 (1), 310 (2), 310 (3),..., 310 (m) is configured. (At this time, a plurality of code replacement pointers 124 may be generated for each of a plurality of code replacement processes for each code block.) The generation of the decoded code candidate block list is performed by a general logical operation circuit and a buffer. It can be easily realized by the storage circuit.
[0062]
1, a plurality of decoded code candidate blocks 310 (1), 310 (2), 310 (3),..., 310 (m) constituting a decoded code candidate block list 125 are each a decoded code candidate block sequence 126. Is input to the code error check circuit 311, and the presence or absence of a code error in each decoded code candidate block is checked using the error check code string of each transmission code block added by the check code addition circuit 302. The result is instructed to the decoding code candidate block selection circuit 313 through the decoding code candidate block selection signal 312a, and the normal decoding code candidate block having no code error is deleted after the added error detection code string is deleted, and the deterministic decoding is performed. Output as a code block. The time series of the deterministic decoding code block is output as the deterministic decoding code sequence 127, which becomes the information reproduction code sequence for the transmission recording code sequence 120. In the code error check circuit 311, if an error exists in any of the simultaneously input decoded code candidate blocks and a normal decoded code candidate block cannot be selected, a code error exists in the decoded code sequence. Is transmitted in synchronization with the deterministic decoding code sequence 127 which is the decoding result, and can be used in the subsequent code processing or transmission / recording / reproduction system control processing. The code demodulation circuit 314 performs an inverse conversion or an appropriate predetermined process with respect to the coding process performed by the coding circuit 301 on the deterministic decoded code sequence 127 which is the input decoding result, and performs the original transmission / A reception / reproduction information code sequence 315 corresponding to the recording information code sequence 300 is obtained.
[0063]
A plurality of processes for generating the inverted permutation pointer sequence 124 in the decoded code candidate block list generation circuit 309, a process for generating a decoded number of the decoded code candidate blocks 310 (1), 310 (2),. In the error detection process for each decoded code candidate block in 311, an embodiment is described in which processing is performed using circuit resources provided in parallel with a decoded number of decoded code candidate blocks so as to reduce processing delay. On the other hand, a series of processes of the generation of the code replacement pointer sequence 124, the code replacement process, and the error detection process are sequentially and repeatedly performed using the same circuit resources for each decoded code candidate block in a time-division manner. Accordingly, an embodiment in which the scale of the circuit to be implemented is reduced while allowing an increase in the processing time delay is also possible. Furthermore, in the embodiment, for the sake of explanation, each code block unit is described as being physically separated and divided from each code sequence and processed. However, this is logically performed in block units in terms of a realization circuit configuration. A series of processes from the input of the decoded code candidate block list generation circuit to the code error check circuit 311 and the decoded code candidate block selection circuit 313 are performed as a continuous sequential code process, for example. It can be realized using a buffer storage device having a shift register configuration and a logical operation element.
[0064]
In the present invention, the length of a code block, the configuration and code length of an error detection code to be added, the number of code inversion / replacement processes in a decoded block, and a code error pattern are determined according to the embodiment and the state of the transmission / recording / reproduction channel 305. The number of sequences and the number m of blocks in the decoded code candidate block list 125 are often required to be set to optimal values under a desired decoding reliability and implementation scale. It is easy to make it variable and change it according to the implementation situation. In the simplest embodiment, the length of the transmission code block 111 of the present invention is used in a transmission unit (transmission frame or the like) or a recording / reproduction unit (sector unit in a disk device) of an information transmission / recording / reproducing system for implementing the present invention. There is a form that makes the same. Furthermore, in order to improve the decoding reliability, as described above, the transmission unit of the information transmission / recording / reproducing system is divided into a plurality of transmission recordings of a predetermined length based on the transmission channel and a desired decoding error rate. It is possible to divide into code blocks, add an error detection code to each of them, and perform the processing based on the above embodiment.
[0065]
FIG. 3A shows a first embodiment of the Viterbi decoding process for each transition state for simultaneously outputting the decoding reliability flag 123. In the present embodiment, a flag generation unit 210a and a flag memory unit 210b are provided for the conventional Viterbi decoder configuration of FIG. 6A, and the decoding reliability flag 123 is set to the decoded code sequence 109 based on the process (a). And output simultaneously. The flag generation unit 210a calculates the absolute value of the difference between the surviving path metric likelihood PM (i, n) (k) and PM (j, n) (k) based on the process (a), and It is used as surviving path selection reliability information. For this reason, the path metric likelihood PM (i, n) (k) and PM (j, n) (k) are referred to from the ACS calculation unit 200b, and the absolute value calculation circuit 211 uses these to determine the path metric likelihood. Is calculated. Then, the comparator 213 determines whether or not the difference metric absolute value 217 is smaller than a preset reliability flag determination threshold value D212. If the difference metric absolute value 217 is smaller, the selection from the ACS calculator 200b is performed. A reliability flag 214 indicating that the reliability of the path metric selection determination indicated by the signal 205 has decreased is simultaneously output. The flag memory unit 210b has the same configuration as the path memory unit 200c, and includes flag history storage circuits 215a to 215h corresponding to each of the path history storage circuits 207a to 207h of the path memory unit 200c, and path history selection circuits 208a to 208h. Is provided with flag history selection circuits 216a to 216h corresponding to each of. The flag memory unit 210b receives the same selection signal 205 as the path memory unit 200c and a synchronous operation signal of the same cycle, and repeats the same storage update processing operation. Then, for each operation timing, the contents of the above-mentioned reliability flag 214 are held as an initial value in the leftmost storage element of the flag history recording circuit 215c of the corresponding transition state, and the decoded code is selected in the path memory unit 200c. Through the same selection and updating process as in the above-described process, it is output as a decoding reliability flag 123. As a result, in synchronization with each decoded code on the decoded code sequence 109, the flag information indicating the degree of reliability of the surviving path selection at the decoded code position (error path selection detection position 119) is changed to the decoding reliability flag 123. Is output as The decoding reliability flag 123 provides information indicating the reference position of the code inversion and replacement process in the decoded code candidate block list generation circuit 309.
[0066]
FIG. 3B shows a second embodiment of the Viterbi decoding process for each transition state for simultaneously outputting the decoding reliability flag 123. In this embodiment, specific means for obtaining flag information for the code position of the surviving path selection processing with the lowest reliability for each predetermined section (section corresponding to the decoded code candidate block) on the decoded code sequence 109 is described. Is shown. In this case, similarly to the embodiment of FIG. 3B, the flag generation unit 210a and the flag memory unit 210b are provided for each state transition path selection processing system in the conventional Viterbi decoder configuration of FIG. And a process is performed based on the difference metric absolute value 217 at the time of selecting a surviving path in each state transition based on the process (a). In the present embodiment, the flag memory unit 210b is the same as the embodiment of FIG. 3A, and stores a difference metric for storing the smallest difference metric absolute value 217 in the past decoding history in the flag generation unit 210a. A circuit 219 and a comparator 213 for checking the magnitude relationship between the contents and the difference metric absolute value 217 obtained at each decoding operation timing are provided. If the difference metric absolute value 217 in the transition path selection at each decoding operation timing is a value equal to or less than the content of the difference metric storage circuit 219, the selection signal 205 from the ACS operation unit 200b indicates. A reliability flag 214 indicating that the selection determination of the path metric is low reliability is output in the same manner as in the embodiment of FIG. 3A, and the difference metric absolute value at this time is output via a difference metric selection circuit 218. The value of the value 217 is selected and input as the content of the difference metric storage circuit 219, and the value of the minimum difference metric absolute value 217 is constantly updated and held. By providing such a flag generation unit 210a, the maximum value that can be taken by the difference metric absolute value 217 at each predetermined decoding timing (for example, the timing corresponding to the start code position of the above-described decoded code candidate block) is calculated by By setting as the storage circuit initial value 220 held in the metric storage circuit 219, it is possible to determine the minimum difference metric absolute value 217 for each decoding section determined by the interval of the initial value 220 setting timing. That is, in the decoding reliability flag 123 within the decoding code section at the initial value 220 setting interval (for example, the decoding code section corresponding to the above-mentioned decoding code candidate block), the low reliability path selection (error path) output last is output. The flag position of the selection detection position 119) can be treated as the code position information of the decoding path selection with the lowest reliability. Generally, in order to obtain flag information for code positions from the lowest reliability to the n-th lowest reliability (n is a predetermined integer), based on the same principle and configuration, the embodiment shown in FIG. This configuration can be easily realized by adopting a configuration in which the flag generation unit 210a and the flag memory unit 210b are connected in cascade over n stages (n = 2 in this embodiment). (In this embodiment, the branch metric calculation unit 200a, the ACS calculation unit 200b, and the path memory unit 200c are omitted because they are the same as those in FIG. 3B.) According to the configuration of this embodiment, each of the decoding reliability flags 123 (n 3), the flag information of the code position of the reliability path selection decoding (error path selection detection position 119) which is low to the n-th in a predetermined decoding section can be obtained in the same manner as in the embodiment of FIG. it can.
[0067]
FIG. 3D shows an embodiment of the decoder configuration in which information on the rejection path length in the low reliability path selection is output simultaneously with the decoding reliability flag information from the Viterbi decoder. This embodiment is shown based on the embodiment of the reliability determination based on the comparison between the reliability flag determination threshold value 212 and the difference metric absolute value 217 based on FIG. In this embodiment, in order to check the rejected path length in the path selection, in the path memory unit 200c, the match detection circuit 222 and the path detection memory circuit (207c in this embodiment) corresponding to each state transition destination are provided. A path history convergence position detection circuit 223 is provided. These path history storage circuits 207c can be referred to when updating the contents of the path history storage circuit via the path history selection circuit 208 via the path history selection circuit 208 (in this embodiment, 207a and With reference to 207b), it is checked whether these path history contents match. For this reason, the match detection circuit 222 checks whether the contents of the storage elements at the corresponding time positions match each other in the path history storage circuits 207a and 207b, and the path history convergence position detection circuit 223 receives this result and Of the storage elements between the path history storage circuits 207a and 207b, from the storage element at the last stage (the rightmost position in the path history storage circuit) to which position the storage elements converge and match, in other words, two From the path history information held by the path history storage circuits 207a and 207b, the length of the unconverged portion from the storage element at the first stage (the leftmost position in the path history storage circuit) is detected, and the length is detected at each decoding operation timing. Is output as convergence position information 224. The coincidence detection circuit 222 can be easily realized by using an exclusive OR operation, and the path history convergence position detection circuit 223 can be easily realized by using a known logical operation circuit. When the low reliability decoding flag information is output from the reliability flag 214, the convergence position information 224 is used as an initial value of the first stage (leftmost position storage element) of the flag history storage circuit 215c in the corresponding path transition state. Is entered. When the reliability flag 214 outputs flag information of high reliability decoding, a so-called null value having no meaning as the path convergence position information 224 is input. The flag selection circuit 225 selects an initial value for the first stage of the flag history storage circuit 215c according to the reliability flag 214. As a result, the decoding reliability flag 123 does not simply indicate the reliability of the decoding path selection, but also outputs information on the length of the rejected surviving path sequence at the code position. Using the information on the rejection path length, the decoding code candidate block list generation circuit 309 at the subsequent stage selects a decoding code error pattern (error syndrome pattern) for code inversion and replacement processing by the code length, and limits the processing. Can be. Although the present embodiment has been described based on the embodiment of FIG. 3A, the present embodiment can be similarly applied to the embodiments of FIGS. 3B and 3C.
[0068]
The present invention can be applied to various information transmission systems using a maximum likelihood sequence decoder, such as a transmission communication system and a recording / reproducing system, through the general embodiment shown in FIG. Can be improved. The improvement of the decoding reliability in the transmission communication system according to the present invention improves the performance of the receiving and decoding device, allows reduction of the transmission power in the transmitting device, and promotes power saving and miniaturization of the device. enable. Further, application of the present invention to a recording / reproducing system can tolerate noise of a reproduced signal and a decrease in signal-to-noise ratio quality, thereby increasing the information storage density on a recording medium, or improving the recording / reproducing signal bandwidth. And a new effect such as allowing the recording / reproducing operation frequency to be expanded.
[0069]
FIG. 4 shows an embodiment in which the present invention is applied to a magnetic disk device as an application example to an information recording / reproducing system. On the recording side in this embodiment, the recording code 400 as recording information is added with a constraint condition such as a run-length limit by the code / modulation circuit 401 and then by the check code adding circuit 302 as described in FIG. , An error detection code string is added for each code block. In a high-density magnetic recording / reproducing system, a partial response channel characterized by a transmission polynomial (1-D) (1 + D) F (D) (F (D) is an arbitrary polynomial) is often used. A decoding process is performed using a convolution process due to interference and using a maximum likelihood sequence decoding circuit. As described above, in such an information transmission system, a continuous inversion code error of one bit or more becomes a dominant decoding code error pattern (error syndrome pattern) in a decoding error. Therefore, an error detection code sequence for detecting a continuous inversion code error of 1 bit or a predetermined length is generated, and a check code addition circuit 302 is applied to the recording code sequence output from the code / modulation circuit 401. Add this through. At this time, as described above (FIG. 9), the recording code output from the code / modulation circuit 401 is divided into a plurality of transmission recording code blocks depending on the decoding error rate of the maximum likelihood sequence decoding and a desired decoding error rate. After a predetermined error detection code string is inserted and added to each code block, the code block is sequentially input again to the code processing circuit 405 as a series of recording code sequences. When the decoding error rate of maximum likelihood sequence decoding is relatively good, and when the average number of errors in the sector that is the unit of reading is relatively small, an error check code string that can detect this is added to the sector. However, the whole sector may be regarded as one code block and processed without dividing the sector into more subdivided recording code blocks. The recording information code sequence output from the check code adding circuit 302 is subjected to predetermined code processing before recording such as a pre-code for a partial response channel by a code processing circuit 405, and the recording information code is converted to a recording current conversion circuit. At 404, after being converted into a recording current, it is supplied via a recording amplifier 405 to a recording / reproducing channel 409 which is an electromagnetic conversion system. In a recording / reproducing channel 409 comprising an electromagnetic conversion system of the recording head 406 / reproducing head 407 and the recording medium 408, the recording information code is magnetically stored and stored. The reproducing side reads out the stored recording information code as an electrical signal output from the recording / reproducing channel 409 in response to the reading request. The reproduction signal processing circuit 410 subjects the read electric signal to amplification processing by the reproduction amplifier 411, gain control by the variable gain amplifier 412, discretization processing by the analog / digital converter 414, and equalization processing by the equalizer 415. After that, the reproduced signal sequence as an output is supplied to the maximum likelihood sequence decoding circuit 308. (The timing extraction / gain control circuit 416 generates a sample timing signal 416a and a gain control signal 416b from the reproduction signal sequence. A series of processing from the input of the code processing circuit 403 to the output of the reproduction signal processing circuit 410 is performed by the recording / reproduction system. The maximum likelihood sequence decoding circuit 308 is configured based on the above-described embodiment. The output of the maximum likelihood sequence decoding circuit 308 is synchronized with the decoded code sequence 109 simultaneously with the decoded code sequence 109. Then, a decoding reliability flag 123 corresponding to each decoding code position is output. As described in the embodiment of FIGS. 1 and 2, using the decoded code sequence 109 and the decoding reliability flag 123, the decoded code candidate block list generation circuit 309 converts the error check code sequence in the check code adding circuit 303. A list of decoded code candidate blocks is generated in units of the added code blocks. The decoding code processing circuit 309a performs predetermined post-coding processing such as post code processing on the decoded code sequence 109. Further, the code replacement pointer generation circuit 309b converts a pointer signal sequence indicating a decoding code position to be subjected to code inversion and replacement processing into a predetermined signal based on the decoding reliability flag 123 and a predetermined decoding code error pattern (decoding error syndrome pattern). Output as many as possible. In response to this, the decoding candidate block generation circuit 309c generates a predetermined number of decoding code candidate blocks by sign inversion and permutation processing of the pointer position indicated by the code permutation pointer sequence 124. In step 303, a normal decoded code candidate block is inspected and selected using the error detection code string added in code block units. The decoding code candidate block selection circuit 313 receives the decoding code candidate block selection signal 312a indicating the result of the check selection, selects and outputs only the normal decoding code block, and supplies the definite decoding code sequence 127 to the demodulator 418. . The demodulator 418 performs an inverse conversion process of the code / modulation circuit 401 on the deterministic decoded code sequence. As a result, a reproduction code 419 that faithfully reproduces the recording code 400 can be obtained on the reproduction side. When a decoding error is detected from any of the decoding candidate blocks, the code error checking circuit 313 outputs an error decoding block flag 312b, and the reproduced code 419 of the code block can be rescued by the present invention. Flag information indicating that a missing decoding error event is included can be transmitted to subsequent processing. In the subsequent error correction processing, more efficient error correction processing can be executed by using this information, and a decoding error can be recovered by executing a reread operation (retry). In this embodiment, a check code addition circuit 303a is provided after the code / modulator 401 to perform code block division processing and insertion / addition of an error check code sequence. This is to prevent the decoding code error pattern from being expanded by the inverse transform process in the demodulator 418, thereby preventing the configuration of the error check code string from becoming complicated and redundant. However, depending on the processing in the code / modulator 401 and the demodulator 418, this may be avoided and may not be a problem. In this embodiment, the code / modulator 401, the check code adding circuit 303, and the demodulator The order of the processing of the code error check circuit 418 and the processing of the code error check circuit 313 (decoded code candidate block selection circuit 414) can be switched in an effective manner according to the embodiment of the present invention. Although the present embodiment has been described by taking the application to a recording / reproducing system of a magnetic disk device as an example, other information recording / reproducing devices such as other magnetic recording / reproducing devices or optical recording / magneto-optical recording / reproducing devices are most suitable. A reproduction system using likelihood sequence decoding can be applied, and a similar embodiment can be applied. According to the present invention, even if the signal-to-noise ratio quality of the output reproduction signal from the recording / reproduction channel 409 is reduced, it is possible to remedy the decrease in the reliability of the decoded code sequence due to this. By increasing the information recording density of the information or the recording / reproducing frequency, it is possible to provide an information recording / reproducing apparatus having a high recording density and a high speed.
[0070]
In addition, the present invention can be easily configured and implemented by an existing digital signal processing circuit, and can be implemented on an integrated circuit that provides an information transmission system and an information recording / reproducing system as described above. It can be mounted on A logic circuit such as a decoded code candidate block list generation circuit 311 required in the present invention can be easily configured with a small number of logic elements and a buffer storage circuit, and is therefore a circuit suitable for mounting on a high-speed and high-integration integrated circuit. Consists of resources. By implementing and implementing the present invention in an integrated circuit, it is possible to reduce the size of a device that uses an information transmission system that has reduced power consumption and speed due to the effects of the present invention and a high-density and high-speed information recording and reproducing system. And can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment showing a basic configuration of the present invention.
FIG. 2 is a diagram for explaining a method of configuring a decoded code candidate block list.
FIG. 3A is a diagram illustrating a first embodiment of a Viterbi decoding processing configuration for simultaneously outputting a decoding reliability flag.
FIG. 3B is a diagram showing a second embodiment of the Viterbi decoding processing configuration for simultaneously outputting a decoding reliability flag.
FIG. 3C is a diagram illustrating a third example of the Viterbi decoding processing configuration that simultaneously outputs a decoding reliability flag.
FIG. 3D is a diagram showing a fourth embodiment of the Viterbi decoding processing configuration for simultaneously outputting a decoding reliability flag.
FIG. 4 is a diagram showing an embodiment in which the present invention is applied to a recording / reproducing apparatus.
FIG. 5A is a diagram showing a flow of an information sequence in an information transmission system or a recording / reproducing system.
FIG. 5b shows an EPR4 partial response runway channel model.
FIG. 5c is a state transition diagram (binary code transmission sequence EPR4 transmission channel).
FIG. 5D is a diagram showing a trellis transition at time k (binary code transmission sequence EPR4 transmission channel).
FIG. 5E is a diagram showing a path transition to each state at time k (binary code transmission sequence EPR4 transmission channel).
FIG. 5f is a diagram (example of a binary code transmission sequence EPR4 transmission channel) showing a state transition path at times k to k + 4.
FIG. 6A is a diagram for describing specific components that implement the Viterbi decoding process.
FIG. 6B is a diagram illustrating a configuration of a maximum likelihood decoder (a maximum likelihood sequence decoder, a Viterbi decoder) based on the Viterbi algorithm.
FIG. 7 is a trellis diagram (binary code transmission sequence EPR4 transmission channel) for describing a maximum likelihood decoding process by surviving path sequence selection.
FIG. 8A is a first trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the relationship between the normal path sequence and the error path sequence in the maximum likelihood decoding process.
FIG. 8B is a second trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the relationship between the normal path sequence and the error path sequence in the maximum likelihood decoding process.
FIG. 8C is a third trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the relationship between the normal path sequence and the error path sequence in the maximum likelihood decoding process.
FIG. 9 is a diagram illustrating a flow of a coding process according to the present invention.
[Explanation of symbols]
100: transmission code sequence, 101: information transmission system, 102: encoder, 103: modulator, 104: channel, 105: additional noise, 106: reception signal processing circuit, 107: reception (decoding input) signal sequence, 108: Maximum likelihood sequence decoder, 109: decoded code sequence, 110a, 110b, 110c: 1-bit delay storage element, 111a, 111b, 111c: Addition / subtraction operation element, 112: Path sequence, 112a, 112b: State transition path (path branch) 113, surviving path sequence, 114, determined maximum likelihood path sequence, 115, normal path sequence, 116, error path sequence, 117, error path selection, 118, decoding error pattern sequence, 119a, 1-bit code error pattern, 119b, 3-bit code error pattern, 119: error path selection detection position, 120: transmission recording code sequence (information , 120a to 120c ... transmission recording information code block (information code block), 121 ... channel transmission code sequence, 121a to 121c ... transmission code block, 122a to 122c ... error check code sequence, 123, 123 (1), 123 (2): decoding reliability flag, 123a: code replacement reference position pointer, 123b: code replacement start position pointer, 124: code replacement pointer sequence, 125: decoded code candidate block list, 125a to 125c: decoded code candidate block, 126, 16a to 126c: decoded code candidate block sequence, 127: deterministic decoded code sequence, 127a to 127c: deterministic decoded code block, 128: maximum likelihood sequence decoding circuit output information, 200a: branch metric operation unit, 200b: ACS operation unit , 200c... Path memory unit, 201 Square error calculation circuit, 202a to 202h: metric storage circuit, 203: metric accumulation adder circuit, 204: comparator, 205: selection signal, 206: metric selection circuit, 207a to 207h: path history storage circuit, 208, 208a to 208h ... Path history selection circuit, 210a, 210a (1), 210a (2) ... Flag generation unit, 210b, 210b (1), 210b (2) ... Flag memory unit, 211 ... Absolute value calculation circuit, 212: Reliability flag Determination threshold value, 213: comparator, 214, 214 (1), 214 (2): reliability flag, 215a to 215c: flag history storage circuit, 216, 216 (a), 216 (b): flag history selection Circuit, 217: Difference metric absolute value, 218, 218 (a), 218 (b): Difference metric selection circuit, 219: Difference Metric selection circuit, 220: Initial value of storage circuit, 221: Flag determination logic element, 222: Match detection circuit, 223: Path history convergence position detection circuit, 224: Convergence position information, 225: Flag selection circuit, 300: Transmission / recording Information code sequence, 301: coding circuit, 302: check code adding circuit, 303a: check code generation circuit, 303b: check code insertion circuit, 304: transmission / recording / reproduction signal transmission system, 305: transmission / recording code signal processing system 305a: code processing circuit, 305b: code signal conversion circuit (modulation), 305c: transmission / recording signal processing circuit, 306: transmission / recording / reproduction channel, 307: reception / reproduction signal processing circuit, 308: maximum likelihood sequence decoding circuit , 309: decoded code candidate block list generation circuit, 309a: decoded code processing circuit, 309b: code replacement pointer Circuit, 309c: decoded code candidate block generation circuit, 310 (1) to (n): decoded code candidate block, 311: code error check circuit, 312a: decoded code candidate block selection signal, 312b: error decoded block flag, 313 ... Decoding code candidate block selection circuit, 314: code demodulation circuit, 315: reception / reproduction information code sequence, 400: recording code, 401: code / modulation circuit, 403: code processing circuit, 404: recording current conversion circuit, 405: recording Amplifier, 406: recording head, 407: reproduction head, 408: recording medium, 409: recording / reproduction channel, 410: reproduction signal processing circuit, 411: reproduction amplifier, 412: variable gain amplifier, 413: low-pass filter, 414 ... Analog / digital converter, 415 ... equalizer, 416 ... timing extraction / gain control circuit, 41 a ... sample timing signal, 416b ... gain control signal, 418 ... demodulator, 419 ... playback code.

Claims (17)

A signal decoding circuit for converting an input signal sequence into a decoded code sequence using a maximum likelihood sequence estimator (maximum likelihood decoder, Viterbi decoder),
(4) The maximum likelihood sequence estimator outputs a first decoded code sequence having the maximum likelihood with respect to the input signal sequence as a signal output means, and corresponds to each code signal output of the decoded code sequence. Generating a sequence of decoding reliability flag signals to perform, and during the decoding operation, the flag signal generation output means for outputting the decoding reliability flag signal in synchronization with each other with each code signal output of the decoded code sequence,
(5) A code string on the decoded code sequence at a predetermined relative position with reference to the code position indicated by the decoded reliability flag information using the decoded code sequence and the sequence of the decoding reliability flag information. Has a code sequence generation circuit means for generating a predetermined number of decoded code candidate sequences different from the first decoded code sequence by replacing the sequence according to a preset replacement code sequence,
(6) having a buffer storage circuit for holding a predetermined number of code sequences consisting of a first decoded code sequence and the decoded code candidate sequence generated by the code sequence generation circuit means, and the buffer storage circuit; A selection circuit for selecting one code sequence by a predetermined selection unit from the plurality of code sequences held in the storage unit, and the code sequence selected by the selection circuit unit is signaled as a decoded code result. Outputting a signal according to the above (4), (5) and (6). 2. The signal decoding circuit according to claim 1, wherein the maximum likelihood sequence estimator is rejected in the maximum likelihood path sequence comparison and selection processing at each decoding operation unit time as a path sequence likelihood of a selected surviving path sequence. And an arithmetic circuit for calculating the magnitude of the likelihood difference from the path sequence likelihood of the path sequence, and the flag signal generation and output means of (4) outputs the calculation output result from the arithmetic circuit. A decoding reliability flag signal is generated based on the decoding reliability flag signal, and the decoding reliability flag signal is output in synchronization with each code signal output of the decoded code sequence output at each decoding operation unit time. A signal decoding circuit characterized by the following. 3. The signal decoding circuit according to claim 2, wherein the flag signal generation and output means of (4) is configured such that the likelihood difference as an operation output result from the operation circuit is less than (or less than) a predetermined reference value. A comparison / determination operation circuit for judging whether or not there is, a decoding reliability flag is generated based on an operation output result from the comparison / determination operation circuit, and the decoding reliability flag signal is output at each decoding operation unit time. A signal decoding circuit, which outputs the decoded code sequence in synchronization with the output of each code signal of the decoded code sequence. 3. The signal decoding circuit according to claim 2, wherein the flag signal generation and output means of (4) sets the magnitude of the likelihood difference, which is an operation output result from the operation circuit, for each predetermined decoding operation period. A comparison / determination operation circuit for determining whether or not the value is smaller than an n-th or less (n is a predetermined natural number) within a decoding operation period; A decoding flag, and outputs the decoding reliability flag signal in synchronization with each code signal output of the decoded code sequence output at each decoding operation unit time. circuit. 5. The signal decoding circuit according to claim 1, wherein (d) the information code sequence corresponding to an input signal sequence to the signal decoding circuit before passing through a code information transmission system channel receives the information code sequence. An error encoder that generates an error detection code sequence for each unit of a code block having a predetermined code length of the information code sequence as a processing circuit unit before transmission, and the error detection code sequence is Code processing circuit means for inserting and adding at a predetermined position corresponding to the code block; (e) the selection circuit means of (6) is synchronized with a unit of the code sequence block on the information code sequence; And (d) selecting the decoded code sequence and the decoded code candidate sequence in units of a decoded code block corresponding to the unit of the code block. (F) The selection circuit means of (6) Decoding code For the unit of the decoding code block on the sequence and the decoding code candidate sequence, the error detection added to the code block on the information code sequence corresponding to the decoding code block in (d). (D), (e), and (f), wherein an error detector for detecting a code error using a code string is provided, and the selecting operation is performed based on a detection result output signal from the error detector. A signal decoding circuit characterized by the following. 6. The signal decoding circuit according to claim 5, wherein the error detection code sequence inserted and added by the code processing circuit of (d) replaces a normal decoded code sequence with the replacement code sequence of (5). The first code error sequence is configured to be able to detect that all the first code error sequences resulting from the processing exist to a predetermined number or less, and the first code error sequence is replaced by the replacement code sequence in (5) . A signal decoding circuit configured to detect that a code error sequence generated by processing is present up to a predetermined number or less. 7. The signal decoding circuit according to claim 1, wherein the code sequence generation circuit in (5) refers to a code sequence portion to be subjected to the replacement process on the first decoded code sequence and converts the code sequence portion. Code string discriminating circuit means for discriminating, and code string selecting circuit means for selecting a specific permutation code sequence to be used for the permutation process from a plurality of permutation code sequences based on a discrimination result by the code string discriminating circuit means; A signal decoding circuit for performing a replacement process using a replacement code sequence selected by a code sequence selection circuit means. 8. The signal decoding circuit according to claim 1, wherein the maximum likelihood sequence estimator is configured to determine a maximum likelihood path sequence comparison and selection process at each decoding operation unit time by using a path sequence likelihood of a selected surviving path sequence. A path sequence code length determining circuit for determining a path sequence code length of a different sequence portion between path sequence likelihoods of the rejected path sequence; and the flag signal generation / output unit of (4), Information on the path sequence code length from the path sequence code length determination circuit means is added to the decoding reliability flag signal output at each decoding operation unit time corresponding to the information, and A signal decoding circuit for outputting information on a path sequence code length in synchronization with each flag signal output of the decoding reliability flag information sequence output at each decoding operation unit time. 9. The signal decoding circuit according to claim 1, wherein a code information transmission system channel having a signal output of 0 is provided in front of said maximum likelihood sequence estimator in response to the input of the same and continuously inverted binary information code sequence. A signal decoding circuit, characterized in that a continuous code error sequence having a predetermined first code length or less is used as the replacement code sequence used in (5). The signal decoding circuit according to any one of claims 5 to 9, wherein a code information transmission system channel having a signal output of 0 with respect to an input of the same and continuously inverted binary information code sequence is the maximum likelihood sequence. A continuous code error sequence having a predetermined first code length or less is used as the replacement code sequence to be used in (5), which is provided in the preceding stage of the estimator, and in (d), the first code A signal decoding circuit using an error detection code for detecting a continuous code error sequence having a length equal to or less than a length. 11. The signal decoding circuit according to claim 9, wherein a binary information code sequence input to the code information transmission system channel has a predetermined second processing circuit means as a processing circuit before transmission to which the information code sequence is input. A signal decoding circuit comprising an information code processing circuit for adding a constraint condition for prohibiting continuous code inversion of a code length exceeding a code length. 12. The signal decoding circuit according to claim 11, wherein the second code length is set to be equal to or less than the first code length. 13. The signal decoding circuit according to any one of claims 1 to 12, wherein in the selection processing of (f), any one of the decoding code sequences and any of the decoding code candidate sequences to be subjected to the selection processing is selected. When a code error is also detected from the decoded code block, a flag output means corresponding to any output of the decoded code block and outputting error detection flag information in synchronization with the output is provided. Signal decoding circuit. 14. The signal decoding circuit according to claim 13 , wherein the error detection flag information output from the flag output means is used, and an input signal sequence portion corresponding to a specific decoded code block indicated by the error detection flag information, or A signal decoding circuit, wherein an input signal sequence having a predetermined length including an input signal sequence portion is input again, and the signal decoding operation is repeated. Information transmitting communication apparatus characterized by comprising a signal decoding circuit according to claims 1 to 14. Information recording and reproducing apparatus characterized by comprising a signal decoding circuit according to claims 1 to 14. The semiconductor integrated circuit characterized by having a signal decoding circuit according to claims 1 to 14.

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