KR19980070857A - Digital magnetic recording and playback device - Google Patents

Abstract

The present invention relates to a digital magnetic recording and reproducing circuit and apparatus for recording and reproducing digital information on a recording medium such as a magnetic disk. To provide, a device for outputting a PR equalization sequence by partial response (PR) equalization of an error correction coded signal reproduced on a magnetic recording medium, a Viterbi for performing a maximum communicative sequence estimation in a PR equalizing sequence, and outputting a maximum communicative sequence An error correction decoder for error correction decoding the detector and the maximum communicable sequence, wherein the Viterbi detector detects the missing error at the time of estimating the maximum communicable sequence, detects the missing error with the maximum communicable sequence, and positions in the detected sequence. The error correction decoder outputs the error correction information, and the error correction decoder uses the error error information to recover the error correction. It was set as the structure comprised by performing a call.

With such a configuration, by detecting the decoding error at the time of estimating the maximum communicability series and correcting the lost error byte derived from the decoding error, the decoding error characteristic as the reproduction processing can be improved. Obtained.

Description

Digital Magnetic Recorder

The present invention relates to a digital magnetic recording and reproducing circuit and apparatus for recording and reproducing digital information on a recording medium such as a magnetic disk, and more particularly, to a signal processing circuit for performing PR equalization and Viterbi decoding and an apparatus using the same. will be.

The demand for high-density recording and high-speed recording on magnetic disk devices is increasing, and the signal processing technology of the recording / reproducing system supporting this has also coped with high-density and high-speed recording. In the recording code, the coding rate R is increased for speed, and R = 8/9 is frequently used at present. In recent years, a higher rate of 16/17 code has been proposed in various ways, and has become a mainstream recording code. In addition, in order to cope with a drop in the signal-to-noise ratio due to inter-signal interference due to high density recording, a partial response for detecting a signal sequence closest to the reproduction signal using known interference configured on the reproduction channel (PR) is described below. The equalization method has been put into practical use. In particular, PR4ML (Partial Response Class 4 with Maximum Likelihood Detection) is already installed in magnetic disk products as LSI.

Fig. 1 shows the structure of a digital magnetic recording and reproducing apparatus conventionally used. As a PR equalizing circuit, a case of using an EPR4 (Extended PR4) system will be described. In the figure, on the recording side, error correction coding is performed by the error correction encoder 10 by using a read, a solomon code, or the like. Reed and solomon codes are frequently used in magnetic recording and reproducing apparatus requiring high reliability because they can correct byte errors. The error-correction-coded sequence is recorded by the recording encoder 11 and converted to a format suitable for the self-playing characteristic by adding a run length restriction or the like. The 8/9 code and, more recently, the 16/17 code are most often used. The record coded series is also converted into a Non Return to Zero Inverted (NRZI) format by a precoder 12, and then a recording medium 15 such as a magnetic disk through an amplifier 13 and a recording head 14. Are recorded magnetically in

On the other hand, on the reproduction side, the information recorded on the magnetic recording medium 15 is reproduced as an electrical analog signal by the reproduction head 16 and the amplifier 17 and controlled by the variable gain amplifier 18 to have a constant amplitude. This prevents the overflow of the input amplitude to the A / D converter 19. The A / D converter 19 uses the analog signal as a digital signal, and all subsequent reproduction processing is digitally processed. The digitized signal is sampled every bit interval and input to the PR equalizing circuit 20 at an appropriate timing. In PR equalization (here, EPR4 equalization), the EPR4 equalization is carried out using the input sample sequence to a channel having a transfer characteristic of 1 + D-D ^ 2-D ^ 3. Where D is a channel memory and ^ is a power arithmetic operation. The EPR4 channel is represented by an eight state transition as shown in FIG. Here, S0, S1, ..., S7 are channel states 000, 001, ..., 111, respectively. According to the value of the input signal (0, 1, respectively-and + in the figure) in an arbitrary state, an equalization signal corresponding to the upper and lower branches (paths) is output, respectively, to the next channel state. Transition In the EPR4 channel, the equalization output is 5 values (2, 1, 0, -1, -2).

The EPR4 equalized series is subjected to maximum communicative decoding by the Viterbi detector 21. This is a process of using the state transition diagram shown in Fig. 24 and estimating the history of the transitioned path with the most certain probability (maximum communist series estimation). The decoding result (0, 1) obtained by the maximum communicative sequence estimation is recorded and decoded by the recording decoder 22, and inversely converted into an input sequence to the reproduction-side recording encoder. The decoded sequence is reproduced by the error correction decoder 23 after the byte error correction is performed by read, solomon decoding, or the like.

The structure of the Viterbi detector 21 is shown in FIG. Here, the thick recording line and the thin recording line are meant to be buses of several bit lines and one bit, respectively (hereinafter, the same notation is used in other drawings). In the figure, EPR4 equalized sequence yk at time k branches the probability that EPR4 equalization output candidates (2, 1, 0, -1, -2) are output by branch metric calculation circuit 41. Calculate as a meter. The branch meter is calculated as the squared distance between the yk and the EPR4 equalization output candidate. Here, the branch meters for 2, 1, 0, -1, and -2 are denoted as BM (2), BM (1), BM (0), BM (-1), and BM (-2), respectively.

After the branch meter is calculated, the addition, comparison, and selection process is executed by the ACS (Add Compare Select) circuit 42. 3 shows the detailed circuit configuration. As shown in the figure, in the ACS circuit, for each state, the branch meter BM and the state probability diagram S (the cumulative value of the branch meter) are added by the adder 100 according to the EPR4 state transition diagram (FIG. 24) and compared. The larger the degree of communism and the corresponding path in the circuit 101 are output as the new state degree of commutation SO, S7, and survivor path information SP0, SP7. Here, survival path information SP0, ..., SP7 are values represented by 1 bit (0, 1) for identifying the upper path and the lower path in the state transition diagram 24. The state degree of dispersion S0, ..., S7 is stored in the delay element T102, respectively, and is provided for the next ACS calculation processing. In addition, although not shown in figure, the output of the delay element 102 shall be feedback-connected to the input of the adder 100, although not shown in figure.

On the other hand, the survival paths SP0, ..., SP7 are input to the data selection circuit 103, and output the binary data d0, ..., d7 corresponding to each survival path information to the path memory circuit 43. In the path memory circuit 43, the binary data d0, ..., d7 are stored for a sufficiently long period (path memory length), and a trace back process (usually a well-known register exchange process) is performed. In addition, the data traced back to the path memory length is output as the Viterbi decoding result.

By the way, when attention is paid to the coding, the grid code has been noted and examined as a method capable of high-density recording exceeding EPR4ML. The lattice code is a type of recording code, in which information after error correction encoding is coded according to an arbitrary rule, and this is fused with a PR channel to extend MSED (Minimum Squared Euclidean Distance) between signals. The lattice code corresponding to the PR4 channel (hereinafter referred to as PR4 lattice code) is examined.

As a PR4 lattice code applied to magnetic recording, there is a MSN (Matched Spectral Null) code. This is to obtain a larger MSED by matching the frequency characteristic of the code with that of the magnetic channel. The principle is described in Matched Spectral-Null Codes for Partial-Response Channels, IEEE Transactions on Information Theory, May 1991 Vol. 37, No 3, pp. 818-855, for example. In this system, coding is performed on the basis of the PR4 channel, so that MSED = 4 is achieved, and an S / N gain of 3 dB is obtained for the uncoded PR4ML.

The MSN code is also applicable to the EPR4 channel. In fact, it is also described in the above document that MSED = 12 can be realized. However, the coding rate is found to be only half as low.

Currently, LSIs using MSN codes with 8/10 and 6 coding rates as PR4 grids have been started, and their characteristics are described in "Design and Performance of a VLSI 120 Mb / s Trellis-Coded Partial Response Channels". , IEEE, Proceedings of 1994 The Magnetic Recording Conference.

In recent years, the lattice encoding method by permutation has been limited as a method of improving the MSN code and further realizing a high rate. This is to replace and connect the channel state corresponding to the last bit of the codeword and the state corresponding to the next bit of the codeword with only the channel bits maintained, and described in "Improved Trellis-Coding for Partial Response Channels, IEEE, Proceedings of 1994". The Magnetic Recording Conference, Finite Truncation Depth Trellis Codes for the Dicode Channel, IEEE, Transactions on Magnetics, November 1995, Vol. 31, No. 6, pp. 3027-pp. 3029 and US Patent No. 5497384, Permuted Trellis Codes for Input Restricted Partial Response Channels. By the lattice coding method by the above substitution, the degree of freedom of code assignment is increased, and a high rate recording code equivalent to 8/9 can be relatively easily realized.

Due to the rapid progress toward high-density recording due to the demand for large-capacity storage, it is impossible for EPR4ML alone to respond to the demand for ultra-high density. In addition, the PR4 grid is not applicable to the high line recording density area, and there is a limit to the MSED. On the other hand, when the grid code is applied to the EPR4 channel, the MSED can be enlarged, but it is difficult to increase the coding rate, resulting in a large number of channel states and a large circuit size.

DISCLOSURE OF THE INVENTION An object of the present invention is to provide a digital magnetic recording and reproducing circuit by a signal processing which is simple in view of the above problems and which enables higher density recording than in the related art, and a digital magnetic recording and reproducing apparatus using the same.

1 is a block diagram of a digital magnetic recording and reproducing apparatus according to the prior art;

2 is a block diagram of a Viterbi detector according to the related art,

3 is a configuration diagram of an ACS circuit according to the related art;

4 is a configuration diagram of an example of a digital magnetic recording / playback apparatus according to the present invention;

FIG. 5 is a configuration diagram of an example of the Viterbi detector in FIG. 4; FIG.

6 is a configuration diagram of the ACS circuit in FIG. 5;

7 is a configuration diagram of a path memory circuit in FIG. 5;

8 is a configuration diagram of a loss error detecting circuit in FIG. 5;

9 is a configuration diagram of another example of the Viterbi detector shown in FIG. 4;

10 is a configuration diagram of an example of the ACS circuit in FIG. 9;

FIG. 11 is a configuration diagram of a path memory circuit in FIG. 9;

12 is a configuration diagram of a missing error detection circuit in FIG. 9;

13 is a configuration diagram of another example of the ACS circuit in FIG. 9;

14 is a configuration diagram of a path determining circuit in FIG. 13;

15 is a configuration diagram of a path memory circuit in FIG. 13;

16 is a configuration diagram of another example of the digital magnetic recording / playback apparatus according to the present invention;

17 (a) and 17 (b) are diagrams for explaining the encoding according to the present invention;

18 is a configuration diagram of an example of the Viterbi detector in FIG. 16;

19 is a configuration diagram of a second error correction decoder in FIG. 18;

20 is a configuration diagram of another example of the Viterbi detector in FIG. 16;

21 is a configuration diagram of an example of the second error correction decoder in FIG. 20;

22 is a configuration diagram of another example of the second error correction decoder in FIG. 20;

23A and 23B illustrate a search method of a best sequence and a 2nd sequence by a Viterbi detector of the present invention;

24 is a grid diagram showing a state transition of a signal sequence.

In the present invention, a reproducing apparatus is provided with a device for detecting a missing error bit of decoding in a Viterbi detector, a device for detecting missing error bytes in a recording decoder, and a device for performing missing byte error correction in an error correction decoder.

Or a recording apparatus, comprising: a device for executing the first error correction encoding and the second error correction encoding on the data; and a device for detecting the missing error bit in the Viterbi detector in the reproduction device; the second error correction decoding in the decoder. A device for detecting a missing error and a device for performing first error correction decoding by using the missing error are provided.

[Examples of the Invention]

First embodiment

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described using drawing. 4 is a diagram showing a first embodiment in the present invention. In the figure, the error correction encoder 10, the recording encoder 11, the precoder 12, the amplifier 13, the recording head 14, the magnetic recording medium 15, the reproduction head 16, the amplifier 17 ), The variable gain amplifier 18, the A / D converter 19 and the PR equalization circuit 20 are the same as those of the conventional apparatus (see FIG. 1).

In the Viterbi detector 24, the recording decoder 25 and the error correction decoder 26 according to the present invention, a device for detecting missing error bits, a device for detecting missing error bytes and a device for correcting missing error bytes are added. Doing. In the present embodiment, a bit or byte determined to have a high probability of a decoding error will be referred to as a missing error bit or a missing error byte. 5 shows the configuration of the Viterbi detector 24. Until the branch meter is calculated by the branch meter calculation circuit, it is the same as the conventional Viterbi detector (Fig. 2).

After the branch meter is calculated, the addition, comparison, and selection processing is performed in the ACS circuit 52 next. In this ACS circuit, the degree of communism for each state is calculated. If it is not affected by noise, only one state probability value is high and the other state probability value is infinitely close to zero. On the contrary, when strongly influenced by noise or the like, the difference between the state probability having the highest value and other state probability decreases. In the present embodiment, when the absolute value of the difference of communicability to be compared in the ACS is smaller than an arbitrary threshold value, it is highly likely that a decoding error due to S / N decrease is likely and the reliability of the data of the selected path is low. And judge this to be a loss error.

Fig. 6 shows the ACS circuit configuration. As shown in the figure, in the ACS circuit 52, for each state, the branch meter and the state probability diagram (the cumulative value of the branch meter) are added by the adder 100 according to the EPR4 state transition diagram (see FIG. 24). Is input to the comparison circuit 111. The comparison circuit 111 outputs the difference values DM0, ..., DM7 of the two states, and sets the code bits as the survival path information SP0, ..., SP7. Here, the difference value is a difference between two input signals in the comparison circuit 111. For example, in a state S0, DM0 = (BM (0) + S0)-(BM (-1) + Calculated as S4). The same applies to DM1, ..., and DM7. Since the digital processing is all performed by two's complement display, the code bits can be used to represent the survival path information SP0, ..., SP7. The state degree of dispersion S0, ..., and S7 are respectively stored in the corresponding delay elements 102, and are provided for the next ACS calculation processing. Although not shown, the delay element 102 outputs are feedback connected to the input of the adder 100, respectively.

The threshold value determination circuit 112 compares the absolute value | DMi | of the differential value DMi with the value of the threshold value R in accordance with the above-described theory, and detects a missing error. As the threshold value R, an ideal value, i.e., a value of 1/2 of the maximum communicability in the absence of an error, specifically, (MSED of PR channel) / 4 is adopted. The threshold value determination circuit 112 outputs ai = 0 when | DMi |> R, and ai = 1 when otherwise. ai acts as a control signal.

On the other hand, the data selection circuit 113 receives the survival path information SPi and the control signal ai and outputs the corresponding data d0 ', ..., d7' to the path memory circuit 53 at each survival path information SPi. Here, data d0 ', ..., d7' are three values of 1, 0, and disappearance X (= 0.5). X represents the missing bit, taking the middle of 1 and 0, or 0.5. ai (i = 0, ..., 7) is a control signal for determining the output di 'of the data selection circuit any one of 1, 0, and X. When ai = 1, di' = X, When ai = 0, the data selection circuit 113 outputs binary data according to SPi.

7 shows a schematic diagram of the path memory circuit 53. In the path memory circuit 53, the path memory registers 200 (respectively reg0. 1) input to the selectors 0, ..., and selector 7 201 by the input survival path information SP0, ..., SP7, respectively. , reg0.2), ..., (reg7.1, reg7.2)) and output to reg0, ..., reg7 (202), respectively. The selector i (i = 0, ..., 7) 201 is a circuit for selecting the output of the path memory register 200 (regi. 1, regi. 2) in the state Si. 1, regi. In 2, the data history of the path leading to the state Si is stored. Its depth is equal to the path memory length.

On the other hand, the regi 202 also operates as a shift register, and its depth is equal to the path memory length (usually about 20 bits in the case of EPR4ML). The binary data di 'input from the data selection circuit 113 is serially input to the regi 202, and outputs data shifted out on the opposite side as a Viterbi decoding result. Here, the decoding result is any one of 1, 0, and X. The register outputs R0, ..., R7 are fed back to the signal lines marked at the corresponding positions, respectively, and the contents of the path memory registers 200 (regi. 1, regi. 2) are updated. If the path memory length is sufficiently long, the serial outputs of the regi 202 are all the same (the paths after the traceback are merged). Therefore, here, decoding data is obtained using reg0 202 in the state S0.

In addition, although the path memory register 200 is shown in the drawing for easy understanding of the concept of operation, in the actual circuit configuration, only the regi 202 is used directly without using the path memory register 200. The above operation can be realized by connecting to the selector i 201.

Since the data sequence as the Viterbi decoding result obtained by the above process is according to the maximum communicative decoding, it is output to the disappearance error detection circuit 54 as the best sequence in FIG. 8 shows the configuration of the disappearance error detection circuit 54. The best sequence is 1, 0 and disappearance X = 0. As one of five, these are identified by the threshold value determination circuit 81. In other words, the input data is d = 0. 25 <d <= 0. When 75 is reached, it is determined that disappearance X has arrived, and the missing error bit detection flag flg-ebit is outputted as 1. Otherwise, the input data is determined to be 1 or 0, and the missing error detection flag flg-ebit is output as 0.

By the above process, the Viterbi detector 24 in FIG. 4 outputs the Viterbi decoding result and the missing error bit detection flag to the recording decoder 25. The record decoder 25 inputs the Viterbi decoding result and the missing error bit detection flag, and executes a record decoding process. Here, the processing is performed in byte units. The record decoder 25 knows that there is an error in the byte after decoding when the missing error bit detection flag is 1, and the error decoding decoder 26 has lost error byte detection flag flg-ebyte = 1 together with the record decoding result. Output When the missing error bit detection flag is 0, it is determined that there is no missing error in the byte after recording and decoding, and the result is output to the error correction decoder 26 as the missing error byte detection flag flg-ebyte = 0 together with the decoding result.

The error correction decoder 26 inputs the record decoding result and the missing error byte detection flag, and performs the lost error correction. If the minimum hamming distance of the sign is d (bytes), errors up to t (bytes) can be corrected in normal random error correction. Here, it is assumed that t satisfies the relationship of d = 2t + 1. The missing error byte detection flag adds the error position information to the recording and decoding result, thereby increasing the error correction capability. When the loss error correction is applied to the code having the hamming distance, the loss error up to d-1 = 2t (byte) can be recovered. This means that if the missing error can be detected accurately, it has a correction capability of about twice the random error correction.

Therefore, according to the present embodiment, it is possible to improve the decoding error characteristic as the reproduction processing by detecting the decoding error at the time of estimating the maximum communist sequence and correcting the lost error byte derived from the decoding error.

Second embodiment

9 is a configuration of a Viterbi detector showing the second embodiment. The system configuration (Fig. 4) except for the Viterbi detector is the same as in the first embodiment. Therefore, the configuration of the Viterbi detector will be described here.

In Fig. 9, the configuration of the branch meter calculation circuit 41 is the same as that of the first embodiment, and the branch meters BM (2), BM (1), BM (0), BM (-1), The BM-2 is input to the ACS circuit 62. The ACS circuit 62 and the path memory circuit 63 are characterized by simultaneously outputting the best sequence obtained by the maximum communicative sequence estimation and the 2nd series most optimally following the best sequence. In this embodiment, both sequences are compared, and the other part is regarded as a decoding error at the time of estimating the maximum communist series, and the missing error bit is set. In this embodiment, a systematic search method is proposed as the output method of the 2nd series and applied to the ACS operation. In the systematic search method, in the ACS operation, a state readability memory register and a path memory for each 2nd series search are provided for each state, and the sorting process is used to determine the maximum and second largest likelihoods and corresponding paths. Choose and remember each. If the path memories for the best and 2nd sequences are completely matched, the path memory corresponding to the third largest communist degree is stored as the 2nd sequence to avoid the perfect match between the best and 2nd sequences. The basic operation of the sorting process is, for example, ACS operation processing in the state S0 as shown in Fig. 23A, and includes {S0 + BM (0), S0 '+ BM (0), S4 + BM (-1). , S4 '+ BM (-1)} is rearranged in order from the larger value, and the survival path corresponding to the maximum value and the next largest value is selected. Here, Si and Si '(i = 0, ..., 7) are the state degree of commutation obtained corresponding to a best series and 2nd series, respectively. By this process, in addition to the best series in the ACS calculation, the 2nd series estimated to have the next highest probability can be simultaneously obtained. The same processing is performed for the other states S1, ..., S7.

Fig. 24 shows an example of estimation of the best series and 2nd series. For the sake of simplicity, it is assumed that all zero data sequences are transmitted to the best sequence, and the path memory length is 10 bits. At this time, 0000000000 and 0011000000 are stored in the path memories for the best sequence and the 2nd sequence, respectively. If a decoding error occurs due to noise or the like at time n-7 to (n-4), the relationship between the best sequence and the 2nd sequence is reversed. In the conventional configuration, since only the best sequence is used as the maximum communicative decoding output, a decoding error occurs at this point. In contrast, the present invention includes a 2nd sequence in which accurate decoding results are stored, and when either one of the best sequence or the 2nd sequence is output, accurate decoding results can be obtained. In this way, by performing the decoding using the 2nd series in combination, the error mapping of MSED = 4 in EPR4ML can be eliminated, and the MSED can be expanded to six equivalents. This means that the S / N gain of EPR4ML improves by 1.8 dB.

The above is the basic concept of the ACS operation using the best and 2nd series by the systematic search method of the present invention. 10 shows the configuration of an ACS circuit 62 for implementing the above-described processing. That is, the state probability diagrams S0, ..., S7, and 2nd for the branch meters BM (2), BM (1), BM (0), BM (-1), and BM (-2) and the best in each state. The state degree of commutation S0 ', ..., S7' for the series is added by the adder 100 according to the state transition diagram (Fig. 24), and the maximum degree of communality (best) and the second by the sorting circuit 120 are added. (2nd), 3rd (3rd) largest communist degree and corresponding survival path information (C0-1, C0-2, C0-3), ... (C7-1, C7-2, C7-3) Outputs Here, the third one is also output, but this is to avoid the perfect match between the best and the 2nd series as described above. That is, the path memory circuit 63 compares the path memories corresponding to the best series and the 2nd series, and outputs 1 with control signals p0, ..., p7 when both sequences are the same. The selector 121 of the ACS circuit selects the degree of commutation for the 3rd series in response to the control signal, and sets this as the 2nd degree of communality Si '(i = 0, ..., 7). The state diffusivity Si 'of the best and 2nd series thus obtained is stored in the corresponding delay elements 102 and provided in the next ACS. The output Si of the delay element 102 is assumed to be feedback connected to the input of the adder 100, respectively. On the other hand, the survival path information Ci-1, Ci-2, Ci-3 (i = 0, ..., 7) for the best, 2nd, and 3rd sequences is input to the path memory circuit 63. Here, the survival path information Ci-1, Ci-2, Ci-3 is represented by 2 bits.

11 shows a schematic diagram of the path memory circuit 63. As shown in FIG. In Fig. 11, the selectors 0, ..., and selector 7 210 each represent a path memory register 200 ((reg0.1, reg0.2, reg0.3, ...) in states S0, ..., S7, respectively. reg0.4), ..., (reg7.1, reg7.2, reg7.3, reg7.4)) is a circuit for selecting the best, 2nd, and 3rd. Here, the path memory registers 200 (regi. 1, regi. 2, regi. 3, regi. 4) (i = 0, ..., 7) respectively represent data of the paths leading to the respective states Si and Si '. The history (for example, denoted by R0, R0 ', R4, R4' in the state S0) is stored for the length of the path memory. By the survival path information Ci-1, Ci-2, Ci-3, the selector circuit 210 selects the path memory registers corresponding to the best, 2nd, and 3rd sequences, and registers ri-1, ri-2, It is output to ri-3 (202). The register 202 is also a shift register. In the data selection circuit 214, data Di-1, Di-2, Di-3 for the best, 2nd, and 3rd sequences are respectively input in series. In the state S0, D0-1 'of the shifted out data D0-1', D0-2 ', D0-3' is a decoding result for the best sequence. D0-2 'and D0-3' are input to the selector 213 as 2nd and 3rd decoding outputs, respectively. When the path memory length is sufficiently long, the serial output is the same in any state (the paths after the traceback are merged). Therefore, here, the decoding results of the best, 2nd, and 3rd series are obtained by using the serial output in the state S0.

The comparison circuit 211 checks whether the contents of the registers ri-1 and ri-2 202 match, and if they match, outputs a control signal pi = 1, otherwise pi = 0 to output the ACS. The signal is transmitted to the selector 121 in the circuit 62. In the case of pi = 1, ri-3 output and D0-3 'are selected from ri-2 output and D0-2', ri-3 output and D0-3 'input to the selector 213, and pi = 0 In this case, select ri-2 output and D0-2 '. The selection result of D0-2 'or D0-3' is the final decoding result for the 2nd series.

In this way, path memory registers for the best and 2nd sequences are selected and stored in the registers ri-best and ri-2nd 212 as Ri and Ri ', respectively. These are feedback-connected to signal lines of corresponding notation, respectively, and are stored in the corresponding path memory registers 200 as updated path memories, respectively.

In addition, although the path memory register 200 is shown in the drawing for easy understanding of the concept of operation, in the actual circuit configuration, the register ri-best and ri- do not use the path memory register 200. The above operation can be realized by directly connecting to the selector i 210 using only 2nd 212.

By the above processing, the Viterbi detector in Fig. 9 decodes data for the best and 2nd sequences in the path memory circuit 63, and outputs the result to the disappearance error detection circuit 64. 12 shows the configuration of the disappearance error detection circuit 64. The best and 2nd sequences are converted into 1-byte parallel data by the S / P (serial / parallel) converter 91 and then input to the exclusive logical sum circuit 92. Here, an exclusive logical sum for each bit in the parallel data is taken. The result of the processing is compared with all zero byte data by the comparison circuit 93, and in other cases, the missing error bit detection flag flg-ebit = 1 is assumed to be missing error, and flg-ebit = 0 otherwise. Output to decoder 25.

The record decoder 25 inputs the Viterbi decoding result and the missing error bit detection flag, and executes a record decoding process. The error correction decoder 26 inputs the recording decoding result and the missing error byte detection flag, and performs the lost error correction. The recording decoder 25 and the error correction decoder 26 operate in the same manner as in the first embodiment.

Third embodiment

Next, a third embodiment will be described with reference to FIG. The basic consideration of this embodiment is the same as that of the second embodiment, and is a system in which the best series and the 2nd series are used together. However, unlike the second embodiment (the threshold value determination method), the method of obtaining the 2nd series differs in the configurations of the ACS circuit 62 and the path memory circuit 63. The other configuration is the same as in the second embodiment. Therefore, here, the 2nd series estimation method by the threshold determination method in a Viterbi detector is described.

Fig. 23B shows the principle of the 2nd series estimation method by the threshold determination method. In this method, in the ACS operation, when the difference in the degree of communism to be compared is smaller than an arbitrary threshold value, the best sequence is output as the path memory of the side selected by the ACS, and the 2nd series is the path memory of the side not selected by the ACS. If the difference in communicability is not smaller than an arbitrary threshold value, the path memory of the side selected by the ACS is output to both the best and the 2nd series. In other words, when the difference in the degree of communicability in the ACS is small, it is determined that a decoding error is likely to occur, and the selected path is determined as the best sequence as the first candidate and the path not selected as the second candidate as the second candidate. If the difference in the degree of communism is sufficiently large, the maximum estimated sequence is all stored without distinguishing between the best and the 2nd series. For example, in the ACS in the state S0, the degree of communism to be compared is {α = S0 + BM (0), β = S4 + BM (-1)}. If any one of α and β is correct, the difference dM = α-β of the communicability degree is theoretically 4 when there is no noise. In reality, however, dM is nonuniform due to noise, so that a clear distinction between α and β occurs. Therefore, it is determined whether or not the reliability of the selection result by the ACS is high according to the difference dM of the degree of communicability, and the 2nd series is determined accordingly. If the threshold value is DM, as shown in Fig. 23B, the best and 2nd sequences are determined by the regions A, B, C, and D in the case where the difference dM of the degree of communality and the threshold value DM are determined. The same applies to the other states S1, ..., and S7.

As this threshold value DM, a value of 1/2 of the maximum degree of likelihood in the case of an ideal or error free, specifically, (MSED of PR channel) / 4 is adopted.

13 is a configuration of an ACS circuit 62 that realizes the above-described processing. In the figure, the best and the 2nd series are obtained by applying the threshold determination method. In the drawings, the processes up to addition and comparison are the same as in the conventional invention and the first embodiment.

In the present embodiment, as the output of the comparator 111, the difference DM0, ..., DM7 of the degree of communism is output instead of the survival path. The difference DMi (i = 0, ..., 7) of the communicability degree is input to the path determining circuit 7. Here, according to the above-described principle, the survival path information (C0-1, C0-2), ... (C7-1, C7-2), which represent the best series and the 2nd series by DMi values, is stored in the path memory circuit. Will output Here, (Ci-1, Ci-2) (i = 0, ..., 7) is represented by 1 bit of 0 or 1. The configuration of the path determining circuit 7 is shown in FIG. In the figure, the absolute value is taken by the absolute value converting circuit 71 when the difference DMi of the degree of communality is input. At the same time, the code bit of the DMi is input to the path selection circuit 73. On the other hand, the absolute value of the absolute value is compared with the threshold value DM in the comparison circuit 72. The actual processing subtracts the threshold DM from the absolute value and outputs the sign bit to the path selection circuit 73. The path selection circuit 73 provides survival path information Ci-1, Ci-2 (i = 0, ..., ...) for the best and 2nd sequences in the code bits of the DMi and the two bits of the output of the comparison circuit 72. 7) is output to the path memory circuit 63. Determination areas A, B, C, and D (see FIG. 23B) to which the difference DMi of the communist degree belongs are identified by the processing shown in FIG. 14, and survival path information Ci-1 and Ci-2 for this is determined. Decide

On the other hand, the path memory circuit 63 outputs the Viterbi decoding results for the best and 2nd sequences by the traceback process from the survival path information. 15 shows a schematic diagram of the path memory circuit 63. As shown in FIG. In the drawing, selectors (0.1, 0.2), ..., selectors (7.1, 7.2) 221 are assigned to the best and 2nd sequences in states S0, ..., and S7, respectively. For the path memory registers 200 ((reg1.0.1, reg0. 1.2), ..., (reg7.1.1, reg7.1.2) and (reg0.1.1, reg0.2) 2) registers corresponding to survival path information (Ci-1, Ci-2) (i = 0, ..., 7) in (reg7.1, reg7.2)) Is a circuit for selecting. The path memory registers 200 each contain the best data history R0 of the paths leading to the respective states. R7 and 2nd data histories R0 ', ..., R7' are stored for the length of the path memory. These are feedback-connected to the marked signal lines, respectively. When the survival path information Ci-1 and Ci-2 is input, the selector 221 selects the corresponding path memory register 200, and the registers ri. 1 and ri. Is output. On the other hand, the data selection circuit 222 outputs data corresponding to the survival path information Ci-1 and Ci-2. The registers (ri. 1, ri. 2) 202 are also shift registers, and data for the selected best path and the 2nd path (output of the data selection circuit 222) are serially inputted. The data shifted out is the decoded output. If the path memory length is sufficiently long, the serial output is the same in any state (the paths after the traceback are merged). Therefore, here, the Viterbi decoding results for the best and 2nd sequences are obtained using the serial output in the state S0, respectively.

In addition, although the path memory register 200 is shown in the drawing for easy understanding of the concept of operation, in actual circuit configuration, the path memory register 200 is not used and the register ri. 1 and ri. The above operation can be realized by directly connecting to the selector 221 using only 2 (202).

By the above process, the Viterbi detector in Fig. 6 outputs the decoded data for the best and 2nd sequences from the path memory circuit 63 to the missing error detection circuit 64. The subsequent processing is the same as in the second embodiment (Fig. 9).

Fourth embodiment

Although the first to third embodiments were characterized by the decoding process performed by the playback apparatus, the present embodiment is characterized by both the process of encoding and decoding the information. Fig. 16 shows an overall configuration diagram of this embodiment.

In Fig. 16, a second error correction encoder 9 and a second error correction decoder 28 are provided instead of the recording encoder 11 and the recording decoder 22 in the conventional invention (Fig. 1).

The encoding of the record information will be described.

As in the conventional invention, the digital information A is subjected to the first error correction encoding by the error correction encoder 10 using a read, a solomon code, or the like, and has the form shown in Fig. 17A.

The first error correction coded sequence is further subjected to second encoding by a second error correction encoder 9. First, the sequence shown in Fig. 17A is divided into small blocks of fixed length, for example, in units of 8 bits or 16 bits. The second error correction encoding is performed on the small block. At this time, a Hamming code, a parity check, or the like can be applied to the code. The first encoding and the second encoding may be any method as long as they are error correction encoding. However, in order to increase the encoding rate and the error correction capability, it is better to adopt other methods. After the second error correction encoding is performed, the data becomes a data block of the type shown in Fig. 17B. The data block consists of a synchronization signal and a recording code. The synchronization signal is overhead for detecting the head of the data block. The overhead portion is removed upon entry to the record carrier.

The coded sequence is magnetically recorded on the recording medium 15 such as a magnetic disk through the precoder 12, the amplifier 13, and the recording head 14 as in the conventional invention.

Also on the reproduction side, the information recorded on the magnetic recording medium 15 is reproduced as an electrical analog signal by the reproduction head 16 and the amplifier 17, and the variable gain amplifier 18 and the A / D converter 19 are replaced. A digital signal sampled at an appropriate timing is input to the PR equalization circuit (here, EPR4 equalization) 20 through the digital signal. The EPR4 equalized series is subjected to maximum communicative decoding by the Viterbi detector 27. The Viterbi detector 27 outputs to the second error correction decoder 28 the decoding result obtained by the maximum communicative sequence estimation (which may be output together with the 2nd series). The second error correction decoder 28 uses the Viterbi decoding result and the missing error bit detection flag, and performs second error correction decoding for each write block. This repairs an uncorrectable error by Viterbi decoding. In the repaired sequence described above, the restoration information A 'is reproduced after random byte error correction (first error correction decoding) is performed in the error correction decoder 26 by read and solomon decoding.

18 is a configuration of the Viterbi detector 27 and the second error correction decoder 28 showing the present embodiment. In the drawing, the Viterbi detector 27 is composed of a branch meter calculation circuit 41, an ACS circuit 52, and a path memory circuit 53, but these are the configurations described in the first embodiment (Figs. 5 and 6). (See FIG. 7), so the description is omitted. The Viterbi decoding results (1, 0, X) obtained by the above are input to the second error correction decoder 28. In the second error correction decoder 28, a loss error correction circuit having the configuration shown in Fig. 19 is used. In the present embodiment, the Viterbi decoding output is three values of 1, 0 and disappearance X (= 0. 5), and the loss error correction circuit in Fig. 19 performs the loss error correction process using these. That is, the Viterbi decoding result is converted from serial data to parallel data (data length is A in Fig. 17B) by the S / P converter 170, and is normally lost by the loss error correction decoding unit 171. The loss error is corrected by performing error correction decoding. The corrected result is a decoded output. On the other hand, in the case where the error correction decoding unit 171 cannot correct, that is, when there are more errors than the error correction capability by error correction decoding, the error correction decoder together with the decoding result as the missing error byte detection flag flg-ebyte = 1. Output to (26). The error correction decoder 26 inputs the decoding result and the missing error byte detection flag, and performs the lost error correction. As described in the first embodiment, if a missing error can be accurately detected, the correction capability is improved to about twice the random error correction.

Fifth Embodiment

The fifth embodiment is almost the same as the fourth embodiment, but the configurations of the Viterbi detector 27 and the second error correction decoder are slightly different as shown in FIGS. 20 and 21.

In Fig. 20, the Viterbi detector 27 is composed of a branch meter calculation circuit 41, an ACS circuit 62, and a path memory circuit 63, but these are the configurations described in the second and third embodiments (Fig. 9, 10, 11, 13, and 15), the description thereof will be omitted. In the present embodiment, the Viterbi detector outputs the best sequence and the 2nd sequence to the second error correction decoder 28 by the method described above, that is, the systematic search method or the threshold value determination method. In the second error correction decoder 28, a decoding error detection circuit having the configuration shown in Fig. 21 is used. In the figure, the best and the 2nd series are respectively converted into parallel data (data length is A in Fig. 17B) by the S / P converter 170, and the error detection circuit 180 uses the data length unit. Processing takes place. In the error detection circuit 180, the second error correction decoding is performed simultaneously or independently for each of the best and the 2nd series, and error detection is performed. The error detection circuit 180 calculates an error detection result for each of the best and the 2nd series, that is, syndromes S1 and S2, respectively, and outputs them to the selector 181 together with the decoded best and the 2nd series. The selector 181 judges the sequence of the side where S1 and S2 are 0 (no error detection) as an accurate decoding result, selects it, and outputs it. At the same time, the missing error byte detection flag flg-ebyte is output as zero. When both S1 and S2 are 0, you may output either best or 2nd. At this time, the missing error byte detection flag flg-ebyte is zero. If S1 and S2 are both 1 (with error detection), an error occurs in both series, so the missing error byte detection flag flg-ebyte is 1 and the best sequence is output. The sequence selected by the selector 181 is sent to the error correction decoder 26 together with flg-ebyte as the decoding result. The error correction decoder 26 inputs the decoding result and the missing error byte detection flag, and performs the lost error correction (first error correction decoding).

Sixth embodiment

The sixth embodiment is a modification of the fifth embodiment, and only the second error correction decoder 28 is different from the fifth embodiment. The configuration of the second error correction decoder 28 of this embodiment is shown in FIG.

In the figure, the best and the 2nd series are converted into parallel data (data length is A in Fig. 17B) by the S / P converter 170, and processing is performed in units of the data length. The exclusive logical sum circuit 190 takes the exclusive logical sum for each bit by the exclusive logical sum circuit 190 of the converted parallel data. The result is output to the loss error correction decoding circuit 191 as a loss error detection signal. When all bits of the missing error detection signal are 0, it may be determined that no missing error occurs. If any one of the missing error detection signals is 1, it is considered that a missing error has occurred at the bit position. The missing error correction decoding circuit 191 inputs the best sequence converted into the above parallel data and the missing error detection signal, and performs a lost error correction decoding (second error correction decoding) process. As a result, the missing error byte detection flag flg-ebyte = 0 is outputted when the error is corrected, and flg-ebyte = 1 is outputted when the error is not corrected. The lost error correction decoded sequence is sent to the error correction decoder 26 together with flg-ebyte as the decoding result. The error correction decoder 26 inputs the decoding result and the missing error byte detection flag, and performs the lost error correction (first error correction decoding).

The present invention can be applied to any PR channel (PR4, EEPR4, etc.) other than the EPR4 channel. In addition, it is generally applicable to a signal processing method applying a maximum communicative detection function according to the concept of Viterbi decoding, for example, a Decision Feedback Equalizer with Finite Delay Tree Search (DFE-FDTS) method.

According to the present invention, it is possible to improve the decoding error characteristic as the reproduction processing by detecting the decoding error at the time of estimating the maximum communist sequence and correcting the lost error byte derived from the decoding error.

Claims (18)

An apparatus for outputting a PR equalization sequence by partial response (PR) equalization of an error correction coded signal reproduced on a magnetic recording medium; A Viterbi detector for estimating the maximum communicative series on the PR equalization series and outputting the maximum communicative series; An error correction decoder for error correction decoding the maximum communicative sequence; The Viterbi detector detects a loss error at the time of estimating the maximum communist sequence, outputs the loss error information indicating the detection of the missing error and the position in the detected sequence together with the maximum communist sequence, And the error correction decoder performs error correction decoding using the missing error information. The method of claim 1, And the Viterbi detector determines a loss error when the absolute value of the difference between the two compared state states is less than an arbitrary threshold value when calculating, comparing and selecting each state degree. The method of claim 2, The arbitrary threshold value is a digital magnetic regeneration device, characterized in that MSED / 4 of the PR series. The method of claim 2, And the Viterbi detector sets a flag to a bit that detects the loss of the maximum communicative sequence and outputs the missing error information together with the maximum communicable sequence. The method of claim 1, And the Viterbi detector selects the best sequence and the 2nd sequence and estimates the best sequence and the 2nd series, and outputs the exclusive logic sum together with the best sequence with the exclusive logic sum as missing error information. The method of claim 5, And the Viterbi detector stores a path having the maximum degree of communality and the second highest degree of communality for each state when estimating the maximum communicable sequence, so that the Viterbi detector is a best sequence and a 2nd sequence. The method of claim 5, When the Viterbi detector calculates, compares, and selects each state probability, when the absolute value of the difference between the two compared states is less than an arbitrary threshold value, the Viterbi detector includes a path of the best sequence, A path corresponding to the smaller one is a 2nd sequence, and the best sequence and the 2nd sequence are the same when the absolute value of the difference of the state diffusivity is more than an arbitrary threshold value. The method of claim 7, wherein The arbitrary threshold value is a digital magnetic regeneration device, characterized in that MSED / 4 of the PR series. An error correction encoder which performs first error correction encoding on the data, divides the first error correction encoded data into a predetermined length, executes second error correction encoding, and generates data recorded on the recording medium; An apparatus for outputting a PR equalization sequence by partial response (PR) equalization of a reproduction signal reproduced on a recording medium; A Viterbi detector for performing a maximum communicative sequence estimation on the PR equalization sequence and outputting a maximum communicative sequence; A correction decoder for performing a second error correction decoding on the maximum communicative sequence and executing a first error correction decoding; The Viterbi detector detects a missing error at the time of estimating the maximum communicable sequence and sets the maximum communicable sequence value corresponding to the point where the missing error is detected to be a determined value X other than 0.1, The error correction decoder regards the value of X as an error at the time of decoding the second error correction and performs error correction decoding. When error correction is impossible, the second error correction decoded data includes a loss error and missing error information. And error correction is performed using the missing error information at the time of decoding the first error correction. The method of claim 9, The Viterbi detector is a digital magnetic recording and reproducing apparatus characterized in that, when calculating, comparing and selecting each state diffusivity, the absolute value of the difference between two comparable state states is less than an arbitrary threshold value. . The method of claim 10, The arbitrary threshold value is a digital magnetic recording and reproducing apparatus, characterized in that MSED / 4 of PR series. An error correction encoder for performing first error correction encoding on the data, partitioning the first error correction encoded data into a predetermined length, performing second error correction encoding, and generating data to be recorded on the recording medium, An apparatus for outputting a PR equalization sequence by partial response (PR) equalization of a reproduction signal reproduced on a recording medium; A Viterbi detector for estimating the maximum communist series on the PR equalization series, selecting the best series and the 2nd series, and outputting both series; And a correction decoder which performs second error correction decoding on both of the series, and performs first error correction decoding on one of them. The method of claim 12, And the Viterbi detector stores a path having the maximum degree of communality and the second largest degree of communality for each state at the time of estimating the maximum degree of commutation, so that the Viterbi detector is a best sequence and a 2nd sequence. The method of claim 12, When the Viterbi detector calculates, compares, and selects each state probability, when the absolute value of the difference between the two compared states is less than an arbitrary threshold value, the Viterbi detector includes a path of the best sequence, A digital magnetic recording and reproducing apparatus characterized by setting the path corresponding to the smaller one as the 2nd sequence, and making the best sequence and the 2nd sequence equal when the absolute value of the difference in the state diffusivity is equal to or greater than an arbitrary threshold value. The method of claim 14, The arbitrary threshold value is a digital magnetic reproduction recording apparatus characterized by being MSED / 4 of PR series. The method of claim 12, The error correction decoder calculates syndromes for decoding the second error correction of the two series, respectively, and first error correction and decodes the series of which the syndrome is 0, and if the syndromes of both series are all 1, the second error. And the correction-decoded data includes the missing error and gives the missing error information, and performs first error correction decoding using the best sequence and the missing error information. The method of claim 12, The error correction decoder uses the exclusive logical sum of the second error correction decoding results of the two series as the loss error information, and performs the first error correction decoding using the best sequence and the loss error information. Playback device. Output the PR equalization sequence by partial response (PR) equalization of the error correction coded signal reproduced on the magnetic recording medium, Outputting the maximum communicative sequence by performing estimation of the maximum communicative sequence on the PR equalization series; Error correcting and decoding the maximum likelihood sequence, A loss error is detected at the time of estimating the maximum communicative sequence, and the loss error information indicating the detection of the missing error along with the maximum communicable sequence and the position in the detected sequence is output; And error correction decoding is performed using the missing error information during the error correction decoding.