JPH11330985A - Signal decoding method and circuit, information transmission and communication device using the circuit and information storage and reproduction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and effectively improve the decoding reliability by outputting the decoding reliability flag information that indicates a code series area having high possibility of wrong decoding decision processing following a decoding code string if the likelihood difference that is checked in the maximum likelihood decision processing of each decoding code series is smaller than a prescribed standard. SOLUTION: A maximum likelihood sequence decoding circuit 308 inputs a receiving signal series 107 and then generates and outputs a decoding code series z(k) having the maximum likelihood and a decoding reliability flag 123 corresponding to each code position. A decoding code candidate block list generation circuit 309 refers to a substitute code string that is previously set on the basis of the code position indicating the flag 123. Based on this referring result, a decoding code candidate block selection circuit 313 detects a fixed decoding code string 127 out of a set where the circuit 309 substituted the code string set on the string z(k) of a prescribed relative position. As a result, the decoding error code can be effectively corrected after the maximum likelihood sequence is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal decoding method, and more particularly to a signal decoding circuit to which the method is applied, an information transmission communication device using the same, and an information storage / reproduction device.

[0002]

2. Description of the Related Art In a high-speed information communication system or a high-density information recording / reproducing system, a maximum-likelihood sequence detection (MLSD) is used to improve the reliability of data reproduction from a low-quality transmission or recording / reproducing signal. ) Is widely used for data decoding and convolutional coding.

The maximum likelihood sequence detection is a technique for minimizing an error occurrence probability in a decoded code sequence by estimating a decoded code sequence in a time-series manner using the memory property or correlation of the decoded data. , The received signal sequence {Y (n)} (n
(Y is an integer indicating the discrete signal generation order and time) is given to the decoding input, and {Y (n)} is received from all possible transmission information (code) sequences {X (n)} A sequence (maximum likelihood sequence) having the highest likelihood (likelihood) is selected, and this is output as a decoded information (code) sequence {Z (n)}. That is, given the entire sequence of a certain received signal sequence {Y (n)}, the received signal sequence {Y (n)} is received under the condition that a certain transmission sequence {X (n)} is assumed. Posterior prior probability P [{Y (n)} /
{X (n)}] is maximized, transmission sequence {X (n)} is selected, and maximum likelihood sequence estimation of decoded sequence {Z (n)} is performed. At this time, the transmission sequence {X (n)} is not estimated independently of each other, but in the context. Such maximum likelihood sequence detection is performed under the condition that all possible transmission sequences {X (n)} are transmitted with equal probability, in other words, each transmission sequence {X (n)}
Under the condition that no information on the transmission probability of (n)} is given at the time of decoding, the normal decoding probability P [{X (n)} & {Z (n)}] (the transmission sequence {X (n)} The decoding of the best decoding error probability is provided by maximizing the decoding sequence {Z (n)}).

The maximum likelihood sequence detection is performed by a Viterbi algorithm (Viterbi Algo
(rithm), etc., and is efficiently realized. As a paper on maximum likelihood sequence detection and Viterbi algorithm, Day. Forney, “The Viterbi Algorithm”, Procedings of IEE (GDForney, “The Viterbi Algorithm”, Proceedin
gs of the IEEE), Volume 61, Number 3, March 1973, 26
Pages 8-278, and G. Angabok, “Adaptive Maximum Likelihood Receiver for Carrier Modulated Data Transmission
System ”, IEE Transactions on Communications (G. Ungerbock,“ Adap
tive Maximum-Likelihood Receiver for Carrer-Modula
ted Data Transnission Systems ", IEEE Transactions
on Communications), Com-22, Number 5, 1974
May 1984, pages 624-638, and these articles show a receiver using maximum likelihood sequence detection or a basic form of a part thereof. In addition, practical means of realizing the Viterbi algorithm include healing law, “Implementing the Viterbi algorithm”, and IEE
Signal Processing Magazine (Hui-LingLou, "Imp
lementing the Vitrbi Algoithm ", IEEE Signal Proces
sing Magazine), September 1995, pp. 42-52; Fetways and H. Meir, "High-Speed Parallel Viterbi Decoding: Algorithm and VSL Architecture", IEE Communication Signal Magazine (G. Fettweis and H. Meyr, "High-Sp
eed Parallel Viterbi Decoding: Algorithm and VLSI-
architecture ", IEEE Communications Magazine), 19
May 1991, pages 46-55.

[0005] Such a maximum likelihood sequence detection technique rapidly spreads and develops through application to information communication systems and transmission systems, and plays a major role in securing reliability of information transmission and maintaining communication quality. Play. Also, U.S. Pat.
As disclosed in US Pat. The method is a typical known technique.

[0006]

In such maximum likelihood sequence detection, a sequence (maximum likelihood sequence) having the highest probability of being received (likelihood) is selected from the context of a received signal sequence, and this is decoded with the highest likelihood. It is output as an information (code) sequence, and is used as a decoding result. For this reason, in many known techniques, various constraints and storage elements are added to a transmission code string or a transmission channel to increase the correlation of decoded data, and the Euclidean signal between received signal sequences for all transmission code sequences is increased. By increasing the distance (likelihood difference), the margin for identifying the likelihood difference is expanded. However, in such a method, the addition of various constraints on the transmission code sequence and the transmission signal sequence causes a gain due to the expansion of the Euclidean signal distance of the reception signal sequence, while increasing the redundancy in the transmission information sequence. Invite. For this reason, there is a natural limit in improving the information transmission efficiency and ensuring the reliability of the information transmission by this type of method, and transmission channels with strong band restrictions, especially high-speed information communication systems and high-speed -When applied to a high-density information recording / reproducing system, the band loss due to the transmission information sequence redundancy is large, so that it is not always an effective method.
Further, such a method often requires an excessively complicated transmission code processing circuit and an additional circuit, and a decoder based on maximum likelihood sequence detection requires an exponential function to take into account the increased correlation of decoded data. Unavoidable requirements of a typical circuit scale.

[0007]

According to the present invention, there is provided means for efficiently improving the maximum likelihood decoding error rate (decoding reliability) in signal decoding by the maximum likelihood sequence detection technique and realizing this easily. I do. For this reason, the present invention discloses means for effectively correcting the decoding error code after the detection of the maximum likelihood sequence by utilizing the characteristics of the decoding error event in the detection of the maximum likelihood sequence. In the present invention, the likelihood difference in the maximum likelihood determination process for each decoded code sequence is examined in order to identify a code position where the possibility of occurrence of an error event on the decoded code sequence in the maximum likelihood sequence detection is high. When the likelihood difference is small based on a predetermined criterion, there is provided means for outputting, along with the decoded code sequence, decoding reliability flag information for indicating as a code sequence location having a high possibility of error decoding determination processing. . Further, in the present invention, a decoding error in the maximum likelihood sequence detection occurs depending on a Euclidean signal distance between received signal sequences, depends on a pattern of a transmission code sequence, and has a limited specific decoding code error pattern. The error event due to (error syndrome) dominate the best non-decoding error probability, and the occurrence pattern of the decoding error uses the fact that a large deviation occurs in the occurrence probability frequency. For this reason, code replacement (inversion) processing is performed on the position of the possibility of an error event on the decoded code string indicated using the above-mentioned decoding reliability flag information in accordance with a specific decoded code error pattern (error syndrome). Thus, means is provided for generating a decoded code candidate string of the decoded number and selecting a normal decoded code string from the decoded code candidate string of the decoded number and the original maximum likelihood decoded code string. For this reason, an error detection code string for checking the presence or absence of a decoding error event according to the above specific decoding code error pattern (error syndrome) is added to the transmission code string in advance. At this time, the error detection code string is used to detect a random error event due to noise. Is added to In the transmission code sequence, an error detection code sequence is inserted and added in units of a code block having a predetermined code length set from the probability of occurrence of an error event (average occurrence interval). The decoding code candidate sequence is generated by the above-described code replacement (inversion) processing and the normal decoding code sequence is selected by decoding error detection, using the decoding code block corresponding to the unit as a unit. As described above, after eliminating the error detection code string from the code block of the normal decoding code string selected for inspection, by sequentially outputting this as a decoding result, a more reliable decoded code result can be obtained. Provided. As described above, according to the present invention, in the detection of the maximum likelihood sequence, an error event of a decoding code error pattern (error syndrome) that is stochastically biased occurs, and the reliability achieved by the maximum likelihood decoded sequence is relatively good. There is a property that it is extremely rare that random error events that govern the error rate are concentrated at short intervals. Thereby, the error detection code sequence can be configured for the purpose of detecting only an average random error event according to a specific decoding code error pattern (error syndrome). This makes it possible to construct an error detection code string with a certain characteristic. As described above, means for simply and effectively improving the decoding reliability by the maximum likelihood sequence detection is provided.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention are closely related to the use of a maximum likelihood sequence decoder in the reproduction of digital data, and this maximum likelihood sequence decoder is generally widely implemented using a Viterbi algorithm or the like. Is done. First, in order to show an embodiment of the present invention, an outline of a maximum likelihood sequence decoder based on the Viterbi algorithm will be described with reference to FIGS.

FIG. 5 (a) schematically shows the flow of an information sequence in an information transmission system and a recording / reproducing system. In a transmission or recording process, a transmission code sequence {X (k)} 100 (k is a natural number indicating a time on the sequence), which is transmission or recording information, is modulated by a coder 102 after a predetermined constraint condition is added thereto. The signal is converted into an analog or digital signal information sequence that can be transmitted via the channel 104 by the device 103 and output to the channel 104.
The channel 104 is an information transmission medium including a transmission or recording medium, a transducer, a sensor, and the like, and particularly corresponds to a recording / reproduction system including a recording head / information storage medium / reproduction head in an information storage / reproduction device.
Further, an additional noise 105 is added to the signal in the transmission process, and this makes decoding of the received (decoded input) signal sequence {Y (k)} 107 into the original information uncertain in the reception or reproduction process. . In the reception or reproduction process, a signal output from the channel 104 is subjected to predetermined processing by a reception signal processing circuit 106, and then a decoding code is obtained from the obtained reception (decoding input) signal sequence {Y (k)} 107. Series {Z
(k)} is decoded to the maximum likelihood sequence decoder 108.
Done through. In this maximum likelihood sequence decoder 108,
Transmission code sequence {X (k)} 10 which is the original transmission or recording information
0, for which the most likely decoded code sequence
{Z (k)} 109 is estimated.

For the maximum likelihood sequence decoder 108, there are various storage elements in the information transmission system 101, which is a pre-processing step from the encoder 102 to the reception signal processing circuit 106. For example, the encoder 102 performs decoding error detection / correction using a convolutional code, a trellis code, or the like, or in order to apply some constraint conditions necessary in a transmission process such as a run-length restriction to a transmission code, Redundancy may be intentionally added to the transmission code sequence {X (k)} 100 by a convolution process or a mapping process of input / output codes of the encoder 102 sequentially stored in a finite number of storage elements. In the transmission process from the modulator 103 to the reception signal processing circuit 106, there may be a storage element on the channel due to natural or intentional addition of intersymbol interference or the like. When such a storage element is present in each process of the information transmission system 101, each value of the received signal sequence {Y (k)} 107 becomes the value of the corresponding transmission code sequence {X (k)} 100 Not the one-to-one correspondence with
It is determined in correspondence with the state in the storage element depending on the history of {X (k)} 100. Maximum likelihood sequence decoder 108
Then, by estimating the transition of the internal state held by the storage element on the information transmission system 101 and utilizing the storage property (redundancy) of the transmission system, the reliability and quality of the decoding process for noise can be improved. For the transmission code sequence {X (k)} 100, a more accurate decoded code sequence {Z (k)} 109 can be provided on the receiving / reproducing side.

FIG. 5C shows the received signal sequence {Y (k)} 107, transmission code sequence {X (k)} 100, and information transmission system 101 in the transmission channel model shown in FIG. 3 is an example of a Markov state transition diagram model showing a correspondence relationship with states in a storage element. In this example of the state transition diagram, the information transmission system 101 has three 1-bit delay storage elements 110a to 110c (D1, D2, and D) as shown in FIG.
Assume that the model can be equivalently represented by the model according to 3). Then, each time k of the received signal sequence {Y (k)} 107
Are the one-bit delay storage elements 110a-110
The history of the code bits at three times immediately before the transmission code sequence {X (k)} held in 110c and the addition / subtraction operation elements 111a to 111
1c, it is determined by the relationship of the following linear convolution operation.

Y (k) = X (k) + X (k-1) -X (k-2) -X (k-3) The transmission code sequence {X (k)} 100 has a binary code ( X (k) = + 1 or -1), and the information transmission system 101 can take a total of eight states depending on the combination of the contents of the 3-bit delay storage element. The information transmission system 101 modeled in this way is called a class 4 extended partial response (EPR4) channel, and is often used in an information transmission channel of a magnetic recording / reproducing system. This is disclosed in detail in US Patent No. 203413. Also, with respect to the expression of the above-mentioned convolution operation characteristic possessed by the class 4 extended partial response channel, the partial response characteristic polynomial G (D) = 1 + DD ² -D ³ = (1-D) (1+
D) ² (D ^k indicates a k-bit delay operator) is used, but in a magnetic recording / reproducing system that realizes high-density recording, the characteristic polynomial G (D) = (1- D) (1 + D) ⁿ
A partial response channel characterized by (where n is an appropriate natural number) is actively applied.

In order for the maximum likelihood sequence decoder 108 to perform maximum likelihood sequence estimation using the storage property (redundancy) of the above-mentioned information transmission system 101, the storage inside the storage element on the information transmission system 101 is performed. It is necessary to define and describe the transition of the state. The state transition diagram of FIG. 5C shows that each time one bit of the transmission code sequence {X (k)} is transmitted, each storage element of the class 4 extended partial response channel information transmission system 101 shown in FIG. Are changed in the holding state, and what kind of received signal sequence {Y (k)} 107 is
It is received as the expected signal value {E (k)} or represents the transition process in all cases. 8 in this figure
One state Sj (j = 0, 1, 2,..., 7) and one-bit delay storage elements D1, D2, and D3 on the information transmission system 101 (1 in FIG. 5B)
10a-c), the binary transmission code {X (k)} (X (k)
= + 1 or -1) is shown in the correspondence table in FIG. 5C. Arbitrary transmission code sequence {X (k)} 10
When 0 is given, the transmission code sequence and the expected value sequence of the received signal indicate {X (k)} and {X (k)} indicated by the unique transition path sequence on the state transition diagram.
It is represented by {E (k)}.

FIG. 5 (d) shows a trellis (lattice) diagram obtained by expanding the state transition diagram of FIG. 5 (c) in the horizontal and time axes in order to express the time transition of this state transition path sequence. It is an expression. The transition state corresponding to each time k is denoted by Sj (k) (ie, S0 (k), S1 (k), S2 (k),..., S7 (k)). The state of the code holding in the storage elements D1, D2, D3 determined by the input of the code X (k) is shown. Further, at each time k, the state S (k−1) is changed to the state Sj.
Each branch arrow (branch) indicating the transition to (k) has a transmission code X for causing a state transition from the state Si to the state Sj.
(i, j) (in other words, the decoded code when this transition is determined) and when this transition occurs, the expected value E (i, j) of the received signal output from the transmission channel is X (i, j). ) / E (i, j)
In the form (In the time-invariant information transmission system 101, the state transition structure is temporally constant and does not change with time k. Therefore, X (i, j) and E (i, j) also change with time k. However, it is a constant value that depends only on the state Si and the state Sj.
Can be easily general. From this figure, the correspondence between the transmission code {X (k)} at each time k, the state transition path and the expected value of the received signal {E (k)} can be clearly expressed. For example, as shown in the example of FIG. 5 (f), time k to (k + 4)
5 state transition paths (branches) 1 connected in
The path sequence 112 represented by 12a is a 5-bit transmission code sequence {+ 1, + 1, -1, + 1, -1} and the information transmission system 101 channel state transition S0 (k-1) → S1 (k ) → S3 (k + 1) → S6 (k + 2) → S5
(k + 3) → S2 (k + 4), and the expected value of the received signal sequence output from the channel at this time is ｛+ 2, +
4,0, -2,0}.

In consideration of the state transition of the information transmission system 101, the maximum likelihood sequence estimation in the maximum likelihood sequence decoder 108 includes the reception signal sequence {Y (n)} on which the actually observed noise is superimposed. The amount of error from the expected value {E (n)} of each path on the state transition diagram is evaluated, and the received signal
{Y (n)} uniquely determines the transition of the state transition path that minimizes the total error, and sets the transmission code sequence {X (n)} for this determined path as the decoded sequence {Z (n)}. Output.
This is nothing but estimation of a signal (code) sequence using a pattern matching method based on the principle of the so-called least square method. The Viterbi algorithm is a means for efficiently realizing pattern matching on a continuous time-series signal in real time within a finite hardware resource (a storage element for storing time-series signal information) and a finite processing delay time. I will provide a.

Next, means for specifically implementing maximum likelihood sequence decoding (maximum likelihood decoding or Viterbi decoding) by the Viterbi algorithm will be described. Here, as an example of the target information transmission system 101, the EPR4 channel shown in FIG. 5B is assumed, and the state transition diagram and the diagram of the EPR4 transmission channel by the binary transmission code sequence in FIG. The outline and basic configuration of the Viterbi decoding process will be described with reference to the trellis diagram of FIG. In the following specification,
The embodiment will be described based on the above-described example of the EPR4 transmission channel using the binary transmission code string. The Viterbi algorithm applies a probabilistic method to every event described by a state transition model as shown in FIG. Estimate the maximum likelihood event transition with the highest likelihood, that is, it can be applied to any problem that results in the maximum likelihood transition sequence estimation. Further, the following description of the embodiments does not depend on the specific properties or restrictions of the EPR4 transmission channel, but includes information described in various state transition diagrams having storage elements in various forms described above. The present invention discloses a general embodiment that can be extended to a target channel or model in a similar manner without any restrictions on a transmission system channel or model and can be easily applied.

Here, attention is first focused on FIG. 5 (d) which defines the state transition process at one time k on the trellis diagram for the EPR4 channel. Viterbi decoding, in accordance with the definition of the state transition by this specific trellis diagram, corresponds to each input (received decoding input) signal value Y (k) at time k corresponding to this and each state transition path branch (arrow). By evaluating the error from the received signal expected value {E (i, j)}, the path branches that transition to each of the states S0 (k) to S7 (k) at each time are narrowed down one by one. Is repeated. Therefore, each state S0 (k-1) to S7 (k-1) selected by repeating the same processing until the previous time (k-1)
Are stored as surviving path sequences P0 (k-1) to P7 (k-1), one for each state. Also, for each of the surviving path sequences P0 (k-1) to P7 (k-1) that reach the respective states S0 (k-1) to S7 (k-1), the reception indicated on each path sequence is performed. Signal expected value series ｛E
(K) Cumulative errors (path metrics) M0 (k-1) to M7 (k-1) between｝ and the actual received signal sequence {Y (k)} are evaluated, and the surviving path sequence is evaluated. It is simultaneously stored as a metric (likelihood) indicating the likelihood of each. The surviving path sequences P0 (k-1) to P7 (k-1) and the path metric M0 (k-1) for each state S0 (k-1) to S7 (k-1) up to this time (k-1) ~ M7 (k-
The contents of 1) are updated to new surviving path sequences P0 (k) to P7 (k) and path metrics M0 (k) to M7 (k) by the processing described below at the next time k. This is repeated as a recursive process for each time.

As shown in FIG. 5E, focusing on each state on the trellis diagram, the state Sn (k) at time k
As the transition process to (n = 0,1, ～, 7), state Si (k-1) and state
If there is a possibility of transition from any one of Sj (k-1) (i, j = 0, 1, to 7,), the specific processing procedure is summarized as follows.

(1) For the received signal value Y (k) input at time k, the expected value of the received signal corresponding to each transition path from state Si (k-1) and state Sj (k-1) Using E (i, n) and E (j, n), square error values (branch metrics) BM (i, n) (k) and BM (j, n) (k ) Is calculated as follows.

Transition branch metric from state Si (k-1) to Sn (k): BM (i, n) (k) = [Y (k) -E (i, n)] ^ 2 state Sj (k Transition metric from -1) to Sn (k): BM (j, n) (k) = [Y (k) -E (j, n)] ^ 2 The metric due to the square error is the received signal sequence {Y It is known that an optimal likelihood metric for maximum likelihood sequence estimation when a noise sequence superimposed on (k)} is independent white Gaussian noise is given. Another error evaluation value such as an absolute value error can be used depending on the decoding implementation conditions.

(2) From each of the states Si (k-1) and Sj (k-1),
Cumulative errors (path metrics) PM (i, n) (k) and PM (j, n) for likelihood comparison for the path sequence transitioning to state Sn (k)
(k) is calculated. Therefore, the surviving paths Pi (k-1) and Pj (k-1) to the states Si (k-1) and Sj (k-1) evaluated by the processing up to the previous time (k-1) For each of the corresponding path sequence accumulated errors (path metrics) Mi (k-1) and Mj (k-1),
State transition branch metric BM calculated in (1)
(i, n) (k) and BM (j, n) (k) are respectively newly added to perform the following addition operation.

Path metric from state Si (k-1) to Sn (k): PM (i, n) (k) = Mi (k-1) + BM (i, n) (k) State Sj (k -1) to the path metric from Sn (k): PM (j, n) (k) = Mj (k-1) + BM (j, n) (k) Further, the path metric PM for these two path transitions
The values of (i, n) (k) and PM (j, n) (k) are compared in magnitude and a likelihood comparison is performed. The path metric, which is the accumulated error of each path sequence, causes the smaller transition path to reach state Sn (k) at time k.
The path sequence is selected as a more reliable and highly likely path sequence, and the other is rejected. Further, the compared path metric PM (i, n) (k)
And PM (j, n) (k), using the path metric value on the selected path side, Mn (k) as a new path metric value of the surviving path sequence that transits to state Sn (k). Update the contents of

The surviving path metric leading to state Sn (k): Mn (k) = Min [PM (i, n) (k), PM (j, n) (k)] Calculation to Select (3) Update the surviving path sequence history Pn (k) for state Sn (k) at time k. In Pn (k), connection information of (D + 1) transition states on the surviving path that goes back from the current time k to the finite time D earlier is stored in time order. For example, Pn (k) =
Processing up to time k by referring to the stored contents {Sn (k), Si (k-1), Sj (k-2), ~, Sl (k-D + 1), Sm (kD)} The state transition on the surviving path sequence leading to the state Sn (k), selected in, is Sm (kD) → Sl (k−D + 1) → Sj (k−2) → Si (k−1) →
It is shown that they are connected and change in the order of Sn (k). According to (2), whether the surviving transition path to the state Sn (k) at the time k is a transition path from Si (k-1) or a transition path from Sj (k-1) Is selected and confirmed, a new surviving path sequence history Pn (k) to the state Sn (k) determined by the selection processing is the state Si (k-1) up to the previous time (k-1). Of the surviving path sequence histories Pi (k-1) and Pj (k-1) for Sj (k-1), the surviving path sequence history of the selected path side state is updated as follows. .

History of surviving path sequence leading to state Sn (k): Pn (k) = {Sn (k), Pi (k−1)} (when selecting a transition path from Si (k−1)) = { Sn (k), Pj (k-1)} (when a transition path is selected from Sj (k-1))
Select (k-1) or Pj (k-1), and move this temporal storage location to the past one time at a time,
After extracting the ((D + 2) th element) as a result of Viterbi decoding, the result of adding a new transition state Sn (k) to the storage location of the latest time is transcribed as the storage content of Pn (k). Means operation. In the prior art, this is generally configured by a storage circuit such as a shift register that sequentially shifts the storage content at each time (shift register exchange method), and a configuration method using various storage circuits is disclosed. Have been. Further, in many cases, instead of storing the information (state number) of the selected transition state itself, the transmission code for the path branch to the selected transition state is stored as the contents of the path sequence history Pk (n). Is stored. For example, when the transition path from the state Si (k-1) is selected as the surviving path for the state Sn (k) at the time k, the recorded contents in the surviving path history for this state are the states Si (k The value of the transmission code X (i, n) corresponding to the path branch from -1) to Sn (k) can be used. Thereby, when the stored path history information is referred to, the transmission code sequence {X (n)} indicated by the surviving path can be immediately obtained as a decoded code result.

In the description of the update processing of the surviving path sequence history information in (3) above, the storage information for the time k in the surviving path sequence history Pn (k) reaching the state Sn (k) (the path history for the latest time). Information) is constant in the state Sn (k) regardless of the state of the path selection from the time k-1. Therefore, in practice, the path information itself does not need to be physically stored, and only the surviving path sequence history information before time k-1 connected to this state Sn (k) is physically stored in the storage circuit. It only has to be recorded. Path history storage information Sn for time k
(k) can be represented by the fact (storage location information) that this path history information is stored as the surviving path sequence history Pn (k) leading to the state Sn (k), and in the process at the next time k + 1 When referring to the storage contents of the surviving path sequence history Pn (k), the path history storage information Sn for this time k
What is necessary is just to supplement and refer to (k).

As described above, the same applies to the case where the value of the transmission code X (i, n) corresponding to the selected path branch is stored as the content recorded in the surviving path history. In the surviving path sequence history Pn (k), state S
History information from time k fixed by being a path transition to n (k) to a time before a predetermined time (history of a 3-bit transmission code from time k to time k-2 in the case of an EPR4 channel) is This is omitted by indicating by the storage position information itself that it is stored as the surviving path sequence history Pn (k), and this information is supplemented at the time of reference, so that the hardware amount of the storage device can be saved.

A series of Viterbi decoding processes (1), (2), and (3) are performed every time the received signal value Y (k) at each time is input.
It is processed repeatedly. The specific components for implementing this are shown in FIG.

The calculation of the branch metrics BM (i, n) (k) and BM (j, n) (k) in (1) is performed by the square error calculation circuit 201. The path metrics Mi (k-1) and Mj (k-1) of the surviving paths for the states Si (k-1) and Sj (k-1) are held in the metric storage circuits 202a and 202b, The circuit 203 calculates the path metrics PM (i, n) (k) and PM (j, n) (k) in (2), and the comparator 204 performs a comparison operation on these path metric values. The comparison result is output to the selection signal 205 and the metric selection circuit 20
6, according to the selection signal 205, the path metric PM
(i, n) (k) or PM (j, n) (k) is selected, and using this, a metric storage circuit that holds the surviving path metric Mn (k) to the state Sn (k) The content of 202c is updated and stored. On the other hand, the surviving path histories Pi (k-1) and Pj (k-1) reaching the states Si (k-1) and Sj (k-1) are stored in the path history storage circuit 20.
7a and 207b, the state in (3)
The process of updating the surviving path history Pn (k) to Sn (k)
Path history storage circuit 20 specified by selection signal 205
Either 7a or 207b is selected and referred to by the path history selection circuit 208, the storage position of this content is shifted by one time, and a new content is stored as the content of the path history storage circuit 207c holding Pn (k). And store the updated information. At this time, surviving path history information selected from the last storage position of the path history storage circuit 207a or 207b is output as a decoding result (decoded code sequence Z (k) 109).

In the actual Viterbi decoding, the above processes (1) to (3) for the received signal Y (k) at each time are performed for all states of the trellis diagram for which the maximum likelihood sequence is to be estimated. Each needs to be done independently. Therefore, in the actual configuration of the Viterbi decoder, the state shown in FIG.
Implementing components of the processing for Sn (k) are provided in parallel for the number of states in the same configuration. For example, for the trellis diagram of FIG. 5D, as shown in the configuration of the maximum likelihood decoder based on the Viterbi algorithm of FIG.
The implementation components of FIG. 6A assigned to each of S0 (k) to S7 (k) are provided in a total of eight series in parallel. At this time, metric storage circuits 202a to 202h for storing surviving path metrics M0 (k) to M7 (k), and path history storage circuits 207a to 207h for storing surviving path sequence histories P0 (k) to P7 (k). Is assigned to each of the states S0 (k) to S7 (k), and these reference destinations are connected to a plurality of locations according to the next stage connection state on the trellis diagram of each state. . For example, state Si (k) and state Sj (k + 1)
If there is a path connection relationship of the trellis diagram between (i, j = 0, 1, to 7), one of the reference destinations of the metric storage circuit 202 assigned to the state Si (k) is Of the metric accumulators 203 assigned to the state Sj (k), the other input that adds to the branch metric BM (i, j) (k) is used as the other input, and the path assigned to the state Si (k) One of the reference destinations of the history storage circuit 207 is an input of the path history selection circuit 208 assigned to the state Sj (k).

Also, the value of the expected value E (i, j) of the received signal on the actual trellis diagram is often common to several path branches. The error calculation circuit 201 is also commonly used, and a configuration in which the error calculation circuit 201 is input to the corresponding metric accumulators 203 is often used in practice. As described above, FIG.
The Viterbi decoder configuration, as summarized in
A branch metric operation unit (BMU) 200a that inputs Y (k) and performs (1) processing, and (2) executes processing using this branch metric output to select a surviving path to each state. Selection unit (ACS operation unit)
Further, in response to the selection output, the surviving path history by the process (3) is stored and updated, and the result is roughly classified into a path memory unit (PMU) 200c for narrowing down and determining the decoding result. The above is an implementation method and a configuration method of the maximum likelihood sequence decoding process using the Viterbi algorithm.

Next, in order to clarify the principle of the embodiment of the present invention, FIG. 12 shows an example of a state transition on a trellis diagram on the EPR4 channel in FIG. 5 (d). A process from selection of a surviving path to determination of a decoding result in a conventional Viterbi decoding process will be described. By the above-described conventional Viterbi decoding implementation method and configuration method, a state transition path (each time / state) on the trellis diagram using the received (decoded input) signal sequence {Y (k)} 107 at each time. The path branches 112a are always selected one by one. In this way, by repeatedly selecting the surviving path sequence 113, the path sequences surviving at each time are further narrowed down.

For example, surviving path sequence 1 in FIG.
As shown in the history of FIG. 13, the eight surviving path sequences to each state selected at time k at time k are gradually rejected by the subsequent path selection, and finally at time (k + 10)
At the end of the selection process in, the surviving path sequence (thick line arrow sequence) that is connected converges to one, and at this time, the time (k
-1) to (k + 8) are determined as the determined maximum likelihood path sequence 114 from the converged surviving path sequence.
Is the only state transition path (path branch) 112 b that survives on the deterministic maximum likelihood path sequence 114.
Is determined by referring to the transmission code X (i, j) assigned to The operation of narrowing down the surviving path sequence (path rejection) is performed by moving the contents of the selected path history Pj (k-1) or Pj (k-1) one time in the past in the above-described decoding processing (3). However, it is nothing more than an operation of transcription as a new Pk (n) storage content.

In FIG. 11B, if the path history storage circuits 207a to 207h for storing the surviving path sequence histories P0 (k) to P7 (k) have a sufficient storage length,
By repeatedly selecting and transcribing this path history storage circuit, the contents of the storage locations at the end of each of the storage circuits 207a to 207h (the path branch selection history at the earliest time) converge and match the same storage contents. , Can be used as a decoding result with reference to any of the contents. As described above, the operation of determining the maximum likelihood path in the maximum likelihood sequence decoding is performed by repeating the rejection / selection of the surviving path candidates that reach each state on the determined maximum likelihood path sequence 114 at each time. The final maximum likelihood path sequence 114 that finally converges and is obtained as a decoding result has a higher likelihood in the state transition path selection at all times on this path sequence, and remains only without being rejected. It is a surviving path sequence.

An object of the present invention is to improve a decoding error event in the conventional maximum likelihood sequence decoding process described above and provide a decoding process method having higher reliability. The example of the second trellis transition diagram of FIG. 8A shows an example of the surviving path sequence 113 in the binary code transmission sequence EPR4 transmission path channel, as in FIG. This is for explaining the relationship between the decoding error path sequence and the normal path sequence caused by the uncertainty of. In this figure, the state transition sequence S6 (k
-1) → S5 (k) → S3 (k + 1) → S6 (k + 2) → S4 (k + 3) → S0 (k + 4) → S0
For the normal path sequence 115 represented by the path transition of (k + 5) → S1 (k + 6) → S3 (k + 7), a decoding error event (decoding error sequence)
Is determined by the state transition sequence S6 (k−
1) → S5 (k) → S3 (k + 1) → S6 (k + 2) → S5 (k + 3) → S2 (k + 4) → S4
When the decoding error event (decoding error sequence) is determined by the path transition of (k + 5) → S1 (k + 6) → S3 (k + 7), the time (k +6) flows into state S1 (k + 6) 2
This is caused by the occurrence of the error path selection 117 for one surviving path branch candidate.

That is, the time (k + 2) on the normal path sequence 117
Erroneous comparison selection between two surviving path branch candidates that branch off from state S6 (k + 2) at time (k + 6) and flow into state S1 (k + 6) at time (k + 6). Partial path sequence S6 (k + 2) → S4 (k + 3) → S0 (k + 4) → S0 (k + 5) → S1 on the normal path sequence 115 which is one of the branch candidates
(k + 6) (thick dotted arrow path sequence) is the other path sequence of the surviving path branch candidate S6 (k + 2) → S5 (k + 3) → S2 (k + 4)
→ S4 (k + 5) → S1 (k + 6), and a decoding error has occurred as a code sequence error. As processing in the decoding circuit, state S1 (k + 6) at time (k + 6)
In the above-described decoding process (2) for (6), the size determination of the surviving path metrics PM (0,1) (k + 6) and PM (4,1) (k + 6): M1 (k) = Min [PM (0,1) (k + 6), PM (4,1) (k + 6)], PM (4,1) instead of PM (0,1) (k + 6)
(k + 6) is selected. As a result, the state transition S0 (k + 5) → S1
Instead of the surviving path sequence on the (k + 6) side, state transition S4 (k + 6
5) → The surviving path sequence on the side of S1 (k + 6) is selected and determined,
In the decoding process (3) for updating and storing the surviving path sequence history, a path history replacement process of P1 (k + 6) = {S1 (k + 6), P4 (k + 5)} is executed, whereby An error occurs. As a result, the time (k + 5) state S0 (k + 5)
The contents of the surviving path sequence history P0 (k + 5) having the normal path sequence 115 are discarded, and the contents of the surviving path sequence history P4 (k + 5) having the error path sequence 116 are selected as the surviving path sequences. Remain in the updated path history storage circuit. In a noise situation, the selection error of the surviving path branch candidate does not occur with a uniform probability frequency in each state on the deterministic maximum likelihood path sequence 114, but the two surviving path sequences flowing into each state. As the cumulative sum of the differences between the expected values of the received signals of the candidates (the distance between signal sequences or the path metric difference) is smaller, the possibility and frequency of an error in the comparison operation processing in the maximum likelihood decoding processing (2) are increased. That is, in the comparison / selection of the path metric likelihood between two surviving path sequences, the smaller the expected value of the discrimination difference (likelihood difference) between the path metrics and the narrower the discrimination margin of the comparison judgment with respect to noise, the smaller the above randomness becomes. A decoding error event due to noise is more likely to occur.

The expected values of the received signal sequence of the normal path sequence 115 and the error path sequence 116 in FIG.
At each 4-bit time from 3) to time (k * 6),
4, -2,0, + 2} and {-2,0, -2,0}, the cumulative difference of their squared errors (distance between signal sequences) is
It becomes 16. The cumulative sum 16 of the square errors is equal to the minimum cumulative square error (minimum square Euclidean distance, minimum free distance) guaranteed between all the received signal sequences on the binary code transmission sequence EPR4 channel. In addition, the fact that the decoding reliability (decoding error rate) of the transmission channel under noise is mainly determined by an error event between transmission code sequences having such a least square Euclidean distance is determined by the transmission / transmission error. This is a well-known fact in communication theory.

In the example of FIG. 8A, due to the error in the comparison and selection of the path metric likelihood in the state S1 (k + 6), the time (k + 3) in the surviving path history P1 (k + 6) is changed. (k
The contents of 4 bits up to +6) are replaced with the contents of the error path sequence 116. From the occurrence process of the error event in such maximum likelihood decoding, the possibility that the above likelihood comparison error event and the path selection error event have occurred in the transition state at each time of the determined maximum likelihood path sequence 114 is considered. Estimate high points, and
If the content of the error replacement in the surviving path history storage circuit due to the path selection error event can be estimated, a decoded code sequence having the next best decoding reliability with respect to the determined maximum likelihood path sequence 114 can be obtained. Furthermore, if this is compared with the definite maximum likelihood path sequence 114 using another code error determination means, the validity as a transmission code sequence is checked, and it is selectively used as the final decoded code sequence. In addition, it is possible to efficiently increase the reliability of the decoded code. Therefore, a necessary component of the present invention is a process for estimating a location where a selection error event has occurred, and (b) a surviving path history
(A) estimating the contents of the error path sequence replaced by the error event ((a) likelihood comparison and path code error pattern on the determined maximum likelihood path sequence 114);
(C) the position information of the error event obtained in (a), and (b)
(D) using the code error pattern information obtained by the above and information on the maximum likelihood decoding sequence corresponding to the determined maximum likelihood path sequence 114,
From the decoded code sequence candidates of the inverse number generated in (c),
It consists of four processing steps of checking a valid transmission code sequence and selectively outputting it as a final decoded code sequence. The principle and outline of each step will be described below.

Method of implementing the process (a): In the surviving path selection at each time on the determined maximum likelihood path sequence 114, the likelihood comparison and the possibility of occurrence of an error event in the path selection are determined by comparing the path metric likelihood to be compared. The determination can be made based on the magnitude (absolute value) of the difference.

Under practical noise conditions, the surviving path metric leading to state Sn (k): Mn (k) = Min [PM (i, n) (k), PM (j, n) (k)] In the selection, the absolute value of the difference between each surviving path metric likelihood is represented by the path selection reliability information in the state Sn (k): Rn (k) = ABS [PM (i, n) (k) -PM (j, n) (k)] and ABS [•] can be used as operations that take absolute values. This is because, when the magnitude relation in the comparison operation of the path metric likelihood is reversed due to noise, the difference in the path metric likelihood is generally ambiguous and small, and the magnitude relation is reversed, and The probability that the path metric likelihood difference becomes a larger value is based on the fact that the probability becomes extremely small as compared with the probability of the above-described comparison operation error. Thereby, the magnitude of the path selection reliability information Rn (k) is evaluated as a low probability of path selection in each state Sn (k), that is, a high path selection reliability. Can be. In each state, when selection is performed from three or more path metrics that flow in, the absolute value of the path metric likelihood difference is evaluated for each two paths, and the selection error between the two surviving paths is determined. The possibility is determined. For each state Sn (k) on the determined maximum likelihood path sequence 114, this path selection reliability information Rn (k) is evaluated, and this is a corresponding part of a state that is equal to or less than a certain reference value, or It is possible to estimate a portion having a minimum value or a value within a predetermined number from the smaller one in a finite length sequence section as a portion where a path selection error event is likely to occur. Can be made. The method of judging the presence / absence of an error event (position of the error event) from the evaluation value of the path selection reliability information Rn (k) depends on the average occurrence probability of the error event from the above various methods. Used selectively.

Method of implementing processes (b) and (c): The content of the error path sequence replaced in the surviving path history due to the path selection error, that is, the error code pattern sequence (error syndrome) is as described above. The path sequence selection error in the maximum likelihood sequence decoding can be easily estimated using the fact that it occurs with an occurrence probability depending on the Euclidean distance between the received signal sequence of the normal path sequence and the error path sequence. That is, by the modulation process and the intentional coding process,
If the distance structure between the received signal sequences is defined in advance by the constraint conditions added to the transmission code sequence and the target trellis transition diagram of the maximum likelihood sequence decoding process, it is often limited to have the least square Euclidean distance. By paying attention to the pair of signal sequences, it is possible to restrict and predict in advance an error code pattern sequence (error syndrome) frequently occurring due to a selection error between the sequences.
Then, by sequentially improving the error events from the events of the error code pattern sequence (error syndrome) having a high frequency of occurrence, the next best decoding error rate (reliability) can be obtained.

For example, the surviving path sequence 1 shown in FIG.
13, the normal path sequence 115 and the error path sequence 11
6 is the path sequence and the received (decoded input) signal sequence 10
7, different sequences are taken between the 4-bit times from time (k + 3) to time (k + 6). As mentioned earlier, the two sequence pairs are
A sequence pair having the least square Euclidean distance on the trellis transition diagram, and an error event between the sequences is one of a most frequent decoding error event and a most frequently occurring decoding error code pattern sequence (error syndrome). It is. That is, on the transmission code sequence or the decoding code sequence 109, these normal path sequence 115 and error path sequence 11
6 has code sequences that are inverted and different only by one bit at time (k + 3), and defines a difference sequence between the two code sequences as a decoded error pattern sequence 118 to define an error event, that is, an error code pattern. When a sequence (error syndrome) is described, it can be represented as a 1-bit code error pattern 119a. (Here, the decoding error pattern sequence 11
In 8, 0 is no code error, +1 is code "1", "0"
-1 indicates a bit position where a code "0" is erroneously changed to "1". That is, on the binary code sequence, only the non-zero position on the decoded error pattern sequence has the meaning of the error occurrence position and is a pointer indicating the code position of the inverted bit error. On the surviving path sequence 113, at the same time, after branching into two paths indicating different transmission (decoding) codes, the same path is passed through different 3-bit length path sequences indicating the same transmission (decoding) code sequence, and the same. Merges with the state S1 (k + 6). This is obvious from the definition of the trellis diagram in which the channel state is determined by the past 3-bit code history, and this is one form of the path sequence pair having the least square Euclidean distance.

As described above, the EPR using the binary transmission code
In the four transmission channels, the replacement of the error path sequence having a length of 4 bits occurs at a high frequency from any trellis diagram state, and the bit time of the occurrence of the path selection error event determined by the process (a) (FIG. In the example of the error path sequence of FIG. 8A, the decoding position relatively 3 bits before (based on the error path selection detection position 119 at the time (k + 6)) (in the example of the error path sequence of FIG. , The error event of the error syndrome in which the normal code at time (k + 3) causes a 1-bit inversion error, that is, the decoded error code pattern (1-bit code error pattern sequence 119a) Can be predicted in advance. In this way, if a frequently occurring error code pattern sequence (error syndrome) is determined in advance from the target trellis transition diagram,
In accordance with this, the code on the maximum likelihood decoded sequence at a relatively fixed position is inverted and replaced based on the path selection error position determined in (a), whereby a decoded sequence with the next highest reliability is obtained. Obtainable.

FIG. 8B shows another example of the relationship between the normal path sequence 115 and the error path sequence 116 in detecting the maximum likelihood sequence on the EPR4 transmission channel using the same binary transmission code as that shown in FIG. 8A. This is a specific example. The occurrence of the error path sequence 116 in this specific example is due to the occurrence of the error path selection 117 in the surviving path selection processing for the state S3 (k + 5) at the time (k + 5) on the determined maximum likelihood path sequence 114. And from time k to time (k + 5)
This occurs as a bit length sequence error. The normal path sequence 115 and the error path sequence 116 on the received (decoded input) signal sequence 107 take the least square Euclidean distance 16,
Similar to the error event in FIG. 8A, it can be regarded as one of the error events occurring at a high frequency of occurrence. When the relationship between the normal path sequence 115 and the error path sequence 116 is compared on the decoded code sequence 109, the decoded error pattern sequence 11
8 is the time (k +
8) based on the error path selection detection position 119 in FIG.
(A) Similarly, decoding of an error syndrome in which a normal code at a continuous 3-bit code position (time k to (k + 2)) up to a decoding position at time (k + 2) relatively 3 bits earlier causes an inversion error. It can be regarded as an error event, and such a 3-bit code error pattern 119b can be predicted in advance as a frequent decoding error event of the channel.

The decoding error event of the 1-bit code error pattern 119a shown in FIG. 8A occurs from any state on the target trellis transition diagram and does not depend on the transmission code sequence. This is one of the decoding error pattern sequences having a high stochastic occurrence frequency determined only by the structure. On the other hand, in an EPR4 transmission channel using a binary transmission code,
There is a signal sequence pair that has a least square Euclidean distance depending on a specific transmission code sequence. FIG. 8B shows a 3-bit code error pattern 119b as this example. In such a code error pattern, a transmission code sequence of "... 01010 ..." or "... 10101 ..." in which code bits on the transmission code sequence are alternately continuously inverted by 3 bits or more is transmitted through the transmission channel. Is the case. When either one of these two transmission (reception) code sequences is transmitted, in the code string portion where the transmission code bits are alternately inverted, successive bits from the last bit position to n (n is an integer of 2 or more) bits A decoding error pattern in which all code bits are inverted may occur at a high frequency.

[0045] For example, the transmission code sequence "... 0 010 000
.. "Is transmitted, the 3-bit code string portion of" 010 "matches the above code pattern, and" ... 0 101 000... "In which each bit of this code string is inverted takes the minimum Euclidean distance. That is, the decoded error pattern sequence 118 is “... 0 −1 +1 −1 0 0 0 0”.
.. ", And becomes an error syndrome error pattern sequence (3-bit code error pattern 119b) that causes a 3-bit continuous inversion error. In addition, the transmission code sequence" ... 0 010 "
When “ 10 000...” Is transmitted, 5 of “01010” is transmitted.
The bit code string portion matches the above code pattern, and the last 3 bits (when n = 2) and 4 bits (n
= When 3), obtained by inverting the respective bits of 5 bits (when n = 4) "... 001 101 000 ...", "... 00 01
01 000 ... "," ... 0 10101 000 ... three series "is a signal sequence pair takes the minimum Euclidean distance.
That is, the decoding error pattern sequence is “… 000 −1 +1 +1 ”.
-1 000 ... "," ... 00 +1 -1 +1 -1 000 ... ","
.., 0 -1 +1 -1 +1 -1000... ", And becomes a code error pattern (3-5 bit code error pattern sequence) of an error syndrome causing a 3-5 bit continuous inversion error.
As described above, when the transmitted transmission code string has a continuous code inversion pattern, an error pattern event in which the subsequence becomes a continuous inversion bit error is also equivalent to the 1-bit code error pattern 119a from the relation of the minimum Euclidean distance. A decoded code error pattern sequence (error syndrome) having a high probability of occurrence occurs.

Accordingly, the decoding position (k-3) three bits before the bit time k of the occurrence of the path selection error event determined by the processing (a) is i bits before (the integer i
If the decoded code sequence 109 up to time (ki-3) of> 1) corresponds to the above-described pattern in which the sequence is alternately and continuously inverted, three consecutive bits from time (k-5) to (k-3) , Or 4 consecutive bits from time (k-6) to (k-3) or time (ki-
3) to (k-3), each of the code strings in which the code bit positions of the consecutive (i + 1) bits have been inverted can obtain a decoded sequence candidate with suboptimal reliability. Thus, (a)
With reference to the error path selection position (error path selection detection position 119) determined in the above, the code on the maximum likelihood decoded sequence at a relatively fixed position is referred to, and based on this, the predetermined length is selectively determined. By performing the inversion and replacement process on the code string portion according to the predetermined error syndrome, it is possible to obtain a decoded sequence having the next highest reliability. In this case, in order to simplify the processing, the code string portion on the decoded code sequence 109 at a relatively fixed position based on the error path selection detection position 119 is referred to without reference to the decoded code sequence 109. By performing the inversion permutation process according to the error syndrome, a decoded sequence candidate with suboptimal reliability may be generated. Further, from 3 bits to a predetermined number of consecutive bits (a number of bits equal to or less than a predetermined number that can be determined by the constraint condition of the transmission code sequence)
According to all code error patterns (error syndromes),
In addition to obtaining the decoded code sequence of the next best likelihood by performing the inversion and replacement processing, there may be a case where a code error pattern (error syndrome) of a specific bit length / pattern is limited or selected.

Further, as described above, when there is a possibility that the inversion / replacement processing by the code error pattern (error syndrome) occurs with reference to the error path selection position 119 determined in (a), this error path selection detection By referring to the contents of the surviving path history storage circuit 207 in the state of the position 119 and examining the length of the rejected path sequence, the length of a possible decoding error sequence (code error pattern, error syndrome) is determined, Only the code error pattern (error syndrome) of the length can be selected and subjected to the inversion replacement process. This makes it possible to limit the number of decoding sequence candidates with the next best decoding reliability. For example, the 1-bit code error pattern 119a described above is the length of the path sequence rejected at the error path selection detection position 119 (a different state transition sequence between the selected surviving path sequence and the rejected path sequence). ) Is 4 bits, it is possible to process in advance the possibility of occurrence of a 3-bit code error pattern 119b having a rejection path length of 6 bits or other error patterns.

FIG. 9 shows that, in the surviving path sequence 113 similar to FIG. 8A, the determined maximum likelihood path sequence 114 is rejected for processing at each time from k to (k + 8). The relationship between a path sequence (reject path sequences a to h) and a code inversion replacement position (a hatched part code position in the table) on the decoded code sequence 109 estimated from the length of each reject path sequence is shown as an example. The rejection path sequence d at time (k + 3) is
Since it is 4 bits in length, when it is determined that the process for the rejection path is an error selection, a 1-bit code error pattern 119a is estimated, and a time k 3 bits before the rejection time (k + 3) is estimated. Are subjected to 1-bit inversion and replacement processing. Time (k + 4) ~
Since the rejection path sequences eg at (k + 6) also have a 4-bit path length, the 1-bit code error pattern 119a is estimated, and the rejection times (k + 4) through (k + 6) From 3
The code on the determined maximum likelihood path sequence 114 at each of the time (k + 1) to (k + 3) before the bit is a target of the 1-bit inversion permutation processing. Also, since the rejection path sequence h at time (k + 7) has a 6-bit path length, a 3-bit code error pattern 119b is estimated, and a continuous 3-bit code from the rejection time (k + 7) to 3 bits before , The code on the determined maximum likelihood path sequence 114 at times (k + 2) to (k + 4) can be determined to be the target of the 3-bit inversion and replacement process. As described above, in the process (a), the length of the rejection path sequence is determined at the same time as the error path selection detection position 119, thereby selecting the code error pattern (error syndrome) to be referred to in the inversion and replacement process. This makes it possible to limit the number of sub-optimal decoding sequence candidates by the inversion permutation process on the maximum likelihood decoding sequence, thereby improving the utilization efficiency of circuit resources.

In the processes (b) and (c) of the present invention, a decoding error pattern sequence having a high frequency of occurrence is set in advance according to the distance between the received signal expected value sequences according to the target transmission channel. Processing (a) based on
Subsequence on the decoded code sequence 109 based on the error path selection / detection position 119 determined in the above is inverted and replaced to generate a decoded sequence candidate with the next best reliability. Therefore, the setting of the decoding error pattern sequence differs depending on the characteristics of the target transmission channel and the constraint conditions added to the transmission code sequence due to coding / modulation processing. A binary transmission code sequence EPR4 used for the above-mentioned magnetic recording / reproducing system channel and the like.
In general, including the channel, the partial response characteristic polynomial G (D) = (1-D) (1 + D) F (D) (where F (D) is an arbitrary characteristic polynomial) is often used in many practical applications. This is the form of the transmission channel to be transmitted. The transmission channel of this form has a characteristic in transmission characteristics that shows zero response to a DC component (continuous sequence of the same code) and a highest transmission frequency component (continuous inverted code sequence) among the frequency components of the binary transmission code sequence. And the above EPR
As represented by the example of the four transmission channels, the most frequent decoding error pattern sequence that defines the least square Euclidean distance between the received signal sequences is represented by one or more consecutive bits due to the common channel state transition structure. The common feature is that this is an inverted code error sequence, and that the continuous inverted code error occurs with the most frequent probability for the portion of the continuous inverted code sequence on the transmission code sequence transmitted on the channel. .

Therefore, the method of performing the processes (b) and (c) in the EPR4 transmission channel described above is generalized, and the channel memory length is set to an integer n (in the case of the EPR4 channel, n =
3), the time (kn) to the time (kn-i + 1) of the decoded code position with reference to the decoded code sequence and the time k corresponding to the path selection error position determined in the process (a).
By inverting and replacing the continuous decoded code sequence up to (i = 1 to each value from the maximum inverted length m), a decoded code sequence of the next best likelihood can be generated. At this time, a plurality of inversion replacement processes are performed.
Whether the decoding is performed with reference to the fact that the decoding code sequence is a continuous inversion code sequence, is performed unconditionally, or is selectively performed according to the length of a rejected surviving path sequence is determined by the EPR4 channel. As in the case of (1), it can be arbitrarily selected according to the embodiment.

The maximum inversion length m, which is the maximum code length of the replacement process, is a predetermined value equal to or less than the maximum continuous code inversion length limited by the constraint on the transmission code sequence, and maintains the performance of the decoding reliability. In addition, from the viewpoint of realization performance and implementation scale, among the m types of the sign inversion permutation processing from 1 to m bits, the embodiment can also set a predetermined length that is practically advantageous in performing At the same time, an arbitrary inversion replacement process may be omitted. Further, in the embodiments described above, the transmission code sequence 100 is channel-transmitted as it is, and the decoded code sequence output from the maximum likelihood sequence decoder is also decoded and output to a code sequence equal to the transmission code sequence. Has been described, in the transmission channel of various embodiments, before the transmission channel input, or for the decoded sequence in the maximum likelihood sequence decoder or immediately after the output,
In many cases, various code conversion processes and signal processing operations such as a precode process or a postcode process are performed. In this case, for a decoded code sequence different from the code sequence on the transmission channel, the relative positional relationship between the error path selection detection position 119 and the position of the code replacement process and the error code position of the code error pattern sequence (error syndrome) are as follows: An error sequence on a decoded sequence can be obtained by performing a mapping conversion on a processing code position by the same code conversion processing and signal processing operation as the information code. For example, when a sequence obtained by subjecting a transmission code sequence on a channel to post code processing (1 + D ² ) (addition of +2 to a binary code) is output as a decoded code sequence,
A code error pattern sequence (error syndrome) significant to the transmission code sequence “... 0 + 1−1 + 1−1 + 100. +1... ”And perform the same processing as a decoded code error pattern sequence (error syndrome) in the inversion permutation process on the decoded code sequence. Since the code conversion process in the information transmission system guarantees the code reproducibility, a one-to-one correspondence between a code error pattern sequence (error syndrome) and a code sequence position before and after the conversion is possible. Therefore, it is possible to execute a process equivalent to the above-described embodiment process on the transmission code sequence on the decoded code sequence subjected to various code processes.

Process (d) Implementation Method: The flow of the encoding process, which is a feature of the present invention, will be described with reference to FIG. 9 to explain the specific flow of the process (d). Information transmission system 10 of FIG.
The transmission code sequence 100 (information code sequence) supplied to 1 is:
In order to be supplied to the transmission channel 104, predetermined processing is performed according to the form of transmission and recording, and the transmission recording code sequence 1
20 (information code sequence). (In the present embodiment, the transmission recording code sequence 120 is the transmission code sequence 100
There is no practical problem even if it is considered synonymous with. ) From the decoded code sequence candidates of the decoded number generated in (c), to check the validity as the transmission code sequence and select the final decoded code sequence as the transmission recording code sequence 120, Transmission record information code blocks 120a, 120b of a predetermined length,
120c.., And an error for detecting that a code error event of the decoded code error pattern (error syndrome) set in (b) and (c) has occurred in the transmission recording information code block. Check code string 122a, 122
., 122c...
1a, 121b, 121c... Then, this is again converted to the original transmission code block transmission recording information code block 1
.. Are processed as one channel transmission code sequence 121 in the time series of 20a, 120b, 120c,..., And transmitted on the transmission channel.

In this process, the transmission recording code sequence 120
Error check code strings 122a, 122b, 12
.. Are parity check codes or cyclic redundancy codes (CRC:
Cycle Redundancy Check) or the like, and can be configured by a known technology for configuring an error detection code / error correction code. For example, the partial response characteristic polynomial G (D) = (1-D) (1+
D) In order to detect a frequently occurring 1 to n-bit (n is a predetermined integer) continuous inversion code error pattern (burst error up to n bits in length) in the above-mentioned transmission channel represented by F (D). Can be applied to a cyclic redundancy code generated by a generator polynomial of degree n. Providing a method of configuring an error detection code having low redundancy and high detection capability for a specific code error pattern is beyond the scope of the present invention, and will not be described here. From the characteristics of the code error pattern (error syndrome), (b)
By configuring an error detection code that detects only the presence of a limited number of code error patterns (error syndromes) set in advance in the process (c), an error detection code having a low redundancy and a simple configuration can be obtained. It is an advantage of the present invention that the reliability of the transmission information can be increased by using this.

On the decoding processing side, the decoded code sequence 109 output from the maximum likelihood sequence decoder and, correspondingly, the next best maximum likelihood decoded code sequence generated in the processes (b) and (c) are: , The transmission code blocks 121a, 121b, 1
Are processed in units corresponding to 21c. That is, the decoded code sequence 109 is obtained from the maximum likelihood sequence decoder, and the code inversion position on the decoded code sequence 109 is determined by the processes (a), (b), and (c), and the code indicating the position is determined. When the replacement pointer sequence 124 is generated,
The decoded code sequence 109 is sequentially converted into decoded code candidate blocks 125a, 125b,
, And a decoded code candidate block sequence 126a generated from the maximum likelihood decoded sequence is generated. Further, each decoded code candidate block 125a, 125b,
In the code unit 125c, code positions in the decoded code candidate block on the decoded code sequence 109 indicated by the code replacement pointer sequence 124 are all independently set in one or more combinations, or in one or more positions. Inversion processing is performed by, for example, selecting a combination in a predetermined manner. Thereby, decoded code candidate block sequences 126b and 126c, which are decoded code sequences of the next best likelihood.
Are generated, and the respective transmission code blocks 121a, 121
1b, 121c... Corresponding to each decoded code candidate block 1
For the code units of 25a, 125b, 125c ...
Decoded code candidate block sequences 126a, 126b, 126
A plurality of decoded code candidate blocks belonging to c ... are expanded,
A decoded code candidate block list 125 is configured. The decoded code candidate blocks 125a, 125b, 1 corresponding to the respective transmission code blocks 121a, 121b, 121c,.
25c... For each code unit, a plurality of decoded code candidate blocks (decoded code candidate block sequences 126a,
26b, 126c...) From among error check code strings 122a, 122b, 122c added during transmission.
, One of the error-free decoded code candidate blocks is checked and selected, and after removing the error-check code sequence, the deterministic decoded code blocks 127a, 127a, 127b, 12
7c are selectively output. Thus, in the present invention,
A list of a decoded code sequence including a maximum likelihood code sequence and a suboptimal maximum likelihood code sequence is formed. From the decoded code candidate block sequences 126a, 126b, 126c,. The blocks (deterministic decoding code blocks 127a, 127b, 127c...) Are inspected and selected, and the final deterministic decoding code sequence 127 is determined.

The code length of the transmission code block, the code length of the error detection code string to be added, and the error detection capability are set according to the noise environment and the decoding error probability in which the present invention is implemented. When the decoding error probability at the output of the maximum likelihood sequence decoder 108 to which the present invention is applied is considered, the decoding error event occurring in this code block is determined from the code length of the set transmission code block 121a, 121b, 121c. The average number is estimated, and error detecting code strings 122a, 122b, 122c... Capable of detecting all the error events are constructed and added. As described above, the present invention achieves a practical decoding error probability by focusing on the fact that the probability that random decoding error events caused by noise elements are concentrated at a certain code point is extremely rare. As described above, the number of decoding error events that can be rescued within a transmission code block (decoding code candidate block) of a predetermined length is limited. As a result, the configuration of the error detection code to be added can be made relatively simple, the code length (redundancy) of the error detection code string can be kept low, and the decoding error rate can be improved. For example, if the error probability of the maximum likelihood sequence decoding is 1.0E-3, the length of the transmission code block (decoding code candidate block) is set to about 1000 bits in the reciprocal order, so that the decoding error event occurring therein can be performed. The number can be about one on average. Therefore, by setting the transmission code block length to 1000 bits or less and adding error detection code strings 122a, 122b, 122c... Capable of detecting a single error event, error event rescue and decoding error rate can be improved. Can be implemented. In general, under a decoding system with a certain decoding error rate, the larger the transmission code block length is set, the higher the detection capability of the added error detection code must be, and the larger the code length of the error detection code sequence is, For the transmission code block length and the error detection code sequence configuration and length, the optimum length is selected according to the embodiment.

On the other hand, each transmission code block 121a, 121
1b, 121c... Added to the error detection code sequence 122
When the detection capability of a, 122b, 122c... and the maximum number of detectable error events in the decoded code candidate block corresponding to the transmission code block are set, each decoded code candidate block detected in the process (a) is set. Is the maximum number of error path selection events within the above, that is, the maximum number of code inversion and replacement processing locations (the number of replacement processes) in each decoded code candidate block in processes (b) and (c) is the maximum detectable error event. It is set to be less than or equal to the number.

In accordance with the number of replacement processes of the code inversion replacement process set as described above, the process (a)
(B) By performing code inversion and replacement processing on some or all combinations of all error code processing positions determined in (c), transmission code blocks 121a and 121
After a plurality of decoded code candidate blocks are generated in units of b, 121c..., and a decoded code candidate block list 125 is generated, a decoded code block corresponding to the transmission code block is subjected to error inspection and selected and output. The above is the description of the implementation method and principle of the present invention.

FIG. 1 is a diagram for explaining a basic configuration of an information transmission / recording / reproducing system for implementing the present invention by the above method. In the encoding process, a transmission / recording information code sequence 300 which is an original information data sequence of transmission / recording.
In general, a predetermined coding process such as an error correction coding process and a coded modulation process is performed by a coding circuit 301 to a known technique according to the embodiment, and the transmission recording code sequence A conversion to 120 is made.

In the present invention, in order to perform the decoding code error detection processing in the above-mentioned processing (d), the transmission recording code sequence 120 is converted into a transmission recording information code block 120 having a predetermined length.
a, 120b, 120c..., and for each of the transmission record information code blocks, an error detection code sequence 122a,
Are generated, and processing for adding them is performed. The check code adding circuit 302 that performs this operation includes a check code generation circuit 303a and a check code insertion circuit 303b.
Consists of The check code adding circuit 302 sequentially converts the transmission recording code sequence 120 (information code sequence), which is a sequential code time sequence, into transmission recording information code blocks 120a, 120b, 120c... ., And generates an error detection code sequence 122a, 122b, 122c... For each block. As described in the above process (d), the error detection code string generated here is the maximum likelihood sequence decoding circuit 30 in the transmission recording system.
8 is configured to detect the presence of a predetermined decoding code error pattern (error syndrome) occurring at a high frequency on the decoding code sequence 109 which is the output of 8 and a predetermined finite number of such predetermined predetermined predetermined coding error patterns. A low-redundancy pattern that can detect only a code error pattern (error syndrome) up to a predetermined finite number is generated. An encoding circuit that performs this is the check code generation circuit 303a. In addition, the check code insertion circuit 303b includes the check code generation circuit 3
Error detection code strings 122a and 122 generated in step 03a
are inserted and added immediately after the transmission recording code block or in a predetermined corresponding code position in the transmission recording code sequence 120 (information code sequence). By this check code insertion circuit 303b, the transmission recording code sequence 1
20 is a transmission recording code block 120a, 120b, 1
20c... For each error code block unit
are inserted and added to generate a channel transmission code sequence 121 which is a code block sequence of the transmission code blocks 121a, 121b, 121c... (see the embodiment of FIG. 9). Thereafter, the channel transmission code sequence 121 is regarded as a single code time sequence composed of a stream of transmission code blocks and processed like the code time sequence of the original transmission recording code sequence 120 (information code sequence). ,
Input to the code transmission process. The transmission / recording / reproducing signal transmission system 304 transmits the channel transmission code sequence 121
It comprises a transmission / recording code signal processing system 305 for converting into an analog or digital signal format that can be transmitted via the recording / reproducing channel 306, and a transmission / recording / reproducing channel 306 which is responsible for transmitting transmission / recording / reproduction information. .
In the transmission / recording code signal processing system 305, a code processing circuit 305a that performs predetermined code processing such as precoding on the channel transmission code sequence 121, and converts the output channel transmission code sequence into a transmittable signal form. And a transmission / recording signal processing circuit 305c for performing predetermined signal processing such as signal correction and amplification processing on the converted transmission signal, as required. It is composed of technology. The embodiment of the present invention does not depend on the components of the transmission / recording / reproduction signal transmission system 304. Transmission / recording / reproduction channel 306
Is an information transmission medium composed of a transmission or recording medium, a transducer, a sensor, and the like. In an information storage / reproduction apparatus, it corresponds to a recording / reproduction system including a recording head / information storage medium / reproduction head. The above is the basic configuration of the present invention on the transmitting / recording side.

Next, a basic configuration on the receiving / reproducing side will be described. The received / reproduced signal sequence output from the transmission / recording / reproducing channel 306 is subjected to predetermined signal processing operations such as amplification processing, gain / phase control processing, noise removal processing, equalization processing, etc. 307. After this processing, the received signal sequence 107 is input to the maximum likelihood sequence decoding circuit 308, and the decoded code sequence 10
9 is decoded and output. According to the present invention, based on the process (a), in the maximum likelihood sequence decoding circuit 308, the possibility of occurrence of an error path sequence selection event when estimating the decoded code sequence 109 (survival path selection process with low reliability, error A function for determining the path selection detection position 119) is provided. Further, a function is provided for generating a decoding reliability flag 123 for instructing the output of the code position (error path selection detection position 119) of the low reliability path sequence, and outputting the flag in synchronization with each code of the decoded code sequence 109. In addition, if necessary,
Surviving path sequence selection (error path selection detection position 119) of low reliability indicated by decoding reliability flag 123
In the decoding reliability flag 123, information on the length of the rejected surviving path sequence (or the length of the code sequence for performing the code inversion permutation estimated based on the length of the surviving path sequence) is stored in the decoding reliability flag 123. In some cases, a function is provided for transmitting the information at the same time. A specific configuration and an example of the maximum likelihood sequence decoding circuit 308 having such a function will be described later in detail.

In the decoding code candidate block list generation circuit 309, the decoding reliability flag 123 is set based on the information indicated by the decoding code sequence 109 and the decoding reliability flag 123, which are output information from the maximum likelihood sequence decoding circuit 308. The code inversion permutation process based on the processes (b) and (c) is performed on the low-reliability decoded portion on the decoded code sequence 109 shown in the figure, and the decoded code candidate blocks 121a, 121b, The decoded code candidate block 310 is a decimation number for each code block unit 121c.
(1), 310 (2), 310 (3) ... 310 (m)
(M is a predetermined natural number) to form a decoded code candidate block list 125. In the decoded code candidate block list generation circuit 309, the decoded code processing circuit 309a
Performs predetermined code processing such as post code processing on the decoded code sequence 109 as necessary, and then performs processing of dividing the code sequence into blocks with the same length and timing as the transmission code block. Further, the code replacement pointer generation circuit 309b generates the decoding reliability flag 12 based on the information of the decoding reliability flag 123 and the information of the decoding error pattern sequence (error syndrome pattern) set in advance.
3 from one or more code positions at a predetermined relative position on the decoded code sequence 109 from the reference code position (for example, the error path selection detection position 119) indicated by the reference code position indicated by No. 3 It sends out pointer information (code replacement pointer sequence 124) indicating that it is the target of the inversion replacement process. The code replacement pointer sequence 124 may selectively instruct a replacement process individually or in combination with a plurality of locations for a plurality of inversion replacement processes in a code block. In some cases, replacement inversion processing using sign inversion patterns having different numbers of numbers may be performed on processing locations. In this case,
For a plurality of code inversion permutation process combinations, a plurality of code permutation pointer sequences 124 indicating the inversion code positions of each code process are generated. As described in the method of performing the processes (b) and (c), information on the length of the rejected path sequence (length of the inverted replacement code sequence) in surviving path selection is added to the decoding reliability flag 121 and supplied. In this case, the process of limiting and selecting the decoded code error pattern sequence (error syndrome pattern) in the permutation inversion process performed based on this is performed by restricting the generation of the code replacement pointer sequence 124 in the code replacement pointer generation circuit 309b. Do. Also, in the case where the presence / absence of the inversion / replacement processing and the limitation / selection of the decoded error code pattern sequence (error syndrome pattern) are determined by the pattern on the decoded code sequence 109 of the inverted / substituted portion, similarly, referring to the decoded code sequence 109 This is performed by limiting the generation of the code replacement pointer sequence 124 in the code replacement pointer generation circuit 309b. The decoded code candidate block generation circuit 309c receives the code replacement pointer sequence 124 corresponding to the block-divided decoded code sequence 109, and performs a code inversion process indicated by the code replacement pointer sequence 124 on the decoded code sequence 109. And a plurality of decoded code candidate blocks 310 using the maximum likelihood decoded code block and the next best likelihood decoded code block.
(1), 310 (2), 310 (3), ..., 310
(M) is generated, and a decoded code candidate block list 125 is formed. FIG. 2 shows an embodiment summarizing the above-described operations for constructing the decoded code candidate block list. Based on the code position indicated by the decoding reliability flag 123 which is the output information 128 of the maximum likelihood sequence decoding circuit 308, the code replacement pointer generation circuit 309b performs the relative sign inversion according to the principle described in (b) and (c). A code replacement start position pointer 123b indicating the replacement position is generated. Further, based on the code replacement start position pointer 123b as a reference, in accordance with a predetermined code error pattern (error syndrome),
Sign replacement pointer sequence 12 for directly indicating the sign inversion position
4 is generated. Decoded code candidate block generation circuit 309
In c, for each code block unit on the decoded code sequence 109, for each part of the code replacement process indicated by the code replacement pointer sequence 124, or for a combination of a plurality of parts, all or some Is selected, a code on the decoded code sequence 109 is subjected to inversion and permutation processing, and a plurality of decoded code candidate blocks 310 (1), 3 (3) including a code block of the original decoded code sequence 109 which is not subjected to inversion permutation.
A decoded code candidate block list 125 including 10 (2), 310 (3),..., 310 (m) is configured. (At this time, a plurality of code replacement pointers 124 may be generated for each of a plurality of code replacement processes for each code block.) The generation of the decoded code candidate block list is performed by a general logical operation circuit and a buffer. It can be easily realized by the storage circuit.

In FIG. 1, a plurality of decoded code candidate blocks 310 forming a decoded code candidate block list 125 are shown.
(1), 310 (2), 310 (3), ..., 310
(M) is input to the code error check circuit 311 as a decoded code candidate block sequence 126, and is used for each decoded code candidate block using the error check code sequence of each transmission code block added in the check code adding circuit 302. Is checked for a code error. The result is instructed to the decoding code candidate block selection circuit 313 through the decoding code candidate block selection signal 312a, and the normal decoding code candidate block having no code error is deleted after the error detection code string added thereto is deleted. Output as a code block. The time series of this deterministic decoding code block is the deterministic decoding code series 12
7, which is an information reproduction code sequence for the transmission recording code sequence 120. The code error check circuit 31
In 1, if an error exists in any of the simultaneously input decoded code candidate blocks and a normal decoded code candidate block cannot be selected, in order to indicate that a code error exists on the decoded code sequence, The error decoding block flag 312b is sent out in synchronization with the definite decoding code sequence 127 which is the decoding result, and can be used in the subsequent code processing or transmission / recording / playback control processing. The code demodulation circuit 314 subjects the deterministic decoded code sequence 127, which is the input decoding result, to inverse conversion or appropriate predetermined processing with respect to the code processing performed by the coding circuit 301, and performs the original transmission / reception. A reception / reproduction information code sequence 315 corresponding to the recording information code sequence 300 is obtained.

The decoding code candidate block list generation circuit 309 generates a plurality of inverted permutation pointer sequences 124, and performs the decoding process to generate decoded code candidate blocks 310 (1), 310 (2),. The error detection processing for each decoded code candidate block in the error check circuit 311 describes an embodiment in which processing is performed using circuit resources provided in parallel with a decoded number of decoded code candidate blocks so as to reduce processing delay. . On the other hand, a series of processes of the generation of the code replacement pointer sequence 124, the code replacement process, and the error detection process are sequentially performed using the same circuit resources for each decoded code candidate block in a time-division manner.
By repeating the process, it is possible to adopt an embodiment in which the scale of the circuit to be implemented is reduced while allowing an increase in the processing time delay. Furthermore, in the embodiment, for the sake of explanation, each code block unit is described as being physically separated and divided from each code sequence and processed. However, this is logically performed in block units in terms of a realization circuit configuration. A series of processing from the input of the decoded code candidate block list generation circuit to the code error check circuit 311 and the decoded code candidate block selection circuit 313 is performed as a continuous sequential code processing flow, for example. This can be realized using a buffer storage device having a shift register configuration and a logical operation element.

In the present invention, the length of a code block, the configuration and code length of an error detection code to be added, the number of code inversion permutations in a decoded block, and the like are determined according to the embodiment and the state of the transmission / recording / reproduction channel 305. Number of code error pattern sequences and decoded code candidate block list 12
It is often required that the number m of blocks in 5 is set to an optimum value based on a desired decoding reliability and an implementation scale, but these parameters are variable and can be changed according to the implementation situation. It is easy to do. In the simplest embodiment, the length of the transmission code block 111 of the present invention is used in a transmission unit (transmission frame or the like) or a recording / reproduction unit (sector unit in a disk device) of an information transmission / recording / reproduction system embodying the present invention. There is a form to make the same. Furthermore, in order to improve the decoding reliability, as described above, based on the transmission channel and the desired decoding error rate,
It is possible to divide the transmission unit of the information transmission / recording / reproducing system into a plurality of transmission / recording code blocks having a predetermined length, add an error detection code to each of the blocks, and perform a process based on the above embodiment. it can.

FIG. 3A shows a first embodiment of the Viterbi decoding process for each transition state for simultaneously outputting the decoding reliability flag 123. In the present embodiment, a flag generation unit 210a and a flag memory unit 210b are provided for the conventional Viterbi decoder configuration of FIG. 6A, and the decoding reliability flag 123 is converted to the decoded code sequence 109 based on the process (a). Are synchronized and output simultaneously. Flag generator 21
In step 0a, based on the processing (a), the absolute value of the difference between the surviving path metric likelihood PM (i, n) (k) and PM (j, n) (k) is calculated, and this is used to select the surviving path. Used as reliability information.
For this reason, the absolute value calculation circuit 2 refers to the path metric likelihood PM (i, n) (k) and PM (j, n) (k) from the ACS calculation unit 200b.
In step 11, the difference metric absolute value 217 between the path metric likelihoods is calculated using these values. The comparator 213 determines whether or not the difference metric absolute value 217 is smaller than a predetermined reliability flag determination threshold value D212. The reliability flag 21 indicating that the reliability of the selection determination of the path metric indicated by the signal 205 is low.
4 are output simultaneously. The flag memory unit 210b has the same configuration as the path memory unit 200c,
Flag history storage circuits 215a to 215h corresponding to each of the path history storage circuits 207a to 207h of 00c and flag history selection circuits 216a to 216h corresponding to each of the path history selection circuits 208a to 208h are provided. The flag memory unit 210b receives the same selection signal 205 as the path memory unit 200c and a synchronous operation signal of the same cycle, and repeats the same storage update processing operation. Then, for each operation timing, the content of the reliability flag 214 is
The corresponding transition state is retained as the initial value in the leftmost storage element of the flag history recording circuit 215c, and the decoded code is subjected to the same selection updating process as the selection process in the path memory unit 200c, and the decoding reliability flag 123 Output as As a result, in synchronization with each decoded code on the decoded code sequence 109, the flag information indicating the degree of reliability of the surviving path selection at the decoded code position (error path selection detection position 119) is changed to the decoding reliability flag 123. Is output as The decoding reliability flag 123 provides information indicating the reference position of the code inversion and replacement process in the decoded code candidate block list generation circuit 309.

FIG. 3B shows a second embodiment of the Viterbi decoding process for each transition state for simultaneously outputting the decoding reliability flag 123. In this embodiment, specific means for obtaining flag information for the code position of the surviving path selection process with the lowest reliability for each predetermined section (section corresponding to the decoded code candidate block) on the decoded code sequence 109 is described. Is shown. Also in this case, similarly to the embodiment of FIG. 3B, the conventional Viterbi decoder configuration of FIG.
A flag generation unit 210 for each state transition path selection processing system
a and a flag memory unit 210b are provided, and the processing is performed based on the difference metric absolute value 217 when the surviving path is selected in each state transition based on the processing (a).
In the present embodiment, the flag memory unit 210b is configured as shown in FIG.
In the same manner as in the embodiment, a difference metric storage circuit 219 for holding the smallest difference metric absolute value 217 in the past decoding history in the flag generation unit 210a, a difference metric obtained by this content and each decoding operation timing A comparator 213 for checking the magnitude relationship with the absolute value 217 is provided. If the difference metric absolute value 217 in the transition path selection at each decoding operation timing is equal to or less than the content of the difference metric storage circuit 219, the selection signal 205 from the ACS operation unit 200b indicates. A reliability flag 214 indicating that the selection determination of the path metric is low reliability is output in the same manner as in the embodiment of FIG.
8, the value of the difference metric absolute value 217 at this time is selectively input as the content of the difference metric storage circuit 219, and the value of the minimum difference metric absolute value 217 is always updated and held. By providing such a flag generation unit 210a, predetermined decoding timing (for example, timing corresponding to the start code position of the above-described decoded code candidate block)
For each, the maximum value that the difference metric absolute value 217 can take is
By setting as the storage circuit initial value 220 held in the difference metric storage circuit 219, the minimum difference metric absolute value 217 can be determined for each decoding section determined by the interval of the initial value 220 setting timing. That is, in the decoding reliability flag 123 in the decoding code section of the initial value 220 setting interval (for example, the decoding code section corresponding to the above-described decoding code candidate block), the low reliability path selection (error path) output last is output. Selection detection position 119)
Can be treated as the code position information of the decoding path selection with the lowest reliability. In general, the n-th
In order to obtain flag information for code positions up to the second lowest reliability (n is a predetermined integer), based on the same principle and configuration, as in the embodiment of FIG.
This can be easily realized by adopting a configuration in which 10a and the flag memory unit 210b are connected in cascade over n stages (n = 2 in this embodiment). (In this embodiment, the branch metric calculation unit 200a, the ACS calculation unit 200b, and the path memory unit 200c are omitted because they are the same as those in FIG. 3B.) According to the configuration of this embodiment, each decoding reliability flag 123 (n 3), the flag information of the code position of the reliability path selection decoding (error path selection detection position 119) having the lowest reliability up to the n-th in a predetermined decoding section is shown in FIG.
(B) It can be obtained as in the embodiment.

FIG. 3 (d) shows an embodiment of the decoder configuration in the case where the information of the rejection path length in the low reliability path selection is output simultaneously with the decoding reliability flag information from the Viterbi decoder. This embodiment is shown based on an embodiment of the reliability determination based on the comparison between the reliability flag determination threshold value 212 and the difference metric absolute value 217 based on FIG. In this embodiment, in order to check the rejected path length in the path selection, in the path memory unit 200c, the match detection circuit 222 and the path detection memory circuit (207c in this embodiment) corresponding to each state transition destination are provided. A path history convergence position detection circuit 223 is provided. These are stored in the path history storage circuit 207c via the path history selection circuit 208. The path history storage circuits (207a and 207a in this embodiment) which can be referred to when updating the contents of the path history storage circuit. With reference to 207b), it is checked whether these path history contents match. For this reason, the match detection circuit 222 checks whether the contents of the storage elements at the corresponding time positions match each other in the path history storage circuits 207a and 207b, and the path history convergence position detection circuit 223 receives this result, and Of the storage elements between the path history storage circuits 207a and 207b, from the storage element at the last stage (the rightmost position in the path history storage circuit) to which position the storage elements are converged and matched,
In other words, the two path history storage circuits 207a and 207a
07b, the length of the unconverged portion from the storage element at the first stage (the leftmost position in the path history storage circuit) is detected, and this is used as convergence position information 224 for each decoding operation timing. Output. The match detection circuit 222
The path history convergence position detection circuit 223 can be easily realized by using an exclusive OR operation, and also by using a known logical operation circuit. When low reliability decoding flag information is output from the reliability flag 214, the corresponding convergence position information 224 is stored in the flag history storage circuit 215 of the corresponding path transition state.
This is input as the initial value of the first stage of c (the leftmost position storage element). When the reliability flag 214 outputs flag information of high reliability decoding, the path convergence position information 224
A so-called null value having no meaning as is input. The flag selection circuit 225 outputs the reliability flag 21
The initial value selection for the first stage of the flag history storage circuit 215c according to No. 4 is performed. Thereby, the decoding reliability flag 123 becomes
This does not simply indicate the reliability of the decoding path selection, but also outputs information on the length of the rejected surviving path sequence at the code position. Using the information on the rejection path length, the decoding code candidate block list generation circuit 309 at the subsequent stage selects a decoding code error pattern (error syndrome pattern) for code inversion and replacement processing by the code length and limits the processing. Can be. In this embodiment,
Although shown based on the embodiment of FIG. 3 (a), it is equally applicable to the embodiments of FIGS. 3 (b) and 3 (c).

The present invention can be applied to various information transmission systems using a maximum likelihood sequence decoder, such as a transmission communication system and a recording / reproducing system, through the general embodiment shown in FIG. Reliability can be improved.
The improvement of the decoding reliability in the transmission communication system according to the present invention improves the performance of the receiving / decoding device, allows the transmission power in the transmitting device to be reduced, and promotes power saving and miniaturization of the device. to enable. Further, application of the present invention to a recording / reproducing system can tolerate the noise of the reproduced signal and a decrease in the signal-to-noise ratio quality, thereby increasing the information storage density on the recording medium or reducing the recording / reproducing signal bandwidth. And a new effect such as allowing the recording / reproducing operation frequency to be expanded.

FIG. 4 shows an embodiment in which the present invention is applied to a magnetic disk drive as an example of application to an information recording / reproducing system. On the recording side in this embodiment, the recording code 400 as recording information is added with a constraint condition such as a run-length limit by a code / modulation circuit 401 and then by a check code adding circuit 302 as described in FIG. , An error detection code string is added for each code block. In a high-density magnetic recording / reproducing system, a partial response channel characterized by a transmission polynomial (1-D) (1 + D) F (D) (F (D) is an arbitrary polynomial) is often used. The decoding process is performed using the maximum likelihood sequence decoding circuit by using the convolution process due to the intersymbol interference. As described above, in such an information transmission system, a continuous inversion code error of 1 bit or more becomes a dominant decoding code error pattern (error syndrome pattern) in a decoding error. Therefore, an error detection code string for detecting a continuous inversion code error of 1 bit or a predetermined length is generated, and a check code addition circuit 302 is applied to the recording code sequence output from the code / modulation circuit 401. Add this through. At this time, as described above (FIG. 9),
According to the decoding error rate of the maximum likelihood sequence decoding and a desired decoding error rate, the recording code output from the code / modulation circuit 401 is divided into a plurality of transmission recording code blocks, and a predetermined error detection code sequence is provided in each code block. After being inserted and added, it is sequentially input to the code processing circuit 405 again as a series of recording code sequences. When the decoding error rate of maximum likelihood sequence decoding is relatively good, and when the average number of errors in the sector that is the unit of reading is relatively small, an error check code string that can detect this is added to the sector. However, the whole sector may be regarded as one code block and processed without dividing the sector into more subdivided recording code blocks. The recording information code sequence output from the check code adding circuit 302 is subjected to a predetermined code processing before recording such as a pre-code for a partial response channel in a code processing circuit 405, and the recording information code is converted into a recording current conversion circuit. In 404, after being converted into a recording current, it is supplied to a recording / reproducing channel 409, which is an electromagnetic conversion system, via a recording amplifier 405. In a recording / reproducing channel 409 composed of an electromagnetic conversion system of the recording head 406 / reproducing head 407 and the recording medium 408, the recording information code is magnetically stored and stored. On the reproducing side, this stored recording information code is recorded and recorded on the recording / reproducing channel 4 in response to the reading request.
09 as an electrical signal output. The reproduction signal processing circuit 410 subjects the read electric signal to amplification processing by a reproduction amplifier 411 and a variable gain amplifier 412
, A discretization process by an analog / digital converter 414, an equalization process by an equalizer 415, and the like, and supplies a reproduced signal sequence as an output to the maximum likelihood sequence decoding circuit 308. (The timing extraction / gain control circuit 416 converts the sample timing signal 4
16a and a gain control signal 416b. A series of processes from the input of the code processing circuit 403 to the output of the reproduction signal processing circuit 410 may take various forms depending on the recording / reproducing system.
It is realized by a known technique. ) The maximum likelihood sequence decoding circuit 308 is configured based on the above-described embodiment, and outputs the decoded code sequence 109 simultaneously with and in synchronization with the decoded code sequence 109.
A decoding reliability flag 123 corresponding to each decoding code position is output. As described in the embodiment of FIGS. 1 and 2, the decoded code sequence 109 and the decoding reliability flag 123
And a decoded code candidate block list generation circuit 309
Then, a check code addition circuit 303 generates a list of decoded code candidate blocks in units of code blocks to which an error check code string is added. Decoding code processing circuit 309a
Then, predetermined post-code processing such as post-code processing is performed on the decoded code sequence 109. Further, the code replacement pointer generation circuit 309b converts a pointer signal sequence indicating a decoding code position to be subjected to code inversion and replacement processing into a predetermined signal based on the decoding reliability flag 123 and a predetermined decoding code error pattern (decoding error syndrome pattern). Output as many as possible. In response to this, the decoding candidate block generation circuit 309c converts a predetermined number of decoded code candidate blocks into the code replacement pointer series 12
4 is generated by the sign inversion and substitution process at the pointer position indicated by reference numeral 4, and the code error check circuit 311
In step 03, a normal decoded code candidate block is inspected and selected using the error detection code string added in code block units. Decoding code candidate block selection circuit 313
Receives the decoded code candidate block selection signal 312a indicating the result of the check selection, selects and outputs only the normal decoded code block, and outputs the deterministic decoded code sequence 127 to the demodulator 418.
To supply. The demodulator 418 performs an inverse conversion process of the code / modulation circuit 401 on the deterministic decoded code sequence. As a result, a reproduction code 419 that faithfully reproduces the recording code 400 can be obtained on the reproduction side. When a decoding error is detected from any of the decoding candidate blocks, the error checking circuit 313 outputs an error decoding block flag 312b, and outputs the reproduction code 41 of the code block.
In 9, flag information indicating that a decoding error event that could not be remedied by the present invention is included can be transmitted to subsequent processing. In the subsequent error correction processing, more efficient error correction processing can be executed by using this information, and a decoding error can be recovered by executing a reread operation (retry). In this embodiment, a check code addition circuit 303a is provided after the code / modulator 401 to perform code block division processing and error check code sequence insertion and addition. This is to avoid that the configuration of the error check code string becomes complicated and redundant due to the decoding code error pattern being expanded by the inverse transform processing in the demodulator 418. However, depending on the processing in the code / modulator 401 and the demodulator 418, this may be avoided and not a problem.
In this embodiment, the code / modulator 401 and the check code adding circuit 303, and the demodulator 418 and the code error check circuit 3
13 (decoding code candidate block selection circuit 414) can be switched in an effective manner according to the embodiment of the present invention. Although the present embodiment has been described by taking an example of application to a recording / reproducing system of a magnetic disk device, other magnetic recording / reproducing devices or many information recording / reproducing devices such as an optical recording / magneto-optical recording / reproducing device are most suitable. A reproduction system using likelihood sequence decoding can be applied, and the same embodiment can be applied. According to the present invention, the recording / reproducing channel 409
Even if the signal to noise ratio quality of the output reproduction signal from
As a result, a decrease in the reliability of the decoded code sequence can be remedied, and the information recording density on the recording medium 408 of the recording / reproducing system is increased, or the recording / reproducing frequency is increased. A recording / reproducing device can be provided.

Further, the present invention can be easily configured and implemented by an existing digital signal processing circuit, thereby providing the above information transmission system and information recording / reproducing system. It can be mounted on an integrated circuit. A logic circuit such as a decoded code candidate block list generation circuit 311 required in the present invention can be easily configured with a small number of logic elements and a buffer storage circuit, and is therefore a circuit suitable for mounting on a high-speed and high-integration integrated circuit. Consists of resources. By implementing and implementing the present invention in an integrated circuit, devices using a power-saving and high-speed information transmission system and a high-density and high-speed information recording / reproducing system due to the effects of the present invention can be reduced in size. And can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment showing a basic configuration of the present invention.

FIG. 2 is a diagram for explaining a method of configuring a decoded code candidate block list.

FIG. 3A is a diagram illustrating a first embodiment of a Viterbi decoding processing configuration for simultaneously outputting a decoding reliability flag.

FIG. 3B is a diagram showing a second embodiment of the Viterbi decoding processing configuration for simultaneously outputting a decoding reliability flag.

FIG. 3C is a diagram illustrating a third example of a Viterbi decoding processing configuration that simultaneously outputs a decoding reliability flag.

FIG. 3D is a diagram showing a fourth embodiment of the Viterbi decoding processing configuration for simultaneously outputting a decoding reliability flag.

FIG. 4 is a diagram showing an embodiment in which the present invention is applied to a recording / reproducing apparatus.

FIG. 5A is a diagram showing a flow of an information sequence in an information transmission system or a recording / reproducing system.

FIG. 5b shows an EPR4 partial response runway channel model.

FIG. 5c is a state transition diagram (binary code transmission sequence EPR4 transmission channel).

FIG. 5D is a diagram showing a trellis transition at time k (binary code transmission sequence EPR4 transmission channel).

FIG. 5E is a diagram showing a path transition to each state at time k (binary code transmission sequence EPR4 transmission channel).

FIG. 5f is a diagram (example of a binary code transmission sequence EPR4 transmission channel) showing a state transition path at times k to k + 4.

FIG. 6A is a diagram for describing specific components that implement the Viterbi decoding process.

FIG. 6B is a diagram showing a configuration of a maximum likelihood decoder (maximum likelihood sequence decoder, Viterbi decoder) based on the Viterbi algorithm.

FIG. 7 is a trellis diagram (binary code transmission sequence EP) for explaining a maximum likelihood decoding process by selecting a surviving path sequence.
R4 transmission channel).

FIG. 8A is a first trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the relationship between a normal path sequence and an error path sequence in the maximum likelihood decoding process.

FIG. 8B is a second trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the relationship between the normal path sequence and the error path sequence in the maximum likelihood decoding process.

FIG. 8C is a third trellis diagram (binary code transmission sequence EPR4 transmission channel) for describing the relationship between the normal path sequence and the error path sequence in the maximum likelihood decoding process.

FIG. 9 is a diagram for explaining a flow of a coding process according to the present invention.

[Explanation of symbols]

100: transmission code sequence, 101: information transmission system, 102:
Encoder 103, modulator 104, channel 105
Additional noise, 106: received signal processing circuit, 107: received (decoded input) signal sequence, 108: maximum likelihood sequence decoder, 109: decoded code sequence, 110a, 110b, 11
0c... 1-bit delay storage element, 111a, 111b, 1
11c: addition / subtraction operation element, 112: path sequence, 112a,
112b state transition path (path branch), 113 survival path sequence, 114 determined maximum likelihood path sequence, 115
Normal path sequence, 116: error path sequence, 117: error path selection, 118: decoded error pattern sequence, 119a: 1
Bit code error pattern, 119b ... 3-bit code error pattern, 119 ... Error path selection detection position, 120 ... Transmission recording code sequence (information code sequence), 120a to 120c
... Transmission recording information code block (information code block), 1
21: channel transmission code sequence, 121a to 121c: transmission code block, 122a to 122c: error check code sequence, 123, 123 (1), 123 (2): decoding reliability flag, 123a: code replacement reference position pointer, 123
b: code replacement start position pointer, 124: code replacement pointer sequence, 125: decoded code candidate block list, 12
5a to 125c: decoded code candidate blocks, 126, 16
a to 126c: decoded code candidate block sequence, 127: deterministic decoded code sequence, 127a to 127c: deterministic decoded code block, 128: maximum likelihood sequence decoding circuit output information, 2
00a: branch metric calculation unit, 200b: ACS
Arithmetic unit, 200c: path memory unit, 201: square error arithmetic circuit, 202a to 202h: metric storage circuit, 2
03: metric cumulative addition circuit, 204: comparator, 20
5: selection signal, 206: metric selection circuit, 207a
To 207h: path history storage circuit, 208, 208a to 2
08h: Path history selection circuit, 210a, 210a
(1), 210a (2)... Flag generation unit, 210b, 2
10b (1), 210b (2)... Flag memory unit, 21
1: absolute value calculation circuit, 212: reliability flag determination threshold value, 213: comparator, 214, 214 (1), 214
(2): reliability flag, 215a to 215c: flag history storage circuit, 216, 216 (a), 216 (b): flag history selection circuit, 217: difference metric absolute value, 21
8, 218 (a), 218 (b) ... difference metric selection circuit, 219 ... difference metric selection circuit, 220 ... storage circuit initial value, 221 ... flag determination logic element, 222 ... match detection circuit, 223 ... path history convergence position Detector circuit, 224 ...
Convergence position information, 225: flag selection circuit, 300: transmission / recording information code sequence, 301: coding circuit, 302: check code addition circuit, 303a: check code generation circuit, 303
b: check code insertion circuit, 304: transmission / recording / reproduction signal transmission system, 305: transmission / recording code signal processing system, 305a ...
Code processing circuit, 305b ... Code signal conversion circuit (modulation),
305c: transmission / recording signal processing circuit, 306: transmission / recording / reproduction channel, 307: reception / reproduction signal processing circuit, 3
08: maximum likelihood sequence decoding circuit, 309: decoded code candidate block list generation circuit, 309a: decoded code processing circuit, 309b: code replacement pointer generation circuit, 309c ...
Decoding code candidate block generation circuit, 310 (1) to (n)
... Decoding code candidate block, 311 ... Code error check circuit,
312a ... decoded code candidate block selection signal, 312b ...
Error decoding block flag, 313: decoding code candidate block selection circuit, 314: code demodulation circuit, 315: reception / reproduction information code sequence, 400: recording code, 401: code / modulation circuit, 403: code processing circuit, 404: recording Current conversion circuit, 405: recording amplifier, 406: recording head, 40
7 playback head, 408 recording medium, 409 recording / playback channel, 410 playback signal processing circuit, 411 playback amplifier, 412 variable gain amplifier, 413 low-pass filter, 414 analog / digital converter, 415 ... Equalizer, 416 ... Timing extraction / gain control circuit, 416
a: sample timing signal, 416b: gain control signal, 418: demodulator, 419: reproduced code.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Naoya Kobayashi 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (32)

[Claims] 1. A signal decoding method for converting an input signal sequence into a decoded code sequence by using a maximum likelihood sequence estimation method (age-likelihood decoding method, Viterbi decoding method), wherein (1) the maximum likelihood sequence estimation method Output the first decoded code sequence having the maximum likelihood with respect to the input signal sequence, and generate a sequence of decoding reliability flag information corresponding to each code position of the decoded code sequence. (2) With reference to the code position indicated by the sequence of the decoding reliability flag information, the code sequence on the decoded code sequence at a predetermined relative position is replaced with reference to a preset replacement code sequence. Thereby, generating a predetermined number of decoded code candidate sequences different from the first decoded code sequence, (3) from the first decoded code sequence and the predetermined number of decoded code candidate sequences generated in (2) From a set of code sequences The predetermined selection means selects one of the code sequences, the signal decoding method characterized in that due to output as decoded code results in (1) (2) (3). 2. The signal decoding method according to claim 1, wherein the decoding reliability flag information sequence according to claim 1 is selected for each decoding code sequence selection process at each decoding operation unit time by the maximum likelihood sequence estimation method. On the surviving path sequence corresponding to the first decoded code sequence, based on the magnitude of the likelihood difference between the path sequence likelihood of the selected surviving path sequence and the path sequence likelihood of the rejected path sequence. A signal decoding method which is generated and indicates whether or not there is reliability in a decoding code sequence selection process at each decoding operation unit time. 3. The signal decoding method according to claim 2, wherein the decoding reliability flag information sequence according to claim 1 (1) determines whether the magnitude of the likelihood difference is equal to or less than (or less than) a predetermined reference value. A signal decoding method, which is generated by determining whether the reliability of the decoding code sequence selection process at each decoding operation unit time is high or low. 4. The signal decoding method according to claim 2, wherein the decoding reliability flag information sequence according to claim 1 (1) is such that the magnitude of the likelihood difference is determined for each predetermined decoding operation period. Is generated by determining whether or not the value is smaller than the n-th or less (n is a predetermined natural number), and indicates whether or not the reliability of the decoding code sequence selection processing at each decoding operation unit time is present. A signal decoding method characterized in that: 5. The signal decoding method according to claim 1, wherein
(A) In an information code sequence corresponding to an input signal sequence to the signal decoding method before passing through a channel of an information transmission system, an error detection code sequence is generated for each code block unit having a predetermined code length of the information code sequence. The error detection code sequence is inserted and added at a predetermined position corresponding to the code block on the information code sequence. (B) The selection processing according to claim 1 (3), (C) requesting the decoded code sequence and the decoded code candidate sequence in units of a decoded code block corresponding to the code block unit in synchronization with the above code string block unit. The selection process of item 1 (3) is performed on the information code sequence corresponding to the decoded code block in (a) with respect to the unit of the decoded code block on the decoded code sequence and the decoded code candidate sequence. The corresponding sign of (A) and (b) that the selection is determined based on whether or not a code error is detected in the decoding code block using the error detection code string added to the lock. And (c) a signal decoding method. 6. The signal decoding method according to claim 5, wherein the error detection code sequence inserted and added in claim 5 (a) is a regular decoded code sequence by the replacement code sequence in claim 1 (2). Is configured to be able to detect that all the first code error sequences resulting from the permutation processing are present up to a predetermined number or less, and the first code error sequence is determined by the permutation code sequence according to claim 1 (2). A signal decoding method characterized in that it is configured to be able to detect that all the second code error sequences generated by performing the replacement processing on an error sequence are present up to a predetermined number or less. 7. The signal decoding method according to claim 1, wherein
3. The signal decoding method according to claim 1, wherein the replacement code sequence used in claim 1 is selected by referring to a code sequence to be replaced on the first decoded code sequence. Method. 8. The signal decoding method according to claim 1, wherein
The decoding reliability flag information sequence generated in claim 1 (1) is rejected as a surviving path sequence to be selected for each decoding code sequence selection process at each decoding operation unit time by the maximum likelihood sequence estimation method. Whether the information indicating the path sequence code length of the different sequence part between the path sequences is added, or the path sequence code length is different from the decoding reliability flag information sequence in synchronization with the information. A signal output as a sequence, and wherein the permutation code sequence used in claim 1 (2) is selected by referring to the path sequence code length. Decryption method. 9. The signal decoding method according to claim 1, wherein
3. The permutation used in claim 1 (2), wherein a code information transmission channel having a signal output of 0 is provided at the preceding stage of the maximum likelihood sequence estimation process with respect to the input of the same and continuously inverted binary information code sequence. A signal decoding method using a continuous code error sequence having a predetermined code length or less as a code sequence. 10. A signal decoding method according to claim 5, wherein a code information transmission system channel having a signal output of 0 with respect to an input of the same and continuously inverted binary information code sequence is subjected to the maximum likelihood sequence estimation processing. Wherein a continuous code error sequence having a predetermined first code length or less is used as the replacement code sequence used in claim 1 (2), and in claim 5 (a).
3. The signal decoding method according to claim 1, wherein an error detection code for detecting a continuous code error sequence having a length equal to or less than the first code length is used. 11. A signal decoding method according to claim 9, wherein a continuous code inversion of a code length exceeding a predetermined second code length is performed on the binary information code sequence input to the code information transmission channel. A signal decoding method, wherein a prohibition constraint is added. 12. The signal decoding method according to claim 11, wherein the second code length is set to be equal to or less than the first code length. 13. The signal decoding method according to claim 1, wherein in the selection processing according to claim 5 (c), any one of the decoding code sequences and any of the decoding code candidate sequences to be subjected to the selection processing is selected. A signal decoding method characterized in that when a code error is also detected from a decoded code block, the error detection flag information is output in synchronization with the output of any of the decoded code blocks. 14. A signal decoding method according to claim 13, wherein the output of said error detection flag information is used to perform erasure error correction processing on a code string in a specific decoding code block indicated by said error detection flag information. A signal decoding method characterized by performing. 15. The signal decoding method according to claim 13, wherein an output of said error detection flag information is used, and an input signal sequence portion corresponding to a specific decoded code block indicated by said error detection flag information, or A signal decoding method characterized by re-inputting an input signal sequence having a predetermined length including an input signal sequence portion and repeating the signal decoding method. 16. A signal decoding circuit for converting an input signal sequence into a decoded code sequence using a maximum likelihood sequence estimator (year-old likelihood decoder, Viterbi decoder), wherein (4) the maximum likelihood sequence estimator Is
A signal output unit that outputs a first decoded code sequence having the maximum likelihood with respect to the input signal sequence, and a sequence of a decoding reliability flag signal corresponding to each code signal output of the decoded code sequence. And (5) providing a flag signal generating and outputting means for outputting the decoding reliability flag signal in synchronization with each other together with each code signal output of the decoding code sequence during the decoding operation. Using the sequence of degree flag information, the code sequence on the decoded code sequence at a predetermined relative position is replaced in accordance with a predetermined replacement code sequence with reference to the code position indicated by the decoding reliability flag information. (6) the first decoded code sequence and the code sequence generating circuit means for generating code sequence generating circuit means for generating a predetermined number of decoded code candidate sequences different from the first decoded code sequence. And a buffer storage circuit for holding a predetermined number of code sequences consisting of the decoded code candidate sequence generated by the above, and a predetermined selection from the code sequences held in the buffer storage circuit. (4) and (5), further comprising: selecting means for selecting one code sequence by the means, and outputting a signal of the code sequence selected by the selecting circuit means as a decoded code result.
A signal decoding circuit according to (6). 17. The signal decoding circuit according to claim 16, wherein said maximum likelihood sequence estimator is a path sequence likelihood of a surviving path sequence selected in a maximum likelihood path sequence comparison and selection process at each decoding operation unit time. And a flag signal generation and output means according to claim 16 (4), further comprising: an arithmetic circuit for calculating the magnitude of the likelihood difference between the path sequence likelihood of the rejected path sequence. And outputs a decoding reliability flag signal in synchronization with each code signal output of the decoded code sequence output at each decoding operation unit time. A signal decoding circuit characterized in that: 18. The signal decoding circuit according to claim 17, wherein the flag signal generation and output means according to claim 16 is characterized in that the magnitude of the likelihood difference as an operation output result from the operation circuit is equal to or less than a predetermined reference value. (Or less) is provided, and a decoding reliability flag is generated based on a calculation output result from the comparison determination calculation circuit. A signal decoding circuit for outputting in synchronization with each code signal output of the decoded code sequence output at a decoding operation unit time. 19. The signal decoding circuit according to claim 17, wherein the flag signal generation and output means according to claim 16 (4) outputs the likelihood difference of the operation output result from the operation circuit every predetermined decoding operation period. Comparing and calculating means for determining whether or not the size is smaller than an n-th or less value (n is a predetermined natural number) within the decoding operation period; Generating a decoding reliability flag based on the above, and outputting the decoding reliability flag signal in synchronization with each code signal output of the decoded code sequence output at each decoding operation unit time. A signal decoding circuit characterized by the following. 20. The signal decoding circuit according to claim 16, wherein (d) an information code sequence corresponding to an input signal sequence to said signal decoding circuit before passing through a code information transmission system channel includes:
An error coder that generates an error detection code sequence for each unit of a code block having a predetermined code length of the information code sequence as a processing circuit before transmission that receives the information code sequence;
17. The apparatus according to claim 16, further comprising code processing circuit means for inserting and adding said error detection code string to a predetermined position corresponding to said code block on said information code sequence. Synchronizes with the unit of the code sequence block on the information code sequence, and selects the decoded code sequence and the decoded code candidate sequence in units of the decoded code block corresponding to the unit of the code block. (F) the selecting circuit means of (16) corresponds to the decoded code block in (d) with respect to the unit of the decoded code block on the decoded code sequence and the decoded code candidate sequence. An error detector that performs a code error detection using the error detection code string added to the code block on the information code sequence to perform a selection operation based on a detection result output signal from the error detector. It is shall, of (d) above
(E) A signal decoding circuit according to (f). 21. The signal decoding circuit according to claim 20, wherein the error detection code string inserted and added by the code processing circuit according to claim 20 (d) is represented by the permutation code sequence according to claim 16 (5). The replacement code sequence according to claim 1 (2) is configured to be able to detect that all the first code error sequences generated by performing the replacement process on the regular decoded code sequence exist up to a predetermined number or less. A signal decoding circuit configured to be able to detect that all second code error sequences generated by performing the permutation process on the first code error sequence are present up to a predetermined number or less. 22. A signal decoding circuit according to claim 16, wherein the code string generation circuit according to claim 16 (5) refers to a code sequence portion to be subjected to the replacement process on the first decoded code sequence. Code string discriminating circuit means for discriminating the code string portion, and a code string selecting circuit for selecting a specific permutation code sequence to be used for the permutation process from a plurality of permutation code sequences based on the discrimination result by the code string discrimination circuit means With means,
A signal decoding circuit for performing the replacement process using a replacement code sequence selected by the code string selection circuit means. 23. A signal decoding circuit according to claim 16, wherein said maximum likelihood sequence estimator is a path sequence of a surviving path sequence selected in a maximum likelihood path sequence comparison and selection process at each decoding operation unit time. 17. The flag signal generation method according to claim 16, further comprising: a path sequence code length determination circuit for determining a path sequence code length of a different sequence portion between the likelihood and the path sequence likelihood of the rejected path sequence. The output means adds the information on the path sequence code length from the path sequence code length determination circuit means to the decoding reliability flag signal output at each decoding operation unit time corresponding to the information and outputs the result. Or outputting the information of the path sequence code length in synchronization with each flag signal output of the decoding reliability flag information sequence output at each decoding operation unit time. Signal decoding circuit. 24. The maximum likelihood sequence estimator according to claim 16 or 19, wherein a code information transmission system channel having a signal output of 0 with respect to the input of the same and continuously inverted binary information code sequence is provided. 17. A signal decoding circuit comprising a continuous code error sequence having a predetermined first code length or less as the replacement code sequence used in the preceding step of (16). 25. The maximum likelihood sequence estimator according to claim 20, wherein a code information transmission system channel having a signal output of 0 with respect to the input of the same and continuously inverted binary information code sequence is provided. 21. A continuous code error sequence having a predetermined first code length or less is used as the replacement code sequence used in claim 16 and used in claim 16 (5).
The signal decoding circuit according to (d), wherein an error detection code for detecting a first consecutive code error sequence having a length equal to or less than the code length is used. 26. The signal decoding circuit according to claim 24, wherein the binary information code sequence input to the code information transmission channel includes a processing circuit means before the transmission using the information code sequence as input. A signal decoding circuit comprising an information code processing circuit for adding a constraint condition for prohibiting continuous code inversion of a code length exceeding a predetermined second code length. 27. The signal decoding circuit according to claim 26, wherein the second code length is set to be less than or equal to the first code length. 28. The signal decoding circuit according to claim 16, wherein, in the selection processing of claim 20 (f), any one of the decoding code sequences and any of the decoding code candidate sequences to be subjected to the selection processing is selected. When a code error is also detected from the decoded code block, a flag output means for outputting error detection flag information in synchronization with the output of any of the decoded code blocks is provided. Signal decoding circuit. 29. A signal decoding circuit according to claim 28, wherein the error detection flag information output from said flag output means is used to erase a code string in a specific decoding code block indicated by said error detection flag information. A signal decoding circuit comprising a code error correction circuit for performing a code error correction process. 30. An input signal sequence corresponding to a specific decoded code block indicated by the error detection flag information, using the error detection flag information output from the flag output means in the signal decoding circuit according to claim 28. A signal decoding circuit for re-inputting a portion or an input signal sequence of a predetermined length including the input signal sequence portion and repeating the signal decoding operation. 31. An information transmission communication apparatus comprising the signal decoding circuit according to claim 1. 32. An information storage / reproduction apparatus comprising the signal decoding circuit according to claim 1.