JP3474104B2 - Scan converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan converter used when image data of an arbitrary input side image display system is input and output to a display device of a predetermined output side image display system.

[0002]

2. Description of the Related Art Display devices of a general computing system are required to have various sizes and various resolutions due to problems in use and installation space. For example, if you want to enjoy multimedia software with a large image, use the resolution of 640 x 480 dots, while you want to view as much information as possible on a single screen for your work, or by visual observation with the naked eye. In order to reduce fatigue, it is desirable to display at the highest resolution possible. Also, in connection with the recent development of multimedia technology in computing systems and the start of digital television broadcasting services, there will be cases where the computing system at home and television broadcasting will not be separated in the near future. It is expected that it will be more important to convert image signals of different sync frequencies to each other to match the image display of different sync frequencies between the computing system and the television broadcast receiver. Is becoming.

As described above, a scan converter is usually used as an interface for mutually converting image signals having different plural kinds of synchronizing frequencies.

In general, the scan converter is a display device such as a flat panel display such as a liquid crystal display or a plasma display after converting the horizontal synchronizing frequency according to the image data Sin input from the input source device as shown in FIG. It outputs to 1. At this time, for example, as a display system of the signal of the input source, as shown in FIG. 9, XGA, SVGA, VGA and VTX
There are various types such as T, and the horizontal synchronizing frequency (H) and the vertical synchronizing frequency (V) in these systems depend on factors such as the state of the art at the time these systems were developed.
It is set variously like. Therefore, the main function of the scan converter is to adjust the signals of various frequencies to synchronize with the display device.

In this scan converter, as shown in FIG.
Like RGB (red, green, blue) signal, YUV (luminance component, RY color difference component, BY color difference component) signal, or Y
When predetermined image data such as a CrCb (gamma converted luminance / color difference separation color system) signal is input from the input source device, the first pixel processing unit 11 performs pixel thinning processing as necessary, Image data for one screen (frame) is stored in the frame memory 13 through the memory controller 12. Then, after the image data is read again by the memory controller 12, the second pixel processing unit 1 is read if necessary.
The pixel is padded with 4 and YUV signal or YCrCb
The signal is input to the color format conversion unit 15 and converted into an RGB signal. Then, after the brightness and contrast are adjusted by the brightness / contrast adjusting unit 16, the linearity of the adjustment change of the color different for each display device is corrected by the gamma correcting unit 17,
Dithering section 1 performs approximate color correction when there are few display colors.
Do in 8. Then, the predetermined display adjustment display is image-synthesized and controlled by the on-screen display synthesis unit 19. After that, the output adjustment unit 20 outputs 24-bit RGB signals to each of the odd-numbered port corresponding to the odd-numbered pixel and the even-numbered port corresponding to the even-numbered pixel corresponding to the port format of the display device of the display device 1. Are output alternately. All of these image processing operations are executed by the CPU 21 according to a predetermined software program (driver device).

Here, at least two PLL circuits 22 and 23 are incorporated in the scan converter.
One of the PLL circuits 22 is used for synchronization until the first pixel processing unit 11 reads the image data and then the memory controller 12 writes the image data in the frame memory 13. The other PLL circuit 23 is used to synchronize the operation of reading the image data from the frame memory 13 and outputting the image data to the display device 1.
That is, the memory controller 12 causes the frame memory 1
The writing operation of the image data to the No. 3 is performed in synchronization with the signal from the input source device corresponding to the oscillation frequency of the one PLL circuit 22. On the other hand, the operation in which the memory controller 12 reads the image data in the frame memory 13 is
It is executed so as to correspond to the oscillation frequency of the other PLL circuit 23 and to correspond to the operation clock of the display device 1 at the output destination. In this way, the two separate PLL circuits 22 and 23 transmit the operation clocks of different frequencies based on the control of the CPU 21, and the frame memory 1 is based on this.
By executing the reading and writing of the image data with respect to 3 at different clock frequencies, the horizontal synchronizing frequency of the input and output image signals can be easily changed.

[0007]

The capacity of the frame memory 13 used in the above-mentioned scan converter is required to be at least the size of the output device (that is, the display device 1 on the output side), for example, 1024 ×
For a 768-dot screen, 1024 x 768
A capacity of × 24 = 18,874,368 bits is required.

The frame memory 13 is generally expensive, and it has also been a cause of hindering space saving in the circuit configuration.

Therefore, an object of the present invention is to provide a scan converter which can be constructed at low cost by omitting the frame memory.

[0010]

[Means for Solving the Problems] In order to solve the above problems,
The invention according to claim 1 is a scan converter used when image data of an arbitrary input side image display system is input and output to a display device of a predetermined output side image display system, wherein the input side A measuring unit that measures the horizontal synchronizing frequency of the image display system, a timing control unit that converts the horizontal synchronizing frequency into a predetermined integer magnification according to the measurement result of the measuring unit, and one image data related to the input. An image is provided by internally storing a bank for each horizontal scanning line, and repeatedly reading out the horizontal scanning line stored in the bank a predetermined number of times corresponding to the predetermined integer magnification according to the measurement result of the measuring unit. The resolution conversion unit that converts the resolution of the data, and the horizontal synchronization frequency that has been converted to the predetermined integer scaling factor by the timing control unit, are output from the resolution conversion unit. In which an output controller for outputting the image data to the display device.

According to a second aspect of the present invention, the timing control section counts the horizontal synchronizing signal of the horizontal synchronizing frequency with reference to the vertical synchronizing signal input from the input source device, and the count result at this time The display control unit has a function of determining a horizontal scanning line that does not require display according to the measurement result of the measurement unit, and the output control unit determines that the display-free horizontal scanning line is determined by the timing control unit. It is provided with a masking function for stopping the output of the image data related to the scanning line.

According to a third aspect of the present invention, the bank of the resolution conversion unit has an odd buffer for temporarily storing all odd-numbered pixels in each horizontal scanning line, and each bank in each horizontal scanning line. Of an even-numbered pixel for temporarily storing all the even-numbered pixels of the even-numbered pixel, the output control unit outputs the odd-numbered pixel in one line output from the odd-numbered buffer and the even-numbered pixel output from the even-numbered buffer. It is arranged such that even-numbered pixels in the line are output in parallel.

[0013]

[0014]

1 is a diagram showing a scan converter 30 according to an embodiment of the present invention. This scan converter is installed in advance in a multi-display or the like for displaying image information from, for example, a computing system or a television receiver, and is installed from an input source device as shown in FIG. The horizontal synchronizing frequency of the given image data is output to the display device 31 of the output destination.
It is converted so as to match.

Here, in this embodiment, the display device 3 is used.
As an example of the first example, a liquid crystal display panel (LCD) 31a of 1024 × 768 dots is built in, and this LCD 31a
A general liquid crystal display driven by the driver 31b and the Y driver 31c is applied. Here, the display device 31 has two ports, an odd port into which an odd-numbered pixel (odd pixel) in one horizontal scanning line is input and an even-numbered port into which an even-numbered pixel (even pixel) is input. 24 bits of RGB signals are promptly input to each of the odd-numbered port and the even-numbered port. In this way, 24-bit image data (odd pixel and even pixel) are input in parallel to each of the odd port and the even port, and a total of 48 (= 24 × 2) bits are input. Therefore, even if the image data is input at a frequency that is half the display frequency in the display device 31, sufficient synchronization matching can be achieved.

Then, the scan converter 30 is
Pixel data is odd-numbered buffer (1/2 line) 41a,
42a and even buffers (1/2 line) 41b, 42
Since it is written alternately in b, and read out and output in parallel, it is possible to uniformly double the horizontal synchronizing frequency (HSi) related to the image data input to each, and at the same time, the screen By thinning out the end lines that are unnecessary for display, the frame memory (13) and the two P's as in the conventional example shown in FIG.
Even if the LL circuit (22, 23) is omitted, synchronization matching can be achieved without any problem.

That is, the scan converter 30 includes a resolution conversion section 32 for converting the resolution of an external 24-bit RGB signal (RGB24), and attribute information in pixel units from the resolution conversion section 32 as adjacent pixels. A filter 33 that adjusts between the two, an image adjustment unit 34, a frequency divider 36 that divides the synchronization signal from the external PLL 35,
A timing control unit 37 that controls the operation timings of the resolution conversion unit 32 and the image adjustment unit 34 based on a synchronization signal given from an input source, and a horizontal synchronization signal Hsync and a vertical synchronization signal from an oscillator 38 in the input source device. Vsyn
Sync measuring unit 39 (measuring unit) that measures c, and all elements 32, 34, 3 in these scan converters 30.
The CPU 40 controls the CPUs 6, 37 and 39.

As shown in FIG. 2, the resolution conversion section 32 has two banks 41 and 42 which alternately operate for writing and for reading, and each bank 41, 42.
Is an odd-numbered buffer (1/2 line) 41a, 42a in which an odd-numbered pixel (odd pixel) in one horizontal scanning line is temporarily stored, and an even-numbered pixel (even-numbered pixel) is temporarily stored. Even buffers (1/2 line) 41b and 42b are provided. Each of the buffers 41a, 41b, 42a, 42b is
The bit length is set to half the length of one horizontal scanning line. The alternating switching between the two banks 41 and 42 is executed in response to, for example, the fall of the horizontal synchronizing signal Hsync, and one of the banks 41/42 is connected to the input terminal 43 through the switch 43a for writing image data. When operating, the other bank 42/41 is connected through the switches 45a and 45b to the connection terminal 4 on the filter 33 side.
4a and 44b are connected to operate for reading image data. In addition, the switch 43a is connected to one of the banks 4
In the state where the odd buffers 41a and 42a are connected, the odd-numbered buffers 41a and 42a are input every clock, that is, each pixel (pixel) in one horizontal scanning line is input.
And the even-numbered buffers 41b and 42b are alternately switched.
As a result, each odd buffer 41 of each bank 41, 42
Only odd pixels are stored in a and 42a, and only even pixels are stored in each even buffer 41b and 42b. The switching operation of these switches 43a, 45a, 45b is executed according to an operation control signal from the timing control section 37.

Although an analog RGB signal (A-RGB) is originally output from the input source device, this analog RGB signal (A-RGB) is output by an analog / digital converter (ADC) 46. After being converted into a 24-bit digital RGB signal (RGB24), it is input to the resolution conversion unit 32. Here, FIGS. 1 and 2 show an example using a single ADC.
When the processing speed of the DC 46 is slower than the processing inside the scan converter 30, two analog / digital converters are used in parallel and a 24-bit length digital RGB signal (RGB24) is resolved in parallel. Converter 32
May be input to. In this case, each of the pair of analog / digital converters (ADC) may be connected to each of the odd number buffers 41a, 42a and each of the even number buffers 41b, 42b of each bank 41, 42 via a switch.

The filter 33 is a circuit for performing a pixel smoothing process or other pixel adjustment by performing a weighting calculation process on each pixel with other neighboring pixels that are input prior to the pixel 33. An odd pixel calculation unit 51 that performs processing on odd pixels and an even pixel calculation unit 52 that performs processing on even pixels are provided. Each of the pixel calculation units 51 and 52 has five dot buffers (1 dot) for temporarily storing pixel data for one pixel.
53 to 58, two line buffers (1 line) 59 and 60 having a storage capacity of the number of dots for one line, pixel data from each of these buffers 55 to 60, and the latest input from the resolution conversion unit 32. 9 with the rendered pixel data
Multipliers 61 to 69 for weighting individual data and adders 71 to 71 for adding outputs from all the multipliers 61 to 69.
74 and an output control unit 75 for outputting the data output from the adders 71 to 74 to the image adjustment unit 34.

The first dot buffer 53 and the second dot buffer 53 are connected in series to form the switches 45a, 4a.
It is connected to the resolution conversion unit 32 via 5b. As a result, the first dot buffer 53 stores the pixel data input one clock ahead of the latest pixel data input from the resolution conversion unit 32, and the second dot buffer 54 sets the resolution Pixel data input two clocks ahead of the latest pixel data input from the conversion unit 32 is stored.

As described above, the line buffers 59 and 60 each have a storage capacity for the number of dots for one line, but the data input from the resolution conversion unit 32 is the same for the odd pixel calculation unit 51. Since there are only odd pixels and even pixels for the even pixel calculation unit 52, only half the pixel data per one horizontal scanning line is stored. Therefore, the first line buffer 59 having a storage capacity for the number of dots for one line stores the odd pixels in the two horizontal scanning lines and then sequentially outputs them, and the second line buffer 59 also outputs the odd pixels. The buffer 60 stores even pixels in two horizontal scanning lines and then outputs them in sequence. As a result, the first line buffer 59 and the second line buffer 59
In the line buffer 60, the odd-numbered pixels or even-numbered pixels for each skipped horizontal scanning line are stored and then output.

Then, the third dot buffer 55 and the fourth dot buffer 56 are connected in series and connected to the first line buffer 59. As a result, the third dot buffer 55 stores the pixel data output one clock earlier than the latest pixel data output from the first line buffer 59, and the fourth dot buffer 56 stores Pixel data output prior to the latest pixel data output from the first line buffer 59 by two clocks is stored.

Further, the fifth dot buffer 57 and the sixth dot buffer 58 are connected in series and connected to the second line buffer 60. As a result, the fifth dot buffer 57 stores the pixel data output one clock earlier than the pixel data output most recently from the second line buffer 60, and the sixth dot buffer 58 stores Pixel data that is output two clocks ahead of the latest pixel data that is output from the second line buffer 60 is stored.

The multipliers 61 to 69 are the latest pixel data input from the resolution converter 32 and the buffers 53 to 6 respectively.
Count k for each pixel data output from 0
The weighting is performed by integrating 1 to k9. Also,
The adders 71 to 74 add the data weighted by the multipliers 61 to 69 to determine pixel data adjusted between adjacent pixels. That is, the multiplier 61
Up to 69 and the additions in the adders 71 to 74, the latest pixel data input from the resolution conversion unit 32 corresponds to the two previously input pixels in the horizontal direction and these pixels. Adjustments such as pixel smoothing processing by weighting are performed using the pixels that are input earlier by two lines .

The output control section 75 is a timing control section 37.
According to the instruction control from the
4, the masking function is provided to stop the output of pixel data to the image adjusting unit 34 in accordance with an instruction from the timing control unit 37, particularly in the “thinning process” in units of scanning lines described later. .

Incidentally, each pixel calculation unit 5 in the filter 33
All the operations in 1, 52 are executed based on the timing control signal from the timing control unit 37.

The image adjustment unit 34 includes a color format conversion unit (15), a brightness / contrast adjustment unit (16), a gamma correction unit (17) and a dithering unit (1) in the conventional example shown in FIG.
8) and a circuit corresponding to the on-screen display combining section (19).

As shown in FIG. 1, the frequency divider 36 receives a signal from the PLL 35 in the device which is the input source, and outputs this signal to, for example, 1 /
It is converted to 2 times the frequency of the signal Ru der used to input to the PLL 35. The signal from the PLL 35 is the timing control unit 3
It is taken into 7 and used as an operation base clock for various timing controls.

The sync measuring section 39 obtains a base clock from the oscillator 38 on the circuit board on which the scan converter 30 is mounted, compares the base clock with the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync,
The synchronization frequency attribute of the input source device is determined, and the result is transmitted to the timing control unit 37. The sync frequency attribute of the input source device determined here is, for example, VGA or S.
It is an attribute of a frequency characteristic value preset for each predetermined image display method such as VGA, and makes a determination according to data in a predetermined table stored in a non-volatile ROM or the like.

The timing control section 37 uses the signal given from the PLL 35 as an operation clock, and the Sync measuring section 3
The timings of the resolution conversion unit 32 and the filter 33 are controlled in accordance with the synchronization frequency attribute of the input source device given from 9. For example, when the image display method of the image signal from the input source device is XGA and the synchronization frequency is matched from the beginning with the output destination display device 31, the resolution conversion unit 32. Also, a synchronizing signal having the same cycle as the horizontal synchronizing signal Hsync from the input source device is applied to the filter 33 so that the input / output synchronization frequency is not changed, while the image signal from the input source device is changed. If the image display system is VGA or SVGA,
In the case where the synchronizing frequency is changed with respect to the output destination display device 31, the resolution converting section 32 and the filter 33 are changed with respect to the input / output synchronizing frequency.

Here, as shown in FIG. 3, a thinning-out timing control circuit 77 for thinning out horizontal scanning lines which need not be output when the scan converter 30 outputs to the display device 31 is built in the timing controller 37. ing. The thinning-out timing control circuit 77 determines whether or not to thin out the output of the image data line by line, based on the horizontal synchronization signal Hsync given from the input source device and the information about the determination result in the Sync measuring unit 39. A judgment unit 78, a thinning signal output unit 79 for outputting a thinning signal according to the output from the thinning line judgment unit 78,
The thinned-out signal output unit 79 is provided with an output control unit 75 of the filter 33 and a synchronization signal output stop unit 80 that stops the output of the horizontal synchronization signal Hsync to the display device 31 when the thinned-out signal is output.

The thinning-out line determining section 78 counts the horizontal synchronizing signal Hsync with the input of the vertical synchronizing signal Vsync provided from the input source device as a base point, and the currently input image is the horizontal scanning line. It is a counter that recognizes whether or not. It should be noted that when the count value in the thinned-out line determination unit 78 reaches a value of "0", this is transmitted to the thinned-out signal output unit 79 as a signal for all of the plurality of lines.

The thinning-out signal output unit 79 has a function of judging whether or not the horizontal scanning line counted by the pattern comparing unit 28 is a line to be thinned out according to the judgment result of the Sync measuring unit 39. When it is necessary to thin out, it has a function of outputting a low signal as a thinning signal to the synchronizing signal output stopping unit 80, and transmitting a high signal to the synchronizing signal output stopping unit 803 in other cases.

More specifically, for example, in the case of a simple operation of thinning out only one line of the count values of all the lines in the thinning-out line judging unit 78, the thinning-out line judging unit 78 inputs The OR circuit that recognizes the count value when the counted value becomes "0" value and all the plurality of lines given from this point become "0" value is applied.

On the other hand, in the case of a complicated operation such as thinning out a plurality of lines out of the count values of all the lines in the thinning-out line judgment unit 78, only a simple OR circuit is used as the thinning-out signal output unit 79. It is difficult to determine the proper timing for thinning out only by performing the steps. In this case, the data length of one line of the input image data and the data length of one line of the output image data are limited to a combination of several types corresponding to the type of image display method. If the prepared several types of combinations are prepared as a data table, the thinning line can be determined efficiently. In this case, a non-volatile storage device is provided inside or outside the thinning-out signal output unit 79, and information of the thinning-out line according to the synchronization frequency attribute of the input source device is stored in advance as a data table in this non-volatile storage device. Then, it is sufficient to refer to this data table and determine whether or not it is necessary to thin out the data according to the count result.

The synchronizing signal output stop unit 80 is a logical product circuit for calculating the logical product of the output signal from the thinning signal output unit 79 and the horizontal synchronizing signal Hsync, and the signal from the thinning signal output unit 79 is a high signal. If there is, the horizontal synchronizing signal Hsync is output to the output control unit 75 and the display device 31, while if the signal from the thinning signal output unit 79 is a low signal (thinning signal), the horizontal synchronizing signal Hs is output.
It outputs a low signal regardless of the high / low state of sync.

The operation of the scan converter having the above configuration will be described. First, in the case where the image display system of the image signal from the input source device is XGA, the output destination display device 3
When the synchronization frequency is matched from the beginning to 1, the timing control unit 37 synchronizes the resolution conversion unit 32 and the filter 33 with the same cycle as the horizontal synchronization signal Hsync from the input source device. Apply a signal and do not change the input / output synchronization frequency. At this time, the input horizontal synchronization signal Hsync (input Hsync) 8
1 and the horizontal synchronization signal Hsync (output Hs
ync) 82 is as shown in FIG. In FIG. 4, the total number of horizontal scanning lines related to input / output is 7 for the sake of simplicity.
Although it is a book, the number is actually much larger than this.

On the other hand, when the image display system of the image signal from the input source device is VGA or SVGA and the synchronizing frequency is changed with respect to the output destination display device 31, the timing control section is used. Reference numeral 37 causes the resolution conversion unit 32 and the filter 33 to change the input / output synchronization frequency. FIG. 5 shows an example in which the total number of horizontal scanning lines related to output is 1.8 times the total number of horizontal scanning lines input. In FIG. 5, the input Hsyn
The image data input according to c is output H and output H
Image data output according to sync is indicated by reference numeral 84. Reference numeral 85 indicates the output timing of the output image data in the conventional example. The block delimiters in these image data indicate the horizontal scanning lines in each image data. In FIG. 5, for simplicity of explanation, the total number of horizontal scanning lines for input is set to 5 and the total number of horizontal scanning lines for output is set to 9; It goes without saying that the number is large.

Conventionally, as shown in FIG. 5, the final line (fifth line) Li5 relating to the input image data 83
The end timing of the output image data 85 and the end timing of the final line (9th line) Lpo9 of the output image data 85 are made to coincide with each other. In connection with this, the output image data 85 is not exactly twice the frequency of the input image data 83 for each line period, and in the example of FIG. 5, the ratio of these line periods is 5: It is 9.
For this reason, it has been necessary to perform complicated control as to what kind of data is assigned to each pixel in each line (“1” to “9”) of the conventional output image data 85.

On the other hand, in this embodiment,
Assuming that the frequency of the input Hsync is HSi and the frequency of the output Hsync is HSo, the relationship of “HSo = 2 × HSi” is established, and as a result, the output image data 84 is exactly twice the frequency of the input image data 83. Therefore, the line cycle ratio is 1: 2. The timing of the end of the last line (9th line) Lso9 of the output image data 84 does not match,
After this last line (9th line) Lso9, there is a time during which thinning processing is performed. That is, in the time period in which the thinning processing is performed, the output of the pixel data from the output control unit 75 to the image adjusting unit 34 is not performed under the control of the timing control unit 37. Therefore, in the display device 31, the time period of the thinning processing is performed. Nothing is displayed on the horizontal scanning line corresponding to.

Further, since the ratio of the line periods of the output image data 84 and the input image data 83 is 1: 2, which is simpler than the conventional one, the odd-numbered line ("1") in the output image data 84 is reduced. "3", "5", "7") and even-numbered lines ("2", "4", "6") following each
If "8") is simply arranged in the same pixel array, it is possible to easily achieve pixel matching without performing complicated pixel rearrangement.

The operation in the scan converter 30 at this time will be described in detail. The following operations in the scan converter 30 are all achieved by the CPU 40 controlling the respective elements 32, 33, 34, 35, 37, 39 according to a predetermined driver program.

First, the sync measuring section 39 compares the horizontal sync signal Hsync and the vertical sync signal Vsync provided from the input source device with the base clock signal from the oscillator 38 to determine the sync frequency attribute of the input source device. Judge,
The result is transmitted to the timing control unit 37. On this occasion,
For example, the image display system of the input source device is the XGA system, and the synchronization frequency HSi of the horizontal synchronization signal Hsync is 5
In the case of 8 KHz, the timing control unit 37 is shown in FIG.
As described above, the filter 33 and the image adjustment unit 34 are operated at the same frequency HSi as the input synchronization frequency HSi to output the image data to the display device 31. On the other hand, for example, the image display system of the input source device is the VGA system, and the synchronization frequency HSi of the horizontal synchronization signal Hsync is 32 KH.
In the case of z, in the timing control unit 37, the frequency HSi (64K
Hz), and the image display method of the input source device is SVGA
And the horizontal synchronizing signal Hsync has a synchronizing frequency HSi of 48 KHz, the timing controller 37
Then, as shown in FIG. 6, the filter 33 and the image adjustment unit 34 are operated at the frequency HSi (96 KHz) that is twice the input synchronization frequency HSi to output the image data to the display device 31.

In the resolution conversion unit 32, as shown in FIG. 2, the banks 41 and 42 are switched to switch 43 for each line.
While alternately switching between a, 45a, and 45b, the image data from the input source device is temporarily written and read out to the filter 33 for output. At this time, the odd-numbered buffers 41a and 42a and the even-numbered buffers 41b and 4 are set for each pixel.
2b, and odd-numbered pixels in one line are changed to the odd-numbered buffer 41 as shown in "(3) Write Line buf" in FIG.
a, 42a, and “(4) Write Li in FIG.
even buffer 41b, such as "ne buf"
After writing in 42b, each reading is performed ("(5) (6) Read Line buf" in FIG. 7).

Incidentally, in FIG. 7, as shown in FIG.
~ Input horizontal sync signal H for 6 lines of "F"
It shows a state of operating according to sync ((1) in FIG. 7). However, in (3) to (11) in the figure, the six pixels of "0" to "5" are odd pixel "0".
An example is shown in which processing is divided into “2” and “4” and even-numbered pixels “1”, “3”, and “5”, but in reality, one horizontal scanning line is configured with a pixel number far larger than six. Of course.

At this time, "(5) (6) Read Line bu
In “f”, odd-numbered pixel columns arranged one by one ((3) Write Line buf = “0” “* (blank data)”)
"2", "*", "4", "*") and even pixel rows ((4)
Write Line buf = "*""1""*""3""*"
For each "5"), only the part excluding "*" is extracted and each is read twice. That is, the blank data “*” is packed, and as a result, the half cycle line data compressed into half cycle data is read out twice, and (5) Read L
ine buf = "0""2""4""0""2""4" and (6) Read Line buf = "1""3""5""1"
It is converted into data of "3" and "5".

Each pixel calculation unit 51, 5 of the filter 33
2, the pixel data is temporarily stored in the buffers 53 to 60, and then the multiplier 61 is used at each timing.
To 69 to be weighted by predetermined counts k1 to k9, and then added by adders 71 to 74. As a result, a smooth image can be obtained in both the horizontal and vertical directions, and the image quality is improved. The output result of the filter 33 is “(7) (8) Filter o in FIG.
ut ”.

In parallel with the above operation, in the timing control section 37, the horizontal synchronizing signal Hs is input from the input source device.
Each time ync is input, the thinning line judgment unit 7
8, and the thinning-out signal output unit 7
The horizontal scanning line that needs to be thinned out is discriminated by 9 and if necessary, the data table is referred to and the like is output to the output control unit 75 and the display device 31 through the synchronization signal output stop unit 80.

Here, as a result of the judgment by the timing control unit 37, when the thinning processing is not performed, the thinning signal output unit 79 outputs "1 (high signal)" to the synchronization signal output stopping unit 80. . In the sync signal output stop unit 80, the horizontal sync signal Hsync is output to the output control unit 75 and the display device 31 as it is while the “1 (high signal)” is given from the thinning signal output unit 79.

In this way, when the thinning processing is not performed,
In the processing for the horizontal scanning lines of “A” to “D” and “F” in FIG. 7, each image data is output to the image adjusting unit 34 in accordance with the instruction signal from the timing control unit 37, and the image adjusting unit 34. After a predetermined process is performed by the display device 3 as shown in "(9) (10) Output image data" in FIG.
It is output to 1. In parallel with this, the scan converter 30 outputs a horizontal synchronizing signal Hsync (“(11) Output Hsync” in FIG. 7) related to the output. Here, the image display method of the input source device is VGA or SVG.
The case of A system is shown, and the horizontal synchronizing signal H related to input is shown.
As compared with the sync frequency of sync, the sync frequency of the horizontal sync signal Hsync relating to the output is doubled because the output processing is performed in parallel on the two lines. In the display device 31, the horizontal synchronization signal Hsync output here (“(11) Output H in FIG.
"(9) (10) output image data" in FIG. 7 is displayed line by line based on "sync").

On the other hand, as a result of the judgment in the timing control unit 37, when it is necessary to perform the thinning-out process, the thinning-out signal output unit 79 (logical sum circuit) causes the synchronization signal output stopping unit 80.
, "0 (low signal)" is output. In the synchronization signal output stop unit 80, when the input signal from the thinning signal output unit 79 is “0 (low signal)”, the horizontal synchronization signal Hsync for the output control unit 75 and the display device 31 is generated.
Is stopped (reference numeral T in (11) in FIG.
1). Then, the output of the image data from the output control unit 75 to the image adjustment unit 34 is stopped as indicated by the symbol T2 of “(9) (10) Output image data” in FIG. No image data is output to the processing and display device 31. Further, during the thinning process, the horizontal synchronization signal Hsy from the timing control unit 37 to the display device 31.
Also, nc is not transmitted. Therefore, the display device 31 does not display the horizontal scanning line corresponding to the thinned-out portion.

As described above, in the resolution conversion unit 32, the image data of one line is divided into an odd pixel and an even pixel and written in the odd buffers 41a and 42a and the even buffers 41b and 42b, respectively, and these are read twice. Since the horizontal frequency is doubled, the large-capacity frame memory (1
The synchronization frequency can be easily converted without using 3). Therefore, the entire scan converter can be provided in a small area and at a low price.

Further, at this time, since the filter 33 performs the pixel adjustment processing by weighting the pixels adjacent to each other in both the horizontal scanning direction and the vertical scanning direction, the image quality can be improved.

In the above embodiment, the pixel data is alternately written in the odd number buffers (1/2 line) 41a, 42a and the even number buffers (1/2 line) 41b, 42b, and each of them is read out and output in parallel. By doing so, the frequency of the horizontal synchronizing signal Hsync is doubled by the timing control unit 37, and the buffers 41a, 41b,
The image data in 42a and 42b were read twice, but the present invention is not limited to this. For example, N or more buffers of 3 or more are used to alternately write the pixel data to them, and these are respectively written. You may make it read and output in parallel to the output destination display apparatus 31 by N lines. In this case, the capacity of each buffer is 1 / Nlin
e is good.

In the above embodiment, the display device 31 is used.
As an example of the above, a 1024 × 768-dot liquid crystal display panel (LCD) was applied, but if it is of a digital input type, for example, a plasma display panel (P
It is okay to apply something like DP). Also,
The screen size is not limited to 1024 × 768 dots, and a large screen display such as 1280 × 1024 dots may be used.

[0057]

According to the first aspect of the present invention, the resolution conversion unit temporarily writes the image data for each horizontal scanning line into the bank, and writes these in an integer number of times (for example, V
The data is read out twice each in the case of GA or SVGA, and the horizontal synchronizing frequency related to the output is converted into an integral multiple of the horizontal synchronizing frequency applied to the input (for example, double in the case of VGA or SVGA), and the display device according to this timing Since the scanning display can be performed by, the matching conversion of the synchronizing frequency can be easily performed without using an expensive large-capacity frame memory as in the related art. Therefore, the entire scan converter can be provided in a small area and at a low price.

According to the second aspect of the present invention, the timing control section counts the horizontal synchronizing signals of the horizontal synchronizing frequency with the vertical synchronizing signal input from the input source device as a reference, and counts the result at this time. According to the measurement result of the measurement unit, the display device side determines the horizontal scanning line that does not require display, and the output control unit outputs the image data related to the horizontal scanning line that does not require display, which is determined by the timing control unit. Since it is stopped, it is possible to easily thin out the end lines that are unnecessary on the screen display and easily match the screen size of the display device.

According to the third aspect of the invention, since the odd-numbered pixels and the even-numbered pixels in one line are output in parallel, various pixel adjustment processes after output are odd-numbered. The processing can be speeded up by separately processing the second pixel and the even pixel, and the data transmission to the display device is performed by transmitting the odd pixel and the even pixel separately. The processing can be made efficient.

[0060]

[Brief description of drawings]

FIG. 1 is a block diagram showing a scan converter and a display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a resolution conversion unit, a filter and the like in the scan converter according to the embodiment of the present invention.

FIG. 3 is a block diagram showing an internal configuration of a timing control unit in the scan converter according to the embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between input image data and output image data when XGA type image data is input according to the embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between input image data and output image data when VGA or SVGA image data is input according to the embodiment of the present invention; and input Hsy.
It is a figure which shows nc and output Hsync.

FIG. 6 is a diagram showing a correspondence relationship between an input horizontal synchronizing frequency and an output horizontal synchronizing frequency in each screen display system according to the embodiment of the present invention.

FIG. 7 is a timing chart showing a processing operation of each image data in the scan converter according to the embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional scan converter.

FIG. 9 is a diagram showing a correspondence relationship between a horizontal synchronizing frequency and a vertical synchronizing frequency of a general screen display system.

[Description of Reference Signs] 30 Scan Converter 31 Display Device 31a LCD 32 Resolution Converter 33 Filter 34 Image Adjuster 35 PLL 36 Frequency Divider 37 Timing Controller 38 Oscillator 39 Sync Measurer 40 CPU 41, 42 Bank 41b, 42b Even Buffer 41a, 42a Odd buffer 43 Input terminals 43a, 45a, 45b Switch 51 Odd pixel calculation unit 52 Even pixel calculation unit 53 First dot buffer 54 Second dot buffer 55 Third dot buffer 56 Fourth dot buffer 57 Fourth 5 dot buffer 58 6th dot buffer 59 1st line buffer 59, 60 line buffer 60 2nd line buffer 61-69 multiplier 71-74 adder 75 output control unit 77 thinning-out timing control circuit 78 thinning-out line format Disconnection unit 79 Decimation signal output unit 80 Synchronization signal output stop unit 83 Input image data 84 Output image data 85 Conventional output image data Hsync Horizontal synchronization signal Vsync Vertical synchronization signal

Claims (3)

(57) [Claims] 1. A scan converter used when image data of an arbitrary input side image display system is input and output to a display device of a predetermined output side image display system, wherein A measuring unit that measures the horizontal synchronizing frequency, a timing control unit that converts the horizontal synchronizing frequency into a predetermined integer scale factor according to the measurement result of the measuring unit, and image data related to the input for each horizontal scanning line. A bank for temporary storage is built in, and the horizontal scanning line stored in the bank is repeatedly read a predetermined number of times corresponding to the predetermined integer magnification according to the measurement result in the measuring unit to determine the resolution of image data. The resolution conversion unit for conversion, and the image data output from the resolution conversion unit at the horizontal synchronization frequency converted to the predetermined integer scaling factor by the timing control unit. Scan converter and an output controller for outputting to the display device. 2. The scan converter according to claim 1, wherein the timing control unit counts horizontal synchronizing signals of the horizontal synchronizing frequency with reference to a vertical synchronizing signal input from an input source device, and According to the count result at the time, and the measurement result by the measurement unit, the display device side has a function of determining a horizontal scanning line that is not required to be displayed, and the output control unit is determined by the timing control unit. A scan converter having a masking function for stopping output of image data relating to a horizontal scanning line that does not require display. 3. The scan converter according to claim 1, wherein the bank of the resolution conversion unit temporarily stores all odd-numbered pixels in each horizontal scanning line. The output control unit includes a buffer and an even buffer that temporarily stores all of the even-numbered pixels in each horizontal scanning line, and the output control unit outputs 1 output from the odd buffer.
A scan converter characterized in that an odd-numbered pixel in a line and an even-numbered pixel in one line output from the even buffer are output in parallel.