JP3814625B2 - Display system and image processing apparatus - Google Patents

Description

  The present invention relates to a display system and an image processing apparatus, and more particularly to processing of video data supplied from an external image processing apparatus and display of an image related to the video data.

  In this type of apparatus, in recent years, when an image related to image data output from a computer is displayed, the resolution, the multicolor display, and the variety of products are increasing.

  For example, the number of display colors is 16.7 million colors, and the types are also diversified as 640 × 480, 800 × 600, 1024 × 768, 1280 × 1024, 1600 × 1280 in horizontal display dots and vertical line dots. The resolution is also high.

  On the other hand, the transfer clock of the video signal from the host computer to the display device is also increased in proportion to the increase in resolution.

  For example, in the case of 1280 × 1024, the frame rate is 157.5 MHz at 85 Hz, and in the case of 1600 × 1200, the frame rate is 229.5 MHz at 85 Hz.

  Also, the frame rate tends to increase to reduce flicker, and the frequency of the pixel clock can be further increased.

  However, if the resolution and frame rate are simply increased as described above, the following problems arise.

First, if video data is received and processed with a high-frequency pixel clock, the heat generated by the IC to be processed increases, so that accurate processing cannot be performed, and it is very expensive to perform processing with high accuracy. .
In addition, when receiving video data with a high-frequency pixel clock and receiving with a long cable, a lot of high-frequency radiation noise is generated, and legal regulations cannot be cleared.

  Such a problem becomes a big problem especially when displaying with a flat panel display.

  The object of the present invention is to solve the above-mentioned problems.

  Another object of the present application is to transmit image data according to the capability of the display device and perform good processing and display.

Solves such problems described above, in order to achieve the above object, the present invention provides a display system comprising a display device and an image processing apparatus connected via a cable to each other, said display device, the video data input Display means for displaying an image according to the above, and information indicating a frame rate of video data that can be displayed on the display means is transmitted to the image processing apparatus, and a frequency of a pixel clock of the input video data is set in the image processing First communication means for receiving from the device , wherein the image processing device receives information indicating the frame rate from the display device, and outputs the pixel clock frequency of the video data to be output to the display device to the display shows a second communication means for transmitting device, a memory for storing video data, the frame rate received from the display device Performing a predetermined calculation using the broadcast, have a control means for determining the frequency of the pixel clock of the video data to be output to the display device, the video data to be output to the display device was determined by the control means frequency The data is read from the memory based on the pixel clock .

  As described above, according to the present invention, since the frame rate of displayable video data is transmitted to the image processing apparatus, the video data is not transmitted unnecessarily at high speed.

  In addition, by outputting video data according to the frame rate of video data that can be displayed on the display device, it is possible to output appropriate video data according to the characteristics of the display device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a display system according to the present invention.

  The system shown in FIG. 1 according to the present embodiment includes a host 1 that supplies video data, and a display device 200 that receives the video data from the host 1 and displays an image related to the video data.

  First, the function of each part in FIG. 1 will be described.

  Reference numeral 1 denotes a host that supplies video data to the display device 200, and is mainly a personal computer, a workstation, or a television. 2 receives video data output from the host 1 and separates horizontal and vertical sync signals from the received video data; if the input video data is analog data, converts it into digital data; video data A demultiplexer function that separates video data so that it can be processed in parallel according to the transfer speed, a function that detects when the host 1 outputs interlaced data such as a television, and video data is one frame in multiple fields. Is an input conversion unit having a function of identifying a field number.

  Also, when the input data is digital data, if they are multiplexed in time and the number of transfer lines is reduced, a decoder that restores the multiplexed data, and the multiplexed data A PLL for generating a sampling clock is included.

  In addition, when the display device receives any two or more of analog video data, digital video data, and television data (NTSC, PAL, etc.), selection data for selecting which data to input is output from the host 1. This is received by the control unit 4 under the control of the communication circuit 3 or the hub control unit 17. Then, it is output from the control unit 4 to the input conversion unit 2.

  The input conversion unit 2 switches the input video data according to the selection information from the control unit 4.

  Reference numeral 3 denotes a communication circuit, which relates to video data supplied from the host 1, for example, pixel clock frequency information, frame rate information, interlace / non-interlace identification information, gamma correction data, brightness, contrast, screen position information, display It receives mode (display dot, number of lines) information, identification information of the above video data, and the like.

Also, the frame rate information that can be displayed on the display device 200 and the blanking period information are transmitted to the host 1.

  Data communication between the host 1 and the communication circuit 3 is performed using bidirectional serial communication.

  A control unit 4 controls the display device, and can perform arithmetic processing by the microprocessor and transfer of input / output data. As will be described later, 5 is a digital halftone processing unit for dithering input video data, 6 is a dither table rewriting circuit for rewriting a multi-value dither table and a dither threshold table in the digital halftone processing unit, and 7 is a dither halftone. A memory control unit 9 writes and reads data from / to the frame memory 8 and reads out data of a desired line from the memory as described below in accordance with an instruction from the rewrite control unit 10, and 9 is currently output as dither halftone data of the previous frame. The motion detection unit 10 detects the motion by comparing the dither halftone data and the image detected on the display unit in units of lines based on the motion detection result by the motion detection unit 9 and the rewrite speed information from the display unit 14. A rewrite control unit 11 that controls reading of the memory so as to rewrite, A gradation control unit that processes gradation data when the pixel is divided into two or more on the common side (horizontal direction), 12 adds a scanning address indicating a position to be displayed on the display unit 14 to the image data, The line output unit 13 for transferring to the display unit 14 is controlled by the control unit 4 and the line output unit 12, and is a drive unit for driving the display unit 14, and 14 is a display unit having a matrix structure, and has a memory property. A display panel made of a conductive liquid crystal, a driving circuit, a backlight, and the like. The display unit 14 includes a ROM that stores data indicating the number of colors that can be displayed, the resolution of the panel, a data transfer period necessary for the display unit 14, and the like, and this data is output to the control unit 4. Reference numeral 15 denotes an operation unit for the user to control the image quality and the screen position.

  Reference numeral 16 denotes a power supply unit, and 17 denotes a hub control unit for supplying video data and the like from the host 1 to the display device and peripheral devices connected to the display device.

  The hub control unit 17 can receive a data stream of USB (Universal Serial Bus) and IEEE 1394, which are currently being used, and the peripheral device connected to the display device or the display device. It includes switches for supplying equipment, a decoder for each data, an interface with external equipment, and the like.

  Next, the display operation of the system of FIG. 1 will be described.

  When the power is turned on, the display color number data (including common division number data) that can be displayed on the display unit 14 from the ROM in the display unit 14, the resolution, and the data transfer cycle necessary for the display unit 14 ( Information (which depends on the frame period of the panel) is transferred to the control unit 4.

  Based on these pieces of information, the control unit 4 calculates the minimum frame rate and blanking period that can be received by the display device, and transmits the information to the host 1 via the communication circuit 3.

  On the other hand, the pixel circuit, frame rate, and blanking period information transmitted from the host 1 is received by the communication circuit 3 as described later, and the control circuit 4 calculates a processing clock based on this data and controls the clock generation circuit. To do.

  When the above-mentioned information cannot be received from the host 1, the default value (maximum system clock) is used, or the frame rate, blanking information previously stored in the control unit 4 or the operation unit 15 is used. The frame rate and blanking value set by the user may be used.

  The control unit 4 also outputs necessary data to the dither table rewriting circuit 6 and the gradation control unit 11.

  The dither table rewriting circuit 6 selects a dither threshold necessary for the required number of display colors from a table prepared in advance or calculates a necessary table to calculate the dither threshold in the digital halftone processing unit 5. Rewrite the threshold table.

  At this time, the number of input bits may be determined in advance, or may be determined by receiving the information from the host 1 by the communication circuit 3. Further, the input conversion unit 2 may calculate the display mode from the horizontal synchronizing signal and use the input bit.

  The dither table is rewritten when the display unit is changed, when the host is changed, or when the display mode is changed, even when the power is not turned on.

  When the rewriting of the dither table is completed, first, the video data supplied from the host 1 is converted by the input conversion unit 2 into data in a format suitable for subsequent processing.

  That is, for example, as described above, when the input video data is analog video data for CRT, it is converted into digital data. Further, if it is differential digital data, it is converted to a TTL level or a CMOS level. When the transfer frequency of input video data is high, for example, when it exceeds 100 Hz, the video data is demultiplexed and the transfer frequency is reduced to half.

  When the input video data is an interlace signal such as a television signal, a discrimination signal and a field number identification signal are output.

  As described above, a plurality of video data is supplied to the input conversion unit 2, but one of them is selected by the information obtained by the communication circuit 3 or the hub control unit 17 and supplied to the digital halftone processing unit 5. The

  The video data dithered by the digital halftone processing unit 5 is written into the memory 8. Video data written in the memory 8 is sequentially updated unless writing is prohibited under the control of the rewrite control unit 10.

  On the other hand, the dithered video data is also output to the motion detector 9. The motion detection unit 9 is also supplied with one frame of pre-field video data from the memory 8 in synchronization with the output of the video data from the halftone processing unit 5. The motion detection unit 9 obtains the difference between the input video data of the two frames in units of pixels, and if the value exceeds a certain threshold th, detects that portion as having motion.

  The detection result of the motion detection unit 9 is output to the rewrite control unit 10, and the rewrite control unit 10 controls the memory control unit 7 so as to read the portion where the motion has occurred from the memory 8. The memory control unit 7 reads the video data of the moving part and outputs it to the gradation processing unit 11.

  When no motion part is detected by the motion detection unit 9, the rewrite control unit 10 reads the video data from the memory 8 by multi-interlace or random interlace in order to refresh the entire screen. To control.

In the case of a display device without flicker, the refresh may be performed non-interlaced.

  The video data read from the memory 8 in this way is output to the gradation control unit 11. The gradation control unit 11 converts the video data according to the common division number information output from the control unit 4 and outputs the video data to the line output unit 12.

  The line output unit 12 adds the scan address information output from the rewrite control unit 10 to the video data and outputs the video data to the display unit 14. Here, the scan address information is data indicating a motion part designated to the memory 8 by the rewrite control unit 10.

  The line output unit 12 outputs data indicating the write timing of the display unit 14 to the drive unit 13. The drive unit 13 generates a drive signal for driving the display unit 14 in accordance with the timing, and outputs the drive signal to the driver IC in the display unit 14.

  The display unit 14 rewrites the image of the line specified by the scan address based on the video data supplied from the line output unit 12, the scan address data, and the drive signal supplied from the drive unit.

  As described above, in this embodiment, prior to image display, data indicating the frame rate and blanking that can be displayed on the display device is transmitted to the host 1, and the host 1 transmits the frame transmitted from the display device. Video data is output according to the rate and blanking data.

  Next, a specific operation of the host 1 that receives information such as the frame rate and blanking from the display device and outputs video data will be described.

  FIG. 2 is a block diagram showing a configuration of the graphic controller 100 built in the host 1 and controlling the image data supply operation to the display device 200. The graphic controller of FIG. 2 is connected to the input of FIG. The converter 2 and the communication circuit 3 are connected.

  In FIG. 2, the frame rate and blanking information transmitted as described above from the communication circuit 3 in FIG. 1 is received by the communication circuit 104 and held in a buffer (not shown) in the communication circuit 104.

  The control unit 103 calculates the frequency of the pixel clock based on the frame rate information and blanking information received by the communication circuit 104 and reads out the video data from the memory 108.

  That is, if the received blanking period is longer than the blanking period of the video data handled in the host, the setting is changed to the received blanking period. In addition, the frame rate is calculated using the received value, and further using the resolution value set by the graphic controller itself to calculate the pixel clock of the video data to be output to the display device.

Here, the vertical blanking bv, the horizontal blanking bh , the frame rate (frame frequency) fv, the horizontal frequency fh, the vertical resolution rv, the horizontal resolution rh, and the pixel clock frequency fp have the following relationship.

rv × ((1 / fp) × rh + bh) + bv = (1 / fv)
The control unit 103 calculates the pixel clock so as to satisfy this expression, and changes the frequency dividing ratio of the frequency divider in the PLL 105 and the programmable frequency divider 109 according to the calculation result.

The oscillator 101 outputs a clock having a very high frequency, and the PLL 105 generates a clock that is phase-synchronized with the clock from the oscillator 101.
The frequency division ratio of the frequency divider in the control unit 103PLL105 is controlled, and a clock closest to the calculated pixel clock is output from the PLL105.

  The frequency divider 106 divides the pixel clock output from the PLL 105, generates horizontal and vertical synchronization signals and an image valid signal, and outputs them to the adder 108.

  On the other hand, video data from another video data input source of the host 1 is supplied to the memory 107 and is sequentially written into the memory 107 at a clock according to the operation clock of the host 1.

  At the time of reading, the data is read according to the frame rate and pixel clock calculated by the control unit 103 as described above, and output to the adder 108.

  That is, video data is written into the memory 107 according to the operation clock of the host itself, but when read from the memory 107, it is converted into video data with a frame rate and pixel clock according to the display device. .

  Of course, when the calculated frame rate is lower than the frame rate of the video data written in the memory 107, the frame rate is thinned out and supplied to the display device according to the ratio.

  The adder 108 adds the horizontal / vertical synchronization signal output from the frequency divider 106 to the video data read from the memory 107 and outputs the video data to the input conversion unit 2 in FIG.

  Similarly, a pixel clock signal from the PLL 105 is also output to the input conversion unit 2.

  In addition, the control unit 103 outputs data regarding the frame rate, blanking, and pixel clock cycle for the output video data to the communication circuit 3 in the display device via the communication circuit 104.

  On the display device side, the above-described processing is performed based on the information transmitted in this way, and an image related to the video data is displayed.

  When the frame rate is not sent from the display device side, the frame rate and the pixel clock are calculated based on data stored in advance in the video BIOS 102.

  Thus, in this embodiment, the frame rate and blanking information that can be displayed from the display device side are transmitted to the host, and the host side supplies video data to the display device based on the transmitted information. Therefore, it is possible to prevent the pixel clock of the video data to be transmitted from becoming unnecessarily high.

  Therefore, the above-mentioned problems associated with the increase in the pixel clock frequency do not occur, and in any case, processing according to the capability of the display device can be performed, and video data can be processed accurately. become.

  In the above-described embodiment, the graphic controller 100 is built in the host 1. However, as shown in FIG. 3, the graphic controller 100 is provided outside the host 1, and the graphic controller 100 and the host 1 are connected via the cable 110. It may be removable.

  With this configuration, it is possible to provide the above-described function even to a host that does not have a means for receiving frame rate information from the display device 200 as described above.

  In the above-described embodiment, the control unit 103 calculates the clock frequency by performing calculation after the frame rate and blanking information transmitted from the display device. A ROM table may be provided, and the control unit 103 may select parameters for a plurality of clocks written in the ROM table based on the input frame rate and blanking information.

It is a block diagram which shows the structure of the display system as embodiment of this invention. It is a figure which shows the structure of the graphic controller in the host of FIG. It is a figure which shows the structure of the display system to which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Host 2 Input conversion part 3 Communication circuit 4 Control part 100 Graphic controller 200 Display apparatus

Claims (5)

In a display system comprising a display device and an image processing device connected to each other via a cable,
The display device transmits to the image processing device information indicating a frame rate of video data that can be displayed on the display means and display means for displaying an image related to the input video data, and the input video First communication means for receiving a pixel clock frequency of data from the image processing device ;
The image processing device receives information indicating the frame rate from the display device, and transmits a pixel clock frequency of video data to be output to the display device to the display device ;
A memory for storing video data;
Said display using information indicating the frame rate received from the apparatus performs a predetermined operation, have a control means for determining the frequency of the pixel clock of the video data to be output to the display device,
Video data output to the display device is read from the memory based on a pixel clock having a frequency determined by the control means . Before SL predetermined operation, the display system according to claim 1, wherein the calculation for calculating the pixel clock frequency based on the information and the blanking information indicating a frame rate received from the display device. Wherein, the display system of claim 1, wherein the controlling the row Migihitsuji based writing the video data to the memory in the operation clock of said control means. The display means includes a ROM that stores panel data indicating the number of colors that can be displayed, the resolution of the panel, and the data transfer cycle,
The display unit transfers information indicating the frame rate calculated based on panel data read from the ROM and the blanking information to the image processing device when the display system is powered on. Display system. In an image processing apparatus connected via a cable to a display device having display means for displaying an image related to input video data,
The image processing apparatus receives information indicating a frame rate of video data that can be displayed on the display unit from the display unit, and transmits a pixel clock frequency of the video data to the display unit.
A memory for storing the input video data;
Said display using information indicating the frame rate received from the apparatus performs a predetermined operation, have a control means for determining the frequency of the pixel clock of the video data,
The image processing apparatus according to claim 1, wherein the video data is read from the memory based on the pixel clock .

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