JPH08181956A - Video information transmission method and video display device - Google Patents

Abstract

PURPOSE: To send a large amount of video information without being limited by a transmission speed. CONSTITUTION: A display frame is divided into four divided screen patterns and they are displayed on a TFT liquid crystal panel 35. RGB analog signals are sent from a video information generator 20 in parallel with corresponding pixels of each division screen pattern via 12 video signal lines. When a high definition full color image of 1280×1024 photoelectric picture elements is displayed by a 60Hz refresh rate, a frequency of dot clock is 120MHz and when data by one pixel are sequentially transmitted, the data are to be sent at this frequency. The frequency is decreased to 1/4 (30MHz) by transmitting the 4 picture elements in parallel. The EMI is easily prevented by sending the dot clock while being frequency-divided to 1/64 by a frequency divider 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video information transmission method and apparatus between a video generation apparatus such as a computer apparatus and a video display apparatus such as a display apparatus, and a video display apparatus adapted to the transmission method.

[0002]

2. Description of the Related Art Conventionally, as shown as a typical prior art in FIG. 7, a display device such as a liquid crystal display panel is connected to a so-called notebook personal computer, and video information is transmitted to display a screen. are doing. The image information to be displayed is drawn by the graphic controller 2 writing it as digital data in the video memory 3 based on the program processing of the microprocessor 1. The storage area of the video memory 3 corresponds to the pixels forming the display frame of the screen. Video memory 3
The image information drawn is sequentially read pixel by pixel, and the digital-analog (hereinafter abbreviated as "DA") converter 4 is used to display the three primary colors R for color display.
It is converted into an analog signal for each color of GB. A video signal is transmitted from a video information generation device 5 such as a personal computer or a workstation to a video amplifier 7 via a transmission signal line 6 including video signal cables of three RGB signals. The transmission signal line 6 also includes two signal cables that respectively transmit a horizontal synchronizing signal H and a vertical synchronizing signal V for controlling the display position of the pixel on the screen.

The analog RGB video signal received by the video amplifier 7 is analog digital (hereinafter referred to as "A
It is abbreviated as "D". ) The converter 8 converts each pixel into an 8-bit digital signal for each of the three primary colors RGB. 8
The bit digital RGB signal is converted into a parallel digital signal of 96 bits in total by the serial-parallel converter 9, and the transfer speed is reduced to be given to the signal processing circuit 10. The signal processing circuit 10 performs blinking and scrolling processing.

From the horizontal synchronizing signal H, a phase locked loop (hereinafter abbreviated as "PLL") circuit 11 is provided.
Thus, the dot clock is reproduced, and is used as a reference for the switching timing of processing for each pixel in the AD converter 8 and the serial-parallel converter 9. The dot clock is also input to the timing control circuit 12, and a signal for controlling the gate driver 13 and the frame memory 14 is created together with the horizontal synchronizing signal H and the vertical synchronizing signal V. From the frame memory 14, through the source drivers 15 and 16, a thin film transistor (hereinafter, abbreviated as “TFT”) performs active matrix driving, 1280 × 1.
High definition full color TFT liquid crystal display panel 1 with 024 pixels
The video information for driving 7 is read out in a form suitable for division driving or the like.

When non-interlace display of high-definition full-color video information is performed at a refresh rate of 60 Hz, for example, the transmission frequency required for sequentially transmitting the video information pixel by pixel is about 80 to 130 MHz. It is difficult to operate the TFT in this frequency band, and by dividing the display cells into 4 groups and driving them in parallel,
The operating frequency is reduced to 1/4. The image display device 18 including the TFT liquid crystal panel 17 replaces a conventional display device using a cathode ray tube (hereinafter, abbreviated as “CRT”), but on the image information generating device 5 side, a CRT display is used. Assuming a device, a signal representing video information for raster scanning is transmitted.

As another prior art, Japanese Patent Laid-Open No. 1-1292
Japanese Patent Laid-Open No. 93 discloses a prior art of reproducing a dot clock signal for liquid crystal display from a digital video signal using a PLL circuit. Japanese Unexamined Patent Publication No. 1-191194 discloses a prior art in which video information displayed on a plasma display unit is converted into an analog signal and transmitted. Japanese Unexamined Patent Publication No. 5-303075 discloses a prior art in which a digital video signal for liquid crystal display is transmitted in parallel for a plurality of pixels. Japanese Unexamined Patent Publication No. 5-89126 discloses a concept of confirming the type of display device and performing optimum display control.

[0007]

With the configuration shown in FIG.
Since the video information is sequentially transmitted pixel by pixel, it is necessary to increase the transmission speed as the amount of information increases. The amount of video information that can be transmitted is limited by the electrically realizable transmission rate. Moreover, even if it is electrically feasible, if the transmission frequency becomes high, the cost of the components of the electric circuit becomes high,
The pattern design of the circuit board becomes difficult. Further, since unnecessary radiation increases from the transmission signal line 6, if the length is increased, electromagnetic interference (hereinafter, abbreviated as "EMI") is also likely to occur.

In the prior art of Japanese Patent Laid-Open No. 1-191194, video information is transmitted by an analog signal to improve the transmission speed while preventing EMI, but there is a limit due to the frequency characteristic of the transmission path. JP-A-5-303075
In the prior art of the publication, a digital video signal is applied to a plurality of pixels in parallel to increase the transmission capacity, thereby increasing the transmission information amount without increasing the transmission speed. E in the process of transmission
MI easily occurs.

That is, the digital signal has the amplitude at the logic level of a standard semiconductor integrated circuit such as TTL or CMOS. In the case of TTL, Low level at 0.8 V or less,
It is treated as a high level at 2.0 V or higher. In case of CMOS, Low level at 1.5V or less,
It is treated as a High level at 3.5 V or higher. The analog video signal has an amplitude of about 1 Vp-p where the difference between the minimum peak voltage and the maximum peak voltage is 1 V, as represented by the NTSC composite signal which is a standard for television broadcasting, for example. Since the digital signal has a larger amplitude, it has a large margin against external noise and the like, but on the contrary, it easily becomes a noise generation source and easily causes EMI. In the digital signal, the upper bit on the MSD side and the lower bit on the LSD side have the same logical level amplitude, and even if the level of the analog signal is small, the voltage level of the transmitted digital signal greatly changes.

In the prior art of Japanese Patent Laid-Open No. 1-129293, the dot clock is reproduced from the digital video signal, but there is no countermeasure against EMI and EMI is likely to occur if the transmission frequency becomes high. Further, in this prior art, the change can be accurately detected because it is a digital signal, but the same effect cannot be achieved by using an analog video signal. Japanese Patent Laid-Open No. 5-891
Although Japanese Patent Laid-Open No. 26 describes that the video signal and the display control signal are adapted according to the type of the display device, a concrete idea about how to change between the cathode ray tube and the liquid crystal display panel is disclosed. It has not been.

An object of the present invention is to provide a video information transmission method and device capable of transmitting a large amount of video information without being limited by the transmission speed and EMI, and a video display device to which the method is applied. is there.

[0012]

SUMMARY OF THE INVENTION The present invention provides a method for sequentially transmitting video information from a video information generating device to a video display device for each pixel constituting a display frame. The video information transmission method is characterized in that video information is transmitted in parallel to each of the plurality of pixels by an analog signal. Further, the present invention is characterized in that one display frame is divided into a plurality of display areas and video information is transmitted in parallel to pixels in the plurality of display areas by analog signals. Further, the present invention is characterized in that video information is transmitted by an analog signal in parallel to a plurality of continuous pixels in one display frame. Further, the present invention is characterized in that video information is transmitted by an analog signal in parallel to pixels in a plurality of display frames. Further, according to the present invention, in a method of sequentially transmitting video information from a video information generating device to a video display device for each pixel constituting a display frame, dot clock information indicating a switching cycle of the video information for each pixel is previously stored. The video information transmission method is characterized in that the video signal is transmitted as a clock signal whose frequency is divided into a predetermined integer of 2 or more. Further, the present invention provides the divided clock signal,
It is characterized in that it is combined with video information or synchronization information and transmitted. Further, the present invention is characterized in that the frequency-divided clock signal is suppressed to an amplitude smaller than a logic level specified for a standard semiconductor integrated circuit and transmitted. Further, the video display device of the present invention transmits, to the video information generation device side, unique information regarding division into the plurality of pixels or frequency division into the integral fraction, and the specific information is transmitted at the video information generation device side. According to the unique information, the video information of a format suitable for the video display device is transmitted. Furthermore, the present invention relates to a plurality of pixels that can be transmitted in parallel from the video display side in an apparatus that sequentially transmits video information from the video information generation side to the video display side for each pixel that constitutes a display frame. Information reading means for reading the unique information, and parallel transmission means for transmitting the video information from the video information generating side in parallel as an analog signal to the plurality of pixels according to the unique information read by the information reading means. A video information transmission device characterized by the above. Furthermore, the present invention is a device for displaying video information sequentially transmitted for each pixel constituting a display frame from a video information generation side, and receiving means for receiving video information for a plurality of pixels in parallel as analog signals, A video information transmission device, comprising: display means for simultaneously displaying the received video information by the plurality of pixels.

[0013]

According to the present invention, the video information generating device sends the video information to the video display device by analog signals for each of a plurality of predetermined pixels forming a display frame in parallel to each of the plurality of pixels. To transmit. Since video information is transmitted by an analog signal, EMI is less likely to occur even if the transmission frequency is increased, as compared with the case where it is transmitted by a digital signal. Further, since the video information is transmitted in parallel to the plurality of pixels, the transmission capacity is increased, and the transmission amount of the video information can be increased without increasing the transmission frequency and the transmission speed.

For example, as compared with the conventional case of transmitting video information pixel by pixel, n is an integer of 2 or more, and display data for n pixels is transmitted in parallel using 3n transmission signal lines. This means that it is possible to transmit n times as much video information. When transmitting the same amount of information per unit time, the transmission rate can be reduced to 1 / n. The value of n is appropriately determined according to the size of the information amount or so as to obtain the optimum transmission rate.

According to the invention, one display frame is divided into a plurality of display areas, and video information is transmitted in parallel to pixels in the plurality of display areas by analog signals. It is easy to split the screen display using a liquid crystal display panel or the like.

Further, according to the present invention, video information is transmitted by an analog signal in parallel to a plurality of consecutive pixels in one display frame. Since the video information is usually drawn on the video memory which is addressed corresponding to the arrangement of the pixels of the display frame, instead of sequentially reading one pixel at a time, the video data of a plurality of pixels from the adjacent storage area is read. Information is read at the same time and converted into an analog signal,
Easy to transmit.

According to the invention, since the video information is transmitted in parallel to the pixels in the plurality of display frames by the analog signal, the display device cannot display the plurality of pixels at the same time. Even if there is, without increasing the video information transmission rate per display frame,
The amount of transmitted information can be increased.

Further, according to the present invention, the video information is sequentially transmitted from the video information generating device to the video display device for each pixel constituting the display frame, and the dot clock indicating the switching period of the video information for each pixel. The information is transmitted as a clock signal whose frequency is divided by a predetermined integer of 2 or more. Since the clock signal is transmitted, the video information can be more accurately associated with the pixel than when a clock signal reproduced based on an originally unrelated horizontal synchronizing signal is used. Since the clock signal divides the dot clock signal into an integral fraction, the frequency becomes low even when transmitted from the video information generation device side to the video display device side, and the occurrence of EMI and the like can be suppressed.

According to the invention, the divided clock signal is combined with video information or synchronization information and transmitted. Generally, when video information is transmitted, synchronization information is not transmitted, and when synchronization information is transmitted, video information is not transmitted. If the clock signal is transmitted during a period in which any information is not transmitted, the clock signal for dot clock reproduction can be easily transmitted without increasing the number of transmission signal lines.

Further, according to the present invention, the divided clock signal is suppressed to an amplitude smaller than a logic level specified for a standard semiconductor integrated circuit and transmitted. Since the electrical energy to be transmitted is small, it is possible to prevent EMI from occurring.

Further, according to the invention, the video display device transmits, to the video information generation device side, unique information regarding division into the plurality of pixels or frequency division into the integer. On the side of the video information generation device, the video information of a format suitable for the video display device is transmitted according to the transmitted unique information. Even when the image is displayed on the liquid crystal display panel, the image information is transmitted according to the unique information, so that the generation of EMI can be efficiently suppressed and a large amount of information can be transmitted.

Further, according to the present invention, the video information generating side, which transmits video information for each pixel forming a display frame to the video display side, is provided with unique information relating to a plurality of pixels which can be transmitted in parallel. Information reading means for reading from the video display side is provided. The parallel transmission means transmits the video information from the video information generation side in parallel to the plurality of pixels as an analog signal according to the unique information read by the information reading means. This makes it possible to transmit appropriate video information or dot clock information to video display devices having different pixel division configurations.

Further, according to the present invention, the image information for the plurality of pixels sequentially transmitted for each pixel constituting the display frame is received in parallel as an analog signal by the receiving means from the image information generating side. The display means simultaneously displays the received video information by the plurality of pixels. If a liquid crystal display device or the like is used, it is easy to divide and drive the display screen, and even if the operation speed such as the switching speed is not increased, it is possible to display video information having a large amount of information by EMI.
It can be performed without causing such as.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an electrical configuration for carrying out the present invention. The video information generation device 20 is a graphic control unit inside a small portable computer such as a notebook computer, and includes a microprocessor 21 and a graphic controller 22. Graphic controller 2
2 is controlled by the microprocessor 21 and performs a drawing process for generating video information such as graphics, characters, figures and characters in the video memory 23. The image information drawn in the video memory 23 is read out by 4 pixels at a time, and 4 × 3 = 12 DA converters 2 for each color of RGB.
At 4, it is converted into an analog signal.

From the graphic controller 22, for controlling the display position of the pixel in the display frame,
The horizontal synchronizing signal H and the vertical synchronizing signal V are also derived. Further, the dot clock signal indicating the transmission timing of each pixel for displaying an image is also displayed by the graphic controller 22.
Is generated by the frequency divider 26 and is divided into 1 / n by the frequency divider 25. The level converter 26 suppresses the level change of about 1 Vp-p, which is smaller than the amplitude of a standard digital signal such as TTL or CMOS, and the It is transmitted as CK. A video display device 30 connected to the microprocessor 21 by a transmission signal line 28 via a serial input port 27.
Is read, and the combination of 4 pixels and the value of n are set based on this unique information. The value of n is preferably a power of 2, such as 64, which can be easily divided by a binary counter.

The transmission signal line 28 is used for transmission from the video information generating device 20 side to the video display device 30 side.
A total of 15 signal cables of 12 video signal lines and 3 sync signal lines for the horizontal sync signal H, the vertical sync signal V and the clock signal CK are prepared. Furthermore, a signal cable for transmitting the serial signal S from the video display device 30 side to the video information generation device 20 side is also prepared.

Unique information relating to the video information transmission of the video display device 30 is set in the memory 31. This unique information can be read by the one-chip microcomputer 32. The unique information read is the serial output port 3
3 to the video information generation device 20 side. The reading and transmitting operations are performed immediately after the video display device 30 is connected to the video information generation device 20. The unique information is related to video information transmission such as a screen mode that can be used as the TFT liquid crystal panel 35, pixel data transfer speed, pixel data transfer order, and screen division mode. The screen mode is a combination of the screen resolution and the number of colors. The resolution is, for example, 1280 × 1024 pixels, and may be 640 × 480 pixels. The number of colors is
If each RGB has 4 bits, there are 4096 colors and it is determined by the product of the gradation numbers of the three primary colors RGB. The split screen mode is
This is a combination of the number of divisions and the division method.

Of the transmission signal lines 28, a total of twelve analog RGB video signals are input to the video amplifier 37 and amplified, and the A / D converter 38 converts the three primary colors R by four pixels.
It is converted into an 8-bit digital signal for each GB. The converted digital signals of 32 RGB signals each are subjected to signal processing by the signal processing circuit 39 and divided into two systems of 48 signals each. The clock signal CK is converted into a standard logic level such as TTL by the level converter 40, multiplied by 64 in the PLL circuit 41, and reproduced as a dot clock. The dot clock is given to the AD converter 38 and the signal processing circuit 39 and serves as a temporal reference for the processing for each pixel. The dot clock, along with the horizontal and vertical sync signals H and V,
It is also given to the timing control circuit 42 and is used to control the display position of the video screen.

The TFT liquid crystal panel 35 has a 128 by the gate driver 43 in order to perform high definition full color display.
One of the gate lines of 0 TFT active matrix is sequentially selected. The source line of the TFT active matrix is allocated to each of the three primary colors RGB and to each of the divided four groups by 8 bits. Two
Each source driver 44, 45 has four groups for each color
A total of 3 × 4 × 4 = 48 signal lines are input in parallel bit by bit.

FIG. 2 shows a screen division mode according to an embodiment of the present invention. One display frame is divided into two in the horizontal and vertical directions, and is divided into four in total. The operating frequency of the liquid crystal driving integrated circuit such as the gate driver 43 and the source drivers 44 and 45 is TF as a load.
Since the T active matrix is also capacitive, it cannot be made too high, and the drive frequency is divided to lower it. The drive for the split screens 1 to 4 corresponds to each of the split screens.
, ... are performed in parallel for the pixels. On the side of the video information generation device 20, if the video information is read from the video memory 23 and transmitted according to such a screen division mode, the serial / parallel converter 9 and the frame memory 14 of FIG. Divided driving can be performed without using it.

FIG. 3 shows a screen division mode according to another embodiment of the present invention. In this embodiment, a plurality of consecutive pixels in one display frame are driven in parallel. In the case of four divisions, four pixels are driven in parallel as shown in. Further, as shown in FIG. 4, it is possible to combine FIG. 2 and FIG.
The mode of screen division of the TFT liquid crystal display panel 35 is determined according to the structure of the TFT active matrix, and is set as unique information in the memory 31. Reading from the video memory 23 on the video information generating device 20 side may be performed according to the screen division mode.

FIG. 5 shows, as another embodiment of the present invention, a method of transmitting video information in parallel for four display frames 1 to 4 which are continuously displayed. In order to execute this embodiment, a structure as shown in FIG. 6 is required. From the video memory 23 of the video information generating device 50, the pixels at the same display position of the display frames 1 to 4 ,.
The video information for ... Is sequentially read in parallel. However, the graphic controller 22 and the video memory 23 can also draw the preceding display frame. Further, in this configuration, the dot clock is frequency-divided by the frequency divider 25 to 1/64, then converted into a level of 1 Vp-p by the level conversion signal combiner 51, and combined with the horizontal synchronizing signal H. A transmission signal line 52 including a horizontal synchronization signal H that is a combination of clock signals connects the video generation device 50 and the video display device 60.

On the side of the video display device 60, the clock signal is separated from the horizontal synchronizing signal H by the signal separation level converter 61 and converted into the TTL level. The frequency of the dot clock signal is 120 MHz, for example.
64 is 1.875 MHz. The frequency of the horizontal synchronizing signal H is 100 kHz or less, and the frequency difference is large, so if a high-pass filter and a low-pass filter are combined,
Both can be easily separated. The frequency of the vertical synchronizing signal V is about 60 Hz, and the frequency difference between the vertical synchronizing signal V and the clock signal is large and separation is easy. It is also possible to combine the clock signal with the video signal, for example, by adding the clock signal for a predetermined time like a burst signal in the NTSC composite color video signal. Furthermore, the transmission line of the serial signal S is configured to be bidirectional,
Used to read unique information at the start of operation,
Normally, it can also be used for transmitting clock signals.

In the timing control circuit 62, the signal processing circuit 63 and the frame memory 64 are controlled so that the video information transmitted in parallel for four frames is once stored in the frame memory 64.
, And read it frame by frame and display it on the TFT liquid crystal panel 35. At the time of display, division driving can be performed as in the prior art of FIG.

In each of the embodiments described above, the video information for four pixels can be transmitted in parallel, and the transmission rate of pixel data, which is 120 MHz for each pixel, can be reduced to 30 MHz, which is ¼. By increasing the number of divisions, it is possible to further reduce the transmission rate or increase the amount of information transmission per unit time. Although the screen division mode is determined according to the configuration of the display device, the transmission capacity can be easily increased by continuously transmitting a plurality of frames.

[0036]

As described above, according to the present invention, video information is transmitted from a video information generation device to a video display device in parallel to a plurality of pixels forming a display frame by an analog signal. Since video information is transmitted by an analog signal, EMI is less likely to occur even if the transmission frequency is increased as compared with the case of transmitting by a digital signal.
Also, since video information is transmitted to multiple pixels in parallel, the amount of information that can be sent per unit time can be increased, and the amount of video information transmitted can be increased even if the transmission frequency is not increased to increase the transmission speed. Can be increased.
For example, as compared with the case where the video information is transmitted pixel by pixel, the video information for pixels of an integer multiple of 2 or more can be transmitted. When the same amount of information is transmitted per unit time, the transmission speed can be reduced to a whole number.

Further, according to the present invention, one display frame is divided into a plurality of display areas, and video information is transmitted in parallel to the pixels in the plurality of display areas by analog signals. If you use a liquid crystal display panel,
It is possible to easily realize split screen display. further,
A serial-parallel converter and a frame memory, which are required in a conventional liquid crystal display device, etc. are not required, so that the number of parts can be reduced, and the size and cost can be reduced.

Further, according to the present invention, the video information is parallel to a plurality of continuous pixels in one display frame,
It is transmitted by an analog signal. Instead of sequentially reading the video information for each pixel from the video memory that is addressed in correspondence with the arrangement of the pixels of the display frame, the video information for a plurality of pixels is simultaneously read from the adjacent storage area, Since the signal is converted into an analog signal and transmitted, the amount of transmission per unit time can be easily increased.

Further, according to the present invention, since the video information is transmitted in parallel to the pixels in the plurality of display frames by the analog signal, the display device cannot display the plurality of pixels at the same time. Even if there is, without increasing the video information transmission rate per display frame,
The amount of transmitted information can be increased.

Further, according to the present invention, the video information is sequentially transmitted from the video information generating device to the video display device for each pixel constituting the display frame, and the dot clock indicating the switching period of the video information for each pixel. The information is transmitted as a clock signal whose frequency is divided by a predetermined integer of 2 or more. The video information can be accurately associated with the pixel by the clock signal. Since the clock signal divides the dot clock signal into an integral fraction, the frequency becomes low even when transmitted from the video information generation device side to the video display device side, and the occurrence of EMI and the like can be suppressed.

Further, according to the present invention, the divided clock signal is combined with video information or synchronization information and transmitted. If the clock signal is transmitted during a period in which any information is not transmitted, the clock signal for dot clock reproduction can be easily transmitted without increasing the number of transmission signal lines.

Further, according to the present invention, the frequency-divided clock signal is suppressed to an amplitude smaller than the logic level specified for the standard semiconductor integrated circuit and transmitted. Since the electrical energy to be transmitted is small, it is possible to prevent EMI from occurring. Particularly, when the clock signal is transmitted in combination with the synchronization signal or the like, the clock signal can be easily separated from the synchronization signal by providing the level difference.

Further, according to the present invention, specific information regarding division into a plurality of pixels or frequency division into integers is transmitted from the video display device side to the video information generation device side. On the side of the video information generation device, the video information of a format suitable for the video display device is transmitted according to the transmitted unique information. Even when the image is displayed on the liquid crystal display panel, the image information is transmitted according to the unique information, so that the generation of EMI can be suppressed and a large amount of information can be efficiently transmitted.

Furthermore, according to the present invention, the parallel transmission means on the side of the video information generating device transmits the video information to the video display side for each pixel constituting the display frame. Specific information relating to a plurality of pixels that can be transmitted in parallel is read from the information display device side by the information reading means. The parallel transmission means transmits the video information from the video information generation side in parallel to a plurality of pixels as an analog signal according to the read unique information. This makes it possible to transmit appropriate video information or dot clock information to video display devices having different pixel division configurations.

Further, according to the present invention, the receiving means receives the video information for a plurality of pixels sequentially transmitted from the video information generating side for each pixel constituting the display frame in parallel as an analog signal. The display means simultaneously displays the plurality of received video information. If a liquid crystal display device or the like is used, it is easy to divide and drive the display screen, and it is possible to display video information having a large amount of information while suppressing EMI and the like, without increasing the operating speed such as switching speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of a video information transmission device and a video display device according to the present invention.

FIG. 2 is a schematic diagram showing an embodiment of a video information transmission method according to the present invention.

FIG. 3 is a schematic view showing another embodiment of the video information transmission method according to the present invention.

FIG. 4 is a schematic diagram showing still another embodiment of the video information transmission method according to the present invention.

FIG. 5 is a schematic view showing still another embodiment of the video information transmission method according to the present invention.

FIG. 6 is a block diagram showing an electrical configuration of another embodiment of the video information transmission device and the video display device according to the present invention.

FIG. 7 is a block diagram showing an electrical configuration of a video information transmission device and a video display device according to the prior art.

[Explanation of symbols]

 20, 50 Video information generation device 22 Graphic controller 23 Video memory 24 DA converter 25 Frequency divider 26, 40 Level converter 27 Serial input port 28, 52 Transmission signal line 30, 60 Video display device 31 Memory 33 Serial output port 35 TFT liquid crystal panel 38 AD converter 39, 63 Signal processing circuit 41 PLL circuit 42, 62 Timing control circuit 43 Gate driver 44, 45 Source driver 51 Level conversion signal synthesizer 61 Signal separation level converter

Claims (10)

[Claims] 1. A method for sequentially transmitting video information from a video information generating device to a video display device for each pixel constituting a display frame, wherein a plurality of predetermined pixels are provided for each of the plurality of pixels. A video information transmission method characterized in that video information is transmitted in parallel by analog signals. 2. The video according to claim 1, wherein one display frame is divided into a plurality of display areas, and video information is transmitted in parallel to pixels in the plurality of display areas by analog signals. Information transmission method. 3. The video information transmission method according to claim 1, wherein video information is transmitted in parallel to a plurality of consecutive pixels in one display frame by an analog signal. 4. The video information transmission method according to claim 1, wherein the video information is transmitted in parallel to pixels in a plurality of display frames by analog signals. 5. A method of sequentially transmitting video information from a video information generating device to a video display device for each pixel constituting a display frame, wherein dot clock information indicating a switching cycle of the video information for each pixel is previously set. A video information transmission method, characterized in that the video signal is transmitted as a clock signal divided by an integer divided by 2 or more. 6. The video information transmission method according to claim 5, wherein the divided clock signal is combined with video information or synchronization information and transmitted. 7. The frequency-divided clock signal is suppressed to an amplitude smaller than a logic level specified for a standard semiconductor integrated circuit before being transmitted.
Or the video information transmission method described in 6. 8. The video display device transmits, to the video information generation device side, specific information regarding division into the plurality of pixels or frequency division into the integral fraction, and the video information generation device side transmits the specific information. The video information transmission method according to any one of claims 1 to 7, wherein video information of a format suitable for the video display device is transmitted according to the generated unique information. 9. An apparatus for sequentially transmitting video information from a video information generation side to a video display side for each pixel constituting a display frame, wherein the video display side relates to a plurality of pixels that can be transmitted in parallel. Information reading means for reading the unique information, and according to the unique information read by the information reading means,
A video information transmission device, comprising: parallel transmission means for transmitting video information from the video information generation side to the plurality of pixels in parallel as an analog signal. 10. A device for displaying video information sequentially transmitted from a video information generating side for each pixel constituting a display frame, a receiving means for receiving video information for a plurality of pixels in parallel as analog signals, and receiving means. A video information transmission device comprising: a display unit that simultaneously displays the generated video information by the plurality of pixels.