JP2944430B2 - Digital video sync detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video synchronization detection circuit, and more particularly to a digital video synchronization detection circuit for detecting a horizontal synchronization signal from a digital composite video signal in which an image signal is data-compressed.

[0002]

2. Description of the Related Art As shown in FIG. 3, a composite video signal of the NTSC system has a color burst signal on a back porch of a horizontal synchronizing signal, followed by an image signal.
This image signal is obtained by superimposing a chroma signal on a luminance signal. As a method for detecting a horizontal synchronization signal from such a composite video signal, there are a threshold level comparison method and a pattern matching method.

The former compares the threshold value set at the falling portion of the horizontal synchronization signal with the data value of the video signal, and after detecting that the data value of the video signal has crossed the threshold level downward. In order to make sure that the chroma signal component in the image signal does not hang down and confuse, the horizontal sync signal is detected by confirming that the data value has been kept below the threshold level for several samples. doing. Here, the threshold level is a SCH phase 0 degree level (Sub-carrier H-sync Ph) defined by the EIA synchronization signal standard (RS-170A).
case 0 deg).

In the latter case, the data value of the horizontal synchronizing signal portion of the video signal is sequentially compared with a preset pattern data value for each sample, and after confirming that all the samples match, the horizontal value is confirmed. Sync signal is detected.

[0005]

However, in the above-described threshold level comparing method, when a high-definition image signal having a large amount of image data is a digital composite video signal in which data is compressed, as shown in FIG. Since the signal is random data having no analog continuity, there may be a data sequence similar to the horizontal synchronization signal portion, and there is a disadvantage that the possibility of erroneous detection is high. In the pattern matching method, if a composite video signal conforms to standard specifications such as the NTSC or PAL system, there is little possibility of erroneous detection. In addition, there is a problem that digital conversion errors due to clock jitter, signal level fluctuation, and the like cannot be dealt with, and versatility is lacking.

An object of the present invention is to provide a digital composite video signal in which an image signal is data-compressed or a signal having a digital conversion error such as an analog composite video signal which is directly converted into a digital signal without any malfunction. An object of the present invention is to provide a digital video synchronization detection circuit capable of reliably detecting synchronization.

[0007]

According to the present invention, there is provided a digital video synchronization detection circuit for detecting a horizontal synchronization signal from an input digital composite video signal and outputting a synchronization detection signal. said the data value of the signal di
Digital conversion error of digital composite video signal
Accordingly, the upper limit value and the lower limit value are compared with a preset pedestal level, thereby detecting a falling start edge of the horizontal synchronizing signal, and the falling edge detecting unit detects the falling edge. starts operating upon detecting a downlink start edge, the digital composite bi and data values of said digital composite video signal
Upper and lower limits depending on the digital conversion error of the video signal
The limit value is compared with a data value of a preset horizontal synchronization falling slope portion, and the digital composite video signal
The data value of the preset horizontal synchronization falling slope is
A sync pulse detection means for outputting a first detection signal by detecting that it is within the allowable range of minutes of data values, the data values of the digital composite video signal the Digitally
According to the digital conversion error of the composite video signal.
The upper and lower limits of the sync tip level
The signal resulting from the comparison with the set data value and this signal
AND the signal with a given time delay
The sync chip level of the horizontal sync signal.
A sync tip detector for outputting a second detection signal out, by comparing the data value with a preset SCH phase 0 degree level of said digital composite video signal, the data value of said digital composite video signal SCH phase 0 for detecting when the SCH phase 0 degree level has crossed downward and outputting a third detection signal
Degree level crossing detection means, and synchronization detection signal generation means for generating the synchronization detection signal based on the first, second, and third detection signals.

[0008]

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart of each signal shown in FIG.

In FIG. 2, the horizontal synchronization signal portion of the input video signal S1 is indicated by continuous points. Each of these points
This corresponds to a data value obtained by sampling the NTSC composite video signal at a frequency four times the frequency of the color subcarrier. Here, the range of sampling points P0 to P14 indicates the pedestal level of the front porch of the horizontal synchronization signal. The range of points C0 to C3 is the falling portion of the horizontal synchronizing signal, and the points after the sampling point C4 indicate the sync chip level of the horizontal synchronizing signal. In addition, S defined by the EIA synchronization signal standard (RS-170A) is provided between the points C1 and C2 at the falling portion of the horizontal synchronization signal.
The CH phase 0 degree level is shown.

In FIG. 1, a falling edge detector 1 detects a falling edge (point C0 shown in FIG. 2) of a horizontal synchronizing signal of the input video signal S1 and resets a reset pulse S1.
12 is output. The synchronization pulse detector 2 starts operation in response to the reset pulse S12, and performs sampling at the falling portion of the horizontal synchronization signal (points C0 to C3 shown in FIG. 2).
Is compared with a preset value to detect the sync chip level start point (point C4 shown in FIG. 2) of the horizontal synchronization signal and output the synchronization pulse detection signal S22. The sync chip detector 3 detects the input video signal S
The sync tip level of the horizontal sync signal (after point C4 shown in FIG. 2) is detected to output a sync tip detection signal S32. The SCH phase 0 degree level crossing detecting section 4 detects that the input video signal S1 has crossed the SCH phase 0 degree level in the downward direction, and outputs an SCH phase 0 degree level crossing detection signal S43. The synchronization detection signal generator 5 outputs a synchronization detection signal S5 based on the synchronization pulse detection signal S22, the sync chip detection signal S32, and the SCH phase 0 degree level crossing detection signal S43.

Each part will be described in more detail.

The falling edge detector 1 includes a pedestal upper limit comparing circuit 11a, a pedestal lower limit comparing circuit 11b,
AND circuit 12, delay circuit 13 and AND circuit 14
And The pedestal upper limit comparing circuit 11a outputs a logic “H” when the data value of the input video signal S1 is equal to or less than a preset upper limit of the pedestal level, and the pedestal lower limit comparing circuit 11b outputs the input video signal S1. Is higher than the preset lower limit of the pedestal level, the logic "H" is output. AND circuit 12 outputs the logical product of the outputs of pedestal upper limit comparing circuit 11a and pedestal lower limit comparing circuit 11b to signal S.
Output as 11. The upper limit and the lower limit are set based on the permissible amount of digital conversion error generated when digitally converting a composite video signal.
Now, if the pedestal level of the input video signal S1 is within the allowable range, the output signal S11 of the AND circuit 12 takes a logic "H" from the point P0 to the point C0 as shown in FIG. Delay circuit 13 delays signal S11 by one data period. AND circuit 14 includes delay circuit 13
By taking the logical product of the output signal of
A reset pulse S12 which takes a logic "H" for one data period until the falling edge of the horizontal synchronization signal is output.

The synchronization pulse detector 2 includes a sequence counter 21, ROMs 22a and 22b, comparison circuits 23a and
23b, AND circuits 24 and 25, a delay circuit 26 and a latch circuit 27. Here, the sequence counter 21 resets at the falling edge of the reset pulse S12, starts counting the sampling clock Sc, and outputs a signal S21 that counts up from 0 → 1 → 2 → 3 as shown in FIG. I do. ROM 22a, 22
b is a falling portion of the horizontal synchronization signal (point C0 shown in FIG. 2).
The allowable upper limit value and the lower limit value of the data value in -C3) are stored in advance. The upper limit and the lower limit are set in consideration of a digital conversion error of the input video signal S1. Then, points C0, C1, C2, and C3 are set in accordance with the count values 0, 1, 2, and 3 of the sequence counter 21.
Each data value in C3 is output. That is,
The ROM 22a outputs the upper limit value of the data value at the points C0, C1, C2, and C3.
The lower limit value of the data value at 0, C1, C2, and C3 is output. The comparison circuits 23a and 23b output the input video signal S1
Is compared with the upper limit value and the lower limit value output from the ROMs 22a and 22b, respectively, and outputs a logic "H" if within the allowable range. The delay circuit 26 has a configuration in which four circuits for delaying the sampling clock period are connected in series, and the AND circuit 25 outputs a logical product of four outputs from the delay circuit 26. Therefore, the output signal of the AND circuit 25 takes the logic "H" when all the data values of the points C0, C1, C2, and C3 at the horizontal synchronization falling portion of the input video signal S1 are within the allowable range. The latch circuit 27
The logic "H" output from the AND circuit 25 is latched, and FIG.
As shown in (1), it is output as the synchronization pulse detection signal S22. The latch circuit 27 is reset by the synchronization detection signal S5.

The sync chip detecting section 3 includes a sync chip upper limit comparing circuit 31a and a sync chip lower limit comparing circuit 31b.
, An AND circuit 32, a delay circuit 33 and an AND circuit 34, and have a configuration similar to that of the falling edge detection unit 1. Here, the sync chip upper limit comparison circuit 3
1a outputs a logic "H" when the data value of the input video signal S1 is equal to or less than a preset sync tip level upper limit value.
b indicates a logic “H” when the data value of the input video signal S1 is equal to or greater than a preset sync chip level lower limit value.
Is output. The upper limit and the lower limit are set in consideration of a digital conversion error of the input video signal S1. The AND circuit 32 outputs the logical product of the output signals of the sync chip upper limit and lower limit comparison circuits 31a and 31b as a signal S31. The delay circuit 33 delays the signal S31 by a predetermined time. The AND circuit 34 takes the logical product of the output signal of the delay circuit 33 and the signal S31, and outputs the result as a sync chip detection signal S32. By the way, as the delay time of the delay circuit 33, for example, by taking the time from the point C4 to C14, the sync chip detection signal S32 becomes
As shown in FIG. 2, when the sync tip level of the input video signal S1 is continuous 10 times within the allowable range, the logic "H" can be set. Therefore, the reliability is improved by increasing the delay time of the delay circuit 33.

The SCH phase 0-degree level traversing detection unit 4
CH phase 0 degree level comparison circuit 41, D-type flip-flop 42 for delaying one data , and AND circuit 43
And a delay circuit 44. Here, the SCH phase 0 degree level comparing circuit 41 compares the data value of the input video signal S1 with a preset SCH phase 0 degree level, and takes a logic “H” when the SCH phase 0 degree level or more. A signal S41a and a signal S41b that takes a logic "H" when the SCH phase is less than the 0 degree level are output.
The D-type flip-flop 42 delays the signal S41a by one clock. The AND circuit 43 obtains the logical product of the signal S41b and the output signal of the D-type flip-flop 42 to form the input video signal S1 as shown in FIG.
Outputs a signal S42 which becomes logic "H" for only one clock period when it crosses the SCH phase 0 degree level downward. The delay circuit 44 gives a predetermined delay (here, 13 clock periods) to the signal S42 so as to match the timing of the sync chip detection signal S32, and as shown in FIG. Output as S43.

The synchronization detection signal generating section 5 is an AND circuit, which takes the logical product of the synchronization pulse detection signal S22, the sync chip detection signal S32, and the SCH phase 0 degree level crossing detection signal S43, as shown in FIG. , Synchronization detection signal S5
Output as At this time, since the latch circuit 27 is reset by the synchronization detection signal S5, the synchronization pulse detection signal S22 becomes logic "L".

[0019]

As described above, according to the present invention, the horizontal synchronization falling start edge and falling edge of the input video signal are obtained.
Shinkuchi of the horizontal synchronizing signal by checking the inclined portion
A sync pulse detection signal is generated by detecting the start point of the synchronization, and a sync tip detection signal is generated by confirming that the data value of the input video signal is continuous with a predetermined sync tip level at a plurality of sampling points. Further, detecting that the input video signal has crossed the SCH phase 0 degree level downward to generate a SCH phase 0 degree level crossing detection signal,
By generating a synchronization detection signal based on these detection signals, even if the image signal is a data compressed composite video signal, erroneous detection can be prevented and horizontal synchronization detection can be performed reliably.

Further, by setting an allowable range as a predetermined set value for comparison with the data value of the input video signal in consideration of a digital conversion error generated when converting an analog composite video signal into a digital signal, Even for a video signal having a digital conversion error, synchronization detection can be reliably performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart of each signal shown in FIG.

FIG. 3 is a diagram showing a composite video signal of the NTSC system.

FIG. 4 is a diagram showing a composite video signal in which an image signal is data-compressed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Falling edge detection part 2 Synchronization pulse detection part 3 Sync chip detection part 4 SCH phase 0 degree level crossing detection part 5 Synchronization detection signal generation part S1 Input video signal S5 Synchronization detection signal S12 Reset pulse S22 Synchronization pulse detection signal S32 Sync chip Detection signal S43 SCH phase 0 degree level crossing detection signal

Claims (1)

(57) [Claims] 1. A digital video synchronization detection circuit from the input to the digital composite video signal by detecting a horizontal synchronizing signal and outputs a synchronization detection signal, the data value of said digital composite video signal before
Digital conversion of digital composite video signal
A falling edge detecting means for detecting a falling start edge of the horizontal synchronization signal by comparing an upper limit value and a lower limit value with a preset pedestal level in accordance with the error; and starts operating upon detecting the falling start edge, the digital composite data values of said digital composite video signal
The upper limit value and the
The lower limit value is compared with a data value of a preset horizontal synchronization falling slope portion, and the digital composite video signal is compared.
Signal value is equal to the predetermined horizontal synchronization falling slope.
The first data value is detected as being within the allowable range of the data value of the portion .
A sync pulse detection means for outputting a detection signal, data values of said digital composite video signal before
Digital conversion of digital composite video signal
The upper and lower limit of the sync tip level part according to the error
The signal resulting from the comparison of the limit value with a preset data value
And the signal obtained by delaying this signal by a predetermined time
The sync tip of the horizontal synchronization signal
A sync chip detecting means for detecting a level and outputting a second detection signal; and comparing a data value of the digital composite video signal with a preset SCH phase 0 degree level, thereby detecting the digital composite video signal. SCH phase 0 degree level crossing detecting means for detecting when the data value crosses the SCH phase 0 degree level in the downward direction and outputting a third detection signal; and the first, second and third detection signals And a synchronization detection signal generating means for generating the synchronization detection signal based on the digital video synchronization detection circuit.