JP2011082583A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2011082583A
JP2011082583A JP2011012779A JP2011012779A JP2011082583A JP 2011082583 A JP2011082583 A JP 2011082583A JP 2011012779 A JP2011012779 A JP 2011012779A JP 2011012779 A JP2011012779 A JP 2011012779A JP 2011082583 A JP2011082583 A JP 2011082583A
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semiconductor element
semiconductor device
resin
bump
resin sealing
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Asumi Yuzuriha
明日美 杠
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Aoi Electronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a light receiving surface opposite to a surface provided with an external electrode and allows it be miniaturized. <P>SOLUTION: A die pad 9B made of metal is formed on a metal plate 91 which has flexibility, and a semiconductor element 2B is mounted on the die pad 9B. Bumps 5B are stacked and formed in a plurality of stages on a terminal 22B of the semiconductor element 2B, and the whole is sealed with a resin seal 92. An upper surface of the resin seal 92 is polished until the bump 5B appears to form the external electrode 6B. The metal plate 91 is peeled from the resin seal 92, and dicing is then performed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体素子を樹脂封止した半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device in which a semiconductor element is sealed with a resin and a method for manufacturing the same.

受光面と反対側の面に電極端子を設けた光半導体装置が従来技術として知られている(たとえば、特許文献1)。また、フリップチップ接続で半導体素子を外部電極に接続した半導体装置が従来技術として知られている(たとえば、特許文献2)。   An optical semiconductor device in which an electrode terminal is provided on the surface opposite to the light receiving surface is known as a prior art (for example, Patent Document 1). Further, a semiconductor device in which a semiconductor element is connected to an external electrode by flip chip connection is known as a conventional technique (for example, Patent Document 2).

特開2007−5687号公報JP 2007-5687 A 特開2006−278914号公報JP 2006-278914 A

特許文献1に記載されているような従来の光半導体装置では、ワイヤボンディングにより配線するため、半導体素子の上面の端子に接続されたワイヤがループを描いた後、半導体素子の下面側の端子電極と接続する。このため、光半導体装置が大きくなるという問題点がある。特許文献2に記載の半導体装置では、半導体素子から発生する熱を、バンプを介して放熱するため、放熱効率が悪いという問題点がある。   In the conventional optical semiconductor device as described in Patent Document 1, since wiring is performed by wire bonding, a wire connected to a terminal on the upper surface of the semiconductor element draws a loop, and then a terminal electrode on the lower surface side of the semiconductor element Connect with. For this reason, there exists a problem that an optical semiconductor device becomes large. In the semiconductor device described in Patent Document 2, the heat generated from the semiconductor element is radiated through the bumps, so that there is a problem that the heat radiation efficiency is poor.

(1)請求項1の発明は、半導体素子を樹脂封止した半導体装置において、半導体素子の一方の面側の樹脂表面に設けられ、複数段に重ねて形成されたバンプを介して半導体素子の端子電極が接続され、表面に露出する外部電極と、半導体素子の他方の面が接続され、表面に露出する金属板からなるダイパッドとを備えることを特徴とする。
(2)請求項2の発明は、請求項1に記載の半導体装置において、樹脂表面および最上段のバンプの上面は研磨面とされ、外部電極は、バンプの研磨面と樹脂の研磨面に跨って形成されていることを特徴とする。
(3)請求項3の発明の半導体装置の製造方法は、可撓性を有する板上に金属からなるダイパッドを形成するダイパッド形成工程と、ダイパッド上に半導体素子を搭載する半導体素子搭載工程と、ダイパッド上に搭載した半導体素子にバンプを複数段に重ねて形成するバンプ形成工程と、半導体素子と、バンプと、ダイパッドとを樹脂封止して樹脂封止体を作製する樹脂封止工程と、複数段に重ねて形成されたバンプの中、最上段のバンプが表面に現れるまで樹脂封止体を研磨する研磨工程と、樹脂封止体の研磨面に、バンプと接続する外部電極を形成する外部電極形成工程と、樹脂封止体から前記可撓性を有する板を剥離する剥離工程と、樹脂封止体を切断して分割する分割工程とを備えることを特徴とする。
(4)請求項4の発明は、請求項3に記載の半導体装置の製造方法において、バンプ形成工程は、複数段に重ねて形成されたバンプをワイヤボンディング法により形成することを特徴とする半導体装置の製造方法。
(1) The invention of claim 1 is a semiconductor device in which a semiconductor element is resin-sealed, and is provided on the resin surface on one surface side of the semiconductor element, and the semiconductor element is interposed through bumps formed in a plurality of layers. A terminal electrode is connected and an external electrode exposed on the surface and a die pad made of a metal plate connected to the other surface of the semiconductor element and exposed on the surface are provided.
(2) The invention of claim 2 is the semiconductor device according to claim 1, wherein the resin surface and the upper surface of the uppermost bump are polished surfaces, and the external electrode extends over the bump polished surface and the resin polished surface. It is characterized by being formed.
(3) A method of manufacturing a semiconductor device according to claim 3 includes a die pad forming step of forming a metal die pad on a flexible plate, a semiconductor element mounting step of mounting a semiconductor element on the die pad, A bump forming step of forming a plurality of bumps on a semiconductor element mounted on a die pad, and a resin sealing step of producing a resin sealing body by resin sealing the semiconductor element, the bump, and the die pad; Among the bumps formed in multiple layers, a polishing step for polishing the resin sealing body until the uppermost bump appears on the surface, and an external electrode connected to the bump is formed on the polishing surface of the resin sealing body. It comprises an external electrode forming step, a peeling step for peeling the flexible plate from the resin sealing body, and a dividing step for cutting and dividing the resin sealing body.
(4) According to a fourth aspect of the present invention, in the semiconductor device manufacturing method according to the third aspect, in the bump forming step, bumps formed in a plurality of stages are formed by wire bonding. Device manufacturing method.

請求項1の発明によれば、バンプで電極と接合した半導体素子から発生する熱を効率的に放熱することができる。請求項3の発明によれば、請求項1の半導体装置を容易に作製することができる。   According to the first aspect of the present invention, the heat generated from the semiconductor element joined to the electrode by the bump can be efficiently radiated. According to the invention of claim 3, the semiconductor device of claim 1 can be easily manufactured.

本発明の参考実施形態の半導体装置の構成を説明するための図である。It is a figure for demonstrating the structure of the semiconductor device of reference embodiment of this invention. 内部電極形成工程を説明するための図である。It is a figure for demonstrating an internal electrode formation process. 光検出半導体素子の内部電極への搭載を説明するための図である。It is a figure for demonstrating mounting to the internal electrode of a photon detection semiconductor element. 光検出半導体素子搭載工程、配線工程、樹脂封止工程および研磨工程を説明するための図である。It is a figure for demonstrating a photon detection semiconductor element mounting process, a wiring process, a resin sealing process, and a grinding | polishing process. 外部電極形成工程および分割工程を説明するための図である。It is a figure for demonstrating an external electrode formation process and a division | segmentation process. 回路基板に実装された光検出半導体装置を説明するための図である。It is a figure for demonstrating the photon detection semiconductor device mounted in the circuit board. 本発明の第1の実施形態の半導体装置の構成を説明するための図である。It is a figure for demonstrating the structure of the semiconductor device of the 1st Embodiment of this invention. ダイパッド形成工程を説明するための図である。It is a figure for demonstrating a die pad formation process. 半導体素子搭載工程、バンプ形成工程、樹脂封止工程および研磨工程を説明するための図である。It is a figure for demonstrating a semiconductor element mounting process, a bump formation process, a resin sealing process, and a grinding | polishing process. 外部電極形成工程、剥離工程および分割工程を説明するための図である。It is a figure for demonstrating an external electrode formation process, a peeling process, and a division | segmentation process. 回路基板に実装された半導体装置を説明するための図である。It is a figure for demonstrating the semiconductor device mounted in the circuit board. 放熱板として金属板を設けた半導体装置を説明するための図である。It is a figure for demonstrating the semiconductor device which provided the metal plate as a heat sink.

−参考実施形態−
本発明の参考実施形態の半導体装置について図1を参照して説明する。第1の実施形態の半導体装置は光検出半導体装置であり、図1は光検出半導体装置1Aの構成を説明するための図である。
-Reference embodiment-
A semiconductor device according to a reference embodiment of the present invention will be described with reference to FIG. The semiconductor device of the first embodiment is a photodetection semiconductor device, and FIG. 1 is a diagram for explaining the configuration of the photodetection semiconductor device 1A.

図1において、符号1Aは光検出半導体装置、2Aは光検出半導体素子である。光検出半導体素子2Aには光検出部21Aが設けられている。光検出半導体装置1には、開口部(以下、受光開口11Aと呼ぶ)が形成されており、受光開口11Aの底面には光検出半導体素子2Aの光検出部21Aが露出している。光検出半導体装置1Aの受光開口11A側にはガラス基板3Aが設けられており、受光開口11Aはガラス基板3Aによって覆われる。光検出半導体装置1Aは、ガラス基板3Aを介して受光開口11Aに入射したレーザ光などの光を光検出部21Aで受光して検出する。   In FIG. 1, reference numeral 1A denotes a light detection semiconductor device, and 2A denotes a light detection semiconductor element. The light detection semiconductor element 2A is provided with a light detection unit 21A. The light detection semiconductor device 1 has an opening (hereinafter referred to as a light receiving opening 11A), and the light detection portion 21A of the light detection semiconductor element 2A is exposed on the bottom surface of the light receiving opening 11A. A glass substrate 3A is provided on the light receiving opening 11A side of the photodetection semiconductor device 1A, and the light receiving opening 11A is covered with the glass substrate 3A. The light detection semiconductor device 1A receives and detects light such as a laser beam incident on the light receiving opening 11A through the glass substrate 3A by the light detection unit 21A.

ガラス基板3A側の樹脂8Aの樹脂表面には内部電極4Aが設けられており、光検出半導体素子2Aは内部電極4AとAuなどからなるバンプ5Aによって接続されている。光検出半導体装置1Aの受光開口11A側の面(以下、受光面と呼ぶ)の反対側の面(以下、実装面と呼ぶ)の樹脂表面には、外部電極6Aが設けられている。内部電極4Aと外部電極6Aとは略直線のワイヤ7Aによって接続されている。光検出半導体素子2Aと内部電極4Aとバンプ5Aとワイヤ7Aとは、エポキシ樹脂などの樹脂8Aによって封止されている。   An internal electrode 4A is provided on the resin surface of the resin 8A on the glass substrate 3A side, and the photodetecting semiconductor element 2A is connected to the internal electrode 4A by a bump 5A made of Au or the like. An external electrode 6A is provided on a resin surface of a surface (hereinafter referred to as a mounting surface) opposite to a surface (hereinafter referred to as a light receiving surface) on the light receiving opening 11A side of the photodetection semiconductor device 1A. The internal electrode 4A and the external electrode 6A are connected by a substantially straight wire 7A. The light detection semiconductor element 2A, the internal electrode 4A, the bump 5A, and the wire 7A are sealed with a resin 8A such as an epoxy resin.

以上のような構造にすることによって、受光面の反対側の面である実装面において外部電極6Aを介して回路基板と接続することができる。   With the above structure, the circuit board can be connected via the external electrode 6A on the mounting surface, which is the surface opposite to the light receiving surface.

次に、上述した光検出半導体装置1Aの製造方法について、図2〜図5を参照して説明する。光検出半導体装置1Aの製造方法は、内部電極形成工程、光検出半導体素子搭載工程、配線工程、樹脂封止工程、研磨工程、外部電極形成工程および分割工程を備える。   Next, a method for manufacturing the above-described photodetection semiconductor device 1A will be described with reference to FIGS. The manufacturing method of the photodetection semiconductor device 1A includes an internal electrode formation step, a photodetection semiconductor element mounting step, a wiring step, a resin sealing step, a polishing step, an external electrode formation step, and a division step.

(1)内部電極形成工程
内部電極形成工程では、光検出半導体装置1Aの内部電極4Aを形成する。内部電極形成工程について、図2を参照して説明する。
(1) Internal electrode formation process In the internal electrode formation process, the internal electrode 4A of the photodetection semiconductor device 1A is formed. The internal electrode forming process will be described with reference to FIG.

図2(a)に示すように、ガラス基板41の両面の全面にAuペースト42を塗布した後、Auペースト42の塗布面にレジスト43を塗布またはラミネートする。次に、パターンマスクフィルムを密着させ、紫外線により露光する。そして、現像し、図2(b)に示すように、内部電極4Aおよび、後述のダミー電極44を形成する部分を残してレジスト43をエッチングして除去する。ガラス基板41の一方の面には電極を形成しないので、全てのレジスト43を除去する。   As shown in FIG. 2A, after the Au paste 42 is applied to the entire surface of both surfaces of the glass substrate 41, a resist 43 is applied or laminated on the application surface of the Au paste 42. Next, the pattern mask film is brought into close contact and exposed to ultraviolet rays. Then, development is performed, and as shown in FIG. 2B, the resist 43 is removed by etching, leaving portions for forming the internal electrode 4A and a dummy electrode 44 described later. Since no electrode is formed on one surface of the glass substrate 41, the entire resist 43 is removed.

次に、図2(c)に示すように、レジスト43で被覆されていない部分のAuペースト42をエッチングして除去する。そして、レジスト42をガラス基板41から剥離した後、熱処理してAuペースト42を焼き付けることによって、図2(d)に示すように、ガラス基板41上に内部電極4Aとダミー電極44とを形成する。   Next, as shown in FIG. 2C, the portion of the Au paste 42 not covered with the resist 43 is removed by etching. Then, after the resist 42 is peeled off from the glass substrate 41, the Au paste 42 is baked by heat treatment, thereby forming the internal electrode 4A and the dummy electrode 44 on the glass substrate 41 as shown in FIG. .

(2)光検出半導体素子搭載工程
光検出半導体素子搭載工程では、超音波接合により光検出半導体素子2Aをガラス基板41の内部電極4A上にフリップチップ接続する。
(2) Photodetection semiconductor element mounting step In the photodetection semiconductor element mounting step, the photodetection semiconductor element 2A is flip-chip connected to the internal electrode 4A of the glass substrate 41 by ultrasonic bonding.

ここで、光検出半導体素子2Aの作製について説明する。光検出半導体素子2Aの製造に使用されるウエハには、能動素子として光検出部21Aが予め複数形成されている。ウエハ上の各素子上に所定個数のバンプ5Aを形成する。バンプ5Aは、めっき法によってウエハ上に形成される。そして、ウエハをダイシングして個片化し、光検出半導体素子2を作製する。   Here, the production of the photodetection semiconductor element 2A will be described. On the wafer used for manufacturing the photodetection semiconductor element 2A, a plurality of photodetection portions 21A are formed in advance as active elements. A predetermined number of bumps 5A are formed on each element on the wafer. The bumps 5A are formed on the wafer by a plating method. Then, the wafer is diced into individual pieces, and the light detection semiconductor element 2 is manufactured.

光検出半導体素子搭載工程について図3、図4(a)を参照して説明する。ガラス基板41上の光検出半導体素子2Aを搭載する位置において、光検出半導体素子2Aの外周に沿うような位置に、額縁状に異方性導電ペースト(ACP)45を塗布する。このとき、図3(a)に示すように、内部電極4A上に異方性導電ペースト45が塗布される。次に、図3(b)に示すように、バンプ5Aが内部電極4A上に載置されるように光検出半導体素子2Aをガラス基板41に搭載し、光検出半導体素子2Aにボンディングツール51を当てる。そして、ボンディングツール51で光検出半導体素子2Aを加圧、加熱する。その結果、バンプ5Aと内部電極4Aとが電気的に接続するとともに、異方性導電ペースト45は硬化する(図4(a))。   The photodetection semiconductor element mounting process will be described with reference to FIGS. 3 and 4A. An anisotropic conductive paste (ACP) 45 is applied in a frame shape at a position along the outer periphery of the light detection semiconductor element 2A at a position on the glass substrate 41 where the light detection semiconductor element 2A is mounted. At this time, as shown in FIG. 3A, an anisotropic conductive paste 45 is applied on the internal electrode 4A. Next, as shown in FIG. 3B, the photodetection semiconductor element 2A is mounted on the glass substrate 41 so that the bump 5A is placed on the internal electrode 4A, and the bonding tool 51 is attached to the photodetection semiconductor element 2A. Hit it. Then, the photodetection semiconductor element 2 </ b> A is pressurized and heated with the bonding tool 51. As a result, the bump 5A and the internal electrode 4A are electrically connected, and the anisotropic conductive paste 45 is cured (FIG. 4A).

(3)配線工程
配線工程では、光検出半導体装置1Aのワイヤ7Aを形成する。ワイヤ7Aの形成には、ワイヤボンディング技術を利用する。たとえば、ネイルヘッドボンディング法によってワイヤ7Aを形成する場合について説明する。ワイヤ7AにはAuワイヤが使用される。(i)Auワイヤをキャピラリに通し、Auワイヤの先端を溶融してボールを形成する。
(ii)ボールを内部電極4A上に圧着する。これにより、内部電極4A上にネイルヘッドが形成される。
(iii)Auワイヤのループ高さが光検出半導体素子2Aの上面の高さより高くなるよう
にキャピラリを移動した後、キャピラリのエッジでダミー電極44上にAuワイヤを圧着する。Auワイヤのループ高さは、Auワイヤ先端を溶融しボールを形成する際に形成される再結晶部の長さによって調整することもできる。
(iv)クランパでAuワイヤを引っ張り、切断する。
以上のようにして、図4(b)に示すように、ループ高さが光検出半導体素子2Aの上面の高さより高い、内部電極4Aとダミー電極44とを接続したワイヤ7Aが形成される。
(3) Wiring process In the wiring process, the wire 7A of the photodetection semiconductor device 1A is formed. A wire bonding technique is used to form the wire 7A. For example, a case where the wire 7A is formed by a nail head bonding method will be described. An Au wire is used as the wire 7A. (I) The Au wire is passed through the capillary and the tip of the Au wire is melted to form a ball.
(Ii) The ball is crimped onto the internal electrode 4A. Thereby, a nail head is formed on the internal electrode 4A.
(Iii) After moving the capillary so that the loop height of the Au wire is higher than the height of the upper surface of the photodetecting semiconductor element 2A, the Au wire is crimped onto the dummy electrode 44 at the edge of the capillary. The loop height of the Au wire can also be adjusted by the length of the recrystallized portion formed when the Au wire tip is melted to form a ball.
(Iv) Pull the Au wire with a clamper and cut it.
As described above, as shown in FIG. 4B, the wire 7A connecting the internal electrode 4A and the dummy electrode 44 having a loop height higher than the height of the upper surface of the photodetecting semiconductor element 2A is formed.

(4)樹脂封止工程
樹脂封止工程では、光検出半導体素子2Aなどを樹脂封止する。樹脂封止するための樹脂8Aには、たとえば熱硬化性エポキシ系樹脂が使用される。光検出半導体素子2Aの外周部には、異方性導電ペースト45が塗布されているので、光検出半導体素子2Aとガラス基板41との間に樹脂8Aが流れ込まない。このため、図4(c)に示すように、光検出部21Aの周囲の空間61は封止用樹脂未充填となり、光検出部21Aは封止用樹脂8Aに覆われない。そして、樹脂封止したガラス板41を不図示のオーブンに入れて熱処理し、樹脂8Aを硬化させる。以下、図4(c)に示す樹脂8Aを硬化させたものを樹脂封止体62と呼ぶ。
(4) Resin sealing step In the resin sealing step, the photodetection semiconductor element 2A and the like are sealed with resin. For the resin 8A for resin sealing, for example, a thermosetting epoxy resin is used. Since the anisotropic conductive paste 45 is applied to the outer periphery of the light detection semiconductor element 2A, the resin 8A does not flow between the light detection semiconductor element 2A and the glass substrate 41. For this reason, as shown in FIG. 4C, the space 61 around the light detection portion 21A is not filled with the sealing resin, and the light detection portion 21A is not covered with the sealing resin 8A. Then, the resin-sealed glass plate 41 is put in an oven (not shown) and heat-treated to cure the resin 8A. Hereinafter, the cured resin 8A shown in FIG.

(5)研磨工程
研磨工程では、樹脂封止体62の面のうち、ガラス基板41が設けられている面と反対側の面63(以下、上面と呼ぶ)を研磨して、樹脂封止体62の上面を削る。上述したように、ワイヤ7Aのループ高さは光検出半導体素子2Aの上面の高さより高いので、樹脂封止体62の上面を研磨すると、光検出半導体素子2Aが研磨面65に現れる前に、ワイヤ7Aが現れる。さらに研磨すると、図4(d)に示すように、ワイヤ7Aは、内部電極4Aに接続したワイヤ7Aと、ダミー電極44に接続したワイヤ64とに分割される。後述する分割工程で、ダミー電極44とワイヤ64とは、光検出半導体装置1Aから切り離される。したがって、分割代を考慮に入れて、分割された2つのワイヤ7A,64の研磨端間の距離が所定距離以上離れる位置まで樹脂封止体62は研磨される。ワイヤ7Aのループ高さを調整することによって、上述の位置まで樹脂封止体62が研磨されても光検出半導体素子2Aが研磨されないようにする。
(5) Polishing Step In the polishing step, the surface 63 of the resin sealing body 62 opposite to the surface on which the glass substrate 41 is provided (hereinafter referred to as the upper surface) is polished to obtain the resin sealing body. The upper surface of 62 is shaved. As described above, since the loop height of the wire 7A is higher than the height of the upper surface of the photodetection semiconductor element 2A, when the upper surface of the resin sealing body 62 is polished, before the photodetection semiconductor element 2A appears on the polishing surface 65, Wire 7A appears. When further polished, the wire 7A is divided into a wire 7A connected to the internal electrode 4A and a wire 64 connected to the dummy electrode 44, as shown in FIG. In the division step described later, the dummy electrode 44 and the wire 64 are separated from the photodetection semiconductor device 1A. Therefore, taking into account the division allowance, the resin sealing body 62 is polished to a position where the distance between the polishing ends of the two divided wires 7A, 64 is a predetermined distance or more. By adjusting the loop height of the wire 7A, the photodetecting semiconductor element 2A is prevented from being polished even if the resin sealing body 62 is polished to the above-described position.

(6)外部電極形成工程
外部電極形成工程では、樹脂封止体62の研磨面65にワイヤ7Aと接続する外部電極6Aを形成する。外部電極6Aは以下のようにして形成する。
(i)スリットマスク(金属板に孔を形成して作製したマスク)を樹脂封止体62の研磨
面65に貼り付ける。
(ii)スパッタ法によって樹脂封止体62の研磨面65にTiやPdなどの金属電極を形成する。
(iii)スリットマスクを樹脂封止体62の研磨面65から外した後、めっき法によって
Ni層を金属電極上に形成し、その上にめっき法によってAu層を形成する。これにより、電極の接着強度を増加させる。
以上のようにして、図5(a)に示すように、樹脂封止体62の研磨面65に外部電極6Aが形成される。
(6) External Electrode Formation Step In the external electrode formation step, the external electrode 6A connected to the wire 7A is formed on the polishing surface 65 of the resin sealing body 62. The external electrode 6A is formed as follows.
(I) A slit mask (a mask produced by forming a hole in a metal plate) is attached to the polishing surface 65 of the resin sealing body 62.
(Ii) A metal electrode such as Ti or Pd is formed on the polishing surface 65 of the resin sealing body 62 by sputtering.
(Iii) After removing the slit mask from the polishing surface 65 of the resin sealing body 62, a Ni layer is formed on the metal electrode by a plating method, and an Au layer is formed thereon by a plating method. Thereby, the adhesive strength of the electrode is increased.
As described above, the external electrode 6A is formed on the polishing surface 65 of the resin sealing body 62 as shown in FIG.

(7)分割工程
分割工程では、樹脂封止体62を分割して、光検出半導体装置1Aを作製する。分割工程では、図5(b)に示すように、1点鎖線71に沿って、ダイヤモンドブレード・ダイシング法で樹脂封止体62をダイシングする。そして、図5(c)に示すように、一つの樹脂封止体62が分割され、光検出半導体装置1Aが完成する。
(7) Division Step In the division step, the resin sealing body 62 is divided to produce the photodetection semiconductor device 1A. In the dividing step, as shown in FIG. 5B, the resin sealing body 62 is diced along the one-dot chain line 71 by the diamond blade dicing method. Then, as shown in FIG. 5C, one resin sealing body 62 is divided, and the photodetection semiconductor device 1A is completed.

以上のようにして作製された光検出半導体装置1は、図6に示すような回路基板81に半田82を介して実装される。たとえば、光ディスクの情報を読み込むために照射されたレーザ光LBは、光ディスク面で反射して、ガラス基板3Aを通過し、光検出半導体装置1Aの受光開口11Aに入射する。そして、受光開口11Aに入射したレーザ光LBは光検出半導体素子2Aの光検出部21Aで受光され、検出される。   The photodetection semiconductor device 1 manufactured as described above is mounted on a circuit board 81 as shown in FIG. For example, the laser beam LB irradiated for reading information on the optical disk is reflected by the optical disk surface, passes through the glass substrate 3A, and enters the light receiving opening 11A of the light detection semiconductor device 1A. The laser beam LB incident on the light receiving opening 11A is received and detected by the light detection unit 21A of the light detection semiconductor element 2A.

以上の実施形態による光検出半導体装置1Aは次のような作用効果を奏する。
(1)半導体素子2Aの一方の面側の樹脂表面に設けられ、バンプを介して前記半導体素子の端子電極が接続される内部電極と、半導体素子の他方の面側の樹脂表面に設けられ、ワイヤを介して前記内部電極が接続され、表面に露出する外部電極とを備えるようにした。したがって、外部電極6Aが設けられた面と反対側の面に受光面を備えた光検出半導体装置1Aを小型化することができる。
The photodetection semiconductor device 1A according to the above embodiment has the following operational effects.
(1) Provided on the resin surface on one surface side of the semiconductor element 2A, provided on the resin surface on the other surface side of the semiconductor element, an internal electrode to which the terminal electrode of the semiconductor element is connected via a bump, The internal electrode is connected via a wire, and an external electrode exposed on the surface is provided. Therefore, the photodetection semiconductor device 1A having the light receiving surface on the surface opposite to the surface on which the external electrode 6A is provided can be reduced in size.

(2)小さな電極でも接続できるネイルヘッドボンディング法によって、ワイヤ7Aを内部電極4Aに接続するようにした。したがって、内部電極4Aを小さくすることができ、光検出半導体装置1Aを小型化することができる。 (2) The wire 7A is connected to the internal electrode 4A by a nail head bonding method in which even a small electrode can be connected. Therefore, the internal electrode 4A can be reduced, and the photodetection semiconductor device 1A can be reduced in size.

(3)内部電極4Aを形成し、光検出半導体素子2Aを内部電極4A上にフリップチップ接続し、ループ高さが光検出半導体素子2Aの高さより高くなるようにワイヤ7Aを内部電極4Aにワイヤボンディングした。そして、光検出半導体素子2Aと、内部電極4Aと、ワイヤ7Aとを樹脂封止し、ワイヤ7Aが2つに分割されるまで樹脂封止体62を削り、樹脂封止体62の削った面(研磨面65)に、分割されたワイヤ7Aのうちの内部電極4Aと接続したワイヤ7Aと接続する外部電極6Aを形成した。さらに、分割されたワイヤ7Aのうちの内部電極4Aと接続していないワイヤ64を取り除くように外部電極6Aを形成した樹脂封止体62を切断して分割して光検出半導体装置1Aを製造した。したがって、小型化可能な光検出半導体装置1Aを容易に製造することができる。 (3) The internal electrode 4A is formed, the photodetection semiconductor element 2A is flip-chip connected to the internal electrode 4A, and the wire 7A is connected to the internal electrode 4A so that the loop height is higher than the height of the photodetection semiconductor element 2A. Bonded. Then, the photodetection semiconductor element 2A, the internal electrode 4A, and the wire 7A are resin-sealed, and the resin sealing body 62 is shaved until the wire 7A is divided into two, and the surface of the resin sealing body 62 is shaved. The external electrode 6A connected to the wire 7A connected to the internal electrode 4A among the divided wires 7A was formed on the (polished surface 65). Further, the resin sealing body 62 on which the external electrode 6A is formed is cut and divided so as to remove the wire 64 that is not connected to the internal electrode 4A among the divided wires 7A, thereby manufacturing the photodetecting semiconductor device 1A. . Therefore, the photodetection semiconductor device 1A that can be miniaturized can be easily manufactured.

(4)内部電極4Aを形成するときにさらにダミー電極44を形成し、ループ高さが光検出半導体素子2Aの高さより高くなるように内部電極4Aとダミー電極44とをワイヤ7Aでワイヤボンディングするようにした。ワイヤ7Aの内部電極4Aと接続していない側の端も強固に固定されるので、樹脂封止工程で樹脂封止するときにワイヤ7Aが動くのを防止することができる。 (4) When the internal electrode 4A is formed, the dummy electrode 44 is further formed, and the internal electrode 4A and the dummy electrode 44 are wire-bonded with the wire 7A so that the loop height is higher than the height of the light detection semiconductor element 2A. I did it. Since the end of the wire 7A that is not connected to the internal electrode 4A is also firmly fixed, it is possible to prevent the wire 7A from moving when the resin is sealed in the resin sealing step.

以上の実施形態の光検出半導体装置1Aを次のように変形することができる。
(1)受光開口11Aを覆う基板としてガラス基板3Aを使用したが、検出する光を透過する基板であればガラス基板3Aに限定されない。たとえば、プラスチック基板を使用してもよい。
The photodetection semiconductor device 1A of the above embodiment can be modified as follows.
(1) Although the glass substrate 3A is used as a substrate that covers the light receiving opening 11A, the substrate is not limited to the glass substrate 3A as long as it is a substrate that transmits light to be detected. For example, a plastic substrate may be used.

(2)内部電極4Aとワイヤ7Aとをネイルヘッドボンディング法によって接続したが、同じくワイヤ7Aのループ高さを調整できるウェッジボンディング法によって接続するようにしてもよい。 (2) Although the internal electrode 4A and the wire 7A are connected by the nail head bonding method, they may be connected by the wedge bonding method that can also adjust the loop height of the wire 7A.

(3)半導体素子の一方の面側の樹脂表面に設けられ、バンプを介して半導体素子の端子電極が接続される内部電極と、半導体素子の他方の面側の樹脂表面に設けられ、ワイヤを介して内部電極が接続され、表面に露出する外部電極とを備える半導体装置であれば、光検出半導体装置に限定されない。 (3) An internal electrode provided on the resin surface on one surface side of the semiconductor element, to which the terminal electrode of the semiconductor element is connected via a bump, and provided on the resin surface on the other surface side of the semiconductor element, The semiconductor device is not limited to the photodetection semiconductor device as long as the semiconductor device includes an external electrode that is connected to the internal electrode and exposed to the surface.

(4)樹脂8Aはエポキシ系樹脂に限定されない。 (4) The resin 8A is not limited to an epoxy resin.

(5)研磨面65にスパッタ法によって金属電極を形成したが、蒸着法で形成してもよい。また、金属電極の材料もTiやPdに限定されない。金属電極の上にめっき法で形成する金属層もNi層に限定されない。たとえば、Ni層の代りにCu層を形成するようにしてもよい。 (5) Although the metal electrode is formed on the polished surface 65 by sputtering, it may be formed by vapor deposition. Further, the material of the metal electrode is not limited to Ti or Pd. The metal layer formed by plating on the metal electrode is not limited to the Ni layer. For example, a Cu layer may be formed instead of the Ni layer.

−第1の実施形態−
本発明の第1の実施形態の半導体装置について図7を参照して説明する。図7は半導体装置1Bの構成を説明するための図である。
-First embodiment-
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 7 is a diagram for explaining the configuration of the semiconductor device 1B.

図7に示すように、半導体装置1Bは、半導体素子2Bを樹脂8Bで封止したものであり、半導体装置1Bの一方の面には外部電極6Bを、他方の面には、ダイパッド9Bを備える。外部電極6Bと半導体素子2Bの端子22Bとはバンプ5Bを介して接続している。ダイパッド9Bの開放面の裏側の面では、半導体素子2Bがダイボンディングされている。   As shown in FIG. 7, a semiconductor device 1B is obtained by sealing a semiconductor element 2B with a resin 8B. The semiconductor device 1B includes an external electrode 6B on one surface and a die pad 9B on the other surface. . The external electrode 6B and the terminal 22B of the semiconductor element 2B are connected via the bump 5B. The semiconductor element 2B is die-bonded on the back surface of the open surface of the die pad 9B.

次に、上述した半導体装置1Bの製造方法について、図8〜図10を参照して説明する。半導体装置1Bの製造方法は、ダイパッド形成工程、半導体素子搭載工程、バンプ形成工程、樹脂封止工程、研磨工程、外部電極形成工程、剥離工程および分割工程を備える。   Next, a method for manufacturing the above-described semiconductor device 1B will be described with reference to FIGS. The manufacturing method of the semiconductor device 1B includes a die pad forming process, a semiconductor element mounting process, a bump forming process, a resin sealing process, a polishing process, an external electrode forming process, a peeling process, and a dividing process.

(1)ダイパッド形成工程
ダイパッド形成工程では、半導体装置1Bのダイパッド9Bを形成する。ダイパッド形成工程について、図8を参照して説明する。
(1) Die Pad Forming Step In the die pad forming step, the die pad 9B of the semiconductor device 1B is formed. The die pad forming process will be described with reference to FIG.

図8(a)に示すように、金属板91の両面にレジスト42を塗布またはラミネートする。金属板91には、厚さ約0.1mmの平板状のJIS規格のSUSステンレス鋼板またはCu板などの可撓性を有する金属薄板が使用される。次に、アクリルフィルムベースのパターンマスクフィルムを密着させ、紫外線により露光する。そして、現像し、図8(b)に示すように、ダイパッド9Bを形成する部分のレジスト42を除去する。金属板91の一方の面には電極を形成しないので、レジスト42によって全面が覆われたままである。   As shown in FIG. 8A, a resist 42 is applied or laminated on both surfaces of the metal plate 91. As the metal plate 91, a flexible metal thin plate such as a flat JIS stainless steel plate or a Cu plate having a thickness of about 0.1 mm is used. Next, an acrylic film-based pattern mask film is brought into intimate contact and exposed to ultraviolet rays. Then, development is performed, and as shown in FIG. 8B, the resist 42 in the portion where the die pad 9B is formed is removed. Since no electrode is formed on one surface of the metal plate 91, the entire surface remains covered with the resist 42.

次に、金属板41をAuめっき溶液に浸漬し、めっきにより金属板41のレジスト42によって被覆されていない部分にAu層を形成することによって、図8(c)に示すようにダイパッド9Bを形成する。そして、図8(d)に示すように、レジスト42を金属板91から剥離する。   Next, the die plate 9B is formed as shown in FIG. 8C by immersing the metal plate 41 in an Au plating solution and forming an Au layer on the portion of the metal plate 41 not covered with the resist 42 by plating. To do. Then, as shown in FIG. 8D, the resist 42 is peeled from the metal plate 91.

(2)半導体素子搭載工程
半導体素子搭載工程では、ダイパッド9Bの上に不図示のダイボンディング材を塗布し、その上に半導体素子2Bを搭載する(図9(a))。
(2) Semiconductor Element Mounting Step In the semiconductor element mounting step, a die bonding material (not shown) is applied on the die pad 9B, and the semiconductor element 2B is mounted thereon (FIG. 9A).

(3)バンプ形成工程
バンプ形成工程では、ダイパッド9B上に搭載した半導体素子2Bの端子22B上にバンプ5Bを形成する。バンプ5Bの形成には、ワイヤボンディング技術を利用する。たとえば、ネイルヘッドボンディング法によってバンプ5Bを形成する場合について説明する。バンプ5BにはAuワイヤが使用される。
(i)Auワイヤをキャピラリに通し、Auワイヤの先端を溶融してボールを形成する。
(ii)ボールを半導体素子2Bの端子22B上に圧着する。
(iii)クランパでAuワイヤを引っ張り、切断してバンプを形成する。
(iv)Auワイヤをキャピラリに通し、Auワイヤの先端を溶融してボールを形成する。(v)ボールをバンプ上に圧着する。
(vi)クランパでAuワイヤを引っ張り、切断する。
以上のようにして、図9(b)に示すように、2つのバンプを重ねたバンプ5Bが半導体素子2Bの端子22B上に形成される。
(3) Bump formation process In a bump formation process, bump 5B is formed on terminal 22B of semiconductor element 2B mounted on die pad 9B. A wire bonding technique is used for forming the bumps 5B. For example, a case where the bump 5B is formed by a nail head bonding method will be described. Au wires are used for the bumps 5B.
(I) The Au wire is passed through the capillary and the tip of the Au wire is melted to form a ball.
(Ii) The ball is crimped onto the terminal 22B of the semiconductor element 2B.
(Iii) The Au wire is pulled with a clamper and cut to form bumps.
(Iv) The Au wire is passed through the capillary and the tip of the Au wire is melted to form a ball. (V) Crimp the ball onto the bump.
(Vi) Pull the Au wire with a clamper and cut it.
As described above, as shown in FIG. 9B, a bump 5B in which two bumps are overlapped is formed on the terminal 22B of the semiconductor element 2B.

(4)樹脂封止工程
樹脂封止工程では、図9(c)に示すように、バンプ5Bを形成した半導体素子2Bを樹脂封止する。樹脂8Bには、第1の実施形態と同様に熱硬化性エポキシ系樹脂などが使用される。以下、図9(c)に示す樹脂8Bを硬化させたものを樹脂封止体92と呼ぶ。
(4) Resin sealing process In the resin sealing process, as shown in FIG.9 (c), the semiconductor element 2B in which the bump 5B was formed is resin-sealed. As the resin 8B, a thermosetting epoxy resin or the like is used as in the first embodiment. Hereinafter, the cured resin 8B shown in FIG.

(5)研磨工程
研磨工程では、樹脂封止体92の面のうち、ダイパッド9Bが設けられている面と反対側の面(以下、上面と呼ぶ)を研磨して、樹脂封止体92の上面を削る。図9(d)に示すように、研磨面93にバンプ5Bが現れ、バンプ5Bの一部が削れるまで樹脂封止体92は研磨される。
(5) Polishing Step In the polishing step, the surface of the resin sealing body 92 that is opposite to the surface on which the die pad 9B is provided (hereinafter referred to as the upper surface) is polished. Sharpen the top surface. As shown in FIG. 9D, the bump 5B appears on the polishing surface 93, and the resin sealing body 92 is polished until a part of the bump 5B is scraped.

(6)外部電極形成工程
外部電極形成工程では、樹脂封止体92の研磨面93に、バンブ5Bと接続するための外部電極6Bを形成する。外部電極6Bは、第1の実施形態と同様にスパッタ法とめっき法とにより形成される(図10(a))。
(6) External Electrode Forming Step In the external electrode forming step, the external electrode 6B for connecting to the bump 5B is formed on the polishing surface 93 of the resin sealing body 92. The external electrode 6B is formed by sputtering and plating as in the first embodiment (FIG. 10A).

(7)剥離工程
剥離工程では、図10(b)に示すように、樹脂封止体92から金属板91を剥離する。上述したように金属板91は可撓性を有するので、容易に取り外すことができる。
(7) Peeling Step In the peeling step, the metal plate 91 is peeled from the resin sealing body 92 as shown in FIG. As described above, since the metal plate 91 has flexibility, it can be easily removed.

(8)分割工程
分割工程では、金属板91を剥離した樹脂封止体92を分割して、半導体装置1Bを作製する。分割工程では、図10(c)に示すように、1点鎖線94に沿って、ダイヤモンドブレード・ダイシング法で樹脂封止体92をダイシングする。そして、図10(d)に示すように、一つの樹脂封止体92が分割され、半導体装置1Bが完成する。
(8) Division Step In the division step, the resin sealing body 92 from which the metal plate 91 has been peeled is divided to produce the semiconductor device 1B. In the dividing step, as shown in FIG. 10C, the resin sealing body 92 is diced along the one-dot chain line 94 by the diamond blade dicing method. Then, as shown in FIG. 10D, one resin sealing body 92 is divided, and the semiconductor device 1B is completed.

以上のようにして作製された半導体装置1Bの外部電極6Bは、図11に示すように、回路基板95の電極96と半田97を介して実装される。一方、半導体装置1Bのダイパッド9Bは、回路基板95を被せた放熱板98と半田99を介して接続される。このようにすることによって、半導体素子2に発生した熱は速やかに放熱板98で伝導され、放熱される。   The external electrode 6B of the semiconductor device 1B manufactured as described above is mounted via the electrode 96 and the solder 97 of the circuit board 95 as shown in FIG. On the other hand, the die pad 9 </ b> B of the semiconductor device 1 </ b> B is connected to the heat sink 98 covered with the circuit board 95 via the solder 99. By doing so, the heat generated in the semiconductor element 2 is quickly conducted by the heat radiating plate 98 and radiated.

以上の実施形態による半導体装置1Bは次のような作用効果を奏する。
(1)半導体素子2Bの一方の面側の樹脂表面に設けられ、バンプ5Bを介して半導体素子2Bの端子22Bが接続され、表面に露出する外部電極6Bと、半導体素子2Bの他方の面が接続され、表面に露出するダイパッド9Bとを備えるようにした。したがって、バンプ5Bで外部電極6Bと接合した半導体素子2Bが発生する熱を効率的に放熱することができる。
The semiconductor device 1B according to the above embodiment has the following operational effects.
(1) Provided on the resin surface on one surface side of the semiconductor element 2B, the terminal 22B of the semiconductor element 2B is connected via the bump 5B, the external electrode 6B exposed on the surface, and the other surface of the semiconductor element 2B are The die pad 9B is connected and exposed on the surface. Therefore, the heat generated by the semiconductor element 2B joined to the external electrode 6B by the bump 5B can be efficiently radiated.

(2)半導体素子2Bの端子22Bと外部電極6Bとを2つのバンプ5Bを介して接続するようにした。これにより、研磨面93と半導体素子2Bとの間の距離を広げることができるので、研磨工程で削りすぎて半導体素子2Bが研磨されるのを防止することができる。 (2) The terminal 22B of the semiconductor element 2B and the external electrode 6B are connected via two bumps 5B. Thereby, since the distance between the polishing surface 93 and the semiconductor element 2B can be increased, it is possible to prevent the semiconductor element 2B from being polished due to excessive grinding in the polishing process.

(3)可撓性を有する金属板91上にダイパッド9Bを形成し、ダイパッド9B上に半導体素子2Bを搭載し、ダイパッド9B上に搭載した半導体素子2Bにバンプ5Bを形成した。そして、半導体素子2Bと、バンプ5Bと、ダイパッド9Bとを樹脂封止して樹脂封止体92を作製し、バンプ5Bが表面に現れ、バンプ5Bの一部が削れるまで樹脂封止体92を削った。さらに、樹脂封止体92の削り面(研磨面93)に、バンプ5Bと接続する外部電極6Bを形成し、樹脂封止体92から金属板91を剥離し、樹脂封止体92を切断して分割して、半導体装置2Bを作製するようにした。したがって、半導体素子2Bの放熱性に優れた半導体装置2Bを容易に作製することができる。 (3) The die pad 9B was formed on the flexible metal plate 91, the semiconductor element 2B was mounted on the die pad 9B, and the bumps 5B were formed on the semiconductor element 2B mounted on the die pad 9B. Then, the semiconductor element 2B, the bump 5B, and the die pad 9B are resin-sealed to produce a resin sealing body 92. The bump 5B appears on the surface, and the resin sealing body 92 is removed until a part of the bump 5B is scraped. Shaved. Further, external electrodes 6B connected to the bumps 5B are formed on the shaving surface (polishing surface 93) of the resin sealing body 92, the metal plate 91 is peeled from the resin sealing body 92, and the resin sealing body 92 is cut. Thus, the semiconductor device 2B is manufactured. Therefore, the semiconductor device 2B excellent in heat dissipation of the semiconductor element 2B can be easily manufactured.

以上の実施形態の半導体装置1Bを次のように変形することができる。
(1)金属板91を樹脂封止体92から剥がしたが、金属板91を剥がさないで、そのまま樹脂封止体92を分割してもよい。図12に示すように、金属板91が半導体素子2Bの放熱板となり、半導体装置1Cのダイパッド9B側の面の面全体で放熱できるので、さらに放熱効率が高くなる。
The semiconductor device 1B of the above embodiment can be modified as follows.
(1) Although the metal plate 91 is peeled off from the resin sealing body 92, the resin sealing body 92 may be divided as it is without peeling off the metal plate 91. As shown in FIG. 12, the metal plate 91 serves as a heat radiating plate for the semiconductor element 2B, and heat can be radiated over the entire surface of the semiconductor device 1C on the die pad 9B side.

(2)ダイパッド9B上に搭載した半導体素子2Bに形成するバンプの重ねる数は2つに限定されず、半導体装置2Bの厚みや樹脂封止体92を削る削り精度によって適宜選択することができる。半導体装置2Bの厚みを厚くする場合は、重ねるバンプの数を多くし、薄くする場合は、重ねるバンプの数を少なくする。また、樹脂封止体92を削る削り精度が悪い場合、半導体素子2Bが削れるのを防止するために重ねるバンプの数を多くする。 (2) The number of bumps formed on the semiconductor element 2B mounted on the die pad 9B is not limited to two, and can be selected as appropriate depending on the thickness of the semiconductor device 2B and the cutting accuracy of cutting the resin sealing body 92. When the thickness of the semiconductor device 2B is increased, the number of bumps to be stacked is increased, and when the thickness is decreased, the number of bumps to be stacked is decreased. Further, when the shaving accuracy for shaving the resin sealing body 92 is poor, the number of bumps to be stacked is increased in order to prevent the semiconductor element 2B from being shaved.

(3)樹脂8Bはエポキシ系樹脂に限定されない。 (3) The resin 8B is not limited to an epoxy resin.

(4)研磨面93にスパッタ法によって金属電極を形成したが、蒸着法で形成してもよい。また、金属電極の材料もTiやPdに限定されない。金属電極の上にめっきで形成する金属もNi層に限定されない。たとえば、Ni層の代りにCu層を形成するようにしてもよい。 (4) Although the metal electrode is formed on the polished surface 93 by sputtering, it may be formed by vapor deposition. Further, the material of the metal electrode is not limited to Ti or Pd. The metal formed by plating on the metal electrode is not limited to the Ni layer. For example, a Cu layer may be formed instead of the Ni layer.

以上の説明はあくまで一例であり、発明は、上記の実施形態に何ら限定されるものではない。   The above description is merely an example, and the present invention is not limited to the above embodiment.

1A 光検出半導体装置
1B,1C 半導体装置
2A 光検出半導体素子
2B 半導体素子
3A,41 ガラス基板
4A 内部電極
5A,5B バンプ
6A,6B 外部電極
7A ワイヤ
8A,8B 樹脂
9B ダイパッド
11A 受光開口
21A 光検出部
22B 端子
44 ダミー電極
45 異方性導電ペースト
62,92 樹脂封止体
91 金属板
DESCRIPTION OF SYMBOLS 1A Photodetection semiconductor device 1B, 1C Semiconductor device 2A Photodetection semiconductor element 2B Semiconductor element 3A, 41 Glass substrate 4A Internal electrode 5A, 5B Bump 6A, 6B External electrode 7A Wire 8A, 8B Resin 9B Die pad 11A Light reception opening 21A Photodetection part 22B Terminal 44 Dummy electrode 45 Anisotropic conductive paste 62, 92 Resin sealing body 91 Metal plate

Claims (4)

半導体素子を樹脂封止した半導体装置において、
前記半導体素子の一方の面側の樹脂表面に設けられ、複数段に重ねて形成されたバンプを介して前記半導体素子の端子電極が接続され、表面に露出する外部電極と、
前記半導体素子の他方の面が接続され、表面に露出するダイパッドとを備えることを特徴とする半導体装置。
In a semiconductor device in which a semiconductor element is resin-sealed,
An external electrode provided on the resin surface on one side of the semiconductor element, connected to the terminal electrode of the semiconductor element via a bump formed in a plurality of layers, and exposed on the surface;
A semiconductor device comprising: a die pad connected to the other surface of the semiconductor element and exposed on the surface.
請求項1に記載の半導体装置において、
前記樹脂表面および前記最上段のバンプの上面は研磨面とされ、前記外部電極は、前記バンプの研磨面と前記樹脂の研磨面に跨って形成されていることを特徴とする半導体装置。
The semiconductor device according to claim 1,
The semiconductor surface, wherein the resin surface and the upper surface of the uppermost bump are polished surfaces, and the external electrodes are formed across the bump polished surface and the resin polished surface.
可撓性を有する板上に金属からなるダイパッドを形成するダイパッド形成工程と、
前記ダイパッド上に半導体素子を搭載する半導体素子搭載工程と、
前記ダイパッド上に搭載した半導体素子にバンプを複数段に重ねて形成するバンプ形成工程と、
前記半導体素子と、前記バンプと、前記ダイパッドとを樹脂封止して樹脂封止体を作製する樹脂封止工程と、
前記複数段に重ねて形成されたバンプの中、最上段のバンプが表面に現れるまで前記樹脂封止体を研磨する研磨工程と、
前記樹脂封止体の研磨面に、前記バンプと接続する外部電極を形成する外部電極形成工程と、
前記樹脂封止体から前記可撓性を有する板を剥離する剥離工程と、
前記樹脂封止体を切断して分割する分割工程とを備えることを特徴とする半導体装置の製造方法。
A die pad forming step of forming a metal die pad on a flexible plate;
A semiconductor element mounting step of mounting a semiconductor element on the die pad;
A bump forming step of forming a plurality of bumps on the semiconductor element mounted on the die pad;
A resin sealing step of resin-sealing the semiconductor element, the bump, and the die pad to produce a resin sealing body;
Among the bumps formed to overlap the plurality of steps, a polishing step of polishing the resin sealing body until the uppermost bump appears on the surface;
External electrode forming step of forming external electrodes connected to the bumps on the polished surface of the resin sealing body,
A peeling step of peeling the flexible plate from the resin sealing body;
A method for manufacturing a semiconductor device, comprising: a dividing step of cutting and dividing the resin sealing body.
請求項3に記載の半導体装置の製造方法において、
前記バンプ形成工程は、前記複数段に重ねて形成されたバンプをワイヤボンディング法により形成することを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the bump forming step includes forming a bump formed by overlapping the plurality of steps by a wire bonding method.
JP2011012779A 2011-01-25 2011-01-25 Semiconductor device and method of manufacturing the same Pending JP2011082583A (en)

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