JP2004158739A - Resin sealed semiconductor device and manufacturing method therefor - Google Patents

Resin sealed semiconductor device and manufacturing method therefor Download PDF

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Publication number
JP2004158739A
JP2004158739A JP2002324712A JP2002324712A JP2004158739A JP 2004158739 A JP2004158739 A JP 2004158739A JP 2002324712 A JP2002324712 A JP 2002324712A JP 2002324712 A JP2002324712 A JP 2002324712A JP 2004158739 A JP2004158739 A JP 2004158739A
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Prior art keywords
semiconductor chip
main surface
resin
support substrate
semiconductor device
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JP2002324712A
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Japanese (ja)
Inventor
Komei Matsushima
功明 松島
Koji Araki
浩二 荒木
Teruo Takeuchi
輝雄 竹内
Yoshiyuki Shimizu
禎之 清水
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Toshiba Corp
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Toshiba Corp
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Priority to JP2002324712A priority Critical patent/JP2004158739A/en
Publication of JP2004158739A publication Critical patent/JP2004158739A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve the moisture resistance of a thin resin sealed semiconductor device. <P>SOLUTION: The thin resin sealed semiconductor device is adapted such that the sides and the surface of a semiconductor chip 3 and the surface of a support substrate 1 are covered with resin 5, the back surface of the exposed semiconductor chip 3 and the resin 5 on the opposite sides are covered with a metal layer 7, and hence the semiconductor chip 3 does not expose any surface thereof. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、薄型化に有利な樹脂封止型半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
近年、電子機器の小型化に対応するために、薄型で、且つ高信頼性の樹脂封止型半導体装置の開発が盛んにおこなわれている。
【０００３】
この種の樹脂封止型半導体装置としては、図９に示すものが知られている（例えば、特許文献１参照。）。
【０００４】
図９は樹脂封止型半導体装置の製造方法を工程順に示す断面図である。
【０００５】
この特許文献１に開示された樹脂封止型半導体装置では、まず図９（ａ）に示すように、表面上に電極１０２ａを有する支持基板１０１に対して、表面の電極１０２ｂ上に金属バンプ１０４を有する半導体チップ１０３を、その表面が支持基板１０１表面と向き合う、いわゆるフェースダウンに配置し、電極１０２ａとバンプ１０４とを接合した後、支持基板１０１の主面部分、半導体チップ１０３の両側面および裏面部分を樹脂１０５でモールドする。
【０００６】
次に、図９（ｂ）に示すように、グラインダー１０６にて、半導体チップ１０３の裏面上の樹脂１０５を研磨し、半導体チップ１０３の裏面を露呈させた後、更に、図９（ｃ）に示すように、半導体チップ１０３の裏面を、イニシャルチップ厚Ｔ３、例えば１５０〜３００ｕｍからファイナルチップ厚Ｔ５、例えば５０〜１００ｕｍまで研磨し、半導体チップ１０３を薄くする。
【０００７】
そして、図９（ｄ）に示すように、細長い方形状のダイシングソー１０８を用いて、半導体チップ１０３間の切断ラインＤ部分を研削し、図９（ｅ）に示すように、樹脂封止型半導体装置１２０を、個々に切り出す。この切り出し工程によって切り出された樹脂封止型半導体装置１２０は、半導体チップ１０３の裏面側が露呈され、半導体チップ１０３の側面および表面が樹脂１０５で覆われている。
【０００８】
【特許文献１】
特開２００１―５７４０４号公報（第８頁、第１図）
【０００９】
【発明が解決しようとする課題】
上述した従来の樹脂封止型半導体装置においては、半導体チップの厚さが薄く、しかも半導体チップの裏面が露呈されているため、半導体チップと支持基板との電極の接合部分に湿気が侵入し易く、半導体装置の信頼性、特に、耐湿性に劣るという問題がある。
【００１０】
本発明は、上記問題に鑑みてなされたもので、その目的とするところは、耐湿性を改善して、高信頼性を確保できる薄型の樹脂封止型半導体装置およびその製造方法を提供することにある。
【００１１】
【課題を解決するための手段】
上記目的を達成するために、本発明の半導体装置は、主面に電極を有する支持基板と、第１主面に電極を有し、且つこの第１主面が前記支持基板の主面と対向配置された半導体チップと、前記支持基板の電極と前記半導体チップの電極を接合するバンプと、前記第１主面と相対向する半導体チップの第２主面を露呈させ、少なくとも、前記支持基板周辺部の主面部分および前記半導体チップの側面を覆う樹脂と、前記半導体チップの第２主面およびその両側面部の前記樹脂の表面上に形成された導電性フィルムとを具備することを特徴とする。
【００１２】
また、上記目的を達成するために、本発明の半導体装置の製造方法は、主面上に電極を有する支持基板と第１主面に電極を有する半導体チップとを、その両主面が相対向するように配置し、且つ両電極をバンプにより接合する工程と、前記支持基板周辺部の主面部分、少なくとも前記半導体チップの両側面および前記第１主面と相対向する第２主面部分を樹脂モールドする工程と、前記半導体チップの第２主面上の前記樹脂および前記第２主面側の半導体チップの一部を研磨する工程と、前記半導体チップの第２主面およびその半導体チップの両側面部分の樹脂表面に導電性または絶縁性フィルムを形成する工程とを具備したことを特徴とする。
【００１３】
本発明によれば、半導体チップの第２主面およびその両側面部の樹脂表面が、導電性、または絶縁性フィルムですべて覆われているため、耐湿性の優れた薄型の樹脂封止型半導体装置が得られる。しかも、その製造方法はフィルムを形成するだけであり、非常に簡単である。
【００１４】
【発明の実施の形態】
以下本発明の実施形態について図面を参照しながら説明する。
【００１５】
（第１の実施の形態）
まず、本発明の第１の実施の形態に係わる樹脂封止型半導体装置およびその製造方法について、図１を参照して説明する。図１は本発明の第１の実施の形態の樹脂封止型半導体装置の製造方法を工程順に示す断面図である。
【００１６】
図１（ａ）に示すように、表面上にＡｕ、Ｃｕ、およびＡｌ等の電極２ａを有するエポキシ基板、ポリイミド基板、およびセラミック基板等の支持基板１に対して、表面の電極２ｂ上にＰｂ系、Ｓｎ−Ａｇ系、およびＳｎ−Ｂｉ系半田、またはＡｕからなる金属バンプ４を有する半導体チップ３を、その半導体チップ３の表面（第１主面）が支持基板１の表面と向き合う、いわゆるフェースダウンに配置し、電極２ａとバンプ４とを接合した後、支持基板１の主面部分、半導体チップ３の両側面および裏面（第２主面）部分をエポキシ系樹脂５でモールドする。
【００１７】
この樹脂５のモールドに先立って、支持基板１の主面と半導体チップ３の表面との間をある一定の粘度を有する樹脂で覆っておいてもよい。
【００１８】
次に、図１（ｂ）に示すように、グラインダー６にて、半導体チップ３の裏面上の樹脂５を研磨し、半導体チップ３の裏面を露呈させた後、更に、図１（ｃ）に示すように、半導体チップ３の裏面を、イニシャルチップ厚Ｔ３、例えば２００ｕｍからファイナルチップ厚Ｔ５、例えば５０ｕｍまで表面と平行に研磨し、半導体チップ３を薄くする。この工程により、半導体チップ３の裏面とその両側面部の樹脂５の表面とは、同一平面に形成される。
【００１９】
つづいて、図１（ｄ）に示すように、半導体チップ３の裏面およびその両側面部の樹脂５の表面に、導電性フィルムとしての金属層７を形成する。この金属層７は、まず半導体チップ３との密着性を保つ目的で厚さ１００ｎｍのＴｉＮ層を形成し、次に連続的に厚さ５ｕｍのＡｕを形成した積層構造になっている。
【００２０】
ここで、金属層７にはＴｉＮ／Ａｕを用いているが、半導体チップ３との密着性を有する他のＴｉ、ＷＮ、ＷＳｉ、およびＢａＮｉ等の金属を用いてもよい。また、Ａｕの代わりにＣｕ、Ｗおよびその金属化合物を用いてもよい。
【００２１】
そして、図１（ｅ）に示すように、細長い方形状のダイシングソー８を用いて、半導体チップ３間の切断ラインＤ部分を研削し、図１（ｆ）に示すように、樹脂封止型半導体装置２０を、個々に切り出す。この切り出し工程によって切り出された樹脂封止型半導体装置２０は、半導体チップ３の裏面およびその両側部の樹脂５の表面が金属層７で覆われ、半導体チップ３の側面および表面と支持基板１の表面が樹脂５で覆われており、半導体チップ３は、どの面も露呈されていない。
【００２２】
しかも、基板厚Ｔ１と、接合部厚Ｔ２と、ファイナルチップ厚Ｔ５と、および金属層厚Ｔ６からなる半導体装置の厚さが２００ｕｍと薄くなっている。
【００２３】
本実施の形態の樹脂封止型半導体装置においては、半導体チップ３の側面および表面と支持基板１の表面が樹脂５で覆われ、しかも露呈された半導体チップ３の裏面およびその両側面部の樹脂５の表面が金属層７で覆われ、半導体チップ３は、どの面も露呈されておらず、耐湿性が向上し、あわせて、半導体チップ３の裏面に、直接、金属層７が形成されていることから、その放熱効果により装置の熱抵抗も改善され、信頼性が向上する。
【００２４】
また、露呈された半導体チップ３の裏面およびその両側面部の樹脂５の表面に金属層７を形成するだけであり、製造方法も簡単である。
【００２５】
（第１の実施の形態の変形例）
次に、本発明の第１の実施の形態の変形例に係わる樹脂封止型半導体装置およびその製造方法について、図２を参照して説明する。図２はその樹脂封止型半導体装置の断面図である。
【００２６】
この変形例は、第１の実施の形態の金属層７を絶縁性フィルムとしてのコーテイング膜１１に変更した点で異なり、それ以外の構成・工程順については同一であり、以下、異なる点のみ説明する。すなわち、ゴム系、シリコーン系、エポキシ系、テフロン（Ｒ）系、およびウレタン系の樹脂、またはＡｌ２Ｏ３（アルミナ）、ＡｌＮ（窒化アルミ）、ＳｉＣ、およびＳＯＧ（スピンオングラス）を含めたガラス等からなるコーテイング膜１１を上記第１の実施の形態の金属層７に代えて、膜厚数ｕｍから約１０ｕｍ程度形成してなる。
【００２７】
本実施の形態の樹脂封止型半導体装置においては、半導体チップ３の側面および表面と支持基板１の表面が樹脂５で覆われ、しかも、露呈された半導体チップ３の裏面およびその両側面部の樹脂５の表面がコーテイング膜１１で覆われ、半導体チップ３はどの面も露呈されておらず、耐湿性が向上する。また、露呈された半導体チップ３の裏面およびその両側面部の樹脂５の表面にコーテイング膜１１を形成するだけであり、製造方法も簡単である。
【００２８】
（第２の実施の形態）
次に、本発明の第２の実施の形態に係わる樹脂封止型半導体装置およびその製造方法について、図３及び図４を参照して説明する。図３は本発明の第２の実施の形態の樹脂封止型半導体装置に用いられる半導体チップの製造方法を工程順に示す断面図であり、図４は本発明の第２の実施の形態の樹脂封止型半導体装置の製造方法を工程順に示す断面図である。
【００２９】
本実施の形態は、第１の実施の形態と半導体チップ３ａの形状およびその形成方法が異なり、それ以外の構成・工程順については同一である。
【００３０】
本実施の形態における半導体チップ３ａは、まず、図３（ａ）に示すように、研磨され厚さ２００ｕｍのウエーハ９の表面に、ダイシングテープ１０を貼り付けた後、図３（ｂ）に示すように、ウエーハ９の裏面側からウエーハ９の切断ラインＥ部分を、刃先に角度をもたせた形状のダイシングソー８ａを用いて、深さ１７０ｕｍまで研削する。
【００３１】
引き続いて、図３（ｃ）に示すように、連続的にウエーハ９の切断ラインＥ部分を、細長い方形状のダイシングソー８を用いて、ダイシングテープ１０の表面まで研削し、個々に分離する。
【００３２】
ここで、ダイシングする場所の特定方法としては、ウエーハ９の裏面側からウエーハ９の表面側のパターンが識別できる波長を用いた顕微鏡システムにて、ダイシング予定部分を確認し、研削する。例えばシリコンウエーハでは、１３６０ｎｍの単一波長を有するレーザー顕微鏡システムを用いることができる。また、刃先に角度をもたせた形状のダイシングソー８ａと細長い方形状のダイシングソー８による２回のダイシングをデユアルダイサー装置により連続的にダイシングすれば、ダイシングする場所ずれが防止できる。
【００３３】
そして、図３（ｄ）に示すように、ダイシングされ、個々に分離された半導体チップ３ａは、ダイシングテープ１０から剥離される。この個々に分離された半導体チップ３ａは、裏面の両端がカットされたテ−パ形状を有し、表面の面積に比べて裏面の面積が小さい台形状を有する。ここでは、半導体チップ３ａは、裏面の両端部分がカットされたテーパ形状を有するが、裏面の両端部分を階段状にカットされた形状でもよい。
【００３４】
次に、図３（ｅ）に示すように、表面の電極２ｂ上に金属バンプ４を形成することにより、半導体チップ３ａが完成する。
【００３５】
そして、図４（ａ）に示すように、表面上に電極２ａを有する支持基板１に対して、表面の電極２ｂ上に金属バンプ４を有する半導体チップ３ａを、その半導体チップ３ａの表面（第１主面）が支持基板１の表面と向き合う、いわゆるフェースダウンに配置し、電極２ａとバンプ４とを接合した後、支持基板１の主面部分、半導体チップ３ａの両側面および裏面（第２主面）部分をエポキシ系樹脂５でモールドする。
【００３６】
次に、図４（ｂ）に示すように、グラインダー６にて、半導体チップ３ａの裏面上の樹脂５を研磨し、半導体チップ３ａの裏面を露呈させた後、更に、図４（ｃ）に示すように、半導体チップ３ａの裏面を、イニシャルチップ厚Ｔ３、例えば２００ｕｍからファイナルチップ厚Ｔ５、例えば５０ｕｍまで表面と平行に研磨し、半導体チップ３ａを薄くする。この工程により、半導体チップ３ａの裏面とその両側面部の樹脂５の表面とは、同一平面に形成される。
【００３７】
つづいて、図４（ｄ）に示すように、半導体チップ３ａの裏面およびその両側面部の樹脂５の表面に、金属層７を形成する。この金属層７は、まず半導体チップ３ａとの密着性を保つ目的で厚さ１００ｎｍのＴｉＮ層を形成し、次に連続的に厚さ５ｕｍのＡｕを形成した積層構造になっている。そして、細長い方形状のダイシングソー８を用いて、半導体チップ３ａ間の切断ラインＤ部分を研削し、図４（ｅ）に示すように、樹脂封止型半導体装置２０を、個々に切り出す。この切り出し工程によって切り出された樹脂封止型半導体装置２０は、半導体チップ３ａの裏面およびその両側部の樹脂５の表面が金属層７で覆われ、半導体チップ３ａの側面および表面と支持基板１の表面が樹脂５で覆われており、半導体チップ３ａは、どの面も露呈されていない。
【００３８】
しかも、基板厚Ｔ１と、接合部厚Ｔ２と、ファイナルチップ厚Ｔ５と、及び金属層厚Ｔ６からなる半導体装置の厚さが２００ｕｍと薄くなっている。
【００３９】
本実施の形態の半導体装置においては、半導体チップ３ａの側面および表面と支持基板１の表面が樹脂５で覆われ、しかも、露呈された半導体チップ３ａの裏面およびその両側面部の樹脂５が金属層７で覆われ、半導体チップ３ａはどの面も露呈されておらず、耐湿性が向上し、あわせて、半導体チップ３ａの裏面に、直接金属層７が形成されていることから、その放熱効果により装置の熱抵抗も改善され、信頼性が向上する。
【００４０】
さらに、半導体チップ３ａの裏面の両端部分がカットされたテーパー形状を有し、この両端部上に樹脂５が形成されていることから、支持基板１と樹脂５の熱膨張係数の差に起因する半導体チップ３ａの剥離現象が抑制され、いわゆるアンカー効果が生じ、熱サイクルに対しても強い。また、格別な工程を必要とせず、製造方法も簡単である。
【００４１】
（第２の実施の形態の変形例）
次に、本発明の第２の実施の形態の変形例に係わる樹脂封止型半導体装置およびその製造方法について、図５を参照して説明する。図５はその樹脂封止型半導体装置の断面図である。
【００４２】
この変形例は、第２の実施の形態の金属層７をコーテイング膜１１に変更した点で異なり、それ以外の構成・工程順については同一であり、以下、異なる点のみ説明する。すなわち、第２の実施の形態の金属層７に代えて、上記第１の実施の形態の変形例と同じコーテイング膜１１を膜厚数ｕｍから約１０ｕｍ程度形成してなる。
【００４３】
本実施の形態の半導体装置およびその製造方法においては、半導体チップ３ａの側面および表面と支持基板１の表面が樹脂５で覆われ、しかも、露呈された半導体チップ３ａ裏面およびその両側面部の樹脂５がコーテイング膜１１で覆われ、半導体チップ３ａはどの面も露呈されておらず、耐湿性が向上する。
【００４４】
さらに、半導体チップ３ａの裏面の両端部分がカットされたテーパー形状を有し、この両端部上に樹脂５が形成されていることから、支持基板１と樹脂５の熱膨張係数の差に起因する半導体チップ３ａの剥離現象が抑制され、いわゆるアンカー効果が生じ、熱サイクルに強い。また、格別な工程も必要とせず、製造方法も簡単である。
【００４５】
（第３の実施の形態）
次に、本発明の第３の実施の形態に係わる樹脂封止型半導体装置およびその製造方法について、図６及び図７を参照して説明する。図６は本発明の第３の実施の形態の樹脂封止型半導体装置に用いられる半導体チップの製造方法を工程順に示す断面図であり、図７は本発明の第３の実施の形態の樹脂封止型半導体装置を示す断面図である。
【００４６】
本実施の形態は、第１の実施の形態と半導体チップ３ｂの形状およびその形成方法が異なり、それ以外の構成・工程順については同一である。
【００４７】
本実施の形態における半導体チップ３ｂは、まず、図６（ａ）に示すように、研磨され厚さ２００ｕｍのウエーハ９の裏面に、ダイシングテープ１０を貼り付けた後、図６（ｂ）に示すように、ウエーハ９の表面側からウエーハ９の切断ラインＤ部分を、刃先に角度をもたせた形状のダイシングソー８ａを用いて、深さ２０ｕｍまでウエーハ９を研削し、三角形状の溝３０ａを形成する。
【００４８】
つづいて、図６（ｃ）に示すように、ダイシングテープ１０を剥離し、再度ウエーハ９の表面側にダイシングテープ１０を貼り付けた後、図６（ｄ）に示すように、ウエーハ９の切断ラインＤ部分を、ウエーハ９の裏面側から刃先に角度をもたせた形状のダイシングソー８ａを用いて、深さ１６０ｕｍまでウエーハ９を研削し、三角形状の溝３０ｂを形成する。引き続いて、図６（ｅ）に示すように、細長い方形状のダイシングソー８を用いて、溝３０ｂを貫いてダイシングテープ１０表面に達するまで研削し、図６（ｆ）に示すように、半導体チップ３ｂは、完全にダイシングカットされる。
【００４９】
さらに、図６（ｇ）に示すように、ダイシングされ、個々に分離された半導体チップ３ｂは、ダイシングテープ１０から剥離される。この個々に分離された半導体チップ３ｂは、表面の面積に比べて裏面の面積が小さく、表面および裏面の両端部がテーパー状にカットされ、且つ表面および裏面の面積が、その表面および裏面間の横断面積に比べて小さい構造を有する。ここでは、半導体チップ３ｂは、表面および裏面の両端部分がテーパー状にカットされた構造を有するが、表面および裏面の両端部分が階段状にカットされた構造であってもよい。
【００５０】
次に、図６（ｈ）に示すように、表面の電極２ｂ上に金属性のバンプ４を形成することにより、半導体チップ３ｂが完成する。この後、第１の実施の形態における図１と同様な各工程を経て個々の半導体装置２０を得る。
【００５１】
そして、個々に切り出された半導体装置２０は、図７に示すように、半導体チップ３ｂの裏面およびその両側面部の樹脂５が金属層７で覆われ、半導体チップ３ｂ側面および表面と支持基板１表面が樹脂５で覆われており、半導体チップ３ｂはどの面も露呈されていない。しかも、半導体チップ３ｂの表面および裏面の両端部分は、カットされ、基板厚Ｔ１、接合部厚Ｔ２、ファイナルチップ厚Ｔ５および及び金属層厚Ｔ６からなる半導体装置２０の厚さが２００ｕｍと薄くなっている。
【００５２】
本実施の形態の半導体装置においては、半導体チップ３ｂの側面および表面と支持基板１の表面が樹脂５で覆われ、しかも、露呈された半導体チップ３ｂの裏面およびその両側面部の樹脂５が金属層７で覆われ、半導体チップ３ｂはどの面も露呈されておらず、耐湿性が向上し、あわせて、半導体チップ３ｂの裏面に、直接、金属層７が形成されていることから、その放熱効果により装置の熱抵抗も改善され、信頼性が向上する。
【００５３】
さらに、半導体チップ３ｂの表面および裏面の両端部分がカットされたテーパー形状を有し、この両端部上に樹脂５が形成されていることから、支持基板１と樹脂５の熱膨張係数の差に起因する半導体チップ３ｂの剥離現象が抑制され、いわゆるアンカー効果が生じ、さらに熱サイクルに対して強い。また、格別な工程を必要とせず、製造方法も簡単である。
【００５４】
（第３の実施の形態の変形例）
次に、本発明の第３の実施の形態の変形例に係わる樹脂封止型半導体装置およびその製造方法について、図８を参照して説明する。図８はその樹脂封止型半導体装置の断面図である。
【００５５】
この変形例は、第３の実施の形態の金属層７をコーテイング膜１１に変更した点で異なり、それ以外の構成・工程順については同一であり、以下、異なる点にのみ説明する。すなわち、上記第３の実施の形態の金属層７に代えて、第１の実施の形態の変形例と同じコーテイング膜１１を膜厚数ｕｍから約１０ｕｍ程度形成してなる。
【００５６】
本実施の形態の半導体装置においては、半導体チップ３ｂの側面および表面と支持基板１表面が樹脂５で覆われ、しかも、露呈された半導体チップ３ｂ裏面およびその両側面部の樹脂５がコーテイング膜１１で覆われ、半導体チップ３ｂはどの面も露呈されておらず、耐湿性が向上する。
【００５７】
さらに、半導体チップ３ｂの表面および裏面の両端部分がカットされたテーパー形状を有し、この両端部上に樹脂５が形成されていることから、支持基板１と樹脂５の熱膨張係数の差に起因する半導体チップ３ｂの剥離現象が抑制され、いわゆるアンカー効果が生じ、上記実施の形態よりもさらに熱サイクルに対して強い。また、格別な工程も必要とせず、製造方法も簡単である。
【００５８】
【発明の効果】
本発明によれば、耐湿性に優れた高信頼性を有する薄型の樹脂封止型半導体装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態に係わる樹脂封止型半導体装置の製造方法を工程順に示す断面図。
【図２】本発明の第１の実施の形態の変形例に係わる樹脂封止型半導体装置を示す断面図。
【図３】本発明の第２の実施の形態に用いられる半導体チップの製造方法を工程順に示す断面図。
【図４】本発明の第２の実施の形態に係わる樹脂封止型半導体装置の製造方法を工程順に示す断面図。
【図５】本発明の第２の実施の形態の変形例に係わる樹脂封止型半導体装置を示す断面図。
【図６】本発明の第３の実施の形態に用いられる半導体チップの製造方法を工程順に示す断面図。
【図７】本発明の第３の実施の形態に係わる樹脂封止型半導体装置を示す断面図。
【図８】本発明の第３の実施の形態の変形例に係わる樹脂封止型半導体装置を示す断面図。
【図９】従来の樹脂封止型半導体装置の製造方法を工程順に示す断面図。
【符号の説明】
１、１０１ 支持基板
２ａ、２ｂ、１０２ａ、１０２ｂ 電極
３、３ａ、３ｂ、１０３ 半導体チップ
４、１０４ バンプ
５、１０５ 樹脂
６、１０６ グラインダー
７ 金属層
８、８ａ、１０８ ダイシングソー
９ ウエーハ
１０ ダイシングテープ
１１ コーテイング膜
２０、１２０ 樹脂封止型半導体装置
３０ａ、３０ｂ 溝
Ｄ、Ｅ 切断ライン
Ｔ１ 基板厚
Ｔ２ 接合部厚
Ｔ３ イニシャルチップ厚
Ｔ４ 樹脂厚
Ｔ５ ファイナルチップ厚
Ｔ６ 金属層厚[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a resin-encapsulated semiconductor device advantageous for thinning and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a thin, highly reliable resin-encapsulated semiconductor device has been actively developed in order to cope with miniaturization of electronic devices.
[0003]
As this kind of resin-sealed semiconductor device, the one shown in FIG. 9 is known (for example, see Patent Document 1).
[0004]
FIG. 9 is a cross-sectional view illustrating a method for manufacturing the resin-sealed semiconductor device in the order of steps.
[0005]
In the resin-encapsulated semiconductor device disclosed in Patent Document 1, first, as shown in FIG. 9A, a metal bump 104 is formed on an electrode 102b on the surface with respect to a support substrate 101 having an electrode 102a on the surface. Is arranged face-down, the surface of which faces the surface of the support substrate 101, and after bonding the electrodes 102a and the bumps 104, the main surface portion of the support substrate 101, both side surfaces of the semiconductor chip 103 and The back surface is molded with resin 105.
[0006]
Next, as shown in FIG. 9B, the resin 105 on the back surface of the semiconductor chip 103 is polished by a grinder 106 to expose the back surface of the semiconductor chip 103. Then, as shown in FIG. As shown, the back surface of the semiconductor chip 103 is polished from an initial chip thickness T3, for example, 150 to 300 μm, to a final chip thickness T5, for example, 50 to 100 μm, to make the semiconductor chip 103 thin.
[0007]
Then, as shown in FIG. 9D, a cutting line D portion between the semiconductor chips 103 is ground by using an elongated rectangular dicing saw 108, and as shown in FIG. The semiconductor device 120 is cut out individually. In the resin-sealed semiconductor device 120 cut out by this cutting step, the back surface side of the semiconductor chip 103 is exposed, and the side surface and the surface of the semiconductor chip 103 are covered with the resin 105.
[0008]
[Patent Document 1]
JP 2001-57404 A (Page 8, FIG. 1)
[0009]
[Problems to be solved by the invention]
In the above-described conventional resin-encapsulated semiconductor device, since the thickness of the semiconductor chip is thin and the back surface of the semiconductor chip is exposed, moisture easily penetrates into the junction between the electrode of the semiconductor chip and the electrode of the supporting substrate. However, there is a problem that the reliability of the semiconductor device, particularly, the moisture resistance is poor.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a thin resin-encapsulated semiconductor device capable of improving moisture resistance and ensuring high reliability, and a method of manufacturing the same. It is in.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device of the present invention has a support substrate having an electrode on a main surface and an electrode on a first main surface, and the first main surface is opposed to the main surface of the support substrate. Exposing the arranged semiconductor chip, the bumps for joining the electrodes of the support substrate and the electrodes of the semiconductor chip, and the second main surface of the semiconductor chip facing the first main surface, at least in the vicinity of the support substrate; And a conductive film formed on the surface of the resin on the second main surface of the semiconductor chip and on both side surfaces of the second main surface of the semiconductor chip. .
[0012]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a supporting substrate having an electrode on a main surface; and a semiconductor chip having an electrode on a first main surface. And bonding the two electrodes by bumps, and forming a main surface portion around the support substrate, at least both side surfaces of the semiconductor chip, and a second main surface portion facing the first main surface. Resin molding; polishing the resin on the second main surface of the semiconductor chip and part of the semiconductor chip on the second main surface; and polishing the second main surface of the semiconductor chip and the semiconductor chip. Forming a conductive or insulating film on the resin surface on both side portions.
[0013]
According to the present invention, since the resin surface on the second main surface and both side surfaces of the semiconductor chip is entirely covered with a conductive or insulating film, a thin resin-encapsulated semiconductor device having excellent moisture resistance Is obtained. Moreover, the manufacturing method is very simple, only forming a film.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0015]
(First Embodiment)
First, a resin-sealed semiconductor device and a method for manufacturing the same according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view showing a method for manufacturing a resin-sealed semiconductor device according to a first embodiment of the present invention in the order of steps.
[0016]
As shown in FIG. 1 (a), a support substrate 1 such as an epoxy substrate, a polyimide substrate, or a ceramic substrate having an electrode 2a of Au, Cu, Al or the like on the surface is provided with Pb on an electrode 2b on the surface. A semiconductor chip 3 having a metal bump 4 made of a system, Sn-Ag system, Sn-Bi system solder, or Au is so-called that the surface (first main surface) of the semiconductor chip 3 faces the surface of the support substrate 1. After being arranged face down and bonding the electrode 2 a and the bump 4, the main surface of the support substrate 1, both side surfaces and the back surface (second main surface) of the semiconductor chip 3 are molded with an epoxy resin 5.
[0017]
Prior to the molding of the resin 5, the space between the main surface of the support substrate 1 and the surface of the semiconductor chip 3 may be covered with a resin having a certain viscosity.
[0018]
Next, as shown in FIG. 1B, the resin 5 on the back surface of the semiconductor chip 3 is polished by a grinder 6 to expose the back surface of the semiconductor chip 3. As shown, the back surface of the semiconductor chip 3 is polished in parallel with the front surface from an initial chip thickness T3, for example, 200 μm, to a final chip thickness T5, for example, 50 μm, to make the semiconductor chip 3 thin. By this step, the back surface of the semiconductor chip 3 and the surface of the resin 5 on both side surfaces thereof are formed on the same plane.
[0019]
Subsequently, as shown in FIG. 1D, a metal layer 7 as a conductive film is formed on the back surface of the semiconductor chip 3 and the surface of the resin 5 on both side surfaces thereof. The metal layer 7 has a laminated structure in which a 100 nm-thick TiN layer is formed first for the purpose of maintaining adhesion to the semiconductor chip 3 and then a 5 μm-thick Au is continuously formed.
[0020]
Here, TiN / Au is used for the metal layer 7, but other metals such as Ti, WN, WSi, and BaNi having adhesion to the semiconductor chip 3 may be used. Further, Cu, W and its metal compound may be used instead of Au.
[0021]
Then, as shown in FIG. 1E, the cutting line D between the semiconductor chips 3 is ground by using an elongated rectangular dicing saw 8, and as shown in FIG. The semiconductor devices 20 are individually cut out. In the resin-encapsulated semiconductor device 20 cut out by this cutting step, the back surface of the semiconductor chip 3 and the surface of the resin 5 on both sides thereof are covered with the metal layer 7, and the side and surface of the semiconductor chip 3 and the support substrate 1 The surface is covered with the resin 5, and no surface of the semiconductor chip 3 is exposed.
[0022]
Moreover, the thickness of the semiconductor device including the substrate thickness T1, the junction thickness T2, the final chip thickness T5, and the metal layer thickness T6 is as thin as 200 μm.
[0023]
In the resin-encapsulated semiconductor device of the present embodiment, the side and surface of the semiconductor chip 3 and the surface of the support substrate 1 are covered with the resin 5, and the exposed back surface of the semiconductor chip 3 and the resin 5 on both side surfaces thereof are exposed. The surface of the semiconductor chip 3 is covered with the metal layer 7, and no surface of the semiconductor chip 3 is exposed, the moisture resistance is improved, and the metal layer 7 is formed directly on the back surface of the semiconductor chip 3. Therefore, the heat dissipation effect also improves the thermal resistance of the device and improves the reliability.
[0024]
Further, the metal layer 7 is only formed on the exposed surface of the resin 5 on the back surface of the semiconductor chip 3 and on both sides thereof, and the manufacturing method is simple.
[0025]
(Modification of First Embodiment)
Next, a resin-sealed semiconductor device according to a modification of the first embodiment of the present invention and a method of manufacturing the same will be described with reference to FIG. FIG. 2 is a sectional view of the resin-sealed semiconductor device.
[0026]
This modification is different from the first embodiment in that the metal layer 7 in the first embodiment is changed to a coating film 11 as an insulating film, and the other configurations and steps are the same. Hereinafter, only different points will be described. I do. That is, it is made of rubber-based, silicone-based, epoxy-based, Teflon (R) -based, or urethane-based resin, or glass including Al2O3 (alumina), AlN (aluminum nitride), SiC, and SOG (spin-on-glass). The coating film 11 is formed by replacing the metal layer 7 of the first embodiment with a film thickness of several μm to about 10 μm.
[0027]
In the resin-encapsulated semiconductor device of the present embodiment, the side and surface of the semiconductor chip 3 and the surface of the support substrate 1 are covered with the resin 5, and the exposed back surface of the semiconductor chip 3 and the resin on both side surfaces thereof are exposed. 5, the surface of the semiconductor chip 3 is covered with the coating film 11, and no surface of the semiconductor chip 3 is exposed, so that the moisture resistance is improved. In addition, only the coating film 11 is formed on the exposed surface of the resin 5 on the back surface of the semiconductor chip 3 and on both side surfaces thereof, and the manufacturing method is simple.
[0028]
(Second embodiment)
Next, a resin-sealed semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a sectional view showing a method of manufacturing a semiconductor chip used in a resin-encapsulated semiconductor device according to a second embodiment of the present invention in the order of steps, and FIG. 4 is a sectional view showing the resin according to the second embodiment of the present invention. It is sectional drawing which shows the manufacturing method of a sealing type semiconductor device in order of a process.
[0029]
The present embodiment is different from the first embodiment in the shape of the semiconductor chip 3a and the method of forming the same, and the other configurations and steps are the same.
[0030]
First, as shown in FIG. 3A, the semiconductor chip 3a in the present embodiment is shown in FIG. 3B after a dicing tape 10 is attached to the surface of a wafer 9 having a thickness of 200 μm and polished. As described above, the cutting line E portion of the wafer 9 is ground from the back surface side of the wafer 9 to a depth of 170 μm by using the dicing saw 8a having a shape with an angled blade edge.
[0031]
Subsequently, as shown in FIG. 3 (c), the cutting line E portion of the wafer 9 is continuously ground to the surface of the dicing tape 10 by using an elongated rectangular dicing saw 8, and individually separated.
[0032]
Here, as a method of specifying a dicing location, a portion to be diced is confirmed and ground by a microscope system using a wavelength that can identify a pattern on the front surface side of the wafer 9 from the back surface side of the wafer 9. For example, for a silicon wafer, a laser microscope system having a single wavelength of 1360 nm can be used. Further, if the dicing is performed twice by a dual dicing apparatus using a dicing saw 8a having a blade edge at an angle and a dicing saw 8 having an elongated rectangular shape, displacement of the dicing position can be prevented.
[0033]
Then, as shown in FIG. 3D, the semiconductor chips 3a that have been diced and individually separated are separated from the dicing tape 10. The individually separated semiconductor chips 3a have a tapered shape in which both ends of the back surface are cut, and have a trapezoidal shape in which the back surface area is smaller than the front surface area. Here, the semiconductor chip 3a has a tapered shape in which both end portions of the back surface are cut, but may have a shape in which both end portions of the back surface are cut in a stepped shape.
[0034]
Next, as shown in FIG. 3E, the semiconductor chip 3a is completed by forming the metal bumps 4 on the surface electrodes 2b.
[0035]
Then, as shown in FIG. 4 (a), the semiconductor chip 3a having the metal bumps 4 on the electrodes 2b on the front surface is placed on the surface (the first surface) of the semiconductor chip 3a with respect to the support substrate 1 having the electrodes 2a on the surface. After the electrodes 2a and the bumps 4 are joined together, the main surface portion of the support substrate 1, both side surfaces and the back surface (second surface) of the semiconductor chip 3a are arranged. The main surface) is molded with an epoxy resin 5.
[0036]
Next, as shown in FIG. 4B, the resin 5 on the back surface of the semiconductor chip 3a is polished by a grinder 6 to expose the back surface of the semiconductor chip 3a. As shown, the back surface of the semiconductor chip 3a is polished in parallel with the front surface from an initial chip thickness T3, for example, 200 μm, to a final chip thickness T5, for example, 50 μm, to thin the semiconductor chip 3a. By this step, the back surface of the semiconductor chip 3a and the surface of the resin 5 on both side surfaces thereof are formed on the same plane.
[0037]
Subsequently, as shown in FIG. 4D, the metal layer 7 is formed on the back surface of the semiconductor chip 3a and the surface of the resin 5 on both side surfaces thereof. The metal layer 7 has a laminated structure in which a TiN layer having a thickness of 100 nm is formed first for the purpose of maintaining adhesion to the semiconductor chip 3a, and then Au having a thickness of 5 μm is continuously formed. Then, the cutting line D between the semiconductor chips 3a is ground using the elongated rectangular dicing saw 8, and the resin-sealed semiconductor devices 20 are individually cut out as shown in FIG. In the resin-encapsulated semiconductor device 20 cut out by this cutting step, the back surface of the semiconductor chip 3a and the surface of the resin 5 on both sides thereof are covered with the metal layer 7, and the side surface and the surface of the semiconductor chip 3a and the support substrate 1 The surface is covered with the resin 5, and no surface of the semiconductor chip 3a is exposed.
[0038]
Moreover, the thickness of the semiconductor device including the substrate thickness T1, the junction thickness T2, the final chip thickness T5, and the metal layer thickness T6 is as thin as 200 μm.
[0039]
In the semiconductor device of the present embodiment, the side and the front surface of the semiconductor chip 3a and the surface of the support substrate 1 are covered with the resin 5, and the exposed back surface of the semiconductor chip 3a and the resin 5 on both side surfaces thereof are formed of a metal layer. 7, the semiconductor chip 3a is not exposed on any surface, and has improved moisture resistance. In addition, since the metal layer 7 is directly formed on the back surface of the semiconductor chip 3a, the semiconductor chip 3a has a heat radiation effect. The thermal resistance of the device is also improved and reliability is improved.
[0040]
Further, since the semiconductor chip 3a has a tapered shape in which both end portions on the back surface are cut and the resin 5 is formed on both end portions, it is caused by a difference in thermal expansion coefficient between the support substrate 1 and the resin 5. The peeling phenomenon of the semiconductor chip 3a is suppressed, a so-called anchor effect occurs, and the semiconductor chip 3a is resistant to a heat cycle. In addition, no special process is required, and the manufacturing method is simple.
[0041]
(Modification of Second Embodiment)
Next, a resin-sealed semiconductor device and a method of manufacturing the same according to a modification of the second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a sectional view of the resin-sealed semiconductor device.
[0042]
This modification differs from the second embodiment in that the metal layer 7 of the second embodiment is changed to a coating film 11, and the other configurations and steps are the same. Hereinafter, only different points will be described. That is, instead of the metal layer 7 of the second embodiment, the same coating film 11 as that of the modification of the first embodiment is formed in a thickness of about several μm to about 10 μm.
[0043]
In the semiconductor device and the method of manufacturing the same according to the present embodiment, the side surface and the surface of semiconductor chip 3a and the surface of support substrate 1 are covered with resin 5, and the exposed resin back surface of semiconductor chip 3a and resin 5 on both side surfaces thereof are exposed. Is covered with the coating film 11, and no surface of the semiconductor chip 3a is exposed, so that the moisture resistance is improved.
[0044]
Further, since the semiconductor chip 3a has a tapered shape in which both end portions on the back surface are cut and the resin 5 is formed on both end portions, it is caused by a difference in thermal expansion coefficient between the support substrate 1 and the resin 5. The peeling phenomenon of the semiconductor chip 3a is suppressed, a so-called anchor effect occurs, and the semiconductor chip 3a is resistant to a heat cycle. In addition, no special process is required, and the manufacturing method is simple.
[0045]
(Third embodiment)
Next, a resin-sealed semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a sectional view showing a method of manufacturing a semiconductor chip used in a resin-encapsulated semiconductor device according to a third embodiment of the present invention in the order of steps, and FIG. 7 is a sectional view showing a resin according to the third embodiment of the present invention. It is sectional drawing which shows a sealing type semiconductor device.
[0046]
This embodiment is different from the first embodiment in the shape of the semiconductor chip 3b and the method of forming the same, and the other configurations and steps are the same.
[0047]
First, as shown in FIG. 6A, the semiconductor chip 3b in the present embodiment is shown in FIG. 6B after a dicing tape 10 is adhered to the back surface of a polished wafer 9 having a thickness of 200 μm. As described above, the cutting line D portion of the wafer 9 is cut from the surface side of the wafer 9 to the depth of 20 μm by using the dicing saw 8a having an angled blade edge to form a triangular groove 30a. I do.
[0048]
Subsequently, as shown in FIG. 6C, the dicing tape 10 is peeled off, and the dicing tape 10 is attached again to the front surface side of the wafer 9, and then the wafer 9 is cut as shown in FIG. The wafer 9 is ground to a depth of 160 μm by using a dicing saw 8a having a shape in which a line D portion is angled from the back surface side of the wafer 9 to the cutting edge, thereby forming a triangular groove 30b. Subsequently, as shown in FIG. 6E, using an elongated rectangular dicing saw 8, the wafer is ground until it reaches the surface of the dicing tape 10 through the groove 30b, and as shown in FIG. The chip 3b is completely diced and cut.
[0049]
Further, as shown in FIG. 6 (g), the semiconductor chips 3b which have been diced and individually separated are separated from the dicing tape 10. This individually separated semiconductor chip 3b has a back surface area smaller than the front surface area, the both ends of the front surface and the back surface are cut in a tapered shape, and the area of the front surface and the back surface is between the front surface and the back surface. It has a structure that is smaller than the cross-sectional area. Here, the semiconductor chip 3b has a structure in which both end portions of the front surface and the back surface are cut in a tapered shape, but may have a structure in which both end portions of the front surface and the back surface are cut in a step shape.
[0050]
Next, as shown in FIG. 6 (h), the semiconductor chip 3b is completed by forming a metallic bump 4 on the surface electrode 2b. Thereafter, individual semiconductor devices 20 are obtained through the same steps as in FIG. 1 in the first embodiment.
[0051]
Then, as shown in FIG. 7, the semiconductor device 20 cut out individually is covered with the metal layer 7 on the back surface of the semiconductor chip 3b and the resin 5 on both side surfaces thereof, and the side and surface of the semiconductor chip 3b and the surface of the support substrate 1 Are covered with the resin 5, and no surface of the semiconductor chip 3b is exposed. Moreover, both ends of the front and back surfaces of the semiconductor chip 3b are cut, and the thickness of the semiconductor device 20 including the substrate thickness T1, the junction thickness T2, the final chip thickness T5, and the metal layer thickness T6 is reduced to 200 μm. I have.
[0052]
In the semiconductor device of the present embodiment, the side surface and the surface of semiconductor chip 3b and the surface of support substrate 1 are covered with resin 5, and the exposed resin 5 on the back surface and both side surfaces of semiconductor chip 3b is a metal layer. 7, the semiconductor chip 3b is not exposed on any surface, and has improved moisture resistance. In addition, since the metal layer 7 is formed directly on the back surface of the semiconductor chip 3b, its heat radiation effect is improved. Thereby, the thermal resistance of the device is also improved, and the reliability is improved.
[0053]
Further, since the semiconductor chip 3b has a tapered shape in which both ends on the front and back sides are cut, and the resin 5 is formed on both ends, the difference in the coefficient of thermal expansion between the support substrate 1 and the resin 5 is reduced. The resulting peeling of the semiconductor chip 3b is suppressed, a so-called anchor effect occurs, and the semiconductor chip 3b is more resistant to thermal cycles. In addition, no special process is required, and the manufacturing method is simple.
[0054]
(Modification of Third Embodiment)
Next, a resin-sealed semiconductor device and a method of manufacturing the same according to a modification of the third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a sectional view of the resin-sealed semiconductor device.
[0055]
This modification differs from the third embodiment in that the metal layer 7 in the third embodiment is changed to a coating film 11, and the other configurations and steps are the same. Hereinafter, only different points will be described. That is, instead of the metal layer 7 of the third embodiment, the same coating film 11 as that of the modification of the first embodiment is formed with a thickness of several um to about 10 um.
[0056]
In the semiconductor device of the present embodiment, the side and surface of the semiconductor chip 3b and the surface of the support substrate 1 are covered with the resin 5, and the exposed resin back 5 and the resin 5 on both side surfaces thereof are covered with the coating film 11. No surface of the semiconductor chip 3b is covered, and the moisture resistance is improved.
[0057]
Further, since the semiconductor chip 3b has a tapered shape in which both ends of the front surface and the back surface are cut, and the resin 5 is formed on both ends, the difference in the thermal expansion coefficient between the support substrate 1 and the resin 5 is reduced. The resulting peeling of the semiconductor chip 3b is suppressed, and a so-called anchor effect is generated, which is more resistant to a heat cycle than in the above embodiment. In addition, no special process is required, and the manufacturing method is simple.
[0058]
【The invention's effect】
According to the present invention, a thin resin-encapsulated semiconductor device having excellent moisture resistance and high reliability can be provided.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a method for manufacturing a resin-sealed semiconductor device according to a first embodiment of the present invention in the order of steps.
FIG. 2 is a sectional view showing a resin-sealed semiconductor device according to a modification of the first embodiment of the present invention.
FIG. 3 is a sectional view illustrating a method of manufacturing a semiconductor chip used in a second embodiment of the present invention in the order of steps.
FIG. 4 is a sectional view illustrating a method for manufacturing a resin-sealed semiconductor device according to a second embodiment of the present invention in the order of steps.
FIG. 5 is a sectional view showing a resin-sealed semiconductor device according to a modification of the second embodiment of the present invention.
FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor chip used in a third embodiment of the present invention in the order of steps.
FIG. 7 is a sectional view showing a resin-sealed semiconductor device according to a third embodiment of the present invention.
FIG. 8 is a sectional view showing a resin-sealed semiconductor device according to a modification of the third embodiment of the present invention.
FIG. 9 is a sectional view showing a method for manufacturing a conventional resin-encapsulated semiconductor device in the order of steps.
[Explanation of symbols]
1, 101 Support substrate 2a, 2b, 102a, 102b Electrode 3, 3a, 3b, 103 Semiconductor chip 4, 104 Bump 5, 105 Resin 6, 106 Grinder 7 Metal layer 8, 8a, 108 Dicing saw 9 Wafer 10 Dicing tape 11 Coating film 20, 120 Resin-sealed semiconductor device 30a, 30b Groove D, E Cutting line T1 Substrate thickness T2 Joint thickness T3 Initial chip thickness T4 Resin thickness T5 Final chip thickness T6 Metal layer thickness

Claims (7)

主面に電極を有する支持基板と、
第１主面に電極を有し、且つこの第１主面が前記支持基板の主面と対向配置された半導体チップと、
前記支持基板の電極と前記半導体チップの電極を接合するバンプと、
前記第１主面と相対向する半導体チップの第２主面を露呈させ、少なくとも、前記支持基板周辺部の主面部分および前記半導体チップの側面を覆う樹脂と、
前記半導体チップの第２主面およびその両側面部の前記樹脂の表面上に形成された導電性フィルムと、
を具備することを特徴とする樹脂封止型半導体装置。A support substrate having an electrode on the main surface,
A semiconductor chip having an electrode on a first main surface, wherein the first main surface is arranged to face the main surface of the support substrate;
A bump for joining the electrode of the support substrate and the electrode of the semiconductor chip,
A resin for exposing a second main surface of the semiconductor chip opposite to the first main surface and covering at least a main surface portion of a peripheral portion of the support substrate and a side surface of the semiconductor chip;
A conductive film formed on the surface of the resin on the second main surface of the semiconductor chip and on both side surfaces thereof;
A resin-sealed semiconductor device comprising: 主面に電極を有する支持基板と、
第１主面に電極を有し、且つこの第１主面が前記支持基板の主面と対向配置された半導体チップと、
前記支持基板の電極と前記半導体チップの電極を接合するバンプと、
前記第１主面と相対向する半導体チップの第２主面を露呈させ、少なくとも、前記支持基板周辺部の主面部分および前記半導体チップの側面を覆う樹脂と、
前記半導体チップの第２主面およびその両側面部の前記樹脂の表面上に形成された絶縁性フィルムと、
を具備することを特徴とする樹脂封止型半導体装置。A support substrate having an electrode on the main surface,
A semiconductor chip having an electrode on a first main surface, wherein the first main surface is arranged to face the main surface of the support substrate;
A bump for joining the electrode of the support substrate and the electrode of the semiconductor chip,
A resin for exposing a second main surface of the semiconductor chip opposed to the first main surface and covering at least a main surface portion of a peripheral portion of the support substrate and a side surface of the semiconductor chip;
An insulating film formed on the surface of the resin on the second main surface of the semiconductor chip and on both side surfaces thereof;
A resin-sealed semiconductor device comprising: 前記半導体チップの第２主面の面積が、第１主面の面積に比べて小さいことを特徴とする請求項１または２記載の樹脂封止型半導体装置。3. The resin-encapsulated semiconductor device according to claim 1, wherein the area of the second main surface of the semiconductor chip is smaller than the area of the first main surface. 前記半導体チップの第１および第２主面の面積が、その両主面間の横断面積に比べて小さいことを特徴とする請求項１または２記載の樹脂封止型半導体装置。3. The resin-encapsulated semiconductor device according to claim 1, wherein an area of the first and second main surfaces of the semiconductor chip is smaller than a cross-sectional area between the two main surfaces. 主面上に電極を有する支持基板と第１主面に電極を有する半導体チップとを、その両主面が相対向するように配置し、且つ両電極をバンプにより接合する工程と、
前記支持基板周辺部の主面部分、少なくとも前記半導体チップの両側面および前記第１主面と相対向する第２主面部分を樹脂モールドする工程と、
前記半導体チップの第２主面上の前記樹脂および前記第２主面側の半導体チップの一部を研磨する工程と、
前記半導体チップの第２主面およびその半導体チップの両側面部分の樹脂表面に導電性または絶縁性フィルムを形成する工程と、
を具備したことを特徴とする樹脂封止型半導体装置の製造方法。A step of arranging a supporting substrate having an electrode on the main surface and a semiconductor chip having an electrode on the first main surface such that both main surfaces thereof face each other, and joining both electrodes by bumps;
Resin-molding a main surface portion of the peripheral portion of the support substrate, at least a second main surface portion opposing the first main surface and both side surfaces of the semiconductor chip;
Polishing a portion of the resin on the second main surface of the semiconductor chip and a portion of the semiconductor chip on the second main surface side;
Forming a conductive or insulating film on the resin surface of the second main surface of the semiconductor chip and on both side surfaces of the semiconductor chip;
A method for manufacturing a resin-encapsulated semiconductor device, comprising: 主面上に電極を有する支持基板と、その第２主面の面積が第１主面の面積に比べて小さい半導体チップとを、その第１面が前記支持基板の主面と相対向するように配置し、且つ両電極をバンプにより接合する工程と、
前記支持基板周辺部の主面部分、少なくとも前記半導体チップの両側面および第１主面と相対向する第２主面部分とを樹脂モールドする工程と、
前記半導体チップの第２主面上の前記樹脂および前記半導体チップの一部を研磨する工程と、
前記半導体チップの第１主面と平行な第２主面およびその半導体チップの両側面部分の樹脂表面に導電性または絶縁性フィルムを形成する工程と、
を具備したことを特徴とする樹脂封止型半導体装置の製造方法。A support substrate having an electrode on a main surface and a semiconductor chip having a second main surface area smaller than an area of the first main surface are arranged such that the first surface faces the main surface of the support substrate. And bonding both electrodes by bumps,
A step of resin-molding a main surface portion of the peripheral portion of the support substrate, at least a second main surface portion opposed to both side surfaces and the first main surface of the semiconductor chip;
Polishing the resin on the second main surface of the semiconductor chip and part of the semiconductor chip;
Forming a conductive or insulating film on a resin surface on a second main surface parallel to the first main surface of the semiconductor chip and on both side surfaces of the semiconductor chip;
A method for manufacturing a resin-encapsulated semiconductor device, comprising: 主面上に電極を有する支持基板と、その第１および第２主面の面積がその両主面間の横断面積に比べて小さい半導体チップとを、その第１主面が前記支持基板の主面と相対向するように配置し、且つ両電極をバンプにより接合する工程と、
前記支持基板周辺部の主面部分と、少なくとも前記半導体チップの両側面および第１主面と相対向する第２主面部分とを樹脂モールドする工程と、
前記半導体チップの第２主面上の前記樹脂および前記第２主面側の半導体チップの一部を研磨する工程と、
前記半導体チップの第２主面およびその半導体チップの両側面部分の樹脂表面に導電性または絶縁性フィルムを形成する工程と、
を具備したことを特徴とする樹脂封止型半導体装置の製造方法。A support substrate having an electrode on a main surface, and a semiconductor chip having first and second main surfaces whose area is smaller than a cross-sectional area between the two main surfaces, a first main surface of which is the main surface of the support substrate. A step of arranging them so as to face each other and bonding both electrodes by bumps;
A step of resin-molding a main surface portion of the peripheral portion of the support substrate and at least a second main surface portion opposed to both side surfaces and the first main surface of the semiconductor chip;
Polishing a portion of the resin on the second main surface of the semiconductor chip and a portion of the semiconductor chip on the second main surface side;
Forming a conductive or insulating film on the resin surface of the second main surface of the semiconductor chip and on both side surfaces of the semiconductor chip;
A method for manufacturing a resin-encapsulated semiconductor device, comprising:
JP2002324712A 2002-11-08 2002-11-08 Resin sealed semiconductor device and manufacturing method therefor Pending JP2004158739A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196657A (en) * 2005-01-13 2006-07-27 New Japan Radio Co Ltd Manufacturing method of semiconductor device
JP2014011268A (en) * 2012-06-28 2014-01-20 Disco Abrasive Syst Ltd Method for sealing semiconductor chip with resin
JP2014512691A (en) * 2011-04-22 2014-05-22 テセラ インコーポレイテッド Multi-chip module with stacked downward connecting dies
US8802196B2 (en) 2009-07-27 2014-08-12 Cts Corporation Encapsulated ceramic element and method of making the same
CN104756225A (en) * 2012-09-20 2015-07-01 斯莱戈科技公司 Extremely thin package
JP2016031986A (en) * 2014-07-28 2016-03-07 株式会社ディスコ Wafer processing method
US10784165B2 (en) 2018-02-27 2020-09-22 Kabushiki Kaisha Toshiba Semiconductor device and dicing method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196657A (en) * 2005-01-13 2006-07-27 New Japan Radio Co Ltd Manufacturing method of semiconductor device
US8802196B2 (en) 2009-07-27 2014-08-12 Cts Corporation Encapsulated ceramic element and method of making the same
JP2014512691A (en) * 2011-04-22 2014-05-22 テセラ インコーポレイテッド Multi-chip module with stacked downward connecting dies
JP2014011268A (en) * 2012-06-28 2014-01-20 Disco Abrasive Syst Ltd Method for sealing semiconductor chip with resin
CN104756225A (en) * 2012-09-20 2015-07-01 斯莱戈科技公司 Extremely thin package
JP2015532017A (en) * 2012-09-20 2015-11-05 シレゴ・テクノロジー・インコーポレーテッドＳｉｌｅｇｏ Ｔｅｃｈｎｏｌｏｇｙ Ｉｎｃｏｒｐｏｒａｔｅｄ Ultra-thin package
US9735018B2 (en) 2012-09-20 2017-08-15 Silego Technology, Inc. Extremely thin package
CN111508908A (en) * 2012-09-20 2020-08-07 斯莱戈科技公司 Very thin package
JP2016031986A (en) * 2014-07-28 2016-03-07 株式会社ディスコ Wafer processing method
US10784165B2 (en) 2018-02-27 2020-09-22 Kabushiki Kaisha Toshiba Semiconductor device and dicing method

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