JP2010087160A - Method of manufacturing nonvolatile semiconductor storage, and nonvolatile semiconductor storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce parasitic capacitance between gate electrodes by suppressing lamination of an insulation film between gate electrodes in structure for adopting an air gap structure between the gate electrodes. <P>SOLUTION: An SOG film is formed as a sacrifice layer so that an upper surface is positioned above an upper surface of a polycrystalline silicon layer 4 and below an upper surface of gate electrodes MG, SGS, SGD between gate electrodes MG-MG, MG-SGS, and MG-SGD. Then, a silicon oxide film 9 having etching selectivity with the SOG film is formed so that the silicon oxide film 9 is along an upper side face of the gate electrodes MG, SGS, SGD and an upper surface of the SOG film. While the silicon oxide film 9 is allowed to reside as a spacer along an upper side face of the gate electrodes MG, SGS, SGD, an upper opening 11a leading to an upper surface of the SOG film is formed by anisotropic etching treatment, and the SOG film is removed through the upper opening 11a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device having a gate electrode formed by stacking a charge storage layer, a second gate insulating film, and a control electrode on a semiconductor substrate via a first gate insulating film, and a nonvolatile memory The present invention relates to a conductive semiconductor memory device.

  In the development of nonvolatile semiconductor memory devices, miniaturization of elements has been progressing year by year in order to achieve a large capacity and low cost. For example, in the NAND flash memory device, the wiring pitches such as word lines are being miniaturized. However, as the miniaturization progresses, the insulating film between the gate electrodes becomes thinner, so that the capacitance between the wirings increases, and it is becoming difficult to ignore the device characteristics.

  In order to avoid this, it is necessary to replace a silicon oxide film (relative permittivity ε = 3.9) generally used as an insulating film material between the gate electrodes with a material having a low relative permittivity. . Therefore, an air gap configuration is considered in which air (relative permittivity ε = 1), which is a substance having the lowest relative permittivity, is used as an insulating film between the gate electrodes (see, for example, Patent Documents 1 and 2).

  However, according to the technical idea described in Patent Document 1, if the width between the gate electrodes becomes narrower as the miniaturization progresses, the bottom portion of the insulating film laminated from the lower side of the cavity portion is thickly laminated. The parasitic capacitance increases, which is not preferable.

Further, even if the technical idea described in Patent Document 2 is applied, if the width between the gate electrodes becomes narrower as the miniaturization progresses, for example, if a silicon nitride film is formed between adjacent gate electrodes, The parasitic capacitance increases, which is not preferable.
Special table 2007-501531 US Patent Application Publication No. 2007/0096202

  The present invention relates to a method of manufacturing a non-volatile semiconductor memory device and a non-volatile semiconductor memory device capable of reducing the parasitic capacitance between the gate electrodes by suppressing the lamination of the insulating film between the gate electrodes in the structure employing the air gap structure between the gate electrodes. It is an object to provide a conductive semiconductor memory device.

  One embodiment of the present invention includes a step of forming a plurality of gate electrodes in which a charge storage layer, a second insulating film, and a control electrode are sequentially stacked over a semiconductor substrate with a first insulating film interposed therebetween, and the plurality of gate electrodes A sacrificial layer of SOG (Spin-On-Glass) film, silicon nitride film, or polysilicon film is formed so that the upper surface is positioned above the upper surface of the charge storage layer and below the upper surface of the control electrode. Forming a third insulating film having etching selectivity with the sacrificial layer along the side surface of the control electrode and along the upper surface of the sacrificial layer; and A step of forming an opening that passes through the upper surface of the sacrificial layer while remaining as a spacer along the side surface of the control electrode by anisotropic etching; and a step of removing the sacrificial layer through the opening. ing.

  According to one embodiment of the present invention, a semiconductor substrate including an active region, a charge storage layer formed over the active region of the semiconductor substrate with a gate insulating film interposed therebetween, and a gate formed over the charge storage layer A plurality of gate electrodes each including an insulating film and a control electrode formed on the inter-gate insulating film; and an inter-gate electrode insulating film formed of a silicon oxide film between the plurality of gate electrodes. An inner lower end located below the upper surface of the charge storage layer, and an inner projecting portion formed above the lower surface of the inter-gate insulating film and projecting inward, the inner lower end and And an inter-gate electrode insulating film provided with a cavity in a state where the upper opening is constricted inside the inner protrusion.

  According to the present invention, in a structure that employs an air gap structure between gate electrodes, it is possible to suppress stacking of an insulating film between the gate electrodes and reduce parasitic capacitance between the gate electrodes.

  Hereinafter, an embodiment in which the present invention is applied to a NAND flash memory device will be described with reference to the drawings. In the following description in the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 1 shows an equivalent circuit of a part of a memory cell array in a NAND flash memory device. As shown in FIG. 1, NAND cell units UC are arranged in a matrix in the memory cell array Ar of the NAND flash memory device 1. In this NAND cell unit UC, two (a plurality of) select gate transistors Trs1, Trs2 and adjacent ones located between the two select gate transistors Trs1, Trs2 share a source / drain region in series. A plurality of (for example, 32) memory cell transistors Trm are connected.

  In FIG. 1, the memory cell transistors Trm arranged in the X direction (word line direction, channel width direction) are commonly connected by a word line (control gate line) WL. Further, the select gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a common select gate line SGL1. Further, the selection gate transistors Trs2 are commonly connected by a common selection gate line SGL2.

  FIG. 2 shows a partial layout pattern of the memory cell region. As shown in FIG. 2, the plurality of NAND cell units UC are formed in an active area Sa separated from each other by an element isolation region Sb having an STI (Shallow Trench Isolation) structure extending in the Y direction. A selection gate electrode SGD is formed in a planar intersection region between the selection gate line SGL1 and the active region Sa. A selection gate electrode SGS is formed in a planar intersection region between the selection gate line SGL2 and the active region Sa. A memory cell gate electrode MG is formed in a planar intersection region between the word line WL and the active region Sa. A common source line contact CSL is formed between the select gate lines SGL2 and SGL2 along the X direction. Bit line contacts CBa and CBb are arranged one by one in a staggered pattern on a plurality of active regions Sa positioned between select gate lines SGL1 and SGL1 and spaced in the X direction.

  FIG. 3 schematically shows a longitudinal sectional view taken along line AA of FIG. As shown in FIG. 3, a well (not shown) is formed on the surface layer of the first conductivity type semiconductor substrate 2 (for example, a p-type silicon substrate), and a gate insulating film 3 is formed on the upper surface of the semiconductor substrate 2. Is formed. On the upper surface of the gate insulating film 3, two (plural) gate electrodes SGD and SGS are formed apart from each other. In addition, between the two select gate electrodes SGD-SGS, a gate insulating film 3 is formed on the upper surface of the semiconductor substrate 2, and a plurality (for example, 32 pieces) of the gate insulating film 3 are separated from each other on the upper surface of the gate insulating film 3. , 64) memory cell gate electrodes MG are formed. The semiconductor substrate 2 may be an n-type silicon substrate.

  The memory cell gate electrode MG is configured by stacking a floating gate electrode FG as a charge storage layer, an intergate insulating film 5, and a control electrode CG. The select gate electrodes SGD and SGS are substantially the same structure and made of the same material as that of the memory cell gate electrode MG, but an opening is formed at the center of the inter-gate insulating film 5. The floating gate electrode FG and the control electrode CG are configured as a gate electrode integrally formed.

  The floating gate electrode FG is composed of, for example, the polycrystalline silicon layer 4 and functions as a charge storage layer. The intergate insulating film 5 is formed of, for example, an ONO film (silicon oxide film-silicon nitride film-silicon oxide film). The NONON film (silicon nitride film-silicon oxide film-silicon nitride film-silicon oxide film-silicon nitride film) may be formed by performing radical nitriding before and after the ONO film is formed, or alumina may be used. You may form with the film | membrane containing. The control electrode CG includes, for example, a polycrystalline silicon layer 6 and a silicide layer in which the upper portion of the polycrystalline silicon layer 6 is silicided with any one kind of metal such as cobalt (Co), tungsten (W), nickel (Ni), and the like. 7 is laminated.

  The memory cell gate electrode MG and the selection gate electrodes SGD, SGS are configured by dividing the layers 4 to 7 into a plurality in the Y direction. Source / drain regions 2 a are formed on the surface layer of the semiconductor substrate 2 on both sides in the Y direction of these gate electrodes MG, SGD, and SGS. These source / drain regions 2a indicate regions where impurities of the second conductivity type (N type) opposite to the first conductivity type are introduced and diffused.

  Between the gate electrodes MG-MG, between MG-SGD, and between MG-SGS, a silicon oxide film 8 is formed along the lower surface of the gate electrodes MG, SGD, SGS. Further, between the gate electrodes MG-MG, between MG-SGD, and between MG-SGS, a silicon oxide film 9 is formed as a spacer along the upper side surface of the gate electrodes MG, SGD, SGS. Therefore, these silicon oxide films 8 and 9 are buried as the insulating film 10 between the gate electrodes MG-MG, between the SGD-MG, and between the SGS-MG, and inside the insulating film 10 as an air gap A cavity 11 is provided.

  Between the gate electrodes MG-MG, between MG-SGD, and between MG-SGS, the insulating film 10 includes an inner lower end portion 10b positioned below the upper surface of the polycrystalline silicon layer 4 and a lower surface of the inter-gate insulating film 5. And an inner protrusion 10c formed to protrude inwardly between the gate electrodes MG-MG, between SGD-MG, and between SGS-MG. The insulating film 10 is provided with a cavity 11 inside the inner lower end 10b and the inner protrusion 10c in a state where the upper opening 11a is narrowed.

  Between the gate electrodes SGS-SGS and SGD-SGD facing each other, the silicon oxide film 8 is formed along the side surfaces of the gate electrodes SGS, SGD, and the silicon oxide film 12 and the barrier film are formed inside thereof. The silicon nitride film 13 and the BPSG film 14 are sequentially embedded.

  A silicon oxide film 15 is formed along the upper surfaces of the gate electrodes MG, SGS, and SGD and the upper surface of the silicon oxide film 9 by plasma CVD. Between the gate electrodes SGS-SGS, a common source line contact CSL is formed through the silicon oxide film 15, the BPSG film 14, the silicon nitride film 13, and the silicon oxide film 10 to reach the upper surface of the semiconductor substrate 2. Yes. Between the gate electrodes SGD and SGD, the bit line contact CBb is formed through the silicon oxide film 15, the BPSG film 14, the silicon nitride film 13, and the silicon oxide film 10 in order to reach the upper surface of the semiconductor substrate 2.

  The manufacturing method of the said structure is demonstrated. In addition, the characteristic part which concerns on this embodiment is mainly demonstrated, and description of the process before and behind is abbreviate | omitted. If the problem of the present invention can be solved, it may be added if it is a general process, may be omitted as necessary, and the process may be replaced.

  As shown in FIG. 4, after ion implantation for forming wells and channels in the semiconductor substrate 2, a gate insulating film 3 is formed on the semiconductor substrate 2. Next, the polycrystalline silicon layer 4 for the floating gate electrode FG, the intergate insulating film 5, the polycrystalline silicon layer 6 for the control electrode CG, and the silicon nitride film 17 are sequentially deposited, and a resist (not shown) is formed thereon. The silicon nitride film 17, the polycrystalline silicon layer 6, the inter-gate insulating film 5, and the polycrystalline silicon layer 4 are sequentially separated by RIE (Reactive Ion Etching). At this time, the gate insulating film 3 is also divided as necessary. FIG. 4 shows a state after processing the gate electrode.

  Next, as shown in FIG. 5, along the side surface of the polycrystalline silicon layer 4, the side surface of the inter-gate insulating film 5, the side surface of the polycrystalline silicon layer 6, the side surface and the upper surface of the silicon nitride film 17 by LP-CVD. A silicon oxide film 8 is formed. After the structure shown in FIG. 4 is formed, a second conductivity type (N-type) impurity for forming the source / drain region 2a is ion-implanted into the surface layer between the divided layers 3 to 6 and 17.

  Next, as shown in FIG. 6, an SOG (Spin-On-Glass) film 18 serving as a sacrificial layer is formed by a coating technique. Next, as shown in FIG. 7, the SOG film 18 is planarized by CMP (Chemical Mechanical Polishing).

  Next, as shown in FIG. 8, a resist 19 is applied and patterned so as to cover the respective layers 4 to 6 for the memory cell gate electrode MG, thereby forming a mask pattern. The upper surface of the SOG film 18 between -SGS is opened.

  Next, as shown in FIG. 9, the exposed SOG film 18 is selectively removed by using dilute hydrofluoric acid treatment or the like. Next, as shown in FIG. 10, after the resist 19 is peeled off, a silicon oxide film is deposited by LP-CVD between the select gate electrodes SGD and SGD and between SGS and SGS, and processed as a spacer 12 to select the opposite High-concentration impurities for contact are ion-implanted between the gate electrodes SGD-SGD and between SGS-SGS.

  Next, as shown in FIG. 11, a silicon nitride film 13 is formed in a liner shape along the upper and upper surfaces of the silicon nitride film 17, the upper surfaces of the SOG film 18 and the silicon oxide film 8, and the upper and side surfaces of the spacer 12. Then, a BPSG film 14 is deposited on the silicon nitride film 13 and planarized by a CMP method.

  Next, as shown in FIG. 12, the silicon nitride films 13 and 17 are removed by RIE. Next, as shown in FIG. 13, a metal such as a nickel (Ni) film is formed by sputtering, and a silicide layer 7 is formed on the polycrystalline silicon layer 6 by heat treatment, and unreacted metal is formed. Remove. Next, after the resist 20 is applied, the resist 20 is patterned, and the upper portions of the silicon oxide film 8 and the sacrificial layer 18 filled between the gate electrodes MG and MG, between the SGD and MG, and between the SGS and MG are simultaneously formed. Etch off.

  Next, as shown in FIG. 14, the patterned resist 20 is peeled off, and the silicon oxide film 9 is formed in a liner shape by a predetermined film thickness to thereby form the gate electrodes MG-MG, SGD-MG, SGS. A recess 9a is provided in the upper part between MG.

  Next, as shown in FIG. 15, the silicon oxide film 9 is processed as a spacer along the upper side surface of each gate electrode MG, SGD, SGS by anisotropic etching (for example, RIE), so that the presence of the recess 9a is present. Accordingly, the etching process proceeds only in the region where the recess 9a is formed, and an upper opening 11a (opening) that leads to the upper surface of the SOG film 18 is provided. Next, the SOG film 18 is removed by wet etching, for example. In this case, since the SOG film 18 can be removed under conditions with higher etching selectivity than the silicon oxide film 8 or the silicon oxide film 9 by HTO, the SOG film 18 can be easily peeled off.

  Next, as shown in FIG. 16, the silicon oxide film 15 is deposited by the plasma CVD method with relatively poor coverage so that the upper opening 11a is not blocked, and between the gate electrodes MG-MG and SGD-MG. The silicon oxide film 15 can be formed in a desired state with the cavity 11 provided between the SGS-MG. In this case, since the upper opening portion 11a is constricted by the spacer of the silicon oxide film 9, the amount of silicon oxide film deposited on the lower end side of the cavity portion 11 is reduced, and even between the gate electrodes MG-MG and SGD as compared with the conventional case. Even if the distance between −MG and the distance between SGS and MG becomes narrow, the position of the inner lower end portion 10 b of the insulating film 10 between the gate electrodes can be formed to be located below the upper surface of the polycrystalline silicon layer 4. Therefore, even if the inter-element spacing is reduced, the air gap structure between the adjacent floating gate electrodes FG-FG can be maintained.

  According to the present embodiment, the gate insulating film 3, the polycrystalline silicon layer 4 (floating gate electrode FG), the inter-gate insulating film 5, and the polycrystalline silicon layer 6 are sequentially stacked on the upper surface of the semiconductor substrate 2 and divided. After dividing the laminated film structure of the gate electrodes MG, SGS, and SGD, the gate electrodes MG-MG, MG-SGS, and MG-SGD are above the upper surface of the polycrystalline silicon layer 4 and the control electrode CG. The SOG film 18 is formed so that the upper surface is located below the upper surface of the silicon oxide film, and the silicon oxide having etching selectivity with the SOG film 18 along the side surface of the polycrystalline silicon layer 6 and the upper surface of the SOG film 18 is formed. The film 9 is formed, and the upper opening 11a leading to the upper surface of the SOG film 18 is anisotropically etched while leaving the silicon oxide film 9 as a spacer along the side surface of the polycrystalline silicon layer 6 Therefore, since the SOG film 18 is formed and removed through the upper opening 11a, even if the distance between the gate electrodes MG and MG, between the SGD and MG, and between the SGS and MG becomes narrower than before, the gate electrode The inner lower end portion 10b of the insulating film 10 can be formed so as to be located below the upper surface of the polycrystalline silicon layer 4. Thereby, even if the inter-element spacing is reduced, the air gap structure between the adjacent floating gate electrodes FG-FG can be maintained. Thereby, the parasitic capacitance between gate electrodes can be reduced. It is preferable to remove the SOG film 18 by wet etching.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Although applied to the NAND type flash memory device 1, it may be applied to a NOR type flash memory device, or may be applied to other nonvolatile semiconductor memory devices.
Although the embodiment in which the polycrystalline silicon layer 6 is applied to the floating gate electrode FG has been described, a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure in which a silicon nitride film is applied as a charge storage layer in place of the floating gate electrode FG, A SONOS structure (Silicon-Oxide-Nitride-Oxide-Silicon) may be applied.

  Although the SOG film 18 is applied as the sacrificial layer, the cavity portion 11 can be used instead if it is another material film (for example, polysilicon, silicon nitride film) that can be removed by wet etching after the formation of the silicide layer 7. Can be formed satisfactorily. The control electrode CG may be applied to a poly gate or a metal gate.

Electrical configuration diagram showing an embodiment of the present invention Plan view schematically Longitudinal sectional view schematically showing the main part Sectional view schematically showing one manufacturing stage (Part 1) Cutaway view schematically showing one manufacturing stage (Part 2) Cutaway view schematically showing one manufacturing stage (Part 3) Cutaway view schematically showing one manufacturing stage (Part 4) Cutaway view schematically showing one manufacturing stage (Part 5) Sectional view schematically showing one manufacturing stage (No. 6) Sectional view schematically showing one manufacturing stage (Part 7) Sectional view schematically showing one manufacturing stage (No. 8) Sectional view schematically showing one manufacturing stage (No. 9) Sectional view schematically showing one manufacturing stage (No. 10) Sectional view schematically showing one manufacturing stage (Part 11) Sectional view schematically showing one manufacturing stage (No. 12) Sectional view schematically showing one manufacturing stage (No. 13)

Explanation of symbols

  In the drawings, 1 is a flash memory device (nonvolatile semiconductor memory device), 2 is a semiconductor substrate, 3 is a gate insulating film (first insulating film), 5 is an inter-gate insulating film (second insulating film), and 9 is Spacer (third insulating film), 10 is an insulating film between gate electrodes, 10b is an inner lower end part, 10c is an inner projecting part, 11 is a cavity part, FG is a floating gate electrode (charge storage layer), CG is a control electrode, MG is a memory cell gate electrode (gate electrode), SGS and SGD are selection gate electrodes (gate electrodes), and Sa is an active region.

Claims (3)

Forming a plurality of gate electrodes in which a charge storage layer, a second insulating film, and a control electrode are sequentially stacked on a semiconductor substrate via a first insulating film;
An SOG (Spin-On-Glass) film, a silicon nitride film, or a polysilicon film so that the upper surface is positioned above the upper surface of the charge storage layer and below the upper surface of the control electrode between the plurality of gate electrodes Forming a sacrificial layer by:
Forming a third insulating film having etching selectivity with the sacrificial layer along the side surface of the control electrode and along the upper surface of the sacrificial layer;
Forming an opening leading to the upper surface of the sacrificial layer by anisotropic etching while leaving the third insulating film as a spacer along the side surface of the control electrode;
And a step of removing the sacrificial layer through the opening.   2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the sacrificial layer is removed by wet etching. A semiconductor substrate on which an active region is formed;
A charge storage layer formed on the active region of the semiconductor substrate via a gate insulating film; an intergate insulating film formed on the charge storage layer; and a control electrode formed on the intergate insulating film; A plurality of gate electrodes each comprising:
An inter-gate electrode insulating film formed of a silicon oxide film between the plurality of gate electrodes, wherein the inner and lower end portions are located below the upper surface of the charge storage layer and above the lower surface of the inter-gate insulating film. A gate electrode insulating film provided with a hollow portion in a state where the upper opening is constricted inside the inner lower end portion and the inner projection portion. A non-volatile semiconductor memory device comprising:

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