JP2010040753A - Method of manufacturing nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form an air gap structure without increasing a number of processes in manufacturing processes performing silicide processing on the way. <P>SOLUTION: Laminated layers of a gate insulation film 4, a polycrystalline silicon film 5 having a layered structure of gate electrodes MG, SG1 and SG2, an ONO film 6, a polycrystalline silicon film 7 and a silicon nitride film are formed on a silicon substrate 1, and the laminated layers are separated into a width of each gate electrode. Polysilazane is embedded between the electrodes, and then, a spacer 9, a silicon nitride film 10 and a silicon oxide film 11 are formed between the selection gate electrodes SG1 and SG1 and between the selection gate electrodes SG2 and SG2. Cobalt is formed on an upper surface of the polycrystalline silicon film 7 on an upper part of the gate electrodes to be silicided. Next, the polysilazane is removed and a TEOS oxide film 12 is formed in conditions of poor embedding property, to thereby form gaps AG1, AG2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device having a silicidation process.

  In the development of nonvolatile semiconductor memory devices, miniaturization of elements has been progressing year by year in order to achieve a large capacity and low cost. For example, in a NAND flash memory device, the wiring pitches such as bit lines and word lines are being miniaturized. However, as the miniaturization progresses, the interlayer insulating film between the wirings becomes thinner, so that the capacitance between the wirings increases, and it is becoming difficult to ignore the characteristics of the elements.

  In other words, when the capacitance between wires increases, the capacitance between wires is connected to the tunnel oxide film in parallel, so the capacitance of the tunnel oxide film is the sum of all the capacitances including the capacitance between wires, and the capacitance of the tunnel oxide film is apparent. Get bigger. As a result, the voltage applied to the tunnel oxide film becomes small, so it takes time to write data and inject electrons into the floating gate through the tunnel oxide film. It is a cause.

  In order to avoid this, it is necessary to replace a silicon oxide film (relative permittivity ε = 3.9) generally used as an interlayer insulating film material between word lines with a material having a low relative permittivity. There is. Therefore, as shown in Patent Document 1, an air gap configuration is considered in which air (relative permittivity ε = 1), which is a substance having the lowest relative permittivity, is used as an insulating film between word lines.

  However, it is necessary to cope with an increase in wiring resistance due to the miniaturization of elements. For example, a silicide layer is provided above the control gate of the memory cell transistor in order to reduce the wiring resistance of the word line. However, in the structure in which the tungsten silicide (WSi) layer as shown in Patent Document 1 is formed, the operation of the element is affected, so that it is necessary to form a silicide layer having a lower resistance. ing.

In this case, when a low resistance silicide layer such as nickel (Ni) or cobalt (Co) is provided, it cannot be formed as a silicide layer from the beginning because of the heat treatment temperature, and an amorphous silicon film is used as a control gate electrode. Alternatively, it is necessary to perform a silicidation process by forming a polycrystalline silicon film and exposing the upper surface of the control gate electrode after forming the gate electrode structure. For this reason, there has been a situation where the method of Patent Document 1 cannot be employed as it is.
JP 2007-157927 A

  An object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device capable of forming an air gap structure without increasing the number of processes in a manufacturing process in which silicidation is performed in the middle.

  According to a first aspect of a method for manufacturing a nonvolatile semiconductor memory device of the present invention, a first gate insulating film is formed on a semiconductor substrate, and a first electrode film and a second gate are formed on the first gate insulating film. A step of laminating an insulating film, a second electrode film, and a first insulating film to separate and form a plurality of gate electrodes, and a source / drain on the surface of the semiconductor substrate between the plurality of separated gate electrodes A step of forming a region, a step of embedding a coating type insulating film between the gate electrodes after the formation of the source / drain regions, and a step of peeling and exposing the first insulating film on the upper surface of the gate electrode. A step of siliciding a predetermined amount of the electrode film of 2; a step of removing the coating-type insulating film except for a contact formation region; and a film formation under a condition that the embedding property between the gate electrodes is low. A gap is formed between the electrodes While having characterized in that comprising a step of forming a second insulating film to cover the second electrode layer.

  According to a second aspect of the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a first gate insulating film is formed on a semiconductor substrate, a first electrode film and a second electrode are formed on the first gate insulating film. Laminating the gate insulating film, the second electrode film, and the first insulating film to separate and form a plurality of gate electrodes, and a source on the surface of the semiconductor substrate between the plurality of separately formed gate electrodes A step of forming a drain / drain region, a step of embedding a coating-type insulating film between the gate electrodes after the formation of the source / drain regions, and peeling and exposing the first insulating film on the upper surface of the gate electrode. A step of siliciding the second electrode film by a predetermined amount, a step of forming a second insulating film so as to cover an upper surface of the gate electrode and an upper surface between the gate electrodes, and the second electrode except for a contact formation region. For removing the insulating film Removing the coating-type insulating film except for the contact formation region, and forming the gap between the gate electrodes while forming a gap between the gate electrodes by forming a film under a condition of low embedding between the gate electrodes. And a step of forming a third insulating film so as to cover the second electrode film.

  According to the present invention, it is possible to form an air gap structure without increasing the number of processes in a manufacturing process in which silicidation is performed in the middle.

(First embodiment)
A first embodiment when the present invention is applied to a NAND flash memory device will be described below with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

First, the configuration of the NAND flash memory device of this embodiment will be described. FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.
The memory cell array of the NAND flash memory device includes two selection gate transistors Trs1 and Trs2, and a plurality (for example, 8: 2 raised to the nth power (n: 8), for example, between the selection gate transistors Trs1 and Trs2. Are positive cell numbers)) memory cell transistors Trm, and NAND cell units (memory units) Su are formed in a matrix. In the NAND cell unit Su, a plurality of memory cell transistors Trm share a source / drain region with each other.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2 is a plan view showing a layout pattern of a part of the memory cell region. A plurality of STIs (shallow trench isolations) 2 as element isolation insulating films are formed at predetermined intervals along the Y direction in FIG. 2 on the silicon substrate 1 as a semiconductor substrate, whereby the active region 3 is formed in the X direction in FIG. Are formed separately. Word lines WL of the memory cell transistors are formed at predetermined intervals along the X direction in FIG. 2 orthogonal to the active region 3.

  A selection gate line SGL1 of a pair of selection gate transistors is formed along the X direction in FIG. The distance between the pair of select gate lines SGL1 is wider than the distance between the select gate lines SGL2, and a bit line contact CB is formed in the active region 3. Adjacent bit line contacts CB are alternately arranged at positions close to any one of the selection gate lines SGL1, are arranged in a so-called zigzag pattern, and are formed so as to have a large arrangement interval.

  A source contact line CS is formed in the active region between the pair of selection gate lines SGL2 so as to connect them in common. The gate electrode MG of the memory cell transistor which is the first gate electrode is formed on the active region 3 intersecting with the word line WL, and the gate of the select gate transistor is disposed on the active region 3 intersecting with the select gate lines SGL1 and SGL2, respectively. Electrodes SG1 and SG2 are formed.

  3 is a cross-sectional view of a portion indicated by a cutting line AA in FIG. That is, the gate electrode MG in the active region 3 and the select gate electrodes SG1 and SG2 located at both ends thereof are shown in the center. In FIG. 3, the gate electrode MG and the gate electrodes SG1 and SG2 formed on the silicon substrate 1 are formed through the first gate insulating film 4 and the polycrystalline silicon film 5 as the electrode film for the floating gate electrode. An interelectrode insulating film 6 made of an ONO film or the like as a gate insulating film 2, a polycrystalline silicon film 7 as an electrode film for a control gate electrode, and a cobalt silicide (CoSi) film 8 as a metal silicide layer are sequentially stacked. It has a configuration. A silicon oxide film for improving reliability may be formed on the side walls of the gate electrodes MG and SG1 and SG2. The metal silicide layer may be a nickel silicide (NiSi) film.

  In the inter-gate insulating film 6 of the gate electrode SG, an opening 6a for conducting the polycrystalline silicon film 5 and the polycrystalline silicon film 7 is formed, and the polycrystalline silicon film 7 is embedded in the opening 6a. Impurity diffusion regions 1a serving as source / drain regions are formed between the gate electrodes MG-MG, MG-SG1, and MG-SG2 of the silicon substrate 1, and between the gate electrodes SG1-SG1 and between SG2-SG2. Impurity diffusion regions 1b are formed in the same manner as the impurity diffusion regions 1a. An impurity diffusion region 1c for reducing the contact resistance of the bit line contact is formed at the center of the impurity diffusion region 1b. The impurity diffusion region 1c is narrower than the impurity diffusion region 1b, has a deep diffusion depth (pn junction depth), and has an LDD (lightly doped drain) structure.

  Between the gate electrodes MG-SG1, MG-SG2, and between the gate electrodes MG-MG are provided as void portions (air gaps) AG1, AG2, respectively, as regions where no embedded material exists. The air gaps AG1 and AG2 are provided with the smallest dielectric constant of air as a dielectric interposed between the gate electrodes MG-SG1 and MG-SG2 or between MG-MG. Thereby, the coupling capacity between cells can be reduced.

  Between the pair of gate electrodes SG1-SG1 and SG2-SG2, spacers 9 made of a silicon oxide film are formed on the side walls of the opposing gate electrodes SG1, SG2, respectively, and the surface of the spacer 9 and the surface of the silicon substrate 1 Is formed so as to cover the silicon nitride film 10. The silicon nitride film 10 functions as a stopper film for processing. Further, between the gate electrodes SG1 and SG1, and between SG2 and SG2, a film such as a BPSG (boro-phospho-silicate glass) film such as a BPSG (boro-phospho-silicate glass) film is formed on the inner side of the silicon nitride film 10 and has excellent filling properties. An interlayer insulating film 11 is embedded.

  A TEOS oxide film 12, which is a silicon oxide film, is formed on the entire surface so as to cover the gate electrodes MG, SG1, SG2 and the upper part between them. As will be described later, the TEOS oxide film 12 is formed under conditions with poor embedding, so that the gaps AG1 and AG2 between the gate electrodes MG-SG1, MG-SG2, and MG-MG are positively formed. It is formed in the state left in.

  A contact plug 12 is formed between the gate electrodes SG1 and SG1 so as to reach the surface of the silicon substrate 1 from the upper surface of the TEOS oxide film 12 as illustrated. The contact plugs 13 correspond to the bit line contacts CB, and as described above, the adjacent bit line contacts CB are alternately arranged in a staggered manner, and in the illustrated case, the contact plugs 13 are formed on the right side. . Further, a source contact 14 is formed between the gate electrodes SG2 and SG2 so as to cross between the bit lines WL. The source contact 14 corresponds to the source contact line CS.

  Since the above configuration is adopted, in the configuration in which the silicide film is formed on the gate electrodes MG, SG1, and SG2, as a material that can minimize the coupling capacitance between the wirings between the word lines WL and WL, It can be set as the structure which provides the space | gap part AG1, AG2 made into the state in which the air (a vacuum state is included) with the smallest dielectric constant exists. As a result, the inter-wiring capacitance can be reduced, the voltage applied to the tunnel oxide film can be increased, and the reduction in the data writing speed can be suppressed.

Next, a manufacturing process in the case of manufacturing the above configuration will be described with reference to FIGS.
FIG. 4 shows a state after a processing step for separating the gate electrode MG and the selection gate electrodes SG1 and SG2 on the silicon substrate 1 is performed. A processing process until the gate electrodes MG, SG1, and SG2 are separately formed will be briefly described. First, a first gate insulating film 4 is formed on a silicon substrate 1, and then a polycrystalline silicon film 5 serving as a floating gate, an interelectrode insulating film 6 and polycrystalline silicon serving as a control gate (word line). A film 7 is formed by lamination.

  Further, a silicon nitride film 14 is stacked on the polycrystalline silicon film 7 to serve as a hard mask in dry etching. Thereafter, a resist pattern of the gate electrode MG and the selection gate electrodes SG1 and SG2 is formed by photolithography, and etching is performed by an RIE (reactive ion etching) method to separate and form the gate electrode MG and the selection gate electrodes SG1 and SG2. To do.

  After the interelectrode insulating film 6 is formed on the polycrystalline silicon film 5, a part of the intergate insulating film 6 in the formation region of the gate electrodes SG1 and SG2 is removed to form an opening 6a. When the polycrystalline silicon film 7 is formed on the inter-gate insulating film 6, the polycrystalline silicon film 7 is buried in the opening 6a so as to be electrically conductive.

  Thereafter, although not shown, a silicon oxide film is formed on each side wall portion of the gate electrodes MG, SG1, and SG2. Thereafter, an ion implantation process is performed to form impurity diffusion regions 1a and 1b corresponding to the source / drain regions of the memory cell transistor and the select gate transistor, thereby obtaining the state shown in FIG. Note that the gap AG1 is between the select gate electrodes SG1 and SG1 and between SG2 and SG2, and the gap AG2 is between the gate electrodes MG and MG of the memory cell transistor.

  Next, as shown in FIG. 5, a polysilazane 15 that is a coating type insulating film is buried between the gate electrodes MG, SG1, and SG2. First, a polysilazane solution is applied to the entire surface, and then an annealing process is performed to remove the organic solvent to replace it with a state close to a silicon oxide film. Subsequently, silicon on the upper part of the gate electrodes MG, SG1, and SG2 A structure shown in FIG. 5 is obtained by polishing and planarizing an unnecessary portion of the upper portion by CMP (chemical mechanical polishing) using the nitride film 14 as a stopper material.

Next, as shown in FIG. 6, a resist film 16 is applied by photolithography, and patterned so as to cover a portion of the cell array other than between the select gate electrodes SG1 and SG1 and between SG2 and SG2. Subsequently, the polysilazane 15 existing between the select gate electrodes SG1 and SG1 and between SG2 and SG2 is selectively removed by wet etching using an etchant such as hydrofluoric acid or a hydrofluoric acid / ammonium hydrofluoride mixed solution.
Thereby, the polysilazane 15 between the gate electrodes MG-MG, between the gate electrodes MG-SG1, and between the MG-SG2 covered with the resist 16 remains as it is, and the polysilazane 15 existing between the select gate electrodes SG1-SG1 and between SG2-SG2. Only is removed.

  Next, as shown in FIG. 7, a spacer 9 is formed for forming the impurity diffusion region 1c between the select gate electrodes MG-SG1 and between MG-SG2. As the spacer material, a silicon oxide film such as TEOS is deposited on the entire surface with a predetermined thickness, and spacer processing is performed by an etch back process. Thereafter, an impurity is implanted into the surface layer of the silicon substrate 1 by an ion implantation method to form an impurity diffusion region 1c to form a so-called LDD structure.

  Thereafter, as shown in FIG. 8, a silicon nitride film 10 is formed on the entire upper surface of the above structure. That is, it is formed on the upper surface of the polysilazane 15 on and between the gate electrodes MG, SG1, and SG2, and on the surface of the spacer 9 between the select gate electrodes SG1 and SG1 and between SG2 and SG2 and on the surface portion of the silicon substrate 1. To do. The silicon nitride film 10 is also a stopper for CMP processing and functions as a stopper for forming contacts.

  Next, as shown in FIG. 9, a silicide layer 8 is formed on each gate electrode MG, SG1, SG2. First, an interlayer insulating film 11 such as a BPSG film is embedded between the select gate electrodes MG-SG1 and MG-SG2, and planarized by CMP processing using the silicon nitride film 10 as a stopper. Thereafter, the silicon nitride film 14 on each of the gate electrodes MG, SG1, and SG2 is removed. Subsequently, a cobalt (Co) film is formed on the upper surface as a metal for forming a silicide, heat treatment is performed to salicide, and the polycrystalline silicon film 7 above the control gate electrode is replaced with a cobalt silicide (CoSi) film 8. And Nickel (Ni) or other metals can be used as the metal for forming the silicide.

  Next, as shown in FIG. 10, the resist 17 is patterned by photolithography so as to selectively cover the upper surfaces between the select gate electrodes SG1 and SG1 and between SG2 and SG2. As a result, the upper surface of the polysilazane 15 embedded between the gate electrodes MG, SG1, and SG2 is exposed.

  Subsequently, as shown in FIG. 11, using the resist 17 as a mask, the polysilazane 15 with the upper surface exposed is removed by wet etching with hydrofluoric acid or a hydrofluoric acid / ammonium hydrofluoric acid mixed solution. Then, the resist 17 is peeled off. As a result, the spacer 9, the silicon nitride film 10, and the interlayer insulating film 11 are buried between the select gate electrodes SG1 and SG1 and between SG2 and SG2. In addition, gaps AG1 and AG2 in which no embedded material exists are formed between the gate electrodes MG-SG1, between MG-SG2, and between the gate electrodes MG-MG.

  Next, as shown in FIG. 12, the TEOS oxide film 12 as a silicon oxide film is intentionally deposited on the upper surface of the above configuration under the condition that the embedding property is poor, so that the gaps AG1 and AG2 are not embedded. It forms so that it may become. Thus, the air gaps AG1 and AG2 are formed as an air gap structure in which the upper surface is closed with the TEOS oxide film 12 in a state where air is present inside.

  Thereafter, as shown in FIG. 3, contact plugs 13 are formed by photolithography between the select gate electrodes SG1 and SG1 and between SG2 and SG2. First, a resist pattern for forming a contact hole is formed, and etching is performed from the upper surface of the TEOS oxide film 12 so as to penetrate the interlayer insulating film 11, the silicon nitride film 10, and the gate insulating film 4 to expose the surface of the silicon substrate 1. To form a contact hole. Thereafter, a conductive material for the contact plug is deposited so as to be embedded in the contact hole, and a portion of the conductive material other than in the contact hole is removed by CMP or the like to form the contact plug 13.

  In this case, as a conductor material of the contact plug 13, a titanium (Ti) film, a titanium nitride (TiN) film or the like is first thinly formed as a barrier metal film, and then tungsten (W) or copper (Cu). It is good also as a structure formed so that conductor materials, such as, may be embedded. Thereafter, although not shown, a multilayer wiring process to the upper layer is performed to form a memory chip.

  According to the present embodiment, in the configuration in which the silicide film is formed on the gate electrodes MG, SG1, and SG2, between the wirings between the word lines WL and WL, that is, between the gate electrodes MG and SG1, between MG and SG2, and Between the gate electrodes MG and MG, gaps AG1 and AG2 in which no embedded substance exists can be formed, and as a material that can minimize the coupling capacitance between the gate electrodes MG, A state where air having a minimum dielectric constant (including a vacuum state) can be present.

When forming the gaps AG1 and AG2, when the polycrystalline silicon film 7 above the control gate electrode is silicided to form a cobalt silicide (CoSi) film 8, the inside of the gaps AG1 and AG2 is formed. Since the polysilazane 15 is buried, and the polysilazane 15 is removed after the silicide film 8 is formed, the gaps AG1 and AG2 can be formed while the silicide process is being carried out reliably.
Further, when the upper portion is closed with the TEOS film 12 after removing the polysilazane 15 in order to form the gap portions AG1 and AG2, it can be achieved by positively adopting a condition with poor embedding as the film formation condition. Therefore, the air gap structure can be reliably formed without employing a special process.

  Further, with the polysilazane 15 buried between the gate electrodes MG-SG1, MG-SG2, and between the gate electrodes MG-MG, a spacer 9 is formed between the select gate electrodes SG1-SG1 and between SG2-SG2 to form a high concentration. Since the ion implantation process for forming the impurity diffusion region 1c is performed, it is not necessary to form a resist film or the like using a mask material, so that the impurity diffusion region 1c can be formed in a self-aligned manner without increasing the number of processes. can do.

(Second Embodiment)
FIGS. 13 and 14 show a second embodiment of the present invention. The difference from the first embodiment is an air gap formation step. As in the first embodiment, after the step shown in FIG. 9, that is, the upper part of the polycrystalline silicon film 7 of the control gate electrode is silicided with cobalt to form a cobalt silicide (CoSi) layer 8, as shown in FIG. Then, a silicon oxide film 18 such as a TEOS oxide film is formed on the upper surfaces of all portions of the cell array region and the peripheral region. Thereafter, a resist is applied by photolithography, and a resist film 19 for etching is formed in a pattern that leaves the upper surface between the select gate electrodes SG1 and SG1 and between SG2 and SG2.

  Next, as shown in FIG. 14, the silicon oxide film 18 is formed so that the polysilazane 15 between the cell lines between the word lines, that is, between the gate electrodes MG-SG1, between MG-SG2, and between the gate electrodes MG-MG is exposed. Remove by dry etching. By this. The silicon oxide film 18a remains so as to cover the upper surface portions between the select gate electrodes SG1 and SG1 and between SG2 and SG2. Thereafter, the resist film 18 is removed by ashing or the like.

  Subsequently, when the silicon oxide film 18a is used as a mask, the etching rate of polysilazane is sufficiently larger than the etching rate of the silicon oxide film (polysilazane etching has a better selectivity than the silicon oxide film). VPC) is used to remove the polysilazane 15 between the exposed gate electrodes MG-SG1, MG-SG2, and between the gate electrodes MG-MG. Accordingly, the structure equivalent to the state shown in FIG. 11 in the first embodiment, that is, the gap portion AG1 in which no embedded material exists between the gate electrodes MG-SG1, between MG-SG2, and between the gate electrodes MG-MG. , AG2 can be formed.

Thereafter, as shown in FIG. 12 in the first embodiment, the TEOS oxide film 12 is intentionally deposited on the entire surface as a silicon oxide film under the condition that the embedding property is poor, so that the gaps AG1 and AG2 are formed. It is formed so as not to be embedded. Thus, the air gaps AG1 and AG2 are formed as an air gap structure in which the upper surface is closed with the TEOS oxide film 12 in a state where air is present inside.
In the second embodiment as described above, the same effect as that of the first embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In the present embodiment, the case where the cobalt silicide film 8 is applied as the formation of the gate electrode MG of the memory cell has been introduced. However, the same metal can be used for forming the silicide film by using Ni, Pt, Ti, Ta, and W. An effect can be obtained.

An amorphous silicon film can be used as the polycrystalline silicon film as the floating gate electrode or the control gate electrode.
The interelectrode insulating film 6 can also be a NONON (nitride-oxide-nitride-oxide-nitride) film in addition to the ONO film.
The interelectrode insulating film 6 can also use an aluminum film or a hafnium film at the center.
In the formation process of the word line WL, the etching process may be performed by forming a pattern having a fine width dimension that cannot be obtained by a normal lithography process by the sidewall transfer technique.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device showing a first embodiment of the present invention; Schematic plan view showing a partial layout pattern of the memory cell region Sectional drawing of the part shown by the cutting line AA in FIG. Schematic longitudinal section at one stage of the manufacturing process (Part 1) Schematic longitudinal section at one stage of the manufacturing process (2) Schematic longitudinal section at one stage of the manufacturing process (Part 3) Schematic longitudinal section at one stage of the manufacturing process (Part 4) Schematic longitudinal section at one stage of the manufacturing process (Part 5) Schematic longitudinal section at one stage of the manufacturing process (Part 6) Schematic longitudinal section at one stage of the manufacturing process (Part 7) Schematic longitudinal section at one stage of the manufacturing process (Part 8) Schematic longitudinal section at one stage of the manufacturing process (No. 9) Schematic longitudinal cross-sectional view in the stage of the manufacturing process which shows the 2nd Embodiment of this invention (the 1) Schematic longitudinal section at one stage of the manufacturing process (2)

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 2 is an STI (element isolation region), 3 is an active region, 8 is a cobalt silicide film (metal silicide layer), 10 is a silicon nitride film, 11 is an interlayer insulating film, 12 Is a TEOS oxide film, 13 is a contact plug, 15 is a polysilazane (coating insulating film), MG is a gate electrode of a memory cell transistor, SG1 and SG2 are gate electrodes of a selection gate transistor, and AG1 and AG2 are voids.

Claims (5)

Forming a first gate insulating film on a semiconductor substrate, laminating a first electrode film, a second gate insulating film, a second electrode film, and a first insulating film on the first gate insulating film; Separating and forming a plurality of gate electrodes;
Forming source / drain regions on the surface of the semiconductor substrate between the plurality of gate electrodes formed separately;
Embedding a coating-type insulating film between the gate electrodes after forming the source / drain regions;
Peeling off the first insulating film on the upper surface of the gate electrode and siliciding the exposed second electrode film by a predetermined amount;
Removing the coating-type insulating film except for the contact formation region;
Forming a second insulating film so as to cover the second electrode film while forming a gap between the gate electrodes by forming the film under a condition that the embedding property between the gate electrodes is low. A method for manufacturing a nonvolatile semiconductor memory device, comprising: Forming a first gate insulating film on a semiconductor substrate, laminating a first electrode film, a second gate insulating film, a second electrode film, and a first insulating film on the first gate insulating film; Separating and forming a plurality of gate electrodes;
Forming source / drain regions on the surface of the semiconductor substrate between the plurality of gate electrodes formed separately;
Embedding a coating-type insulating film between the gate electrodes after forming the source / drain regions;
Peeling off the first insulating film on the upper surface of the gate electrode and siliciding the exposed second electrode film by a predetermined amount;
Forming a second insulating film so as to cover the upper surface of the gate electrode and the upper surface between the gate electrodes;
Removing the second insulating film except for a contact formation region;
Removing the coating-type insulating film except for the contact formation region;
Forming a third insulating film so as to cover the second electrode film while forming a gap between the gate electrodes by forming a film under a condition that the embedding property between the gate electrodes is low. A method for manufacturing a nonvolatile semiconductor memory device, comprising: The method for manufacturing a nonvolatile semiconductor memory device according to claim 1,
Prior to the step of silicidating the second electrode film by a predetermined amount,
Removing the coating-type insulating film in a portion of the coating-type insulating film embedded between the gate electrodes to form a contact;
Forming a spacer on the side wall of the gate electrode facing the portion where the coating type insulating film is removed;
Forming a high-concentration impurity region on the surface of the source / drain region in the portion where the spacer is formed;
And a step of embedding a fourth insulating film between the gate electrodes in the portion where the spacer is formed. In the manufacturing method of the non-volatile semiconductor memory device according to claim 1,
The method of manufacturing a nonvolatile semiconductor memory device, wherein the coating type insulating film is a polysilazane (perhydrogenated silazane polymer) film. In the manufacturing method of the non-volatile semiconductor memory device according to claim 1,
The method for manufacturing a nonvolatile semiconductor memory device, wherein the insulating film formed under the condition of low embedding between the gate electrodes so as to cover the gap between the gate electrodes is a TEOS oxide film.

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