JP2010080853A - Nonvolatile semiconductor storage device, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of suppressing increase in capacity between word lines in comparison with the conventional case in the nonvolatile semiconductor storage device having a gap between the word lines. <P>SOLUTION: A plurality of memory cell transistors having laminated structure MG in which a gate insulating film 11, a polycrystal silicon film 12, an inter-electrode insulating film 13 and a polycrystal silicon film 14 are laminated in order, a source/drain region to be formed by sandwiching a channel region at a lower part of the laminated gate structure MG are adjacently arranged on a silicon substrate 1, continuous silicon oxide films are formed on the memory cell transistors so that gaps AG1, AG2 may be formed between the adjacent laminated gate structures MG, and the silicon oxide films 20, 21 are formed on the side of the laminated gate structure MG so that opening area of gaps AG1, AG2 parallel to a substrate surface at a position higher than a formation position of the inter-electrode insulating film 13 may become narrower than opening area of gaps AG1, AG2 parallel to a substrate surface at a position lower than the position. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

  In the development of nonvolatile semiconductor memory devices, miniaturization of elements has been progressing year by year in order to achieve a large capacity and low cost. For example, in the NAND flash memory device, the wiring pitches such as bit lines and word lines are being miniaturized. However, as the miniaturization progresses, the interlayer insulating film between the wirings becomes thinner, so that the capacity between the wirings increases, and it is becoming difficult to ignore the device characteristics.

  In other words, when the capacitance between wires increases, the capacitance between wires becomes connected to the tunnel oxide film in parallel, so the capacitance of the tunnel oxide film is the sum of all the capacitances including the capacitance between wires, and the capacitance of the tunnel oxide film is apparent. Get bigger. As a result, the voltage applied to the tunnel oxide film becomes small, so it takes time to write data and inject electrons into the floating gate through the tunnel oxide film. It is a cause.

  In order to avoid this, it is necessary to replace a silicon oxide film (relative permittivity ε = 3.9) generally used as an interlayer insulating film material between word lines with a material having a low relative permittivity. is there. Therefore, conventionally, an air gap configuration has been proposed in which air (relative permittivity ε = 1), which is a substance having the lowest relative permittivity, is used as an insulating film between word lines (see, for example, Patent Document 1).

  In Patent Document 1, a gate insulating film and a floating gate electrode are formed on a semiconductor substrate so as to have a predetermined shape, and another ground, an inter-gate insulating film and a control gate electrode are sequentially stacked to form the shape of the word line. Patterning is performed to form a gap between adjacent word lines. Thereafter, an insulating film is formed between the upper portions of adjacent word lines while maintaining a gap between the word lines by plasma CVD (Chemical Vapor Deposition) method, so that a non-volatile semiconductor having an air gap in the inter-word line insulating film Manufactures storage devices.

  However, in the manufacturing method described in Patent Document 1, an insulating film is formed between the upper portions of the word lines by using a plasma CVD method having poor embedding characteristics. As a result of the insulating film entering the gap, the insulating film is considerably deposited at the bottom of the gap, and the capacity between the word lines increases.

JP 2007-157927 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device having a gap between word lines and a method for manufacturing the nonvolatile semiconductor memory device capable of suppressing an increase in capacitance between word lines as compared with the conventional one. And

  According to one embodiment of the present invention, a stacked gate structure in which a gate insulating film, a charge storage layer, an interelectrode insulating film, and a control gate electrode are sequentially stacked on a semiconductor substrate, and a channel region under the stacked gate structure are sandwiched A plurality of memory cell transistors having source / drain regions formed on the semiconductor substrate are arranged adjacent to each other, and a continuous silicon oxide film is formed so that a gap is formed between the stacked gate structures adjacent to each other. In the nonvolatile semiconductor memory device formed on the cell transistor, the opening area of the gap in the direction parallel to the substrate surface at the opening area changing position higher than the formation position of the interelectrode insulating film is the opening area changing position. A silicon oxide film is formed on the side surface of the stacked gate structure so as to be narrower than the opening area of the gap in the direction parallel to the substrate surface at a lower position. The nonvolatile semiconductor memory device characterized by made is provided.

  According to one embodiment of the present invention, a gate insulating film, a charge storage layer, an interelectrode insulating film, and a control gate electrode are stacked on a semiconductor substrate, separated into a plurality of stacked gate structures, and the stacked gate structure is masked As a first step of forming source / drain regions on the semiconductor substrate, and forming a first silicon oxide film so as to cover the side surface of the stacked gate structure and the semiconductor substrate between the stacked gate structures A second step; a third step of embedding a coating-type insulating film between the stacked gate structures; and the control gate electrode formed above the control gate electrode so as to expose the control gate electrode of the stacked gate structure. A fourth step of removing the coating-type insulating film and the first silicon oxide film; and the first silicon oxide film and the coating-type insulating film between the stacked gate structures are connected to the inter-electrode insulating film. A fifth step of etching by a predetermined depth higher than a formation position; a side surface and an upper surface of the etched stacked gate structure; the first silicon oxide film between the stacked gate structures; and the coating type insulating film A sixth step of forming a second silicon oxide film thicker than the first silicon oxide film so as to cover the upper surface of the first silicon oxide film; and etching back the second silicon oxide film, In the seventh step of exposing the upper surface of the coating type insulating film, and by wet etching, the coating type insulating film between the stacked gate structures is removed, and the upper part is lower than the lower part between the stacked gate structures. The semiconductor in which the stacked gate structure is formed under the condition that the gap between the stacked gate structures is low and the eighth step of forming a void having a small opening area in a direction parallel to the substrate surface Method of manufacturing a nonvolatile semiconductor memory device which comprises a ninth step, the forming a third silicon oxide film is provided on the plate.

  According to the present invention, in a nonvolatile semiconductor memory device having a gap between word lines, it is possible to provide a nonvolatile semiconductor memory device capable of suppressing an increase in capacitance between word lines as compared with the conventional technology and a method for manufacturing the same. There is an effect that can be.

  A nonvolatile semiconductor memory device and a manufacturing method thereof according to embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. The drawings used in the following embodiments are schematic, and the relationship between the layer thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

Hereinafter, an embodiment in which the present invention is applied to a NAND flash memory device will be described. FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device. The memory cell array of the NAND flash memory device includes two select gate transistors Trs1 and Trs2, and a plurality of (for example, 2 ^n, n is a positive integer) connected in series between the select gate transistors Trs1 and Trs2. )) Of memory cell transistors Trm, NAND cell units (memory units) Su are formed in a matrix. In the NAND cell unit Su, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. One end of the bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 via a source region.

  FIG. 2 is a plan view showing a layout pattern of a part of the memory cell region. A plurality of STIs (Shallow Trench Isolations) 2 as element isolation regions extending in the Y direction in FIG. 2 are formed at predetermined intervals in the X direction on a silicon substrate 1 as a semiconductor substrate, thereby adjacent to each other. The active region 3 is formed in a state separated in the X direction in FIG. The word lines WL of the memory cell transistors Trm are formed at predetermined intervals in the Y direction, extending in the X direction in FIG. 2 orthogonal to the active region 3.

  Further, two selection gate lines SGL1 extending in the X direction in FIG. 2 are formed adjacently and in parallel. Bit line contacts CB are formed in the active region 3 between two adjacent select gate lines SGL1. The bit line contacts CB are arranged in adjacent active regions 3 by alternately changing the positions in the Y direction. That is, between the two selection gate lines SGL1, the bit line contact CB arranged close to one selection gate line SGL1 and the bit line contact CB arranged close to the other selection gate line SGL1 Are arranged in a so-called zigzag pattern, which are alternately arranged.

  As in the case of the selection gate line SGL1, two selection gate lines SGL2 extending in the X direction in FIG. 2 are formed in parallel at the position where the selection gate line SGL1 and the predetermined number of word lines WL exist. Has been. A source line contact CS is disposed in the active region 3 between the two select gate lines SGL2.

  A stacked gate structure MG of the memory cell transistors Trm is formed on the active region 3 intersecting the word line WL, and a gate structure SG1 of the select gate transistors Trs1 and Trs2 is formed on the active region 3 intersecting with the select gate lines SGL1 and SGL2. , SG2 are formed.

  FIG. 3 is a cross-sectional view taken along the line AA of FIG. That is, the gate structures SG1 and SG2 of the selection gate transistors Trs1 and Trs2 in the active region 3 and the stacked gate structure MG of the memory cell transistors Trm disposed between the two selection gate transistors Trs1 and Trs2 are shown. . In FIG. 3, the stacked gate structure MG of the memory cell transistors Trm and the gate structures SG1 and SG2 of the select gate transistors Trs1 and Trs2 formed on the silicon substrate 1 are electrodes for floating gate electrodes via the gate insulating film 11. A polycrystalline silicon film 12 as a film, an interelectrode insulating film 13 made of an ONO film, a polycrystalline silicon film 14 as an electrode film for a control gate electrode, and a nickel silicide (NiSi) film 15 as a metal silicide layer; Are sequentially stacked. Further, the side walls of the gate structures SG1 and SG2 adjacent to the memory cell transistors Trm of the select gate transistors Trs1 and Trs2 and the side walls of the stacked gate structure MG of the memory cell transistors Trm are provided with silicon oxide for improving reliability. The films 20 and 21 are formed. Specifically, it is composed of a silicon oxide film 20 formed at a position below the nickel silicide film 15 and a silicon oxide film 21 formed on the sidewall of the nickel silicide film 15 and thicker than the silicon oxide film 20. The Note that an opening 13a is formed in the interelectrode insulating film 13 of the gate structures SG1 and SG2 of the select gate transistor Trs1 to connect the polycrystalline silicon film 12 and the polycrystalline silicon film 14, and the polycrystalline silicon film is formed in the opening 13a. A silicon film 14 is embedded.

  Impurity diffusion regions 16a serving as source / drain regions are formed between the stacked gate structures MG and MG of the silicon substrate 1 and between the stacked gate structures MG and the gate structures SG1 and SG2. An oxide film 20 is formed. In addition, impurity diffusion regions 16b that become source / drain regions are formed between adjacent gate structures SG1-SG1 and between SG2-SG2, respectively, in the same manner as impurity diffusion regions 16a. An impurity diffusion region 16c for reducing the contact resistance of the bit line contact CB and the source line contact CS is formed in the central portion of the impurity diffusion region 16b. The impurity diffusion region 16c is narrower in width than the impurity diffusion region 16b, has a deep diffusion depth (pn junction depth), and has an LDD (Lightly Doped Drain) structure.

  Further, between the pair of adjacent gate structures SG1 to SG1, and between SG2 and SG2, a spacer film 31 made of a silicon oxide film is formed on the side wall surfaces of the gate structures SG1 and SG2 facing each other, and between the gate structures SG1 and SG1. A gate insulating film 11 and a silicon oxide film 20 are formed on the surface of the silicon substrate 1. A silicon nitride film 104 functioning as a stopper film for processing is formed so as to cover the surfaces of the spacer film 31 and the silicon oxide film 20. Further, a coating type insulating film having good fluidity and excellent embedding property, such as a BPSG (Boron PhosphoSilicate Glass) film, is provided inside the region surrounded by the silicon nitride film 104 between the gate structures SG1 and SG1 and between SG2 and SG2. An interlayer insulating film 41 formed by the above is embedded.

  Between the stacked gate structure MG and the gate structures SG1 and SG2 and between the stacked gate structures MG and MG, there are regions where there are no buried portions as air gaps (air gaps) AG1 and AG2, respectively. The air gaps AG1 and AG2 have a structure in which air (or a vacuum state) having the lowest dielectric constant is provided as a dielectric between the stacked gate structure MG and the gate structures SG1 and SG2 and between the stacked gate structures MG and MG. Yes. Thereby, the coupling capacity between cells can be reduced.

  Specifically, silicon oxide films 20 and 21 are formed on the side and bottom surfaces of the trenches formed between the stacked gate structure MG and the gate structures SG1 and SG2 and between the stacked gate structures MG and MG. The gaps AG1 and AG2 are formed in a structure closed by the insulating film 42. The bottom surfaces of the gaps AG1 and AG2 are positioned lower than the interelectrode insulating film 13. Further, the upper part of the gaps AG1, AG2 is a position where the nickel silicide film 15 constituting the control gate electrode is formed (opening area changing position), and the opening area in the direction parallel to the substrate surface is larger than that. It is smaller than the opening area in the direction parallel to the substrate surface at the lower position. That is, the film thickness of the silicon oxide film (hereinafter also referred to as a spacer film) 21 formed on the side wall at the position where the nickel silicide film 15 is formed is larger than the film thickness of the silicon oxide film 20 below the position. It is thick. Thus, in the cross section perpendicular to the extending direction of the word line (control gate electrode) shown in FIG. 3, the gaps AG1 and AG2 are formed with the lower gap 22 located below the nickel silicide film 15 and the nickel silicide. The upper gap 23 is located at the same height as the film 15 and has an opening cross section smaller than the lower gap 22.

  An interlayer insulating film 42 made of a TEOS film is formed on the entire surface so as to cover the stacked gate structure MG, the gate structures SG1 and SG2, and the upper part therebetween. As will be described later, the interlayer insulating film 42 is formed under conditions with poor embeddability so that gaps AG1 and AG2 between the stacked gate structure MG and the gate structures SG1 and SG2 and between the stacked gate structures MG and MG are formed. It is formed in a state that is actively left.

  A contact plug 45 is formed between the gate structures SG1 and SG1 so as to reach the surface of the silicon substrate 1 from the upper surface of the interlayer insulating film. The contact plug 45 corresponds to the bit line contact CB, and as described above, the adjacent bit line contacts CB are alternately arranged in a staggered manner, and in the case of FIG. Yes. Further, a contact plug 46 reaching the surface of the silicon substrate 1 from the upper surface of the interlayer insulating film 42 is formed between the gate structures SG2 and SG2. The contact plug 46 corresponds to the source line contact CS and is formed so as to cross between the bit lines BL.

  In such a NAND flash memory in which a silicide film is formed on top of the stacked gate structure MG and the gate structures SG1 and SG2, air having the smallest dielectric constant (including a vacuum state) between adjacent word lines WL-WL. By providing the gaps AG1 and AG2 in which the gap exists, the coupling capacitance between the adjacent word lines WL-WL can be minimized. As a result, the inter-wiring capacitance can be reduced, the voltage applied to the tunnel oxide film can be increased, and the reduction in the data writing speed can be suppressed.

  Next, a method for manufacturing a nonvolatile semiconductor memory device having such a structure will be described. 4-1 to 4-16 are cross-sectional views schematically showing an example of a method for manufacturing the nonvolatile semiconductor memory device according to this embodiment.

  First, a gate insulating film 11 and a polycrystalline silicon film 12 to be a floating gate electrode are formed on a silicon substrate 1, and select gate transistors Trs1, adjacent in the extending direction of the select gate lines SGL1, SGL2 and the word line WL. Patterning is performed so as to separate Trs2 and the memory cell transistor Trm, thereby forming an STI (not shown). Thereafter, an interelectrode insulating film 13 and a polycrystalline silicon film 14 to be a control gate electrode (word line) are laminated. In addition, a silicon nitride film 101 serving as a hard mask in dry etching is stacked on the polycrystalline silicon film 14. Thereafter, a resist pattern for forming the laminated gate structure MG and the gate structures SG1 and SG2 is formed by using a photolithography technique, and etching is performed by a RIE (Reactive Ion Etching) method using the resist pattern as a mask. The select gate transistors Trs1, Trs2 and the memory cell transistor Trm adjacent to each other in the direction orthogonal to the select gate lines SGL1, SGL2 and the word line WL are separated. Thereby, the stacked gate structure MG and the gate structures SG1 and SG2 are formed. After the interelectrode insulating film 13 is formed on the polycrystalline silicon film 12, a part of the interelectrode insulating film 13 in the gate structure SG1, SG2 formation region of the select gate transistors Trs1, Trs2 is removed, and the opening 13a is formed. It is formed. Thus, when the polycrystalline silicon film 14 is formed on the interelectrode insulating film 13, the polycrystalline silicon film 14 is buried in the opening 13a, and the polycrystalline silicon film 12 and the polycrystalline silicon film 14 are electrically connected. It becomes possible to connect to.

  Thereafter, a silicon oxide film 20 for increasing the reliability is formed on the silicon substrate 1 on which the separated stacked gate structures MG and the gate structures SG1 and SG2 are formed. At this time, the silicon oxide film 20 is formed so as to cover the side walls of each stacked gate structure MG and the gate structures SG1 and SG2, and between the stacked gate structures MG and MG, and between the stacked gate structures MG and the gate structures SG1 and SG2. To do. Next, an ion implantation process is performed between the stacked gate structures MG and MG, between the stacked gate structures MG and the gate structures SG1 and SG2, and between the gate structures SG1 and SG1, and between SG2 and SG2. Impurity diffusion regions 16a and 16b corresponding to the source / drain regions of Trm and select gate transistors Trs1 and Trs2 are formed. As a result, the product shown in FIG. 4A is obtained. Note that the space between the gate structures SG1, SG2 and the stacked gate structure MG corresponds to the air gap AG1, and the space between the stacked gate structures MG and MG corresponds to the air gap AG2.

  Next, an SOG (Spin On Glass) film 102, which is a coating type insulating film, is applied on the silicon substrate 1 on which the stacked gate structure MG and the gate structures SG1 and SG2 are formed, and the stacked gate structures MG- The gate structures SG1 and SG2 are embedded so as to cover the upper part thereof (FIG. 4-2). Specifically, first, a polysilazane solution is applied to the entire surface, and thereafter, an annealing process is performed to remove the organic solvent to replace it with a state close to a silicon oxide film, thereby forming the SOG film 102.

  Thereafter, unnecessary portions of the SOG film 102 are polished and removed by a CMP (Chemical Mechanical Polishing) method until the silicon oxide film 20 above the stacked gate structure MG and the gate structures SG1 and SG2 is exposed (FIG. 4). 3).

  Next, a resist 103 is applied on the SOG film 102 from which the silicon oxide film 20 is exposed, and a portion of the memory cell array other than between the adjacent gate structures SG1 to SG1 and between SG2 to SG2 is covered using a photolithography technique. Then, patterning is performed to form a mask pattern (FIG. 4-4). Subsequently, the SOG film 102 existing between the adjacent gate structures SG1 to SG1 and SG2 to SG2 is selectively removed by wet etching using an etchant such as hydrofluoric acid or a hydrofluoric acid / ammonium fluoride mixed solution. (FIGS. 4-5). As a result, the SOG film 102 between the stacked gate structures MG-MG and the stacked gate structure MG-gate structures SG1, SG2 covered with the resist 103 remains as it is, and exists between the gate structures SG1-SG1 and SG2-SG2. Only the SOG film 102 is removed.

  After removing the resist 103, a spacer film 31 for forming the impurity diffusion region 16c is formed between the adjacent gate structures SG1 and SG1 and between SG2 and SG2. As the spacer material, a silicon oxide film such as TEOS (Tetraethyl orthosilicate) can be used. In this case, patterning is performed so as to cover the portion of the cell array other than between the adjacent gate structures SG1 to SG1 and between SG2 and SG2, and after forming a mask pattern, a silicon oxide film is deposited on the entire surface with a predetermined thickness and etched. By back processing, spacer processing is performed only on the side wall portion of the gate structure SG1, SG2 facing the adjacent gate structure SG1, SG2. At this time, the silicon oxide film 20 and the SOG film 102 between the stacked gate structures MG-MG and between the stacked gate structure MG-gate structures SG1, SG2 are partially removed. Thereafter, impurities are implanted into the surface layer of the silicon substrate 1 between adjacent gate structures SG1 and SG1 and between SG2 and SG2 by ion implantation and activated by heat treatment to form an impurity diffusion region 16c (FIG. 4-6). ).

  Next, a silicon nitride film 104 having a predetermined thickness is formed on the entire upper surface of the above configuration. That is, it is formed on the stacked gate structure MG, the gate structures SG1 and SG2, and the upper surface of the SOG film 102 between them, and between the adjacent gate structures SG1 and SG1, between the SG2 and SG2, and the silicon oxide film 20 Form on the surface. This silicon nitride film 104 is a stopper for CMP processing to be performed in a later process, and also functions as a stopper when forming a contact. Further, irregularities are formed on the upper surface of the silicon nitride film 104 in accordance with the base. Specifically, recesses are formed between the stacked gate structure MG and the gate structures SG1 and SG2 and between the stacked gate structures MG and MG. Thereafter, a BPSG film 105, which is a coating type insulating film, is formed on the entire surface of the silicon nitride film 104 (FIGS. 4-7).

  Next, the BPSG film 105 is planarized by CMP using the silicon nitride film 104 as a stopper (FIGS. 4-8). As a result, an interlayer insulating film 41 having a structure in which the BPSG film 105 is embedded is formed between the adjacent gate structures SG1 to SG1 and SG2 to SG2.

  Next, the silicon nitride films 104 and 101 on the upper portions of the stacked gate structure MG and the gate structures SG1 and SG2 are etched back using the RIE method (FIG. 4-9). As a result, in each stacked gate structure MG and the gate structures SG1 and SG2, the polycrystalline silicon film 14 which is a control gate electrode is exposed, and between each stacked gate structure MG-MG and between the stacked gate structures MG and the gate structures SG1 and SG2. Then, the silicon oxide film 20 and the SOG film 102 formed on the side walls of the stacked gate structure MG and the gate structures SG1 and SG2 are exposed.

  Thereafter, a nickel (Ni) film is formed on the upper surface as a metal for forming a silicide by a film forming method such as a sputtering method, heat treatment is performed, salicide is performed, and an upper portion of the polycrystalline silicon film 14 constituting the control gate electrode is formed. Is a nickel silicide film 15 (FIG. 4-10).

  Next, the resist 106 is patterned by a photolithography technique so as to selectively cover the upper surfaces between the adjacent gate structures SG1 and SG1 and SG2 and SG2 (FIG. 4-11). As a result, the upper surfaces of the SOG film 102 and the silicon oxide film 20 embedded between the stacked gate structure MG and the gate structures SG1 and SG2 are exposed.

  Subsequently, using the resist 106 and the nickel silicide film 15 as a mask, the SOG film 102 and the silicon oxide film 20 with the upper surface exposed are etched to a predetermined depth by the RIE method (FIG. 4-12). Here, etching is performed until the upper surfaces of the SOG film 102 and the silicon oxide film 20 substantially coincide with the lower surface of the nickel silicide film 15 under the condition that the silicon oxide film is more easily etched than the nickel silicide film 15.

  After the resist 106 is peeled off, a silicon oxide film 107 is formed on the upper surface by using a film forming method with good coverage (FIG. 4-13). The silicon oxide film 107 is formed so as to cover the etched back SOG 102 film, the surface of the silicon oxide film 20, and the side surface of the nickel silicide film 15. Thereafter, using the RIE method, the formed silicon oxide film 107 is etched back (FIG. 4-14). As a result, the spacer film 21 made of the silicon oxide film 107 is formed on the side surface of the nickel silicide film 15. Further, an opening 21a is formed between the spacer films 21, and the lower SOG film 102 is exposed through the opening 21a.

  Thereafter, the SOG film 102 is removed from the openings 21a formed between the spacer films 21 by wet etching (FIG. 4-15). As a result, gaps AG1, AG2 are formed between the gate structures SG1, SG2 and the stacked gate structure MG and between the stacked gate structures MG, respectively. The gaps AG1, AG2 include a lower gap 22 located below the nickel silicide film 15 where the SOG film 102 was formed, an upper gap 23 formed at the same height as the nickel silicide film 15, Consists of. The opening area of the upper gap portion 23 in the direction parallel to the substrate surface is smaller than the opening area of the lower gap portion 22 in the direction parallel to the substrate surface.

  As a result, the spacer film 31, the silicon nitride film 104, and the interlayer insulating film 41 are buried between the adjacent gate structures SG1-SG1 and SG2-SG2, but the stacked gate structure MG-gate structures SG1, SG2 Although the silicon oxide films 20 and 21 are formed on the side walls and the bottom between the stacked gate structures MG-MG, the gaps AG1 and AG2 in which no other embedded material exists are formed.

  Next, an interlayer insulating film 42 as a silicon oxide film is deposited on the upper surface of the above configuration under conditions where the embedding property is poor (FIG. 4-16). For example, the TEOS film can be formed by a plasma CVD method. At this time, the deposition is performed under poor embeddability, and the opening area of the upper gap portion 23 is smaller than the opening area of the lower gap portion 22 in the gap portions AG1 and AG2. With the TEOS film hardly embedded in AG2, the interlayer insulating film 42 can be formed between the stacked gate structure MG and the gate structures SG1 and SG2 and between the stacked gate structures MG and MG. As a result, the air gaps AG1 and AG2 are formed as an air gap structure in which the upper surface is closed with the interlayer insulating film 42 in a state where air exists.

  Thereafter, as shown in FIG. 3, contact plugs 45 and 46 are formed by photolithography between the gate structures SG1 and SG1 and between SG2 and SG2. That is, a resist pattern for forming a contact hole is formed, and the surface of the silicon substrate 1 is penetrated from the upper surface of the interlayer insulating film 42 through the interlayer insulating film 41, the silicon nitride film 104, the silicon oxide film 20, and the gate insulating film 11. Etching is performed so as to expose the contact hole. Thereafter, a conductive material for the contact plug is deposited so as to be embedded in the contact hole, and a portion of the conductive material other than in the contact hole is removed by CMP or the like to form the contact plugs 45 and 46.

  In this case, as the contact plugs 45 and 46, a conductive material such as a titanium (Ti) film or a titanium nitride (TiN) film is first thinly formed as a barrier metal film, and then tungsten (W) or copper ( A structure in which a conductive material such as Cu) is embedded may be employed. Thereafter, although not shown, a multilayer wiring process to the upper layer is performed to form a memory chip.

  In the above description, the case where the nickel silicide film 15 is formed as the silicide film on the upper part of the control gate electrode of the stacked gate structure MG and the gate structures SG1 and SG2, is exemplified. However, the metal forming the silicide film is The same effect can be obtained by using Co, Pt, Ti, Ta, and W. An amorphous silicon film can also be used as the polycrystalline silicon films 12 and 14 used for the floating gate electrode or the control gate electrode. Further, as the interelectrode insulating film 13, a NONON (Nitride-Oxide-Nitride-Oxide-Nitride) film can be used in addition to the ONO film. The interelectrode insulating film 13 can also use an aluminum film or a hafnium film at the center. Further, in the formation process of the word line WL, a pattern having a fine width dimension that cannot be obtained by a normal lithography process by the sidewall transfer technique may be formed and etched.

  According to this embodiment, after forming the nickel silicide film 15 on the control gate electrode, the SOG film 102 between the word lines WL is removed by a predetermined depth, and the silicon oxide formed between the stacked gate structures is formed thereon. A silicon oxide film 107 thicker than the film 20 is formed, and an opening 21a is formed in the silicon oxide film 107 between the word lines WL so that the upper surface of the SOG film 102 is exposed by etch back, and the SOG film 102 is formed from the opening 21a. Therefore, the gaps AG1 and AG2 having a smaller opening area can be formed in the upper part. As a result, during the subsequent formation of the interlayer insulating film 42 by the plasma CVD method, the amount of the silicon oxide film constituting the interlayer insulating film 42 that falls into the gaps AG1, AG2 is set to the gap where the upper opening area is not reduced. This can be reduced as compared with the case where a silicon oxide film is formed on the portion, and a more complete hollow structure can be achieved.

  In addition, according to the first embodiment, the amount of silicon oxide film falling into the gaps AG1 and AG2 is smaller than that in the conventional structure, so that the capacitance between the stacked gate structures can be reduced. It also has the effect.

3 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device. FIG. It is a top view which shows the layout pattern of a part of memory cell area | region. It is AA sectional drawing of FIG. It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 1). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 2). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 3). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 4). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 5). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 6). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 7). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 8). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 9). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 10). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 11). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 12). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 13). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 14). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 15). It is sectional drawing which shows typically an example of the manufacturing method of the non-volatile semiconductor memory device by this embodiment (the 16).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 11 ... Gate insulating film, 12, 14 ... Polycrystalline silicon film, 13 ... Interelectrode insulating film, 13a ... Opening, 15 ... Nickel silicide film, 16a, 16b, 16c ... Impurity diffusion region, 20, 107 ... Silicon oxide film, 21 ... Silicon oxide film (spacer film), 22 ... Lower air gap, 23 ... Upper air gap, 31 ... Spacer film, 41,42 ... Interlayer insulating film, 45,46 ... Contact plug, 101,104 ... Silicon nitride film, 102 ... SOG film, 103, 106 ... Resist, 105 ... BPSG film, AG1, AG2 ... Gaps, MG ... Stacked gate structure, SG1, SG2 ... Gate structure, Trm ... Memory cell transistor, Trs1, Trs2 ... selection gate transistor, WL ... word line.

Claims (5)

A stacked gate structure in which a gate insulating film, a charge storage layer, an interelectrode insulating film, and a control gate electrode are sequentially stacked on a semiconductor substrate, and a channel region under the stacked gate structure is formed on the semiconductor substrate. A nonvolatile memory in which a plurality of memory cell transistors each having a source / drain region are arranged adjacent to each other, and a continuous silicon oxide film is formed on the memory cell transistors so that a gap is formed between the adjacent stacked gate structures. In a semiconductor memory device,
The opening area of the gap in the direction parallel to the substrate surface at the opening area change position higher than the formation position of the interelectrode insulating film is the direction in the direction parallel to the substrate surface at a position lower than the opening area change position. A non-volatile semiconductor memory device, wherein a silicon oxide film is formed on a side surface of the stacked gate structure so as to be narrower than an opening area of the gap.   2. The nonvolatile semiconductor device according to claim 1, wherein a silicon oxide film is formed on the semiconductor substrate between the stacked gate structures so that a lower end of the gap is located below the interelectrode insulating film. Semiconductor memory device. A gate insulating film, a charge storage layer, an interelectrode insulating film, and a control gate electrode are stacked on a semiconductor substrate, separated into a plurality of stacked gate structures, and source / drain regions are formed on the semiconductor substrate using the stacked gate structure as a mask. A first step of forming;
A second step of forming a first silicon oxide film so as to cover the side surface of the stacked gate structure and the semiconductor substrate between the stacked gate structures;
A third step of embedding a coating type insulating film between the stacked gate structures;
A fourth step of removing the coating insulating film and the first silicon oxide film formed above the control gate electrode so as to expose the control gate electrode of the stacked gate structure;
A fifth step of etching the first silicon oxide film and the coating type insulating film between the stacked gate structures by a predetermined depth higher than a position where the interelectrode insulating film is formed;
Thicker than the first silicon oxide film so as to cover the etched side surface and upper surface of the stacked gate structure, and the upper surface of the first silicon oxide film and the coating type insulating film between the stacked gate structures. A sixth step of forming a second silicon oxide film;
Etching back the second silicon oxide film to expose an upper surface of the coating type insulating film between the stacked gate structures;
The coating type insulating film between the stacked gate structures is removed by wet etching, and a gap is formed between the stacked gate structures with a smaller opening area in the direction parallel to the substrate surface in the upper part than in the lower part. 8 processes,
A ninth step of forming a third silicon oxide film on the semiconductor substrate on which the stacked gate structure is formed under the condition that the burying property between the stacked gate structures is low;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: Forming a silicon film as the control gate electrode in the first step;
The fifth step includes
Forming a metal film containing a metal that forms silicide by reacting with silicon on the control gate electrode;
Performing a heat treatment to form a silicide film on the control gate electrode;
Etching the first silicon oxide film and the coating insulating film between the stacked gate structures by a predetermined depth using the silicide film as a mask;
The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, comprising:   5. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein in the ninth step, the third silicon oxide film is formed by a plasma CVD method.

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