JP2008152329A - Circuit analysis method, circuit analysis program, and circuit simulation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the circuit area of a semiconductor device to be designed. <P>SOLUTION: A circuit simulation device 10 includes: a delay time verifying part 252 for calculating a delay time T<SB>d</SB>under a prescribed environmental condition concerning static timing verification with respect to a logical circuit 100 after layout, and performing hold verification; and a layout correcting part 253. When hold violation is determined in the hold verification, the delay time verifying part 252 selects a correcting method corresponding to the environmental condition from the plurality of layout correcting methods. The layout correcting part 253 corrects the layout of the logical circuit with the use of the correcting method selected by the delay time verifying part. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a circuit analysis method, a circuit analysis program, and a circuit simulation apparatus for a semiconductor integrated circuit, and more particularly to a timing correction method during static timing verification.

  In a synchronous circuit constituting a system LSI (Large-Scale Integration), signal and clock delays have a significant effect on the operation of the entire LSI. For this reason, in LSI design, static timing analysis (STA) for verifying whether a synchronous circuit operates without any problem (see Non-Patent Document 1: “Introduction to System LSI Design” by Corona) ).

  In the STA, it is verified whether a circuit to be analyzed operates at a desired clock frequency. That is, it is verified whether the delay time between the flip-flops (FF) satisfies a desired timing constraint. The STA calculates the delay time using only the logical structure for all paths from the input to the output in the combination circuit of the synchronous circuit. Therefore, the STA can execute timing verification at a higher speed than the dynamic timing verification.

  Normally, the STA is executed at the time of sign-off determination after layout design in LSI design (final confirmation of design). In STA performed at the time of sign-off determination after layout design, analysis is performed based on the back-annotated actual wiring length. In back annotation, parasitic elements (capacitance, resistance, inductor, etc.) in a logic circuit (design target circuit) after layout design are extracted, and using these, it is confirmed whether the design target circuit satisfies the target performance. At this time, an SDF (Standard Delay Format) file that defines delay information of elements and wirings is generated. The analysis target circuit of the STA is a logic circuit between two flip-flops. Here, a clock signal whose clock skew is reduced by clock tree synthesis is input to the two flip-flops. In the STA, first, based on an SDF (Standard Delay Format) file and a netlist, delay times (delay times with respect to a clock signal) in all paths between two flip-flops through the analysis target circuit are extracted. It is then determined whether these delay times meet the desired timing constraints.

  Usually, in the STA, timing verification is performed in consideration of manufacturing variations in the manufacturing process of the analysis target circuit. For this reason, in the SDF file, a delay time corresponding to the manufacturing variation is defined. The delay time of elements and wirings varies depending on manufacturing variations that are difficult to control in the transistor process (transistor diffusion process) and the wiring process (wiring diffusion process). For example, the delay time varies depending on manufacturing variations such as wiring width, transistor gate length, and ion distribution in the ion implantation region. For this reason, the maximum delay time (SLOW) and the minimum delay time (FAST) of the delay time varying due to such manufacturing variations are defined in the SDF file. Hereinafter, a condition that causes a variation in delay time verified in the STA is referred to as a STA condition.

  In recent years, with the miniaturization of technology, fluctuations in delay time due to the use environment of a circuit have come to greatly affect circuit operation. That is, it is necessary to perform STA under STA conditions corresponding to the use environment. For example, the delay time decreases when the power supply voltage becomes higher than a predetermined reference voltage, and increases when the power supply voltage becomes low. In addition, the delay time decreases when the ambient temperature is lower than a predetermined reference temperature, and increases when the ambient temperature is high. For this reason, recently, STA has been performed in consideration of the magnitude of the power supply voltage and the fluctuation of the ambient temperature of the circuit.

  With reference to FIG. 9, the flow of STA according to the prior art will be described. After the layout phase is completed, the resistance value and the capacitance value of each element and wiring of the analysis target circuit are extracted with reference to the designed layout information and the net list (step S11). Next, the delay time is calculated for each element and wiring corresponding to the STA condition to be verified, and is generated as an SDF file (step S12). Usually, the STA conditions to be verified vary depending on the technology of the analysis target circuit. Here, for example, the SDF file (MIN.SDF) that defines the minimum delay time, the SDF file (MAX.SDF) that defines the maximum delay time, and the minimum delay time when a power supply voltage lower than a predetermined voltage is supplied. SDF files corresponding to four conditions are prepared: an SDF file to be defined (MIN_LV.SDF) and an SDF file (MAX_HV.SDF) that defines a maximum delay time when a power supply voltage higher than a predetermined voltage is supplied. Here, a voltage lower and a higher voltage than the predetermined voltage may be read as the lowest voltage and the highest voltage in the variation of the power supply voltage.

  Next, using the generated SDF file and netlist, the delay times of all the paths between the flip-flops are calculated. Here, the delay time is calculated by an EDA tool using a library value created based on data actually measured from an evaluation sample or the like. For example, the SDF file used is MIN. In the case of SDF, the minimum delay time for each path between flip-flops is calculated. Next, it is determined whether the calculated delay time meets a desired setup condition (setup verification: step S13). At this time, if a setup violation occurs, the delay time is corrected by correcting the layout of the analysis target circuit, changing the driving capability of the cell, or the like (setup correction: step S14). In the prior art, when a setup violation occurs in the setup verification, the layout is corrected according to the STA condition (used SDF file).

  If there is no setup violation in step S13, it is determined whether the delay time for each path calculated in step S13 meets the hold condition (hold verification: step S15). At this time, if a hold violation occurs, the hold time is corrected by changing the layout to add a cell (hereinafter referred to as a delay cell) including a gate element (delay element) such as a buffer between the flip-flops to be analyzed. (Hold correction: step S16). Note that the execution order of the setup verification and setup correction and the hold verification and hold correction may be reversed or performed in parallel.

  After the setup correction (step S14) and the hold correction (step S16), the process proceeds to step S11 again, and setup verification and hold verification are executed. Here, when the path delay time for all the prepared SDF files satisfies the setup condition and the hold condition (Yes in step S17), the timing FIX is performed, and the STA ends. Here, although SDF files corresponding to four STA conditions are prepared, STAs may be executed using SDF files that define delay information under other environmental conditions. Even in the STA using these SDF files, when there is a setup violation or a hold violation, the setup correction and the hold correction are executed in the same manner as described above.

A conventional technique for performing hold verification in an STA is described in, for example, Japanese Patent Laid-Open No. 2005-275783 (see Patent Document 1).
Suzuki Goro, “Introduction to System LSI Design”, Corona, published in March 2003, p71-p88 Japanese Patent Application Laid-Open No. 2005-275783

  As described above, in the related art, when a hold violation occurs, the hold correction is uniformly performed by adding delay cells regardless of the STA condition (used SDF file). However, in this case, the circuit area after design increases due to the added delay cell, and the manufacturing cost and power consumption of the design circuit increase. Further, the delay cell added at the time of hold correction may greatly change the setup time under the same condition, and the corrected layout may cause a setup violation. For this reason, it is necessary to make further setup correction (change of layout) by hold correction, and TAT (Turn Around Time) increases.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention] in parentheses. This number / symbol is added to clarify the correspondence between the description of [Claims] and the description of the best mode for carrying out the invention. It should not be used for interpretation of the technical scope of the invention described in [Scope].

The circuit simulation apparatus (10) according to the present invention calculates a delay time (T _d ) under a predetermined environmental condition (23) and performs hold verification in static timing verification for the logic circuit (100) after layout. A delay time verification unit (252) and a layout correction unit (253) are provided. When the delay time verification unit (252) determines a hold violation in the hold verification, the delay time verification unit (252) selects a correction method according to the environmental condition (23) from a plurality of layout correction methods. The layout correction unit (253) corrects the layout of the logic circuit by the correction method selected by the delay time verification unit. Thereby, the timing of the logic circuit (100) after layout is corrected, and the layout design is completed. According to the prior art, the timing correction for the hold violation is only the addition of the delay cell, but according to the present invention, the timing can be corrected also by the addition of the wiring.

  The plurality of layout correction methods according to the present invention preferably include a method of adding a delay cell to a logic circuit and a method of adding a wiring of an appropriate length having a delay amount necessary for hold correction to the logic circuit. . Here, the delay time verification unit (252) performs hold verification under the environmental condition (23), and if there is a hold violation, a method of adding wiring according to the verified environmental condition (23), or delay cell Select the method to add as the correction method.

  The circuit simulation apparatus (10) according to the present invention further includes a storage device (13) in which a table (24) in which environmental conditions (23) and a plurality of layout correction methods are associated is stored according to the technology of the logic circuit. It is preferable to comprise. In this case, the delay time verification unit (252) performs hold verification under the environmental condition (23). If the hold violation is found, the delay time verification unit (252) refers to the table (24) according to the technology of the logic circuit to be analyzed, and performs verification. A layout correction method corresponding to the environmental condition (23) is selected.

  Also, depending on the design circuit technology, the amount of correction of the hold time due to the addition of the wiring may be larger than the amount of correction due to the addition of the delay cell under the condition that the power supply voltage is higher than the predetermined voltage. In such a case, correction of the delay time by adding wiring is effective. Similarly, depending on the technology of the design circuit, the correction amount of the hold time due to the addition of the wiring may be larger than the correction amount due to the addition of the delay cell under the condition where the ambient temperature is higher than the predetermined temperature. In such a case as well, it is effective to correct the delay time by adding wiring.

  When the hold time is corrected, the correction amount of the delay time when a delay element is added to the circuit to be designed and the correction amount when a wiring delay is added show different values. Further, the amount of correction varies depending on each condition such as manufacturing variation of the circuit to be designed and usage environment. For example, when the process conditions considering manufacturing variations are the same, under the condition that the ambient temperature is high, the correction amount by adding the wiring delay may be larger than the correction by adding the delay cell. . However, the relationship between the correction amount of the delay time for each correction method and the STA conditions such as the usage environment differs depending on the technology of the circuit to be designed and is not uniquely identified. In the present invention, the hold correction is performed by a correction method according to the manufacturing variation of the analysis target circuit and the use environment. When the hold time is corrected by correcting the layout by adding wiring, an increase in circuit area can be suppressed as compared with the correction by adding delay cells.

  When the hold time is corrected, the layout is changed, so the setup time in the corrected circuit varies. For this reason, the STA repeats timing verification (setup verification and hold verification) and layout correction until a desired timing constraint is satisfied for each STA condition. However, due to a hold correction under a certain STA condition (condition A), a setup violation may occur under another STA condition (condition B) where the violation disappears. In this case, if a hold correction method with a small delay time correction amount in the condition B is adopted as the hold correction method in the condition A, it is possible to prevent the occurrence of a setup violation due to the hold correction. As described above, according to the present invention, by appropriately selecting a method for correcting the hold time, it is possible to prevent the delay time under other STA conditions from greatly changing even after the hold correction. As a result, the number of times of timing correction in the STA is reduced as compared with the case where only delay cells are added, and the timing can be efficiently converged to a desired timing.

  According to the circuit analysis method, the circuit analysis program, and the circuit simulation apparatus according to the present invention, the circuit area of the semiconductor device to be designed can be reduced.

  In addition, a semiconductor device with reduced power consumption can be designed.

  Furthermore, the design time of the semiconductor device can be shortened.

  Hereinafter, an embodiment of a circuit simulation apparatus 10 according to the present invention will be described with reference to the accompanying drawings. In the present embodiment, a circuit simulation apparatus that executes STA at the sign-off after the layout phase will be described. In STA (static timing verification), whether or not a logic-synthesized gate level logic circuit operates at a desired clock frequency is confirmed by verifying whether or not a desired timing constraint is satisfied. In the present embodiment, the circuit simulation device 10 performs setup verification and hold verification for verifying whether the delay time of a signal between flip-flops satisfies a desired setup condition and hold condition.

1. Configuration The configuration of a circuit simulation apparatus 10 according to the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a configuration diagram of a circuit simulation apparatus 10. Referring to FIG. 1, a circuit simulation device 10 according to the present invention includes a CPU 11, a RAM 12, a storage device 13, an input device 14, and an output device 15 that are connected to each other via a bus 16. The storage device 13 is a storage device such as a hard disk or a memory. The input device 14 outputs various data to the CPU 11 and the storage device 13 by being operated by a user such as a keyboard and a mouse. The output device 15 is exemplified by a monitor and a printer, and outputs the result of the circuit analysis output from the CPU 11 in a format that the user can visually recognize.

  In response to the input from the input device 14, the CPU 11 executes the circuit analysis program 25 in the storage device 13 and performs circuit analysis processing. At this time, various data and programs from the storage device 13 are temporarily stored in the RAM 12, and the CPU 11 executes various processes using the data in the RAM 12.

  The storage device 13 stores a net list 21, a macro library (library 22), an STA condition 23, a hold correction correspondence table 24, a circuit analysis program 25, and layout information 26.

  The netlist 21 includes an element card that describes the connection, type, size (number of elements), etc. of elements constituting the circuit to be analyzed, and non-linear active elements such as diodes and transistors among the elements constituting the circuit. Device parameters and condition information (such as initial values) for controlling the circuit analysis method. The library 22 is library values (element information and connection information) created for macrocells that can be used in the design target circuit. The storage device 13 stores layout information 26 designed in the layout phase. The layout information 26 includes information related to the placement of macro cells in the circuit to be designed, wiring between macro cells, and the like.

  The STA condition 23 is a STA condition for calculating a delay time verified in the STA. Here, the STA condition 23 is a condition that causes a variation in the delay time to be verified, and includes a process condition that considers manufacturing variations and an environmental condition when the analysis target circuit is used. The storage device 13 stores different STA conditions 23 for each technology, and the STA conditions corresponding to the specified technology are used during the STA. FIG. 7 shows an example of the STA condition 23 verified in the present embodiment and the type of the SDF file 27 created under the STA condition. In this embodiment, there are four delay time fluctuation factors, namely, manufacturing variations in the Tr diffusion process (Tr process), manufacturing variations in the wiring diffusion process (wiring process), power supply voltage variations (power supply voltage), and ambient temperature. The STA is executed under eight types of STA conditions 23 in which variations (temperatures) are combined.

  The FAST and SLOW shown in FIG. 7 are the minimum delay time (FAST) and the maximum delay time (SLOW) when the Tr process, wiring process, power supply voltage, and temperature that cause the delay time fluctuate independently. Indicates. For example, the minimum value of the delay time that varies due to manufacturing variations in the wiring diffusion process (for example, wiring width variations) is referred to as a wiring process FAST, and the maximum value is referred to as a wiring process SLOW. Similarly, the minimum value of the delay time that fluctuates due to manufacturing variations in the Tr diffusion process (for example, variations in gate length and ion implantation amount distribution) is referred to as Tr process FAST, and the maximum value is referred to as Tr process SLOW. The minimum value of the delay time corresponding to the fluctuation of the power supply voltage to be used is called the power supply voltage FAST, and the maximum value is called the power supply voltage SLOW. Similarly, the minimum value of the delay time according to the temperature fluctuation around the circuit is referred to as temperature FAST, and the maximum value is referred to as temperature SLOW.

  The hold correction correspondence table 24 is a table for selecting a hold correction method when a hold error occurs. Specifically, the hold correction correspondence table 24 describes a hold correction method corresponding to the STA condition 23 to be verified. The STA condition 23 to be verified and the hold correction method according to the STA condition 23 are different for each technology. For this reason, it is preferable that a different hold correction correspondence table 24 is prepared for each technology. The hold correction correspondence table 24 may be stored in the storage device 13 in advance, or may be created based on information input from the input device 14 at the time of design.

FIG. 8 shows the hold correction correspondence table 24 in the present embodiment. Hold modified correspondence table 24 in the present embodiment, the magnitude relation between the gate delay factor D _G and wiring delay factor D _L corresponding to the type of SDF file 27 is described. A delay time verification unit 252 described later refers to the hold correction correspondence table 24 and selects a hold correction method based on the type of the SDF file 27, that is, the size of the delay coefficient corresponding to the STA condition 23.

  The circuit analysis program 25 is executed by the CPU 11 and executes STA after layout design and layout correction processing for timing correction. The circuit analysis program 25 is executed by the CPU 11 to realize the functions of the delay information generation unit 251, the delay time verification unit 252, and the layout correction unit 253 shown in FIG.

  FIG. 6 is a functional block diagram of the circuit simulation apparatus 10 according to the present invention. Referring to FIG. 6, delay information generation section 251 generates a SDF file 27 that defines delay information of each element or wiring under the STA condition based on layout information 26 after layout design or layout correction. It is a calculation tool. The delay information generation unit 251 extracts the parasitic resistance and parasitic capacitance of each element and wiring of the design target circuit from the layout information 26, and generates the SDF file 27 using these.

  The delay information generation unit 252 calculates the delay time of each element and wiring under the STA condition 23 corresponding to the technology, and stores it in the storage device as the SDF file 27. In the present embodiment, eight types of SDF files 27 shown in FIG. 7 are generated. The number of SDF files 27 (combination of STA conditions) varies depending on the technology of the circuit to be designed. For this reason, the number of SDF files 27 used for the STA and the contents of the STA conditions are not limited to the numbers and contents shown in the present embodiment.

With reference to FIG. 7, the following eight types of files are prepared as the SDF file 27 generated in the present embodiment.
(1) SDF file (MIN.SDF) defining minimum delay time (STA condition 23: all conditions are FAST)
(2) SDF file (MAX.SDF) defining maximum delay time (STA condition 23: all conditions are SLOW)
(3) MIN. SDF file (MIN_HT.SDF) that defines the delay time (STA condition 23: temperature only SLOW) when the temperature fluctuates to the high temperature side with respect to SDF
(4) MIN. SDF file (MIN_LV.SDF) that defines the delay time (STA condition 23: power supply voltage only SLOW) when the voltage fluctuates to the low voltage side with respect to SDF
(5) MIN_HT. SDF file (MIN_HT_SW.SDF) defining a delay time (STA condition 23: Tr process and power supply voltage is FAST, wiring process and temperature is SLOW) when delay is increased by the wiring process with respect to SDF
(6) MAX. SDF file (MAX_LT.SDF) that defines a delay time (STA condition 23: Tr process and power supply voltage are SLOW, wiring process and temperature are FAST) when the temperature fluctuates to the low temperature side with respect to SDF
(7) MAX. SDF file (MAX_HV.SDF) that defines the delay time (STA condition 23: power supply voltage only FAST) when the voltage fluctuates to the high voltage side with respect to SDF
(8) MAX_LT. SDF file (MAX_HT_FW.SDF) defining delay time (STA condition 23: temperature only FAST) when delay is reduced by the wiring process with respect to SDF

  The delay time verification unit 252 calculates the delay time of all paths between two flip-flops connected via the circuit to be verified, and performs setup verification and hold verification for each. The layout correction unit 253 determines a layout correction method based on the verification result in the delay time verification unit 252, and corrects the layout of the circuit to be verified (between flip-flops). At this time, the layout correction unit 254 refers to the hold correction correspondence table 24 corresponding to the technology of the circuit to be designed, and determines a layout correction method.

  The hold correction correspondence table 24 stored in the storage device 13 will be described with reference to FIG. In the present invention, as a hold correction method, a layout correction method for adding a delay cell to a circuit to be verified and a layout correction method for adding a wiring having a length necessary for hold correction are prepared. The correction amount of the delay time by these correction methods varies depending on the STA condition described above. For this reason, the correction amount for each correction method under each STA condition is stored in advance as the hold correspondence table 24. Here, a value obtained by converting the correction amount of the delay time by each correction method into a coefficient is stored in the hold correspondence table 24 as a correction amount for each correction method. The hold correspondence table 24 is used to select a layout correction method that corrects the timing violation most effectively under each STA condition. For this reason, the correction amount stored here may be either the correction amount (absolute value) for each correction method for correcting the timing violation, or the relative value of the correction amount due to the addition of the wiring and the correction amount due to the addition of the delay cell. .

FIG. 8 shows an example of the hold correction correspondence table 24. Here, a hold correction correspondence table is shown in which STA conditions (types of SDF file 27) and delay coefficients obtained by converting the correction amount of the delay time are associated with each other and stored. Specifically, the delay coefficient corresponding to the correction method for adding a delay cell is set as the gate delay coefficient D _G , the delay coefficient corresponding to the correction method by adding the wiring is set as the wiring delay coefficient D _L, and the delay coefficient for each SDF file 27 is Stored. Also, the size of the gate delay factor D _G and wiring delay factor D _L is different for each technology design target circuit, it is preferable to hold modified correspondence table 24 corresponding to each technology is prepared. Incidentally, in FIG. 8, instead of the specific values of the gate delay factor D _G and wiring delay factor D _L, but only both the magnitude relationship is described, specific values may be written.

The STA verification contents (setup verification and hold verification) in the circuit simulation apparatus 10 will be described with reference to FIGS. FIG. 3 is a circuit diagram showing a circuit to be verified. As shown in FIG. 3, in the STA, the circuit to be designed after layout is divided into combination circuits 100 of arbitrary sizes, and the respective delay times are verified. At this time, timing verification between the flip-flops FF1 and FF2 via the combinational circuit 100 is executed. Specifically, the signal D that is output from the flip-flop FF1 and reaches the flip-flop FF2 via the combinational circuit 100 is delayed by the gate and wiring in the combinational circuit 100. In the STA, the circuit simulation device 10 calculates delay times T _d for all paths passing through the combinational circuit 100, and executes setup verification and hold verification for the delay times T _d .

FIG. 4 is a timing chart of the signal D input to the flip-flop FF2, the clock CLK, and the signal Q output from the flip-flop. The setup verification and hold verification in the STA will be described with reference to FIG. The clock cycle input to the flip-flop FF2 T _C, from the rising edge of the signal D, the time until the rising edge of the clock CLK for inputting a signal D (the setup time) and T _S, setup conditions, T _d a _<T C -T _S. In addition, when the hold time _{T h,} hold conditions will be _T d> _{T h.} That is, the circuit simulation apparatus 10, to the desired setup time _{T S} and the hold time _{T h,} the delay time in each path to validate a satisfy _{T h <T d <T C} -T S, not satisfied In this case, timing adjustment is performed by correcting the layout of the analysis target circuit.

2. Operation With reference to FIGS. 5 to 8, the STA operation of the circuit simulation apparatus 10 according to the present invention will be described. FIG. 5 is a flowchart illustrating the STA operation according to the present invention. In the present embodiment, the STA condition 23 shown in FIG. 7 and the hold correction correspondence table 24 shown in FIG. 8 are used.

  With reference to FIGS. 5 and 6, the operation of the STA in this embodiment will be described. First, the delay information generation unit 251 extracts parasitic resistance and parasitic capacitance in each element and wiring in the analysis target circuit after layout design (step S1). Here, the analysis target circuit is a combinational circuit 100 that is divided into an appropriate size by a flip-flop from the design target circuit after layout design. Next, the delay information generation unit 251 calculates a delay time for each element and wiring according to the STA condition 23 and generates the SDF file 27 (step S2). In step S2 at the beginning of the STA, eight types of SDF files 27 corresponding to all the STA conditions 23 are generated.

The delay time verification unit 252 refers to the net list 21 and the library 22 and delays T _d for all paths between flip-flops to be analyzed from the SDF file 27 generated based on the layout information 26 of the circuit to be analyzed. To extract. Further, with respect to the desired setup time T _S, is, whether or setup verification whether the above setup condition is satisfied (Setup Verification: step S4). If a setup violation occurs in the setup verification (No in step S3), the layout correcting unit 253 corrects the layout of the analysis target circuit and updates the layout information 26 (setup correction: step S4) as in the conventional technique.

If the set-up OK in the setup verification (step S3Yes), the delay time verification unit 252, with respect to the desired hold time T _h, the delay time T _d to execute a hold assess whether the above-mentioned hold condition is satisfied (Hold Verification: Step S5). Here, hold verification is performed on the extracted delay time _Td as in step S3. That is, hold verification is performed under the STA condition 23 corresponding to the technology of the analysis target circuit. In the hold verification, if it is determined that the hold violation (step S5No), the delay time verification unit 252, depending on the STA condition 23 when extracting the delay time T _d which is a hold violation, select a correction method of the layout (Step S7). At this time, the delay time verification unit 252 refers to the hold correction correspondence table 23 and corrects based on the magnitude of the delay coefficient corresponding to the SDF file 27 used for extracting the delay time T _d that caused the hold violation. Select.

Delay time verification unit 252 in the present embodiment, with reference to the delay coefficients corresponding to the SDF file 27, if the gate delay factor D _G Wiring delay factor greater than D _L, selecting the timing correction by adding delay cells ( Step S6 No). The wiring delay factor _{D L} is greater than the gate delay factor _{D G,} layout correction unit 254 selects a layout correction method according to additional wiring delay (step S6Yes). The layout correction unit 253 corrects the layout of the analysis target circuit by the layout correction method selected by the delay time verification unit 252 and updates the layout information 26 (step S7 or S8).

In the present embodiment, when the delay time _Td extracted from the SDF file 27 (MIN.SDF, MIN_LV.SDF, MAX_LT_FW.SDF, MAX_LT.SDF, MAX.SDF) is a hold violation, the gate delay coefficient D _G > The wiring delay coefficient _DL is obtained. In this case, the layout correction unit 253 corrects the timing by correcting the layout by adding a delay cell (No in steps S6 and S7). If the delay time _Td extracted from the SDF file 27 (MIN_HT.SDF, MIN_HT_SW.SDF, MAX_HV.SDF) is a hold violation, the wiring delay coefficient D _L > the gate delay coefficient D _G. In this case, the layout correction unit 253 corrects timing by performing layout correction that adds a wiring having a length necessary for hold correction (steps S6 Yes, S8). The values of the gate delay coefficient D _G and the wiring delay coefficient D _L are not limited to the present embodiment because they differ depending on the technology of the circuit to be designed.

  When the layout information 26 is updated in step S4, S7, or S8, the process proceeds to step S1. The delay information generation unit 521 generates an SDF file 27 based on the STA condition 23 in accordance with the updated layout information 26 (step S2), and the delay time verification unit 252 analyzes using the generated SDF file 27. Setup verification and hold verification of the target circuit are executed (steps S3 to S8).

  As described above, the processes in steps S1 to S8 are repeated until the delay time of the paths for all the prepared SDF files satisfies the setup condition and the hold condition (No in step S9). When the setup is OK and the hold is OK under all STA conditions (Yes in step S9), the circuit simulation device 10 fixes the timing of the analysis target circuit (determines the layout) and ends the STA. In addition, STA is similarly performed on all the analysis target circuits of the entire design circuit to determine the layout of the design target circuit. When the layout design is completed, a pattern is formed according to the layout determined in the next step, and a design target circuit is generated.

  The circuit simulation apparatus 10 according to the present invention performs a hold correction by selecting a correction method according to the STA condition from a timing correction method by adding a cell and a timing correction method by adding a wiring. When calculating the delay time in the path, there are cases where the correction amount due to the gate delay is high and the correction amount due to the wiring delay is high depending on the STA condition. Therefore, it is necessary to select a timing correction method for hold violation in consideration of these correction amounts according to the STA conditions. In the present embodiment, when a hold violation occurs under the STA condition where the ambient temperature is high and the power supply voltage is high among the eight STA conditions verified, regardless of the conditions of the Tr process and the wiring process, Hold correction is performed by adding wiring. However, since the relationship between the STA condition and the selection of the correction method is determined by the technology of the circuit to be designed, it is not limited to this.

  As described above, according to the present invention, the delay adjustment is performed by the delay element having the highest correction amount in accordance with the use environment of the circuit to be designed, so that the layout correction suitable for the circuit use state can be performed. In addition, since unnecessary cells are not added, a reduction in circuit area and power consumption can be expected. Furthermore, the hold correction by adding the wiring does not change the setup time greatly compared to the hold correction by adding the delay cell. For this reason, timing can be converged in a short time, and TAT in semiconductor design can be shortened.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. .

FIG. 1 is a block diagram showing the configuration of a circuit simulation apparatus according to the present invention. FIG. 2 is a diagram showing the configuration of a circuit analysis program according to the present invention. FIG. 3 is a block diagram showing an analysis target circuit that is a target of the STA according to the present invention. FIG. 4 is a timing chart for explaining delay times to be subjected to setup verification and bold verification in the STA according to the present invention. FIG. 5 is a flowchart showing the STA operation of the circuit simulation apparatus according to the present invention. FIG. 6 is a functional block diagram showing the configuration of the circuit simulation apparatus according to the present invention. FIG. 7 is a table showing an example of STA conditions verified by the STA according to the present invention and SDF files generated under the conditions. FIG. 8 is a table showing an example of the hold correction correspondence table according to the present invention. FIG. 9 is a flowchart showing the STA operation according to the prior art.

Explanation of symbols

10: Circuit simulation device 11: CPU
12: RAM
13: Storage device 14: Input device 15: Output device 21: Net list 22: Library 23: STA condition 24: Hold correction correspondence table 25: Circuit analysis program 26: Layout information 27: SDF file 251: Delay information generation unit 252: Delay time verification unit 253: layout correction unit 100: combinational circuit (circuit to be analyzed)
FF1, FF2: flip-flop

Claims (21)

A circuit analysis method using a computer,
(A) In the static timing verification for the logic circuit after the layout design, verifying the hold time under a predetermined environmental condition;
(B) If it is determined that the hold has been violated in the step (A), a step of selecting a correction method corresponding to the environmental condition from a plurality of layout correction methods;
(C) correcting the layout of the logic circuit using the selected correction method. The circuit analysis method according to claim 1,
The plurality of layout correction methods include a method of adding a cell including a gate element to the logic circuit and a method of adding a wiring to the logic circuit. In the circuit analysis method according to claim 1 or 2,
According to the technology of the logic circuit, further comprising the step of preparing a table in which the environmental conditions are associated with the plurality of layout correction methods,
When the step (B) is determined to be a hold violation in the step (A),
A circuit analysis method comprising a step of referring to the table according to the technology of the logic circuit to be analyzed and selecting a layout correction method corresponding to the verified environmental condition from the plurality of layout correction methods. The circuit analysis method according to claim 3,
In the table, the environmental condition is described in association with a correction amount of a delay time that varies due to layout correction under the environmental condition.
When the step (B) is determined to be a hold violation in the step (A),
A circuit analysis method comprising a step of referring to the table according to a technology of a logic circuit to be analyzed and selecting a layout correction having a large correction amount as the layout correction method. In the circuit analysis method according to any one of claims 2 to 4,
The step (A) includes (a1) verifying a hold time in the logic circuit under a high voltage condition in which the power supply voltage of the logic circuit is higher than a predetermined voltage as the environmental condition,
The step (B) includes a step of selecting a method of adding the wiring as the layout correction method when the hold violation is determined in the step (a1). The circuit analysis method according to claim 5,
The step (A) includes (a2) a step of verifying a hold time in the logic circuit under a high temperature condition where the ambient temperature of the logic circuit is higher than a predetermined temperature as the environmental condition,
The step (B) includes a step of selecting a method of adding the wiring as the layout correction method when the hold violation is determined in the step (a2). In the circuit analysis method according to claim 5 or 6,
The step (A) includes (a3) verifying a hold time under a low voltage condition lower than a predetermined voltage as the environmental condition,
The step (B) includes a step of selecting a method of adding cells to the logic circuit as a method of correcting the layout when it is determined that a hold violation has occurred in the step (a3). In the circuit analysis method according to any one of claims 1 to 7,
(D) in static timing verification for the logic circuit, verifying setup time under the environmental conditions;
(E) If it is determined in step (D) that the timing is violated, correcting the layout of the logic circuit;
A circuit analysis method further comprising: The circuit analysis method according to claim 8,
In the step (D), when it is determined that there is no timing violation, the circuit analysis method moves to the step (A). A circuit analysis method according to any one of claims 1 to 9,
Forming a pattern of the logic circuit in accordance with a layout of the logic circuit determined to have no timing violation in the circuit analysis method. A circuit analysis program for causing a computer to implement the circuit analysis method according to claim 1. In static timing verification for the logic circuit after layout, a delay time verification unit that calculates a delay time under a predetermined environmental condition and performs hold verification;
When the delay time verification unit determines a hold violation in the hold verification, the correction method according to the environmental condition is selected from a plurality of layout correction methods,
A circuit simulation apparatus comprising: a layout correction unit that corrects a layout of the logic circuit by the correction method selected by the delay time verification unit. The circuit simulation apparatus according to claim 12,
The plurality of layout correction methods include a circuit simulation apparatus including a method of adding a cell including a gate element to the logic circuit and a method of adding a wiring having a predetermined length to the logic circuit. In the circuit simulation device according to claim 12 or 13,
According to the technology of the logic circuit, further comprising a storage device that stores a table in which the environmental conditions are associated with the plurality of layout correction methods,
The delay time verification unit performs the hold verification under the environmental condition, and when there is a hold violation, refers to the table according to the technology of the logic circuit to be analyzed and corrects the layout corresponding to the verified environmental condition. A circuit simulation apparatus for selecting a method from the plurality of layout correction methods. The circuit simulation apparatus according to claim 14,
In the table, the environmental condition is described in association with a correction amount of a delay time that varies due to layout correction under the environmental condition.
The delay time verification unit performs the hold verification under the environmental condition, and when there is a hold violation, the delay time verification unit refers to the table according to the technology of the logic circuit to be analyzed, and performs the layout correction with a large correction amount. Circuit simulation device selected as a correction method. In the circuit simulation device according to any one of claims 12 to 15,
The delay time verification unit performs the hold verification under a high voltage condition where the power supply voltage of the logic circuit is higher than a predetermined voltage as the environmental condition. Circuit simulation device selected as a correction method. The circuit simulation apparatus according to claim 16, wherein
The delay time verification unit executes the hold verification under a high temperature condition where the ambient temperature of the logic circuit is higher than a predetermined temperature as the environmental condition, and selects a method of adding the wiring when the hold violation is found. Circuit simulation device. The circuit simulation device according to claim 16 or 17,
The delay time verification unit performs a hold verification under a low voltage condition lower than a predetermined voltage as the environmental condition, and selects a method of adding a cell to the logic circuit as the correction method when a hold violation occurs. Circuit simulation device. The circuit simulation apparatus according to any one of claims 12 to 18,
The delay time verification unit executes setup verification under the environmental conditions for the logic circuit,
The layout correction unit corrects a layout of the logic circuit when a setup violation occurs in the setup verification. The circuit simulation device according to claim 19,
The delay time verification unit executes the hold verification when determining that there is no timing violation in the setup verification. The circuit simulation device according to any one of claims 12 to 20,
A storage device in which a SDF (Standard Delay Format) file defining a delay time under the environmental conditions and a netlist are stored;
The delay time verification unit calculates a delay time of a signal passing through the logic circuit using the SDF file and the netlist, and executes the static timing verification.

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