JP2006350548A - Creation method, creation program and creation device of timing library - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce time for creating a timing library by reducing frequency of circuit simulation in creation of the timing library of a circuit having many I/O paths. <P>SOLUTION: When a timing library creation device 100 creates a timing library of a 4-bit register circuit, simulation is performed only for a part of 1-bit registers on all operating conditions contained in the timing library, and a timing library is created assuming that the delay value and timing constraint value obtained as a result are also the delay values and timing constraint values of other 1 bit registers. For a part of 1-bit registers to which simulation is performed, simulation is performed at first to four 1-bit registers under some operating conditions out of a plurality of operating conditions contained in the timing library, and the one whose obtained delay value and timing constraint value are the maximum is chosen. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a timing library creation method, creation program, and creation apparatus including delay values, timing constraint values, and the like, which are referred to by an EDA (Electric Design Automation) tool used in the design of a semiconductor integrated circuit.

  When verifying operation timing in LSI (Large Scale Integration) design, the EDA tool refers to a timing library that expresses delay characteristics, timing constraint characteristics, and the like of the cell library. Here, the cell library is a basic logic circuit component prepared in advance to develop a complex circuit. In LSI development that requires a circuit to be realized in a smaller area. For example, a circuit in which a plurality of 1-bit register circuits and the like are connected is formed into a library as one cell. This is because the wiring margin of the upper layer wiring of the cell can be increased and the cell area can be reduced by adjusting the layout in the cell. More specifically, for example, if the 1-bit register circuits are arranged together next to each other and the sources and drains of the transistors in the 1-bit register circuit are made common, it is more preferable than connecting a cell library of 1-bit registers. A multi-bit register circuit can be realized with a small area. In an LSI in which a plurality of bit register circuits having the same number of bits are frequently used, realizing the plurality of bit register circuits as a library is particularly effective for reducing the circuit area.

The delay characteristics and timing constraint characteristics of the cell library expressed in the timing library are obtained by simulating various patterns combining conditions such as various input signal states, input signal transition times, and output load capacities. Desired. In addition, the delay characteristics and timing constraint characteristics of a cell having a plurality of input / output paths can be obtained for each input / output path by simulating a pattern that combines ON / OFF and rising / falling of the input signal. Is required. Therefore, when the number of input / output paths of the cell library is increased, such as when a large number of 1-bit registers are made into a library, the number of simulations becomes enormous. In view of this, a technique has been proposed in which the number of simulations is reduced by reducing the number of patterns that combine ON / OFF of input signals when obtaining delay values and timing constraint values (see, for example, Patent Document 1). .
JP-A-7-311791

  However, since the delay value and timing constraint value change depending on conditions such as the transition time of the input signal and the output load capacity, it is necessary to obtain the delay value and timing constraint value according to the conditions such as the transition time of the input signal and the output load capacity. There is. Therefore, even if the number of patterns combining ON / OFF and rising / falling of the input signal is reduced, all the combinations of conditions such as the transition time of the input signal and the output load capacity for each pattern of the input signal are combined. When the simulation is performed on the pattern, the number of circuit simulations is enormous, and there is a problem that the execution time of the circuit simulation becomes long. Further, for example, a timing constraint value that cannot be obtained by one simulation, such as a setup time of a flip-flop circuit, is obtained by using a binary search algorithm that repeatedly sets a predicted value of the timing constraint value and performs the simulation. For this reason, the number of simulations was particularly enormous.

  An object of the present invention is to reduce the number of circuit simulations and to significantly reduce the time required to create a timing library in view of the above points.

In order to solve the above problems, the invention of claim 1
A method for creating a timing library including respective timing characteristic values under a plurality of operating conditions for a plurality of input / output signal paths in a logic circuit of a semiconductor integrated circuit,
For all of the plurality of input / output signal paths, a circuit operation simulation is performed under some of the plurality of operation conditions, and timing characteristic values for the respective input / output paths under the respective operation conditions are obtained. A first timing characteristic value acquisition step;
A selection step of selecting a representative input / output signal path based on the timing characteristic value;
A second timing characteristic value acquisition step for obtaining a timing characteristic value under each operating condition by performing a simulation of circuit operation under an operating condition different from the part of the operating conditions for the representative input / output signal path;
Timing library creation processing step of creating a timing library using the timing characteristic value obtained for the representative input / output signal path as a characteristic value for another input / output signal path;
It is characterized by having.

  As a result, the timing library is created using the timing characteristic value of the representative input / output signal path as the timing characteristic value of the other input / output signal path. The side characteristic value etc. can be obtained with a small number of circuit simulations, and a timing library can be created in a short time.

The invention of claim 2
A method of creating a timing library according to claim 1,
The input / output signal path is a signal path corresponding to a combination of each input signal and output signal in the multi-bit register circuit.

  As a result, since the multi-bit register circuit has little variation in timing characteristic values such as delay values and timing constraint values of each 1-bit register, the number of circuit simulation patterns can be easily reduced while maintaining the accuracy of the timing characteristic values. .

The invention of claim 3
A method of creating a timing library according to claim 1,
The timing characteristic value is a delay value between input and output signals.

  As a result, the number of circuit simulation patterns necessary for obtaining the delay value can be reduced.

The invention of claim 4
A method of creating a timing library according to claim 3,
In the selecting step, at least one input / output signal path having the maximum or minimum delay value obtained in the first timing characteristic value acquiring step is selected as a representative input / output signal path.

  As a result, the timing library is created using the delay value of the input / output signal path with the largest delay value and the input / output signal path with the smallest delay value as the delay value of the other input / output signal paths. It can be obtained with a small number of circuit simulations.

The invention of claim 5
A method of creating a timing library according to claim 1,
The timing characteristic value is a timing constraint value to be satisfied by transition timings of a plurality of input signals.

  Thereby, the number of circuit simulation patterns necessary for obtaining the timing constraint value can be reduced. In particular, since the timing constraint value is obtained using a binary search algorithm or the like that repeatedly sets the prediction value of the timing constraint value and performs simulation, the effect of reducing the simulation pattern is great.

The invention of claim 6
A method for creating a timing library according to claim 5, comprising:
In the selection step, the input / output signal path having the maximum timing constraint value obtained in the first timing characteristic value acquisition step is selected as the representative input / output signal path.

  As a result, a timing library is created with the timing constraint value of the input / output signal path having the largest timing constraint value for the predetermined clock as the timing constraint value of the other input / output signal path, so the timing constraint value on the safe side Can be obtained with a small number of circuit simulations while maintaining a constant accuracy.

The invention of claim 7
A method of creating a timing library according to claim 1,
The operating condition is characterized in that it is a plurality of operating conditions for at least one of a power supply voltage, an input voltage transition time, an output load capacity, and a temperature.

  As a result, the number of simulation patterns for obtaining timing characteristic values under various operating conditions in which at least one of power supply voltage, input voltage transition time, output load capacity, or temperature is different can be reduced.

The invention of claim 10 provides
A method of creating a timing library including timing characteristic values according to characteristics of input signals in a logic circuit of a semiconductor integrated circuit,
A first characteristic value acquisition step of obtaining a characteristic of an output signal according to an input signal having a predetermined characteristic in a first partial logic circuit constituting the logic circuit by performing a simulation of a circuit operation;
A partial logic circuit timing library showing a timing characteristic value corresponding to the characteristic of the input signal for the second partial logic circuit to which the output signal of the first partial logic circuit is input, and the first characteristic value acquisition step Based on the obtained characteristic of the output signal of the first partial logic circuit input to the second partial logic circuit, the timing characteristic value for the second partial logic circuit is obtained, thereby obtaining the logic circuit. A second characteristic value obtaining step for obtaining a timing characteristic value for the logic circuit according to the characteristic of the input signal;
It is characterized by having.

  As a result, the timing constraint value of the entire logic circuit can be obtained with a small number of simulations and a short simulation time by using a timing library prepared in advance for the partial logic circuit.

The invention of claim 11
A method for creating a timing library according to claim 10, comprising:
The second partial logic circuit has an output signal as an output signal of the logic circuit,
The partial logic circuit timing library shows the relationship between the voltage transition time of the input signal and the delay value between the input / output terminals or the voltage transition time of the output signal in the second partial logic circuit,
The characteristic of the output signal of the first partial logic circuit obtained in the first characteristic value acquisition step is a voltage transition time of the output signal corresponding to the input signal having a predetermined voltage transition time,
In the second characteristic value calculation step, the delay value between the input / output terminals of the logic circuit and the output are obtained by obtaining the delay value between the input / output terminals in the second partial logic circuit or the voltage transition time of the output signal. It is characterized in that at least one of signal voltage transition times is obtained.

  Thus, when creating a timing library including delay values between input / output terminals and output signal voltage transition times under a plurality of conditions with different output loads, only the first partial logic circuit with a constant output load is simulated. Therefore, a timing library can be created with a small number of simulations.

The invention of claim 12
A method for creating a timing library according to claim 10, comprising:
The input signal to the first partial logic circuit is an input signal to the logic circuit,
The second partial logic circuit receives at least a plurality of input signals including an output signal of the first partial logic circuit,
The partial logic circuit timing library shows a relationship between voltage transition times of the plurality of input signals in the second partial logic circuit and timing constraint values that the voltage transition timings of the plurality of input signals should satisfy. And
The characteristic of the output signal of the first partial logic circuit obtained in the first characteristic value acquisition step is a voltage transition time of the output signal corresponding to the input signal having a predetermined voltage transition time,
The second characteristic value calculating step calculates a timing constraint value for the logic circuit by determining a timing constraint value that the voltage transition timings of the plurality of input signals in the second partial logic circuit should satisfy. Features.

  As a result, the timing constraint value of a plurality of input signals such as a register circuit depends on the voltage transition time of the input signal. Therefore, the number of simulations can be reduced by using the second partial logic circuit timing library prepared in advance. Thus, timing constraint values for a plurality of input signals are obtained. Therefore, since it is not necessary to perform a binary search algorithm or the like that repeatedly sets the prediction value of the timing constraint value and the simulation for the entire logic circuit, the effect of reducing the simulation pattern is great.

  According to the present invention, the number of circuit simulations can be reduced, and the time required for creating a timing library can be greatly reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, components having functions similar to those of the other embodiments are denoted by the same reference numerals and description thereof is omitted.

Embodiment 1 of the Invention
As a first embodiment of the present invention, a timing library creating apparatus 100 as shown in FIG. 1 and an example in which a timing library 1008 of a 4-bit register circuit is created by this will be described in detail with reference to the drawings. The timing library creation device 100 is not particularly limited, but can be configured by incorporating a program that causes a computer to execute the functions of the timing library creation device 100 described below, for example.

  For example, as shown in FIG. 2, the timing library 1008 includes delay values 203 corresponding to combinations of various voltage transition times 201 of clock signals and various output load capacitance values 202, and as shown in FIG. A timing constraint value 303 corresponding to a combination of various voltage transition times 301 of the clock signal and various voltage transition times 302 of the data input signal is shown.

  The timing library creating apparatus 100 performs a simulation for all of the operating conditions corresponding to the delay values and timing constraint values that should be included in the timing library only for some 1-bit registers, and the delay values obtained as a result thereof The timing library is created assuming that the timing constraint value is also the delay value and timing constraint value of another 1-bit register. In order to select a part of the 1-bit registers for which the simulation is performed, first, a part of a plurality of operating conditions of delay values and timing constraint values to be included in the timing library for the four 1-bit registers is selected. Simulation is performed under operating conditions (conditions for selection). Then, the one having the maximum obtained delay value or timing constraint value is selected (determined). The timing verification is performed using the delay value and timing constraint value of the 1-bit register having the maximum delay value and timing constraint value as the delay value and timing constraint value of all 1-bit registers. This is because the timing is satisfied.

(Device configuration)
More specifically, the timing library creating apparatus 100 controls a circuit simulator 102 and outputs a timing library 1008, for example, as shown in FIG. 1, for example, and simulates circuit operation such as SPICE (Simulation). A circuit simulator 102 such as Program with Integrated Circuit Emphasis is provided.

  The simulator control apparatus 101 transfers data used for simulation to the circuit simulator 102, instructs execution of the simulation, and controls timing constraint value calculation by delay value calculation or binary search algorithm. Further, among all the 1-bit registers, a process of selecting a 1-bit register having the maximum delay value and timing constraint value in the simulation result under the selection condition is performed.

  The circuit simulator 102 performs a simulation based on input of data related to simulation conditions, input signal patterns, and the like, and outputs a simulation result.

(Data input to the timing library creation device 100)
Examples of data input to the timing library creation apparatus 100 include the following.

(1) Maximum delay value register selection condition data 1001
FIG. 4 shows an example of maximum delay value register selection condition data 1001. This data shows two conditions, one for the power supply voltage and one for the temperature, two for the clock signal transition time of 50 ps and 2 ns, and two for the output load capacitance value of 1 fF and 100 fF. Based on this data, for the four 1-bit registers, there are two combinations of the clock signal transition time of 50 ps and 2 ns, and the output load capacitance value of 2 types of 1 fF and 100 fF, a total of 2 × 2 combinations. Simulation is performed. Based on these four simulation results, the register having the maximum delay value is selected for each combination condition.

(2) Delay signal extraction simulation signal pattern 1002
FIG. 5 shows an example of a delay value extraction simulation signal pattern 1002. For example, when the delay value is different between when the data output signal rises and when it falls, the delay value needs to be obtained separately for each case. The delay value extraction simulation signal pattern 1002 indicates a signal pattern whose delay value should be obtained. R shown in the figure indicates that the signal changes from 0 to 1. R, 0 in the upper stage means that the data output signal changes to 0 due to the rising edge of the clock, and R, 1 means that the data output signal changes to 1 due to the rising edge of the clock. ing. Based on this data, a simulation for determining the delay value for the above two cases is performed.

(3) Delay value extraction condition data 1003 for timing library creation
FIG. 6 shows an example of the delay value extraction condition data 1003 for creating the timing library. This data shows all the operating conditions of the delay values to be included in the timing library. Specifically, in the example of the figure, there are seven operating conditions in which the clock signal transition time is 50 ps to 2 ns and the output load capacitance value is 1 fF to 100 fF. FIG. 2 shows an example of delay values corresponding to 9 × 3 conditions, but in the following, it is assumed that delay values corresponding to 63 × 7 conditions as shown in FIG. 6 are obtained. explain.

(4) Maximum timing constraint value register selection condition data 1004
Similar to the data for obtaining the delay value, FIG. 7 shows an example of the maximum timing constraint value register selection condition data 1004. This data shows two conditions of a data input signal transition time of 50 ps and 2 ns and a clock signal transition time of 50 ps and 2 ns. Based on this data, four 1-bit registers have two combinations of data input signal transition times of 50 ps and 2 ns and two combinations of clock signal transition times of 50 ps and 2 ns. A simulation is performed. Based on these four simulation results, a register having the maximum timing constraint value is selected for each combination condition.

(5) Timing constraint value extraction simulation signal pattern 1005
FIG. 8 shows an example of a simulation signal pattern 1005 for extracting timing constraint values. For example, when the timing constraint value differs between when the data input signal rises and when it falls, the timing constraint value needs to be obtained separately for each case. The timing constraint value extraction simulation signal pattern 1005 indicates a signal pattern for which those timing constraint values should be obtained. In the figure, R indicates that the signal changes from 0 to 1, and F indicates that the signal changes from 1 to 0. The upper stage has R and R when the data input signal rises, and the timing constraint value when the rise is output by the rise of the clock signal. The lower stage has R and F when the data input signal falls. In this case, it means that a simulation should be performed in order to obtain respective timing constraint values when the falling edge is output by the rising edge of the clock.

(6) Timing constraint value extraction condition data 1006 for creating a timing library
FIG. 9 shows an example of timing constraint value extraction condition data 1006 for creating a timing library. This data indicates all the operating conditions of the timing constraint values to be included in the timing library. Specifically, in the example of FIG. 5, five operating conditions are shown in which the data input signal transition time ranges from 50 ps to 2 ns, and the clock signal transition time ranges from 50 ps to 2 ns. FIG. 3 shows an example of timing constraint values corresponding to 9 conditions of 3 × 3. In the following, timing constraint values corresponding to 25 conditions of 5 × 5 as shown in FIG. 9 are obtained. It will be explained as a thing.

(7) Subcircuit data 1007
The subcircuit data 1007 is obtained by modeling a simulation target circuit. For example, the circuit simulator interprets information such as transistor size, wiring RC (Resistance Capacitance) and wiring resistance in the target circuit, and connection information thereof. It is shown as possible. The detailed description of the sub-circuit data 1007 is described in “STAR-Hspice Manual Release v. 2000.2 Japanese version publisher Avant”, but the description is omitted because it is not directly related to the invention. .

(Timing library creation target circuit)
Next, the configuration of the 4-bit register circuit 400, which is a target for creating a timing library in the present embodiment, will be described with reference to FIG. The 4-bit register circuit 400 includes four 1-bit registers, a first register 404, a second register 405, a third register 406, and a fourth register 407, each having a data input pin 401, a clock pin 402, and a data output pin 403. It is configured. Here, an example in which an edge-triggered 1-bit flip-flop cell is used as a 1-bit register is shown, but a flip-flop cell or a latch cell having a storage function may be used.

  FIG. 11 is a timing chart showing the operation of the 1-bit register constituting the 4-bit register circuit 400. In the figure, for simplicity of explanation, it is shown that there is no signal waveform dullness. The 1-bit register stores a data input signal at the rising edge of the clock signal and outputs the stored signal as a data output signal.

(About delay values and timing constraint values)
FIG. 12 is a timing chart showing the delay value of the 1-bit register. Here, the delay value is defined by the time difference from when the clock signal rises to the threshold voltage until the data output signal changes to the threshold voltage.

  FIG. 13 is a timing chart showing the setup time and hold time of the timing constraint value of the 1-bit register. The setup time refers to the time that the level of the data input signal must be maintained before the rising edge of the clock signal, and the hold time refers to the time that the level of the data input signal must be maintained after the rising edge of the clock signal. . If the setup time and hold time are satisfied, the expected data output signal is output as shown in the time chart of FIG. 13, but if not satisfied, the expected data output signal is not output and a malfunction occurs.

  FIG. 14 is a timing chart showing an operation simulated at each step of the method for calculating the timing constraint value using the binary search algorithm used in this embodiment. In this algorithm, the simulation is performed while the solution search range is narrowed until the solution (timing constraint value) search range becomes a value equal to or higher than the specified accuracy, and the timing constraint value is calculated. For example, in the example shown in the figure, when a simulation is performed in which the rising time of the clock signal is fixed every time and a data input signal is raised at STEP 0 in STEP 1, the data output signal is determined and stored in the storage element. It is confirmed that In STEP 2, when a simulation for raising the data input signal at the time of Tend is performed, it is confirmed that the data output signal becomes indefinite and is not stored in the storage element. From STEP1 and STEP2, it can be seen that the timing constraint value to be found is within the solution search range. Next, in STEP 3, a simulation for starting up the data input signal at time Tmid is performed, and it is confirmed whether the data output signal is fixed or indefinite. Here, Tmid indicates a time of (0 + Tend) / 2. If it is determined, the timing constraint value to be obtained exists between Tmid and Tend, and a simulation for raising the data input signal at the time of (Tmid + Tend) / 2 is performed next. If it becomes indefinite, the timing constraint value to be obtained exists between 0 and Tmid, and a simulation for raising the data input signal at the time of Tmid / 2 is performed next. The above steps are repeated until the solution search range reaches a value greater than or equal to the specified accuracy, and a timing constraint value is calculated.

(Operation of Timing Library Creation Device 100)
Hereinafter, the operation of the timing library creating apparatus 100 will be described with reference to FIG.

  (S101) First, simulation is performed by the circuit simulator 102 based on the maximum delay value register selection condition data 1001 and the delay value extraction simulation signal pattern 1002, and the delay value 1101 of each 1-bit register of the 4-bit register circuit 400. Is calculated. (First Timing Characteristic Value Acquisition Step)

  (S102) The simulator controller 101 compares the delay value 1101 of each 1-bit register, and 1 bit having the maximum delay value for each of the four combinations indicated by the maximum delay value register selection condition data 1001 Information indicating which register is the register is stored as maximum delay value register information 1102. Further, such information is obtained and stored for each signal pattern shown in the delay value extraction simulation signal pattern 1002. For example, with respect to the 4-bit register circuit 400, when the data output signal rises, when the first register 404 has the maximum delay value, the information indicating the first register 404 for extracting the delay value at the rise time is the maximum delay value register. Information is stored as information 1102. When the data output signal falls, if either the second register 405 or the third register 406 has the maximum delay value, information indicating the second register 405 and the third register 406 is used for extracting the delay value at the time of falling. Stored as maximum delay value register information 1102. Here, as the maximum delay value register information 1102, for example, information indicating the position of each 1-bit register is used. (Selection step)

  (S103) Based on the maximum delay value register information 1102, the delay value extraction simulation signal pattern 1002, and the timing library creation delay value extraction condition data 1003, the circuit simulator 102 performs a simulation. However, the simulation does not have to be performed for the conditions already simulated in (S101) among the conditions indicated in the delay value extraction condition data 1003 for timing library creation. When the delay value at the rising edge of the data output signal is obtained, a simulation is executed only for the first register 404, and the values calculated thereby are stored in the second register 405, the third register 406, and the fourth register 407. Stored as a delay value. When obtaining the delay value at the time of falling, a simulation is executed for the second register 405 and the third register 406, and the larger one of the delay values of the second register 405 and the third register 406 is the first value. Stored as delay values of the register 404 and the fourth register 407. As a result, the delay values for all 63 types of conditions specified in the delay value extraction condition data 1003 for timing library creation are stored as delay value information 1103 for all simulation conditions of all 1-bit registers of the 4-bit register circuit 400. The (Second timing characteristic value acquisition step)

  (S104) Next, simulation is performed by the circuit simulator 102 based on the maximum timing constraint value register selection condition data 1004 and the timing constraint value extraction simulation signal pattern 1005, and each 1-bit register of the 4-bit register circuit 400 is simulated. A timing constraint value 1104 is calculated. In this embodiment, a binary search algorithm is used to calculate the timing constraint value. At this time, the simulator control apparatus 101 controls the timing at which the input signal changes in the simulation. (First Timing Characteristic Value Acquisition Step)

  (S105) The simulator controller 101 causes the timing constraint value 1104 of each 1-bit register to have the maximum timing constraint value for the four combinations of conditions indicated by the maximum timing constraint value register selection condition data 1004. Information indicating which register is the bit register is stored as maximum timing constraint value register information 1105. Such information is stored for the setup time and hold time, respectively, when the data input signal rises and falls. For example, when the data input signal rises and falls with respect to the 4-bit register circuit 400, if the first register 404 has the maximum setup time, the setup time extraction at the rise and the setup time extraction at the fall Information indicating the first register 404 is stored as maximum timing constraint value register information 1105 for use. When the data input signal rises, assuming that the second register 405 has the maximum hold time, information indicating the second register 405 is extracted as the maximum timing constraint value register information 1105 for extracting the rise time hold time. When the data input signal falls, assuming that either the second register 405 or the third register 406 has the maximum hold time, the second register 405 and the third register 406 are shown for extracting the hold time at the fall. The information is stored as maximum timing constraint value register information 1105. Here, as the maximum timing constraint value register information 1105, for example, information indicating the position of each 1-bit register is used. (Selection step)

  (S106) The circuit simulator 102 performs simulation using the maximum timing constraint value register information 1105, the timing constraint value extraction simulation signal pattern 1005, and the timing library creation timing constraint value extraction condition data 1006. However, the simulation need not be performed for the conditions already simulated in (S104) among the conditions indicated in the timing constraint creation timing constraint value extraction condition data 1006. When obtaining the setup time at the rising edge of the data input signal, the simulation is executed only for the first register 404, and the value calculated thereby is stored as the setup time at the rising edge of the four 1-bit registers. When obtaining the setup time when the data input signal falls, circuit simulation is executed only for the first register 404, and the value calculated here is stored as the setup time when the four 1-bit registers fall. . When obtaining the rising hold time of the input signal, the simulation is executed only for the second register 405, and the calculated value is stored as the rising hold time of the four 1-bit registers. When determining the hold time at the time of falling of the data input signal, simulation is executed for the second register 405 and the third register 406, and the simulation results are stored in the second register 405 and the third register 406, respectively. For the first register 404 and the fourth register 407, the value with the larger hold time of the second register 405 or the third register 406 is stored. As a result, the maximum timing constraint value in all 25 types of conditions specified by the timing constraint creation timing constraint value extraction condition data 1006 is the timing constraint value for all simulation conditions of all 1-bit registers of the 4-bit register circuit 400. It is stored as information 1106. (Second timing characteristic value acquisition step)

(S107)
Finally, the simulator control apparatus 101 adds the desired EDA tool library format (timing library format) to the delay value information 1103 for all simulation conditions of all 1-bit registers and the timing constraint value information 1106 for all simulation conditions of all 1-bit registers. The timing library 1008 of the 4-bit register circuit 400 is generated. (Timing library creation processing step)

(About the effect of reducing the number of simulations for delay value extraction according to this embodiment)
As described above, the simulation is performed using the maximum delay value register selection condition data 1001 for four of the 63 conditions, and the number of combinations of the conditions is only for the 1-bit register circuit having the maximum delay value. Performs a simulation using 63 types of timing library creation delay value extraction condition data 1003, and substitutes the result with another 1-bit register, thereby creating timing library creation delays for all four 1-bit register circuits. The number of simulations can be greatly reduced and the simulation time can be shortened compared with the case where simulation is performed using the value extraction condition data 1003.

  Specifically, first, the four combinations shown in the maximum delay value register selection condition data 1001 in (S101) are simulated for four 1-bit registers, so 4 × 4 16 simulations are performed. Is performed for the rising change time and the falling change time shown in the simulation signal pattern 1002 for delay value extraction. Next, in (S103), among the 63 types of combinations shown in the timing library creation delay value extraction condition data 1003, four types of combinations have already been simulated in (S101). The first combination 404 selected to have the maximum rising delay value in step S102, the second register 405 selected to have the maximum falling delay value, and the third register This is done for the register 406. Therefore, the number of simulations for extracting the delay value in the present embodiment is 75 times of 16 + 59 for obtaining the delay value at the rising time, and 134 times of 16 + 59 × 2 for obtaining the delay value at the falling time, for a total of 209. Times. For all four 1-bit register circuits, when the simulation is performed using the delay value extraction condition data 1003 for creating timing libraries having 63 combinations of conditions, the number of simulations is the delay value at the rise time and the delay at the fall time. Since 4 × 63 252 times are required to obtain each value, the total is 504 times. Therefore, according to the present embodiment, the number of simulations can be reduced to 42% for all four 1-bit register circuits, compared to the case where the simulation is performed using the delay value extraction condition data 1003 for creating the timing library. .

(About the effect of reducing the number of simulations for extracting timing constraint values according to the present embodiment)
Furthermore, as described above, the simulation is performed using the maximum timing constraint value register selection condition data 1004 for four types of 25 conditions, and only for the 1-bit register circuit having the maximum timing constraint value, By performing simulation using timing constraint creation timing constraint value extraction condition data 1006 having 25 types of condition combinations, timing library creation timing constraint value extraction condition data 1006 is obtained for all four 1-bit register circuits. The number of simulations can be greatly reduced and the simulation time can be shortened compared to the case where the simulation is performed. In particular, the timing constraint values such as the setup time and the hold time are obtained by using a binary search algorithm or the like that repeatedly sets the predicted value of the timing constraint value and performs the simulation, so that the effect of reducing the number of simulations is great.

  Specifically, simulations of the four types of combinations indicated in the maximum timing constraint value register selection condition data 1004 in (S104) are shown in the timing constraint value extraction simulation signal pattern 1005 for four 1-bit registers. This is performed to extract the setup time and hold time when the data input signal rises and falls. Since the timing constraint value is calculated using a binary search algorithm, if the number of simulations performed by the binary search algorithm is N, the number of simulations in (S104) is 4 × 4 × 2 × 2 × N. A total of 64N times. Next, in (S106), among the 25 types of combinations shown in the timing library creation timing constraint value extraction condition data 1006, four types of combinations have already been simulated in (S104). The remaining 21 types of combinations are simulated. The simulation is performed for the first register 404 for the setup time at the rise change and the fall change, and for the second register 405 for the hold time at the rise change, and is held at the fall change. Time is performed for the second register 405 and the third register 406. Therefore, the number of simulations for extracting the timing constraint value in this embodiment is 64N + (21 + 21 + 21 + 21 × 2) × N, which is 169N times in total. For all four 1-bit register circuits, the number of simulations in the case of performing a simulation using the timing constraint creation timing constraint value extraction condition data 1006 for which there are 25 combinations of conditions is the rise change time and the fall change time. Therefore, since it is necessary to simulate both the setup time and the hold time, 4 × 25 × 2 × 2 × N total 400N times. Therefore, according to the present embodiment, the number of simulations can be reduced to 42% for all four 1-bit register circuits, compared with the case where the simulation is performed using the timing constraint creation timing constraint value extraction condition data 1006. Become.

(Other)
In this embodiment, the maximum delay value is obtained. However, when obtaining the minimum delay value, information indicating the register having the minimum delay value is replaced with the maximum delay value register information 1102 in (S102). Is stored in the memory.

  In this embodiment, the delay value and the timing constraint value are obtained for the conditions in which only the clock signal transition time, the data input signal transition time, and the output load capacitance value are changed. However, the power supply voltage, temperature, etc. are changed. The present invention can be applied even when the conditions are determined.

  In addition, the timing library creating apparatus 100 of the present embodiment includes the circuit simulator 102, but it may be configured only by the simulator control apparatus 101 and use an external circuit simulator.

  Further, the obtained characteristic value (timing characteristic value) is not limited to the delay value and the timing constraint value, and may be one of them, or other characteristic values used for verifying the operation timing, or various combinations thereof. Furthermore, the target circuit is an example, and the present invention can be applied to a circuit in which combinational logic circuits such as an AND circuit and an OR circuit are combined.

<< Embodiment 2 of the Invention >>
As a second embodiment of the present invention, a timing library creating apparatus 500 as shown in FIG. 16 and an example in which a timing library 2005 of a 4-bit register circuit (logic circuit) is created will be described in detail based on the drawings. . The timing library creation device 500 is not particularly limited, but can be configured by incorporating a program that causes a computer to execute the functions of the timing library creation device 500 described below, for example.

  The timing library creation apparatus 500 performs a simulation with a certain output load capacity and a plurality of input voltage transition times as operating conditions, and measures the voltage transition time of each 1-bit register input terminal at each voltage transition time. Then, interpolation is performed based on the timing library 2002 of the 1-bit register prepared in advance and the measured voltage transition time, and the delay value and the timing constraint value in each 1-bit register constituting the 4-bit register circuit are calculated. ing.

  For example, as shown in FIG. 16, the simulator control apparatus 501 controls the circuit simulator 102 and calculates delay values and timing constraint values in each 1-bit register based on input data. The timing library 2005 is output.

(Data input to the timing library creation device 500)
Examples of input data include the following.

(1) Timing library creation condition data 2001
FIG. 17 shows an example of timing library creation condition data 2001. This shows all operating conditions for each of the delay values and timing constraint values to be included in the timing library.

(2) 1-bit register timing library 2002
The 1-bit register timing library 2002 shows timing characteristic values when each 1-bit register constituting the 4-bit register circuit operates independently. For example, as shown in FIG. The delay value 603 corresponding to the combination of the transition time 601 and various output load capacitance values 602, and as shown in FIG. 19, various voltage transition times 701 of the clock signal and various voltage transition times 702 of the data input signal The timing constraint value 703 corresponding to the combination is shown.

(3) Voltage transition time observation simulation signal pattern 2003
The voltage transition time observation simulation signal pattern 2003 is a simulation signal pattern for measuring the voltage transition time of the input terminal of each 1-bit register, and the specific content is the delay described in the first embodiment (FIG. 5). This is the same as the value extraction simulation signal pattern 1002.

(4) Sub-circuit data 2004 of a 4-bit register circuit
The sub-circuit data 2004 of the 4-bit register circuit is a model of the 4-bit register circuit that is the target of creating the timing library, similarly to the sub-circuit data 1007 described in the first embodiment.

(Timing library creation target circuit)
Next, the configuration of the 4-bit register circuit 800, which is a target for creating a timing library in the present embodiment, will be described with reference to FIG. The 4-bit register circuit 800 includes an input voltage measurement node 801 (input to the logic circuit), a first voltage measurement node 802, a second voltage measurement node 803, a third voltage measurement node 804, and a fourth voltage measurement node 805 (first). 2 input to the partial logic circuit). Here, an example in which an edge-triggered 1-bit flip-flop cell is used as a 1-bit register constituting the 4-bit register circuit 800 is shown, but a flip-flop cell or a latch cell having a storage function may be used.

(Operation of Timing Library Creation Device 500)
Hereinafter, the operation of the timing library creating apparatus 500 will be described with reference to FIG.

  (S201) First, a node for measuring the voltage transition time of the clock signal of each 1-bit register is extracted as an output pin for voltage measurement by the simulator control apparatus 501 based on the sub-circuit data 2004 of the 4-bit register circuit. It is given to the subcircuit data 2004 of the 4-bit register circuit. The node to be measured is extracted by searching the subcircuit file. As a result, the subcircuit data 2101 with voltage measurement node of the 4-bit register circuit 800 is created. By using the subcircuit data 2101 with voltage measurement node, the voltage transition time at the voltage measurement node of each 1-bit register can be observed by simulation.

  (S202) Simulation is performed by the circuit simulator 102 using the voltage measurement node-attached sub-circuit data 2101, timing library creation condition data 2001, and voltage transition time observation simulation signal pattern 2003, and voltage measurement of each 1-bit register is performed. The transition time of the voltage input to the node is calculated. The calculated transition time is stored as voltage transition time information 2102 at the voltage measurement node of each 1-bit register. FIG. 22 shows an example in which the contents of the voltage transition time information 2102 at the voltage measurement node of each 1-bit register are tabulated. In the example of FIG. 22, when a voltage having a voltage transition time of 50 ps is input to the input voltage measurement node 801 of the 4-bit register circuit 800, the first voltage measurement node 802 serving as the clock signal input point of each 1-bit register, The two voltage measurement node 803, the third voltage measurement node 804, and the fourth voltage measurement node 805 show voltage waveforms having voltage transition times of 65 ps, 65.2 ps, 72 ps, and 74 ps, respectively. This simulation is performed for the number of types of clock transition times indicated in the timing library creation condition data 2001. That is, in the example of FIG. 22, voltages having seven transition times of 50 ps, 0.1 ns, 0.2 ns, 0.3 ns, 1 ns, 1.5 ns, and 2 ns are input to the input voltage measurement node 801. Simulations will be performed. (First characteristic value acquisition step)

  (S203) The simulator controller 501 interpolates the values included in the timing library 2002 of the 1-bit register using the voltage transition time information 2102 and the timing library creation condition data 2001 at the voltage measurement node of each 1-bit register. Thus, the delay value and the timing constraint value of each 1-bit register are obtained. (Second characteristic value acquisition step) Then, the delay value and the timing constraint value are converted into a library format of a desired EDA tool, and a timing library 2005 of a 4-bit register circuit is generated.

  Next, the interpolation method in (S203) will be described.

  First, a method for calculating the delay value will be described. As an example, when the transition time of the voltage input to the input voltage measurement node 801 is 50 ps and the output load capacitance value is 1 fF, the first voltage measurement node 802 constituting the 4-bit register circuit 800 is used as one bit. A method for calculating the delay value of the register will be described. In the voltage transition time information 2102 at the voltage measurement node of each 1-bit register in FIG. 22, when the voltage transition time of the input voltage measurement node 801 is 50 ps, the voltage transition time of the first voltage measurement node 802 is 65 ps. In the two-dimensional table of FIG. 18 relating to the 1-bit register timing library 2002, when the output load capacitance value is 1 fF, the delay value is 30 ps if the voltage transition time of the clock signal is 50 ps, and the delay value is 40 ps if it is 0.1 ns. It is. Accordingly, the delay value when the voltage transition time of the first voltage measurement node 802 is 65 ps is 33 ps, for example, obtained by linear interpolation shown in FIG. Similarly, when the transition time of the voltage input to the input voltage measurement node 801 is 0.1 ns, the first voltage measurement node 802 is obtained when the voltage transition time of the input voltage measurement node 801 is 0.1 ns from FIG. 18 is 0.15 ns, the delay value is 40 ps if the voltage transition time of the clock signal is 0.1 ns, and the delay value is 50 ps if it is 0.2 ns. The value is 45 ps.

  Next, a timing constraint value calculation method will be described. As an example, the first voltage measurement node 802 constituting the 4-bit register circuit 800 when the transition time of the voltage input to the input voltage measurement node 801 is 50 ps and the transition time of the data input signal is 50 ps is used as an input terminal. A method for calculating the timing constraint value of the 1-bit register will be described. In the voltage transition time information 2102 at the voltage measurement node of each 1-bit register in FIG. 22, when the voltage transition time of the input voltage measurement node 801 is 50 ps, the voltage transition time of the first voltage measurement node 802 is 65 ps. In the two-dimensional table of FIG. 19 relating to the 1-bit register timing library 2002, when the voltage transition time of the data input signal is 50 ps, the timing constraint value is 35 ps if the voltage transition time of the clock signal is 50 ps, and 0.1 ns. The timing constraint value is 45 ps. Accordingly, when the timing constraint value when the voltage transition time of the first voltage measurement node 802 is 65 ps is obtained by, for example, linear interpolation shown in FIG. 24, it becomes 38 ps. Similarly, when the transition time of the voltage input to the input voltage measurement node 801 is 0.1 ns, the first voltage measurement node 802 is obtained when the voltage transition time of the input voltage measurement node 801 is 0.1 ns from FIG. 19 is 0.15 ns. From FIG. 19, the delay value is 45 ps if the voltage transition time of the clock signal is 0.1 ns, and the delay value is 55 ps if it is 0.2 ns. The value is 50 ps.

(Regarding the effect of reducing the number of simulations according to this embodiment)
Calculation of the delay value and timing constraint value by interpolation as described above is performed for each voltage measurement node (in this embodiment, the first voltage measurement node 802 and the second voltage measurement node) for all combinations of clock transition time and output load capacitance. 803, the third voltage measurement node 804, and the fourth voltage measurement node 805), the timing library can be created with a small number of simulations, and the timing library creation time can be reduced. In the present embodiment, the number of simulations does not depend on the number of 1-bit register circuits included in the timing library creation target circuit, but depends on the number of types of clock signal transition times of operating conditions included in the timing library. Therefore, the apparatus and method as in the present embodiment are particularly useful for creating a timing library of a multi-bit register circuit.

  In addition, it is not necessary to perform simulation separately for each calculation of the delay value and the timing constraint value. Specifically, as in the present embodiment, if the timing library 2002 of the 1-bit register is already prepared, it is only necessary to perform seven simulations in (S202), which greatly reduces the number of simulations. .

(Other)
Although the timing library creating apparatus 500 of this embodiment includes the circuit simulator 102, it may be configured by only the simulator control apparatus 501 and use an external circuit simulator.

  In the present embodiment, an example in which the creation target of the timing library is a 4-bit register has been described. However, the creation target may be a combinational logic circuit or a circuit in which a combinational logic circuit and a register circuit are combined. Further, the required characteristic value (timing characteristic value) is not limited to the delay value and the timing constraint value, but may be one of them, other characteristic values used for verifying the operation timing such as the voltage transition time, and various other values. A combination of these may be used.

  In this embodiment, two data included in the timing library 2002 of the 1-bit register are used to perform linear interpolation for deriving values from a straight line connecting two points represented on a graph. Polynomial interpolation or the like for deriving a value from a curve connecting points representing the data on two or more data may be performed. In some cases, the value can be directly derived from the timing library without interpolation.

  The timing library creation method, simulator control apparatus, and timing library creation program according to the present invention have the effect of reducing the number of circuit simulations and greatly reducing the time required for timing library creation. It is useful as a creation method, creation program, creation apparatus, and the like of a timing library including delay values and timing constraint values, which are referred to by an EDA (Electric Design Automation) tool used in circuit design.

1 is a block diagram illustrating a configuration of a timing library creation device 100 according to a first embodiment. 3 is a table representing an example of a delay value indicated by the timing library 1008 in a two-dimensional table format. 3 is a table representing an example of timing constraint values indicated by the timing library 1008 in a two-dimensional table format. 4 is a table showing an example of maximum delay value register selection condition data 1001. FIG. 4 is a table showing an example of a delay value extraction simulation signal pattern 1002; 4 is a table showing an example of timing library creation delay value extraction condition data 1003. 4 is a table showing an example of maximum timing constraint value register selection condition data 1004. FIG. 4 is a table showing an example of a simulation signal pattern 1005 for extracting timing constraint values. 9 is a table showing an example of timing constraint value extraction condition data 1006 for timing library creation. FIG. 2 is a circuit diagram showing a configuration of a 4-bit register circuit 400 as an example of a timing library creation target. 4 is a timing chart showing an operation of a 1-bit register constituting the 4-bit register circuit 400. FIG. 4 is a timing chart showing a delay value of a 1-bit register constituting the 4-bit register circuit 400. FIG. 4 is a timing chart showing a setup time and a hold time which are timing constraint values of a 1-bit register constituting the 4-bit register circuit 400. FIG. It is a timing chart which shows the operation | movement simulated at each step of the method of calculating a timing constraint value using the binary search algorithm. 3 is a flowchart showing the operation of the timing library creating apparatus 100. 6 is a block diagram illustrating a configuration of a timing library creation device 500 according to Embodiment 2. FIG. 4 is a table showing an example of timing library creation condition data 2001. 3 is a table representing an example of a delay value indicated by the timing library 2002 in a two-dimensional table format. 3 is a table representing an example of timing constraint values indicated by the timing library 2002 in a two-dimensional table format. FIG. 3 is a circuit diagram showing a configuration of a 4-bit register circuit 800 as an example of timing library creation. 4 is a flowchart showing the operation of the timing library creating apparatus 500. 4 is a table showing an example of the contents of voltage transition time information 2102 at the voltage measurement node of each 1-bit register. 4 is a graph showing a linear interpolation method for calculating a delay value. 4 is a graph showing a linear interpolation method for calculating timing constraint values.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Timing library creation apparatus 101 Simulator control apparatus 102 Circuit simulator 201 Clock signal voltage transition time 202 Output load capacitance value 203 Delay value 301 Clock signal voltage transition time 302 Data input signal voltage transition time 303 Timing constraint value 400 4-bit register Circuit 401 Data input pin 402 Clock pin 403 Data output pin 404 1st register 405 2nd register 406 3rd register 407 4th register 500 Timing library creation device 501 Simulator control device 601 Clock signal voltage transition time 602 Output load capacitance value 603 Delay value 701 Clock signal voltage transition time 702 Data input signal voltage transition time 703 Timing constraint value 800 4-bit register circuit 801 Input voltage measurement 802 First voltage measurement node 803 Second voltage measurement node 804 Third voltage measurement node 805 Fourth voltage measurement node 1001 Maximum delay value register selection condition data 1002 Delay value extraction simulation signal pattern 1003 Delay value extraction for timing library creation Condition data 1004 Maximum timing constraint value register selection condition data 1005 Timing constraint value extraction simulation signal pattern 1006 Timing library creation timing constraint value extraction condition data 1007 Subcircuit data 1008 Timing library 1101 Delay value of each 1-bit register 1102 Maximum delay Value register information 1103 Delay value information 1104 for all simulation conditions of all 1-bit registers Timing constraint value 1105 for each 1-bit register Maximum Timing constraint value register information 1106 Timing constraint value information for all simulation conditions of all 1-bit registers 2001 Timing library creation condition data 2002 1-bit register timing library 2003 Voltage transition time observation simulation signal pattern 2004 Sub-circuit of 4-bit register circuit Data 2005 Timing library 2101 of 4-bit register circuit Sub-circuit data 2102 with voltage measurement node Voltage transition time information at voltage measurement node of each 1-bit register

Claims (14)

A method for creating a timing library including respective timing characteristic values under a plurality of operating conditions for a plurality of input / output signal paths in a logic circuit of a semiconductor integrated circuit,
For all of the plurality of input / output signal paths, a circuit operation simulation is performed under some of the plurality of operation conditions, and timing characteristic values for the respective input / output paths under the respective operation conditions are obtained. A first timing characteristic value acquisition step;
A selection step of selecting a representative input / output signal path based on the timing characteristic value;
A second timing characteristic value acquisition step for obtaining a timing characteristic value under each operating condition by performing a simulation of circuit operation under an operating condition different from the part of the operating conditions for the representative input / output signal path;
Timing library creation processing step of creating a timing library using the timing characteristic value obtained for the representative input / output signal path as a characteristic value for another input / output signal path;
A method of creating a timing library, comprising: A method of creating a timing library according to claim 1,
A method of creating a timing library, wherein the input / output signal path is a signal path corresponding to a combination of each input signal and output signal in a multi-bit register circuit. A method of creating a timing library according to claim 1,
A timing library creating method, wherein the timing characteristic value is a delay value between input and output signals. A method of creating a timing library according to claim 3,
Creating a timing library, wherein the selection step selects at least one of the input / output signal paths having the maximum or minimum delay value obtained in the first timing characteristic value acquisition step as a representative input / output signal path; Method. A method of creating a timing library according to claim 1,
A timing library creation method, wherein the timing characteristic value is a timing constraint value to be satisfied by transition timings of a plurality of input signals. A method for creating a timing library according to claim 5, comprising:
The method of creating a timing library, wherein the selecting step selects an input / output signal path having a maximum timing constraint value obtained in the first timing characteristic value acquisition step as a representative input / output signal path. A method of creating a timing library according to claim 1,
The timing library creation method, wherein the operation conditions are a plurality of operation conditions for at least one of a power supply voltage, an input voltage transition time, an output load capacity, and a temperature. A timing library creation program including respective timing characteristic values under a plurality of operation conditions for a plurality of input / output signal paths in a logic circuit of a semiconductor integrated circuit,
For all of the plurality of input / output signal paths, a circuit operation simulation is performed under some of the plurality of operation conditions, and timing characteristic values for the respective input / output paths under the respective operation conditions are obtained. A first timing characteristic value acquisition step;
A selection step of selecting a representative input / output signal path based on the timing characteristic value;
A second timing characteristic value acquisition step for obtaining a timing characteristic value under each operating condition by performing a simulation of circuit operation under an operating condition different from the part of the operating conditions for the representative input / output signal path;
Timing library creation processing step of creating a timing library using the timing characteristic value obtained for the representative input / output signal path as a characteristic value for another input / output signal path;
A program for creating a timing library, characterized by causing a computer to execute. A timing library creating apparatus including timing characteristic values under a plurality of operating conditions for a plurality of input / output signal paths in a logic circuit of a semiconductor integrated circuit,
For all of the plurality of input / output signal paths, the circuit simulator simulates circuit operation under a part of the plurality of operation conditions, and the timing characteristics of each input / output path under each operation condition. A first timing characteristic value obtaining unit for obtaining a value;
A selection unit that selects a representative input / output signal path based on the timing characteristic value;
A second timing characteristic value acquisition unit for causing the circuit simulator to perform a circuit operation simulation under an operating condition different from the above-mentioned part of the operating conditions for the representative input / output signal path, and obtaining a timing characteristic value under each operating condition When,
A timing library creation processing unit that creates a timing library using the timing characteristic value obtained for the representative input / output signal path as a characteristic value for another input / output signal path;
An apparatus for creating a timing library, comprising: A method of creating a timing library including timing characteristic values according to characteristics of input signals in a logic circuit of a semiconductor integrated circuit,
A first characteristic value acquisition step of obtaining a characteristic of an output signal according to an input signal having a predetermined characteristic in a first partial logic circuit constituting the logic circuit by performing a simulation of a circuit operation;
A partial logic circuit timing library showing a timing characteristic value corresponding to the characteristic of the input signal for the second partial logic circuit to which the output signal of the first partial logic circuit is input, and the first characteristic value acquisition step Based on the obtained characteristic of the output signal of the first partial logic circuit input to the second partial logic circuit, the timing characteristic value for the second partial logic circuit is obtained, thereby obtaining the logic circuit. A second characteristic value obtaining step for obtaining a timing characteristic value for the logic circuit according to the characteristic of the input signal;
A method of creating a timing library, comprising: A method for creating a timing library according to claim 10, comprising:
The second partial logic circuit has an output signal as an output signal of the logic circuit,
The partial logic circuit timing library shows the relationship between the voltage transition time of the input signal and the delay value between the input / output terminals or the voltage transition time of the output signal in the second partial logic circuit,
The characteristic of the output signal of the first partial logic circuit obtained in the first characteristic value acquisition step is a voltage transition time of the output signal corresponding to the input signal having a predetermined voltage transition time,
In the second characteristic value calculation step, the delay value between the input / output terminals of the logic circuit and the output are obtained by obtaining the delay value between the input / output terminals in the second partial logic circuit or the voltage transition time of the output signal. A method for creating a timing library, comprising: obtaining at least one of signal voltage transition times. A method for creating a timing library according to claim 10, comprising:
The input signal to the first partial logic circuit is an input signal to the logic circuit,
The second partial logic circuit receives at least a plurality of input signals including an output signal of the first partial logic circuit,
The partial logic circuit timing library shows a relationship between voltage transition times of the plurality of input signals in the second partial logic circuit and timing constraint values that the voltage transition timings of the plurality of input signals should satisfy. And
The characteristic of the output signal of the first partial logic circuit obtained in the first characteristic value acquisition step is a voltage transition time of the output signal corresponding to the input signal having a predetermined voltage transition time,
The second characteristic value calculating step calculates a timing constraint value for the logic circuit by determining a timing constraint value that the voltage transition timings of the plurality of input signals in the second partial logic circuit should satisfy. How to create a featured timing library. A timing library creation program including timing characteristic values corresponding to characteristics of input signals in a logic circuit of a semiconductor integrated circuit,
A first characteristic value acquisition step of obtaining a characteristic of an output signal according to an input signal having a predetermined characteristic in a first partial logic circuit constituting the logic circuit by performing a simulation of a circuit operation;
A partial logic circuit timing library showing a timing characteristic value corresponding to the characteristic of the input signal for the second partial logic circuit to which the output signal of the first partial logic circuit is input, and the first characteristic value acquisition step Based on the obtained characteristic of the output signal of the first partial logic circuit input to the second partial logic circuit, the timing characteristic value for the second partial logic circuit is obtained, thereby obtaining the logic circuit. A second characteristic value obtaining step for obtaining a timing characteristic value for the logic circuit according to the characteristic of the input signal;
A program for creating a timing library, characterized by causing a computer to execute. A timing library creating apparatus including timing characteristic values corresponding to characteristics of input signals in a logic circuit of a semiconductor integrated circuit,
A first characteristic value acquisition unit for obtaining a characteristic of an output signal according to an input signal having a predetermined characteristic in a first partial logic circuit constituting the logic circuit by causing a circuit simulator to perform a simulation of a circuit operation; ,
A partial logic circuit timing library showing a timing characteristic value corresponding to the characteristic of the input signal for the second partial logic circuit to which the output signal of the first partial logic circuit is input, and the first characteristic value acquisition step Based on the obtained characteristic of the output signal of the first partial logic circuit input to the second partial logic circuit, the timing characteristic value for the second partial logic circuit is obtained, thereby obtaining the logic circuit. A second characteristic value acquisition unit for obtaining a timing characteristic value for the logic circuit according to the characteristic of the input signal;
An apparatus for creating a timing library, comprising:

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