JP2008287666A - Circuit operation verification device, method for manufacturing semiconductor integrated circuit, circuit operation verification method, control program and readable storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speedily and accurately verify delay fluctuation of a circuit element by power source voltage fluctuation. <P>SOLUTION: In a voltage fluctuation waveform and voltage change average value calculation means 20, a current waveform in switching of an object design circuit is determined by circuit simulation, a dynamic voltage change is speedily and accurately analyzed by adding the waveform to a separately extracted resistance network of wiring to thereby determine a dynamic voltage fluctuation waveform, and an average value of voltage fluctuation is determined from the voltage fluctuation waveform. In a table creating means 10, a delay fluctuation quantity of the circuit element for each operating voltage is preliminarily formed as a reference table. In reference to the reference table, the delay fluctuation of the circuit element by voltage fluctuation when a value obtained by subtracting an average value of voltage fluctuation (voltage drop) from an ideal voltage is given as operating voltage is speedily and accurately verified. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

   The present invention relates to a circuit operation verification apparatus for verifying delay variation of a circuit element due to voltage variation of a power supply wiring when designing an LSI (Large Scale Semiconductor Integrated Circuit) using an automatic placement and routing method of standard circuit elements, and this circuit Semiconductor integrated circuit manufacturing method for manufacturing semiconductor integrated circuit using data designed using operation verification device, circuit operation verification method using this circuit operation verification device, and computer execution of this circuit operation verification method And a computer-readable readable recording medium on which the control program is recorded.

  In recent years, with the high integration, high speed, and low voltage of LSI, problems related to signal wiring and power supply wiring have become serious. In particular, with regard to the power supply wiring, the power supply voltage drops due to the resistance component of the power supply wiring generated during circuit operation (IR-Drop), or when a current flows transiently, metal atoms move in the wiring, The problem of electromigration is that the wiring is broken or short-circuited with other conductors. If the voltage drop of the power supply voltage along the power supply wiring path becomes large, the circuit operation speed of the LSI may be affected or malfunction may be caused.

  Under such circumstances, in designing LSI, it is important to consider the voltage drop of the power supply wiring. It is generally well known that the analysis method based on circuit simulation is the most accurate method for analyzing the voltage drop. However, it is not possible to verify large-scale circuit elements (chips) using this method. This is not possible due to restrictions on the simulation execution time and the memory installed in the simulation apparatus. Under the circumstances as described above, there is a need for a circuit operation verification method capable of verifying a voltage change of a power supply voltage at high speed and accurately.

  As a method for analyzing the power supply voltage change at high speed, there are a dynamic analysis method and a static analysis method.

  First, a method for statically analyzing a change in power supply voltage will be described. Conventionally, many methods have been proposed as a method for statically analyzing the voltage change of the power supply voltage. As one of them, for example, an analysis method used in Non-Patent Document 1 will be described in detail with reference to FIGS. 9 and 10.

  FIG. 9 is a plan view schematically showing a mask layout result of the entire semiconductor integrated circuit including the logic circuit. In FIG. 9, a plurality of circuit elements, a wiring of the power supply VDD connected to them, and a wiring of the ground voltage VSS are shown.

  FIG. 10 is a circuit diagram showing an equivalent circuit for voltage change analysis used in a static analysis method. In FIG. 10, a circuit is represented by a resistor element, a capacitor element, and a current source model as circuit elements.

  In the static analysis method, the current consumption given to the current source is first calculated based on the average number of signal changes (activation rate or signal transition probability for clock signal transition) (static average consumption). Current calculation). Further, the resistance component of the power supply wiring is extracted from the mask layout as shown in FIG. 9 (extraction of the power supply wiring resistance network). The current source is added to the extracted resistor network, and DC analysis is performed, whereby the voltage change of the power supply wiring is obtained.

That is, assuming that the voltage change amount by the static analysis method is ΔV, the voltage change amount ΔV is
ΔV = Iavg × R Formula (1)
(However, in the above formula (1), Iavg represents the average current consumption given to the current source, and R represents the resistance component of the power supply wiring.)
Is the value represented by

  This method is the mainstream of analysis methods currently used in CAD tools for analyzing voltage changes in power supply wiring. With this method, analysis of large-scale semiconductor integrated circuits (LSIs) that could not be handled due to the limitations of execution time and memory used in the past when analysis was performed using circuit simulation, etc. As a result, the power supply voltage change can be analyzed in a realistic time.

  Next, when performing delay calculation as a determination method for verifying whether or not a circuit malfunctions due to a change in power supply voltage obtained as described above, it is generally performed to consider the power supply voltage change. It has been broken.

  For example, according to the conventional semiconductor integrated circuit delay calculation apparatus and method and timing verification apparatus and method disclosed in Patent Document 1, the power supply voltage for each element calculated by static voltage change analysis, From the circuit delay variation coefficient depending on the operating voltage, a delay value depending on the operating voltage is calculated for each circuit element. Based on the circuit delay information obtained in this way, timing verification is performed by logic simulation to identify a circuit element that causes a timing error.

  In the static analysis method as described above, toggle information obtained by logic simulation using a test pattern is required in order to obtain the average current consumption given to the current source. This toggle information is stored in a file called, for example, a VCD file (Value Change Dump file), and the average current consumption is calculated using this toggle information. Since the VCD file includes simulation results for all signals in the chip, the file size becomes enormous depending on the circuit scale and the simulation interval. Therefore, it may be difficult to generate the VCD file due to the performance of the simulation apparatus.

  In order to avoid this problem, a method of assigning a uniform activation rate to all signals to estimate the average current consumption, or allocating the total power consumption of the chip according to the area ratio of each cell (element) is used. In some cases, however, these methods deteriorate the accuracy of voltage drop analysis.

  Further, in the conventional semiconductor integrated circuit delay calculation apparatus and method and the timing verification apparatus and method disclosed in Patent Document 1, an accurate switching current waveform when the circuit is operated is not taken into consideration. However, the delay variation of the circuit element due to the dynamic power supply voltage variation cannot be accurately considered, and there is a problem in accuracy.

  Next, a method for dynamically analyzing the voltage change of the power supply voltage will be described. In the dynamic analysis method, the resistance, inductance, and capacitance components of the power supply wiring are extracted. A power source current waveform obtained separately is added as a current source to the network composed of the extracted resistance, inductance, and capacitance components, and a transient analysis is performed to obtain an instantaneous value in the voltage change of the power source voltage. .

  A problem in performing a dynamic voltage drop and its delay variation analysis using a commercially available CAD tool will be described below.

  In these delay variation analysis methods using CAD tools, a voltage value obtained by subtracting the peak voltage drop amount from the supply voltage is generally employed as the operating voltage. However, in circuit operation, the voltage value obtained by subtracting the peak voltage drop amount from the supply voltage is an instantaneous voltage value, and this voltage value does not continue transiently as the operating voltage. Therefore, the delay variation estimation by this method is biased to the worst condition, and there is a problem that the design margin is increased more than necessary due to excessive delay estimation, and the design becomes difficult.

For this problem, it is generally known that delay variation due to dynamic voltage drop depends on average power supply voltage drop rather than peak voltage drop. For example, in Non-Patent Document 2, when the average value and the peak value of the voltage waveform having different peak voltages are given as the operating voltage, the peak power supply voltage values are different but the average power supply voltage values are equal. In this case, it is described that the delays of the circuit elements are almost equal. This indicates that when the average power supply voltage value is equal, the delay is also equal. Therefore, when verifying the delay variation due to the dynamic voltage drop, the accuracy can be improved by adopting the average power supply voltage value rather than the peak power supply voltage value. Therefore, in order to obtain an accurate delay variation due to the power supply voltage variation, it is necessary to accurately obtain the average power supply voltage value from the power supply voltage waveform when the circuit element is switched.
Full-Chip Verification of UDSM Designs, R.A. Saleh, Simplex Solutions, Signal Integrity Effects in Custom IC and ASIC Designs, Wiley Interscience, IEEE Press, 2002, pp. 199 245-252. Measurement results of delay degradation due to power supplied noise well correlated with full-chip simulation, Yasuhiro Ogasahara, Eeto cem. JP 2000-195960 A

  However, the conventional delay variation verification method using the static power supply voltage drop analysis method using the average current consumption has the following problems.

  It takes time and effort to generate a logic simulation result as an input information file. In addition, in order to reduce the complexity of pre-processing related to the execution of logic simulation, it is problematic in terms of accuracy that the user gives a uniform activation rate to all signals or gives a rough estimate of current consumption. Furthermore, when the circuit output signal is switched, the power supply current waveform in the transition period of the signal change is not taken into consideration, so that the accuracy is inferior compared with the dynamic analysis.

  In addition, in the delay variation verification method in which the peak voltage obtained by the dynamic power supply voltage drop analysis method is used as the operating voltage, there is a problem that the estimation of the delay variation becomes excessive more than necessary.

  The present invention solves the above-described conventional problems, and uses a circuit operation verification device capable of verifying a delay variation of a circuit element due to a power supply voltage variation at high speed and with high accuracy, and data designed using the circuit operation verification device. Semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit, circuit operation verification method using this circuit operation verification apparatus, control program for causing a computer to execute this circuit operation verification method, and computer readable recording thereof An object is to provide a readable recording medium.

  The circuit operation verification apparatus according to the present invention verifies the delay fluctuation amount when the circuit voltage changes for the circuit elements constituting the semiconductor integrated circuit, based on the average power supply voltage fluctuation amount in consideration of the delay fluctuation due to noise. A device that generates a current source model by obtaining a current waveform when a target circuit is switched, extracts a wiring resistance network from layout data of the target circuit, and extracts the current source into the extracted wiring resistance network; A dynamic voltage fluctuation waveform is obtained by performing a transient analysis with a model added, and an average value of the voltage fluctuation waveform or an average value of the voltage fluctuation amount of the voltage fluctuation waveform is calculated. A value calculation means, a table creation means for creating a delay variation amount of the circuit element for each voltage variation amount of the voltage variation waveform as a reference table, and an average value of the voltage variation waveform as an operating voltage. Or a delay for calculating a delay variation amount for each circuit element of the target circuit with reference to the reference table when a value obtained by subtracting an average value of the voltage variation amount from an ideal voltage value is given as an operating voltage. A fluctuation amount calculating means; and a total delay time calculating means for calculating the total delay time of the target circuit by sequentially adding the calculated delay fluctuation amount of the circuit element to a delay value when timing analysis is performed at an ideal voltage; This achieves the above object.

  Preferably, the voltage fluctuation waveform and the voltage change amount average value calculating means in the circuit operation verification device of the present invention obtains a power source current waveform when the target circuit is switched, creates a current source model, and A power supply voltage fluctuation waveform is obtained by extracting a power supply resistance network from the layout data, adding a current source model to the extracted power supply resistance network, and performing a transient analysis to obtain a dynamic power supply voltage fluctuation waveform. Or the average value of the power supply voltage fluctuation amount of the power supply voltage fluctuation waveform.

  Further preferably, the voltage fluctuation waveform and the average value calculation means for calculating the voltage fluctuation waveform in the circuit operation verification apparatus of the present invention obtain a ground current waveform when the target circuit is switched, create a current source model, and the target circuit The ground wire resistance network is extracted from the layout data of the ground, and the current source model is added to the extracted ground wire resistance network to perform a transient analysis to obtain a dynamic ground wiring voltage fluctuation waveform. The average value of the voltage fluctuation waveform or the average value of the ground wiring voltage fluctuation amount of the ground wiring voltage fluctuation waveform is calculated.

  Further preferably, the table creation means in the circuit operation verification apparatus of the present invention creates a delay variation amount of the circuit element for each power supply voltage variation amount of the power supply voltage variation waveform as a reference table.

  Further preferably, the table creation means in the circuit operation verification device of the present invention creates a delay variation amount of the circuit element for each ground wiring voltage variation amount of the ground wiring voltage variation waveform as a reference table.

  Further preferably, the delay fluctuation amount calculation means in the circuit operation verification device of the present invention uses the average value of the power supply voltage fluctuation waveform as the operating voltage or subtracts the average value of the power supply voltage fluctuation amount from the ideal power supply voltage value. When the obtained value is given to the circuit element of the target circuit as an operating voltage, the delay variation amount for each circuit element of the target circuit is calculated with reference to the reference table.

  Further preferably, the delay fluctuation amount calculating means in the circuit operation verification device of the present invention uses the average value of the ground wiring voltage fluctuation waveform as an operating voltage or the average value of the ground wiring voltage fluctuation amount as an ideal ground voltage value. For the case where the value subtracted from is given as the operating voltage, the delay variation amount for each circuit element of the target circuit is calculated with reference to the reference table.

  Further preferably, the total delay time calculation means in the circuit operation verification device of the present invention uses the calculated delay variation amount for each circuit element of the target circuit as a delay value when timing analysis is performed at an ideal power supply voltage. Add sequentially.

  Further preferably, the total delay time calculation means in the circuit operation verification device of the present invention uses the calculated delay variation amount for each circuit element of the target circuit as a delay value when timing analysis is performed at an ideal ground voltage. Add sequentially.

  Further preferably, the voltage fluctuation waveform and the voltage change amount average value calculation means in the circuit operation verification device of the present invention uses a parasitic circuit component extraction tool to extract a wiring resistance network from the layout data of the target circuit. A resistor net extraction unit is further included.

  Further preferably, the voltage fluctuation waveform and the voltage change amount average value calculation means in the circuit operation verification device of the present invention connects the ideal power supply voltage output terminal or / and the ground wiring voltage output terminal to each logic gate of the target circuit. Then, the switching current waveform obtained by performing the circuit simulation is used as the current source model.

  Further preferably, the voltage fluctuation waveform and voltage change amount average value calculation means in the circuit operation verification apparatus of the present invention adds the current source model to the extracted resistance network of the power supply wiring and / or ground wiring, and performs transient analysis. And a transient analysis unit for obtaining the dynamic voltage fluctuation waveform.

  Further preferably, the voltage fluctuation waveform and the voltage fluctuation amount average value calculation means in the circuit operation verification device of the present invention are a voltage fluctuation for storing a power supply voltage fluctuation waveform and / or a ground wiring voltage fluctuation waveform as the voltage fluctuation waveform. A waveform storage unit is further included.

  Further preferably, the voltage fluctuation waveform and the voltage change amount average value calculation means in the circuit operation verification device of the present invention time-integrates the voltage waveform per clock cycle, and the time-integrated voltage waveform is required for one cycle. A voltage change amount average value calculation unit that calculates an average value of voltage change amounts of the power supply voltage fluctuation waveform and / or the ground wiring voltage fluctuation waveform by dividing by time.

  Further preferably, the voltage fluctuation waveform and voltage change amount average value calculation means in the circuit operation verification device of the present invention has an average voltage change value storage unit for storing the average value of the voltage change amounts.

  Further preferably, the table creation means in the circuit operation verification apparatus of the present invention has a circuit information / circuit simulation condition storage unit for storing circuit information and circuit simulation conditions for each element type.

  Further preferably, the table creation means in the circuit operation verification apparatus of the present invention has a circuit simulation execution unit for creating the reference table by circuit simulation based on the circuit information for each element type and the circuit simulation conditions.

  Further preferably, the circuit simulation execution unit in the circuit operation verification apparatus according to the present invention is configured for each element type with respect to the values of the operating voltage change amount, the input transition time, and the output load capacitance as an ideal voltage as the circuit simulation condition. The delay change amount and output transition time per circuit element are obtained, and the obtained delay change amount and output transition time are created as the reference table and stored in the table storage unit.

  Further preferably, the delay fluctuation amount calculation means in the circuit operation verification device of the present invention is configured such that the voltage variation corresponding to the average value of the voltage fluctuation waveform or the average value of the voltage fluctuation amount, the input transition time, from the reference table. And a reference table take-out unit for taking out the delay fluctuation amount and the output transition time with respect to the output load capacity.

  Further preferably, the delay fluctuation amount calculation means in the circuit operation verification device of the present invention refers to the reference table, and calculates a delay fluctuation amount and output transition time of the circuit element by referring to the reference table. Have

  Further preferably, the delay variation / output transition time calculation unit in the circuit operation verification apparatus of the present invention refers to the reference table with the output transition time of the previous circuit element as the input transition time of the next circuit element.

  Further preferably, the delay variation calculation means in the circuit operation verification apparatus of the present invention further includes a delay variation storage section for storing the calculated delay variation.

  Further preferably, the total delay time calculation means in the circuit operation verification device of the present invention separately analyzes the delay variation amount taking into account the voltage variation stored in the delay variation amount storage section with a normal ideal voltage. The delay time calculated by using the technique and added to the delay time stored in the timing analysis result storage unit to obtain the delay time considering the delay variation due to the voltage variation, and this processing is performed for all the circuit elements of the target circuit. Thus, a total delay time calculation unit for obtaining a total delay time considering delay variation due to voltage variation is provided.

  Further preferably, the average value of the voltage fluctuation waveform in the circuit operation verification apparatus of the present invention is an average voltage value in a waveform area of the voltage fluctuation waveform as the average value of the voltage fluctuation amount, or a maximum of the voltage fluctuation waveform. The average value of the fluctuation voltage and the minimum fluctuation voltage.

  Further preferably, the delay variation due to noise in the circuit operation verification apparatus of the present invention is a delay variation when the target circuit or the target circuit element included in the target circuit is switched.

  Still preferably, in a circuit operation verification apparatus according to the present invention, the delay variation calculation means includes a circuit simulation including an average value of the voltage variation waveform of the target design circuit calculated by the voltage variation waveform and the voltage variation average value calculation means. The circuit simulation condition including the voltage change amount of the reference table closest to the condition and the delay fluctuation amount at that time are read out, the circuit simulation condition including the voltage change amount of the read reference table, and the voltage fluctuation waveform And the delay of the circuit element with respect to the voltage change for each circuit element of the target design circuit by proportional calculation from the difference from the circuit simulation condition including the average value of the voltage fluctuation waveform of the target design circuit calculated by the voltage change amount average value calculation means Calculate the amount of variation.

  Further preferably, the circuit simulation condition in the circuit operation verification device of the present invention includes a voltage change amount, an input transition time, and an output additional capacitance.

  A method for manufacturing a semiconductor integrated circuit according to the present invention is a method for manufacturing a semiconductor integrated circuit using a resist pattern patterned based on circuit information for which circuit operation verification processing has been completed using a circuit operation verification apparatus. The above objective is achieved.

  The circuit operation verification method of the present invention is a circuit operation verification method for verifying the delay fluctuation amount when the voltage is changed with respect to the circuit elements constituting the semiconductor integrated circuit based on the average voltage fluctuation amount in consideration of the delay fluctuation due to noise. The voltage fluctuation waveform and the voltage change amount average value calculation means obtain a current waveform when the target circuit is switched to create a current source model, extract a wiring resistance network from the layout data of the target circuit, By adding the current source model to the extracted resistance network of the wiring and performing a transient analysis, a dynamic voltage fluctuation waveform is obtained, and an average value of the voltage fluctuation waveform and a voltage fluctuation amount average value are calculated. A calculating step, a table creating means for creating a delay variation amount of the circuit element for each voltage variation amount as a reference table, and a delay variation amount calculating means; Delay variation calculation for calculating the delay variation amount for each circuit element of the target circuit with reference to the reference table when the value obtained by subtracting the average value of the voltage variation waveform from the ideal voltage value is given as the operating voltage. And a total delay time in which the total delay time calculation means calculates the total delay time of the target circuit by adding the calculated delay variation of the circuit element to the delay value when the timing analysis is performed at the ideal voltage. And the above object is achieved thereby.

  Preferably, the voltage fluctuation waveform and the voltage change amount average value calculating step in the circuit operation verification method of the present invention determine a power source current waveform when the target circuit is switched, create a current source model, and A power supply wiring resistance network is extracted from the layout data of the power supply, and the current source model is added to the extracted power supply wiring resistance network to perform a transient analysis, thereby calculating a dynamic power supply voltage fluctuation waveform. An average value of the voltage fluctuation waveform or an average value of the power supply voltage fluctuation amount of the power supply voltage fluctuation waveform is calculated, and the table creating step refers to a table of delay fluctuation amounts of circuit elements for each power supply voltage change amount of the power supply voltage fluctuation waveform. The delay fluctuation amount calculating step is configured such that the average value of the power supply voltage fluctuation waveform is set as the operating voltage or the average value of the power supply voltage fluctuation amount is different from the ideal power supply voltage value. When the subtracted value is given to the circuit element of the target circuit as the operating voltage, the delay variation amount for each circuit element of the target circuit is calculated with reference to the reference table, and the total delay time calculating step includes: The calculated delay variation for each circuit element of the target circuit is sequentially added to the delay value when the timing analysis is performed at the ideal power supply voltage.

  Further preferably, in the circuit operation verification method of the present invention, the voltage fluctuation waveform and the voltage change amount average value calculating step obtains a ground current waveform when the target circuit is switched, creates a current source model, and the target circuit The ground wiring resistance network is extracted from the layout data of the above, and the current source model is added to the extracted ground wiring resistance network to perform a transient analysis to calculate a dynamic ground wiring voltage fluctuation waveform. An average value of a ground wiring voltage fluctuation waveform or an average value of a ground wiring voltage fluctuation amount of the ground wiring voltage fluctuation waveform is calculated, and the table creation step includes circuit elements for each ground wiring voltage fluctuation amount of the ground wiring voltage fluctuation waveform. The delay fluctuation amount is generated as a reference table, and the delay fluctuation amount calculating step includes calculating an average value of the ground wiring voltage fluctuation waveform. For the case where the operating voltage is given as the operating voltage or the value obtained by subtracting the average value of the ground wiring voltage fluctuation amount from the ideal ground voltage value, the delay fluctuation amount for each circuit element of the target circuit is stored in the reference table. The total delay time calculating step calculates the delay variation amount for each circuit element of the target circuit, and sequentially adds to the delay value when the timing analysis is performed at the ideal ground voltage.

  Further preferably, in the circuit operation verification method according to the present invention, the power supply voltage fluctuation waveform and the voltage change amount average value calculating step may be performed such that the extraction unit of the wiring resistance network uses the parasitic circuit component extraction tool and the layout data of the target circuit. The resistance network of the wiring is extracted from

  Further preferably, in the circuit operation verification method according to the present invention, the voltage fluctuation waveform and the voltage change amount average value calculating step include connecting an ideal power supply output terminal or / and a ground wiring voltage output terminal to each logic gate of the target circuit. A switching current waveform obtained by performing circuit simulation is used as the current source model.

  Still preferably, in the circuit operation verification method according to the present invention, in the voltage fluctuation waveform and voltage change amount average value calculating step, the transient analysis unit applies the current source model to the extracted resistance network of the power supply wiring and / or the ground wiring. In addition, a transient analysis is performed to obtain the dynamic voltage fluctuation waveform, and the voltage fluctuation waveform is stored in the voltage fluctuation waveform storage unit.

  Further preferably, in the voltage fluctuation waveform and voltage change amount average value calculating step in the circuit operation verification method of the present invention, the voltage change amount average value calculating section time-integrates the voltage waveform per clock cycle, and this time By dividing the integrated voltage waveform by the time required for one cycle, the average value of the voltage change amount of the power supply voltage fluctuation waveform and / or the ground wiring voltage fluctuation waveform is calculated and stored in the average voltage fluctuation value storage unit. .

  Further preferably, the table creation step in the circuit operation verification method of the present invention is such that the circuit simulation execution unit creates the reference table by circuit simulation based on the circuit information for each element type and the circuit simulation conditions. A simulation execution step is further included.

  Further preferably, in the circuit operation verification method of the present invention, the circuit simulation execution step is performed for each element type with respect to values of the operating voltage change amount, the input transition time, and the output load capacitance with respect to the ideal voltage as the circuit simulation condition. The delay change amount and output transition time per circuit element are obtained, and the obtained delay change amount and output transition time are created as the reference table and stored in the table storage unit.

  Further preferably, in the delay variation calculation step in the circuit operation verification method of the present invention, the reference table extraction unit corresponds to the average value of the voltage variation waveform or the average value of the voltage variation from the reference table. The delay variation amount and the output transition time information with respect to the voltage change amount, the input transition time, and the output load capacitance are extracted.

  Further preferably, in the delay variation calculation step in the circuit operation verification method of the present invention, the delay variation / output transition time calculation unit uses the output transition time of the previous circuit element as the input transition time of the next circuit element. Reference the reference table.

  Further preferably, in the delay variation calculation step in the circuit operation verification method of the present invention, the delay variation / output transition time calculation unit refers to the reference table to determine the delay variation and output transition time of the circuit element. Calculate and store in the delay variation storage unit.

  Further preferably, in the total delay time calculating step in the circuit operation verification method of the present invention, the total delay time calculating unit separately calculates the delay variation amount considering the voltage variation stored in the delay variation amount storage unit, This is calculated using the timing analysis method at the ideal voltage and added to the delay time stored in the timing analysis result storage unit to obtain the delay time for each circuit element in consideration of the delay variation due to the voltage variation. By performing the processing for all the circuit elements of the target circuit, the total delay time in consideration of the delay variation due to the voltage variation is obtained.

  The control program according to the present invention describes a processing procedure for causing a computer to execute each step of the circuit operation verification method according to the present invention, thereby achieving the above object.

  The readable recording medium of the present invention is a computer-readable medium in which the control program of the present invention is stored, whereby the above object is achieved.

  The operation of the present invention will be described below with the above configuration.

  When performing delay calculation as a determination method for verifying whether or not the target design circuit malfunctions due to fluctuations in the power supply voltage and / or ground voltage (ground voltage), the inventors of the present application are more accurately caused by voltage drop. In order to verify the delay variation, the voltage drop waveform when the circuit element is switched is obtained, the average value of the voltage fluctuation of this voltage drop waveform is accurately obtained, and the value obtained by subtracting the average value of the voltage fluctuation amount from the ideal voltage is obtained. It has been found that it is necessary to obtain a delay variation by applying it to a circuit element as an operating voltage.

  Therefore, in the present invention, the current waveform when the circuit is switched is obtained by circuit simulation, and the dynamic voltage change is analyzed with high speed and accuracy by adding it as a current source to the resistance network of the wiring extracted separately. Then, a dynamic voltage fluctuation waveform is obtained.

  Furthermore, the average value of this voltage drop waveform is obtained with high accuracy, and the delay fluctuation when the value obtained by subtracting the average value of the voltage drop waveform (average value of the amount of voltage fluctuation) from the ideal voltage is given as the operating voltage in advance. By obtaining the delay variation amount table of the circuit element with respect to the operating voltage, the operation verification can be performed at high speed with high accuracy.

More specifically, the power supply voltage will be described as (1) to (5) below.
(1) Creation of table of delay variation and output transition time with respect to power supply voltage variation For all circuit elements of the library (elements including all drive capabilities) Obtained by simulation. Here, the amount of change in delay is the amount of change in delay when the operating power supply voltage changes with respect to the delay in the ideal power supply voltage. In this case, since the delay change amount with respect to the power supply voltage change amount is different for each element type, it is necessary to obtain all circuit elements. Furthermore, in general, since the delay of the circuit element depends on the input transition time and the output load capacity, a delay variation table is created using the operating voltage change amount, the input transition time, and the output load capacity as parameters, Store in the storage unit. Similarly, since the waveform is propagated from each logic gate to the next-stage logic gate, the output transition time of the previous-stage cell becomes the input transition time of the next-stage cell. Therefore, an output transition time table is created using the operating voltage change amount, the input transition time, and the output load capacity as parameters, and stored in a predetermined storage unit. Note that this library is prepared only once for each process, and can be applied to different design data.
(2) Calculation of switching power supply voltage waveform In general, in an LSI (large-scale semiconductor integrated circuit) operating in a complete clock synchronization type, many logic gate circuits are switched when a state transition of a clock signal occurs. A current source model is created by obtaining a current consumption waveform by switching of these logic gate circuits. Here, the current source model is a switching current waveform obtained by connecting an ideal power supply to each logic gate and executing a circuit simulation. By using this current source model, it is possible to verify a change in power supply voltage due to switching of circuit elements with high speed and accuracy without performing a transistor level circuit simulation.

Next, a resistance network of the power supply wiring is extracted from the layout data. The power supply wiring resistance network can be extracted by using a commercially available LPE (Layout Parameter Extraction) tool (parasitic circuit component extraction tool). A switching voltage waveform of the power supply wiring can be obtained by adding the current source to the extracted power supply wiring resistance network and performing a transient analysis.
(3) Calculation of average value of power supply voltage fluctuation The average value of voltage fluctuation is obtained from the switching voltage waveform of the power supply wiring obtained in (2) above. The average value of the voltage fluctuation can be easily obtained by time-integrating the voltage waveform per clock cycle and dividing by the time required for one cycle.
(4) Calculation of delay fluctuation amount For each circuit element constituting the LSI circuit, each logic element has an operation voltage that is obtained by subtracting the average value of the power supply voltage fluctuation amount obtained in (3) from the ideal power supply voltage. The delay variation amount and output transition time of each circuit element are obtained by referring to the delay variation amount and output transition time of the gate circuit from the table previously obtained in (1) above. In the timing analysis using the static timing analysis, the waveform is propagated from each logic gate to the next logic gate, so that the output transition time of the previous cell becomes the input transition time of the next cell. In the next stage cell, it is possible to obtain the delay fluctuation and the output transition time of the next stage cell by referring to the input transition time, the output load capacity, and the delay fluctuation table for the operating voltage fluctuation amount. By repeating the above processing, it is possible to perform timing analysis in consideration of delay variation due to power supply voltage variation.
(5) Delivery of delay value to static timing analysis By adding the amount of delay change of each element obtained in (4) above to the delay value when timing analysis is performed with an ideal power supply, power supply wiring It is possible to perform a static timing analysis with high accuracy in consideration of a delay variation due to a voltage drop.

  Furthermore, each processing can be performed on the ground voltage of the ground wiring as in the case of the power supply voltage of the power wiring.

  As described above, according to the present invention, in the LSI design using the automatic placement and routing of the standard cell, the relationship between the voltage change amount due to switching and the delay change is accurately obtained by the circuit simulation, and the table is registered in advance for each element type. By doing so, it is possible to perform delay analysis considering voltage fluctuation at high speed without performing circuit simulation for each net.

  Further, a voltage fluctuation waveform is obtained by applying a switching current waveform at an ideal power source as a current source model to a separately extracted wiring resistance network and performing a transient analysis. By giving a voltage obtained by subtracting the average value of the voltage fluctuation amount obtained from the voltage fluctuation waveform from the ideal voltage as the operating voltage, the accuracy of a commercially available CAD tool that performs the delay calculation by giving the peak voltage drop amount as the operating voltage is improved. be able to.

  Furthermore, by referring to a table created in advance by circuit simulation, it is possible to perform delay analysis considering delay variation due to voltage variation at higher speed than performing analysis each time using circuit simulation.

  Embodiments of a circuit operation verification method and a circuit operation verification apparatus using the same according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating an exemplary functional configuration of a circuit operation verification apparatus according to an embodiment of the present invention.

  In FIG. 1, the circuit operation verification apparatus 1 according to the present embodiment is a table creation unit 10 that creates delay variation amounts of circuit elements and output transition time information as reference tables in advance by circuit simulation with respect to voltage variations of power supply voltage and ground voltage. In addition, a dynamic voltage fluctuation waveform is calculated for each element using a current source model and a wiring resistance network, and an average value of the voltage fluctuation waveform or an average value of the voltage fluctuation amount of the voltage fluctuation waveform is calculated. Reference design circuit with reference to voltage variation waveform and voltage variation average value calculating means 20 and delay variation amount and output transition time information of circuit elements for each voltage variation amount in the reference table created by table creating means 10 A delay fluctuation amount calculating means 30 for calculating a delay fluctuation amount of the circuit element corresponding to the average voltage fluctuation amount of the voltage fluctuation waveform for each of the circuit elements; A total delay time calculating means for calculating a delay time in consideration of the delay variation of the circuit element to calculate a total delay time, and the amount of delay variation when the power supply voltage is changed is represented by a delay variation due to noise (for example, power supply The delay variation due to noise is verified by the average power supply voltage variation amount in consideration of the delay variation when the target circuit or the target circuit element included in the target circuit is switched. In addition, it is possible to verify whether or not the target design circuit malfunctions due to voltage fluctuations of the power supply voltage and the ground voltage (ground voltage) based on the total delay time.

  The table creation means 10 includes a circuit information / circuit simulation condition storage unit 11 for storing circuit information and circuit simulation conditions for each element type, and the voltage change for each voltage change amount for each element type by circuit simulation. Circuit simulation execution unit 12 for calculating power supply voltage change dependency for each element type that creates delay variation and output transition time information with respect to the amount, input transition time and output load capacity as a reference table, and a reference for storing the created reference table And a table storage unit 13.

  In the voltage fluctuation waveform and the average value calculation means 20 for voltage variation, the circuit is switched between a wiring resistance network extraction unit that extracts a wiring resistance network from layout data of the target design circuit, and the extracted wiring resistance network. A transient analysis unit 22 for performing transient analysis by adding the current waveform as a current source model, an average voltage variation storage unit 23 for storing a voltage variation waveform for each element calculated by the transient analysis, A voltage change amount average value calculating unit 24 for calculating an average value of the voltage change amount from each voltage change waveform; and an average voltage change value storage unit 25 for storing the calculated average value of the power supply voltage change amount. is doing. The transient analysis unit 22 is connected to a switching current waveform storage unit 221 that stores a current waveform for each element when the circuit is switched.

  The delay variation calculation means 30 includes a reference table extraction unit 31 that extracts the reference table information from the reference table storage unit 13 from the average value of the voltage variation for each circuit element of the target design circuit, and the extracted reference table information (described above). Referring to the voltage variation, input transition time, and delay variation and output transition time information for output load capacity), calculate the delay variation and output transition time of the circuit element for the voltage variation of each circuit element of the target design circuit. A delay variation / output transition time calculation unit 32 and a delay variation storage unit 33 for storing the calculated delay variation. In this case, the delay variation calculation means 30 is the closest reference to the circuit simulation condition including the voltage fluctuation waveform and the average value of the voltage variation of the target design circuit calculated by the voltage variation average value calculation means 20. The circuit simulation condition including the voltage change amount of the table and the delay fluctuation amount at that time are read out, and the circuit simulation condition including the voltage change amount of the read reference table, and the voltage fluctuation waveform and voltage change amount average value calculating means 20 are calculated. From the slight difference from the circuit simulation condition including the average value of the voltage fluctuation amount of the target design circuit, the delay fluctuation amount of the circuit element with respect to the voltage change for each circuit element of the target design circuit can be calculated by proportional calculation or the like. it can.

  The total delay time calculation means 40 adds the delay variation amount of the circuit element calculated from the average value of the voltage change amount to the timing analysis at the ideal voltage (ideal power supply voltage or ideal ground voltage) and calculates the total delay time. A total delay time calculation unit 41 is provided. The total delay time calculation unit 41 is connected to a timing analysis result storage unit 411 that stores a result of timing analysis at an ideal voltage.

  FIG. 2 is a block diagram illustrating a hardware configuration example of a main part of the circuit operation verification apparatus of FIG.

  In FIG. 2, the circuit operation verification device 1 of the present embodiment is configured by a computer system, and an operation input unit 2 such as a keyboard, a mouse, and a screen input device that allows various input commands, and various input commands. A display unit 3 capable of displaying various images such as an initial screen, a selection guidance screen, and a processing result screen on the display screen, a CPU 4 (central processing unit) as a control means for performing overall control, and a CPU 4 A RAM 5 as a temporary storage means that works as a work memory at the time of activation, a ROM 6 as a computer-readable readable recording medium (storage means) in which a control program for operating the CPU 4 and various data used therefor are recorded, A database 7 for storing various data in the circuit operation verification process and making it possible to refer to it It is.

  In addition to the input command from the operation input unit 2, the CPU 4 is based on the control program read from the ROM 6 into the RAM 5 and various data used therefor, and the circuit simulation execution unit 12 and the wiring resistance extraction unit. 21, a transient analysis unit 22, a voltage change amount average value calculation unit 24, a reference table extraction unit 31, a delay variation / output transition time calculation unit 32, and a total delay time calculation unit 41. To do.

  The ROM 6 is configured by a readable recording medium (storage means) such as a hard disk, an optical disk, a magnetic disk, and an IC memory. The control program and various data used for the control program may be downloaded to the ROM 6 from a portable optical disk, a magnetic disk, an IC memory, or the like, or may be downloaded to the ROM 6 from a hard disk of a computer, or wirelessly, wired, or the Internet. It may be downloaded to the ROM 6 via the above. A control program describing a processing procedure for causing a computer to execute the circuit operation verification processing function of FIG. 1 to be described later is stored in a computer-readable readable storage medium, and the circuit operation verification processing is automatically performed by the computer (CPU 4). Is to do.

  The RAM 5 and the database 7 store various data generated as intermediate data during the circuit operation verification process by the CPU 4 each time and can refer to them as necessary. The database 7 may be configured as the same storage unit as the RAM 5.

  The circuit information / circuit simulation condition storage unit 11 for each element type, the reference table storage unit 13, the resistance extraction data storage unit 211, the switching current waveform storage unit 221, and the average voltage fluctuation value storage unit 23 The clock cycle storage unit 241, the average voltage fluctuation value storage unit 25, the delay fluctuation amount storage unit 33, and the timing analysis result storage unit 411 may be in the RAM 5 or ROM 6, or in the database 7. Alternatively, a storage unit may be provided separately from these.

  The operation of each means will be sequentially described below with the above configuration.

  First, the operation of the table creation means 10 will be described in detail.

  The table creation means 10 creates a reference table of circuit element delay variation and output transition time using the operating voltage variation, input transition time, and output load capacitance with respect to the ideal voltage (ideal power supply voltage and ideal ground voltage) as parameters. This reference table is registered as a library. This reference table can be created as follows using a circuit simulator such as SPICE.

  First, paying attention to the delay change with respect to the voltage change of the power supply wiring (VDD side), the operating voltage change amount, the input transition time, and the output load capacitance are used as parameters, and the power supply voltage is set for all the circuit elements constituting the library. Define the amount of change.

  Here, a specific example will be described using the inverter element shown in FIG.

  As shown in FIG. 3, the voltage VDD applied to the power supply wiring of the target circuit element is a value obtained by subtracting the voltage drop from an ideal operating power supply voltage having no voltage change, as shown in the following equation (2). Give as a fixed value.

VDD ′ = V_VDD−ΔVDD Formula (2)
(However, in the above equation (2), V_VDD is an ideal power supply voltage value without voltage change due to resistance, and ΔVDD is a voltage change amount of the power supply wiring.)
In the above equation (2), as the amplitude of the voltage change amount ΔVDD of the power supply wiring, for example, 1 percent of the ideal power supply voltage value is given as a step size, and is given to about 20 percent.

  As the input transition time (input slew) and the output load capacity (output load), values referred to by a CMOS nonlinear delay table used in logic synthesis or the like can be used.

  The operating power supply voltage change amount, the input transition time, and the output load capacitance defined as described above are stored in the circuit information / circuit simulation condition storage unit 11 for each element type as data for circuit simulation input.

  Next, regarding the power supply wiring, using the circuit simulation execution unit 12, in step S11 of FIG. 4, each power supply voltage change amount ΔVDD (about 20% with 1% of the ideal power supply voltage value as a step size as described above) Each time, the delay change amount per circuit element and the output transition time with respect to the power supply voltage change amount ΔVDD, the input transition time, and the output load capacitance value are obtained.

  FIG. 5 is a diagram for explaining an input waveform and an output waveform when the voltage of the power supply wiring is changed and a delay variation thereof with respect to the inverter element as an example of the circuit element shown in FIG.

  In FIG. 5, the vertical axis represents voltage (V), and the horizontal axis represents time (s). A broken line waveform 51 is an input waveform with respect to the original voltage, a broken line waveform 52 is an output waveform with respect to the original voltage, and a bold line. A waveform 53 indicates an input waveform when the power supply voltage changes, and a thin line waveform 54 indicates an output waveform when the power supply voltage changes. Td represents a delay amount in the ideal power supply voltage V_VDD, and Tdk represents a delay amount in the case where the operation power supply voltage is VDD ′. Further, in FIG. 5, the voltage for measuring the delay is defined as V_VDD / 2.

  In step S11 in FIG. 4, the circuit simulation execution unit 12 sets various values of the power supply voltage change amount ΔVDD (increment 1% of the ideal power supply voltage value as described above) for the inverter element as shown in FIG. 4), the power supply voltage change amount ΔVDD, the input transition time and the delay variation amount with respect to the output load capacitance and the output transition time are obtained, respectively. In step S12 of FIG. Each delay variation amount and output transition time with respect to time and output load capacity are tabulated as a reference table and stored in the reference table storage unit 13 shown in FIG. In step S13 in FIG. 4, it is confirmed whether or not these processes have been performed for all circuit elements on the design target circuit. If these processes have been performed for all circuit elements on the design target circuit, If these processes have not been performed for all the circuit elements on the design target circuit, the process returns to step S11.

  For each operating power supply voltage change amount ΔVDD with respect to the ideal power supply voltage, an example of reference table information of the operating power supply voltage change amount ΔVDD, the input transition time, the delay variation amount for the output load capacitance, and the output transition time obtained in this way. This is shown in FIG. The first line of FIG. 6 indicates that the delay fluctuation amount is ΔDelay1 and the output transition time Tran2 when the power supply voltage fluctuation amount is ΔV1, the input transition time is Tran1, and the output load capacitance is Cload1. The first to fifth lines of FIG. 6 show the case where the power supply voltage fluctuation amount is the same as ΔV1 and the input transition time and the output load capacity are different as circuit simulation conditions. Thereafter, the power supply voltage fluctuation amount is ΔV2. In the case of ΔV3,... Since this output transition time is referred to as the input transition time of the next stage circuit element, this output transition time may not be included in the reference table information, but may be included in the reference table information. An output transition time item is included.

  Next, paying attention to the delay change with respect to the voltage change of the ground wiring, as a voltage given to the ground wiring (ground voltage VSS) of the target circuit element, as shown in the following formula (3), an ideal with no voltage change A value obtained by subtracting the voltage drop amount from the normal operating voltage is given as a fixed value of the ground voltage value.

VSS ′ = V_VSS−ΔVSS Formula (3)
(However, in the above equation (3), V_VSS is an ideal ground voltage value without voltage change due to resistance, and ΔVSS is a voltage change amount of the ground wiring.)
Further, by performing the same processing as in the case of the power supply wiring by the circuit simulation execution unit 12, in step S14 in FIG. 4, for each ground wiring voltage change amount ΔVSS, the ground wiring voltage change amount ΔVSS, the input transition The delay change amount and the output transition time with respect to the time and the output load capacity are respectively obtained, and in step S15 of FIG. 4, these are tabulated as a reference table and stored in the reference table storage unit 13 shown in FIG. In step S16 of FIG. 4, it is confirmed whether or not these processes have been performed for all circuit elements on the design target circuit. If these processes have been performed for all circuit elements on the design target circuit, the process is performed. If these processes have not been performed for all the circuit elements on the design target circuit, the process returns to step S14.

  As described above, the relationship between the operating voltage variation and delay variation of the power supply wiring and ground wiring accurately obtained by the circuit simulation by the circuit simulation execution unit 12 is made into a library as a reference table, thereby circuit simulation for each net. Even without this, it is possible to easily and accurately verify the delay variation due to the power supply voltage variation.

  In the table creation means 10, both the delay change with respect to the voltage change of the power supply wiring (VDD side) and the delay change with respect to the voltage change of the ground wiring have been described, but not limited to this, the power supply wiring (VDD side) Either one of the delay change with respect to the voltage change and the delay change with respect to the voltage change of the ground wiring may be used.

  Next, the operation of the voltage fluctuation waveform and voltage change amount average value calculating means 20 shown in FIG. 1 will be described in detail with reference to the flowchart of FIG.

  The voltage fluctuation waveform and voltage change amount average value calculating means 20 calculates an average value of the switching power supply voltage waveform (power supply voltage fluctuation waveform) and the power supply voltage change amount for each element. The switching power supply voltage waveform for each element can be obtained as follows using a current source model and a commercially available wiring parasitic element extraction tool.

  First, from the mask layout data of the semiconductor integrated circuit, a power source current waveform when the design target circuit is switched is obtained to create a current source model. Here, an ideal power supply is connected to each logic gate and a circuit simulation is performed to obtain a switching power supply current waveform for each element, and this switching power supply current waveform is stored in the switching current waveform storage unit 221 as a current source model. Can be used. The switching power supply current waveform for each element is used for transient analysis by the transient analysis unit 22.

  FIG. 8 shows an example of a switching power supply current waveform obtained by the transient analysis unit 22 of FIG. In FIG. 8, the vertical axis indicates the power supply current (A), the horizontal axis indicates time (Time), and Tcycle indicates the clock cycle.

  Next, the resistance component of the power supply wiring is extracted from the mask layout data of the circuit to be designed by using a commercially available LPE (Layout Parameter Extraction) tool (parasitic circuit component extraction tool) by the extraction unit of the wiring resistance network shown in FIG. Extracted and stored in the resistance extraction data storage unit 211 of the power supply wiring.

  Further, with respect to the mask layout of the semiconductor integrated circuit (design target circuit) as shown in FIG. 9, each circuit element is replaced with the current source model, and as shown in FIG. Add as In step S1 of FIG. 7, using the extracted resistance network of the power supply wiring of the resistance extraction data storage unit 211 of the power supply wiring and the current source model added to the switching current waveform storage unit 221, the transient shown in FIG. A transient analysis is performed by the analysis unit 22 to calculate a switching power supply voltage waveform (power supply voltage fluctuation waveform) for each circuit element of the circuit to be designed. This power supply voltage fluctuation waveform is stored in the average voltage fluctuation value storage unit 23 shown in FIG.

  FIG. 11 shows a switching voltage waveform for each element of the power supply wiring obtained by the transient analysis unit 22 of FIG. In FIG. 11, the vertical axis indicates the power supply voltage (V), the horizontal axis indicates time (Ytime), and Tcycle indicates the clock cycle.

  Next, in step S <b> 2 of FIG. 7, the average value calculation unit 24 of the voltage change amount shown in FIG. 1 calculates the average value of the power supply voltage fluctuation waveform for each circuit element of the circuit to be designed. Here, with respect to the switching power supply voltage waveform, the voltage waveform per clock cycle is time-integrated and divided by one clock cycle of the clock cycle storage unit 241 shown in FIG. The average value (average voltage drop amount) of the power supply voltage change amount for each circuit element of the circuit to be designed can be obtained. The average value of the voltage change amount is stored in the average voltage fluctuation value storage unit 25 shown in FIG.

  As described above, by performing the same process for all circuit elements constituting the circuit to be designed, an average value of the power supply voltage fluctuation can be obtained from the voltage change waveform of the power supply wiring for each circuit element.

  Furthermore, by performing the same processing as that for the power supply wiring on the ground wiring, the average value of the ground voltage fluctuation is obtained from the voltage variation waveform of the ground wiring for all circuit elements of the design target circuit. The average value of the ground voltage fluctuation can be stored in the average voltage fluctuation value storage unit 25.

  Also in the case of the voltage fluctuation waveform and the voltage change amount average value calculating means 20, the average value of the power supply voltage fluctuation is obtained from the voltage change waveform of the power supply wiring, and the average of the ground voltage fluctuation is obtained from the voltage change waveform of the ground wiring. Although the case of obtaining a value has been described, the present invention is not limited to this, and either an average value of power supply voltage fluctuations or an average value of ground voltage fluctuations for each circuit element of the circuit to be designed may be obtained. In this case, if the table creation means 10 obtains the delay change with respect to the voltage change of the power supply wiring (VDD side), the voltage fluctuation waveform and the voltage change amount average value calculation means 20 obtain the average value of the power supply voltage fluctuation, and the table If the creation means 10 obtains the delay change with respect to the voltage change of the ground wiring, the voltage fluctuation waveform and voltage change amount average value calculation means 20 needs to obtain the delay change with respect to the ground wiring voltage change.

  Next, the operation of the delay variation calculation means 30 shown in FIG. 1 will be described in detail.

  In the delay fluctuation amount calculation means 30, a value (including an absolute value) obtained by subtracting the average value of the voltage fluctuation amount of the power supply voltage fluctuation waveform and / or the ground wiring voltage fluctuation waveform from the ideal power supply voltage value or / and the ideal ground voltage value. For the case where the operating voltage is given, the delay variation of the circuit element is calculated with reference to the reference table.

  That is, paying attention to the power supply voltage, in the reference table fetching unit 31 shown in FIG. 1, for each circuit element of the target circuit, the average power supply voltage fluctuation value stored in the average voltage fluctuation value storage unit 25 shown in FIG. The delay fluctuation amount and the output transition time are extracted from the power supply voltage change amount ΔVDD, the input transition time, and the delay fluctuation amount and the output transition time stored in the reference table 13 shown in FIG. Here, for the circuit element A (cell A) of interest, the power supply voltage change amount ΔVDD, the delay variation amount with reference to the input transition time and the output load capacitance, and the output transition time are extracted from the reference table 13. Furthermore, since the waveform is propagated from each logic gate to the logic gate of the next stage, the output transition time of the preceding cell is set as the input transition time of the next cell. Therefore, for the next stage circuit element B whose output transition time is the input transition time of the circuit element A, the delay variation amount and the output transition time with reference to the power supply voltage change amount ΔVDD, the input transition time and the output load capacitance are referred to Taken from the table. Similarly, the delay variation amount and the output transition time with reference to the power supply voltage change amount ΔVDD, the input transition time, and the output load capacitance are extracted from the reference table for all the cells (circuit elements) in the subsequent stage.

  Further, the delay variation / output transition time calculation unit 32 refers to the extracted reference table information (the above-mentioned voltage variation, input transition time, and output transition time information for each of the delay variation and output transition capacity), and performs the target design. A delay fluctuation amount of the circuit element corresponding to the average power supply voltage fluctuation value, input transition time, and output load capacitance delay fluctuation amount for each circuit element of the circuit is calculated. In short, from the average power supply voltage fluctuation value of the target design circuit, the input transition time and the output load capacitance delay fluctuation amount closest to the output load capacity delay fluctuation amount, the power supply voltage change amount ΔVDD, the input transition time and the output load capacitance delay fluctuation amount stored in the reference table 13 The delay fluctuation amount corresponding to the average power supply voltage fluctuation value is obtained by interpolation by proportional calculation.

  The delay variation amounts of all the cells obtained in this way are stored in the delay variation storage unit 33 shown in FIG.

  Further, by performing the same processing as that for the power supply wiring on the ground wiring, the delay fluctuation amount with respect to the voltage change amount ΔVSS of the ground wiring is calculated by the delay fluctuation amount / output transition time calculating unit 32, and the delay fluctuation is calculated. It can be stored in the quantity storage unit 33.

  Next, the operation of the total delay time calculation means 40 shown in FIG. 1 will be described in detail.

  The total delay time calculation means 40 adds the calculated delay variation amount of the circuit element to the delay value when the timing analysis is performed at the ideal power supply voltage or / and the ideal ground voltage, to thereby change the power supply voltage variation or / and the ground. The delay time considering the voltage fluctuation is calculated.

  In the total delay time calculation unit 41, the delay variation amount considering the power supply voltage variation stored in the delay variation amount storage unit 33 is separately obtained by using a timing analysis method with a normal ideal power supply voltage and / or an ideal ground voltage. The calculated delay time is added to the delay time stored in the timing analysis result storage unit 411 to obtain a delay time in consideration of the delay variation due to the power supply voltage variation and / or the ground voltage variation. By performing this process for all elements (cells), a total delay time can be obtained in consideration of delay variation due to power supply voltage variation.

  Hereinafter, an example of delay accuracy improvement by the circuit operation verification apparatus 1 of the present embodiment will be described in detail with reference to FIGS.

  For the layout data designed so that the peak power supply voltage drop is 25% or less of the VDD voltage, an inverter element as shown in FIG. 12 is considered as a circuit element included in the layout data.

  FIG. 13 shows the delay when the peak power supply voltage drop amount is ΔVpeak, the voltage value obtained by subtracting it from the power supply voltage VDD is Vpeak, and the Vpeak is the operating voltage, as the delay at the peak power supply voltage. Vpeak does not depend on the operating frequency and is constant. Further, in FIG. 11, with respect to ΔVpeak, the average power supply voltage drop amount Δavg is obtained for each frequency, and the delay when the voltage value Vavg obtained by subtracting it from the power supply voltage VDD is used as the operating voltage is the delay at the average power supply voltage. As shown. Further, FIG. 13 shows the delay improvement rate by the circuit operation verification apparatus 1 of the present embodiment in which Vavg is the operating voltage with respect to the delay when the above Vpeak is the operating voltage. Here, the delay improvement rate is an improvement rate of accuracy when an excessive delay estimation is performed more than necessary using Vpeak, and is an average power supply voltage with respect to a delay when the peak power supply voltage is used as an operating voltage. It shows the improvement rate of overestimation of delay when operating voltage is used. In the case of FIG. 13, it can be seen that the accuracy is improved by a maximum of 96.2% when the frequency is 50 MHz, for example.

  FIG. 14 shows the delay at the time of the average power supply voltage shown in FIG. 13 as the element delay on the first Y axis, and also shows the delay improvement rate shown in FIG. 13 on the second Y axis, and graphs these changes with respect to the frequency. It is.

  As shown in FIG. 13 and FIG. 14, according to the circuit operation verification apparatus 1 of the present embodiment, by using Vavg, it is possible to greatly improve the estimation of excessive delay more than necessary as compared with the case of using Vpeak. Thus, the delay of the circuit operation can be accurately verified.

  As described above, according to the above embodiment, the voltage fluctuation waveform and the average value calculation unit 20 of the voltage change amount obtain the current waveform when the target design circuit is switched by the circuit simulation, and the current is added to the resistance network of the wiring extracted separately. By adding it as a source, a dynamic voltage change is analyzed with high speed and accuracy to obtain a dynamic voltage fluctuation waveform, and an average value of the voltage fluctuation amount is obtained from the voltage fluctuation waveform. Further, in the table creating means 10, the delay variation amount of the circuit element for each operating voltage is created in advance as a reference table, and the average value of the voltage variation amount (voltage drop amount) is determined by referring to the reference table. Whether or not the target design circuit malfunctions can be verified with high speed and high accuracy by the delay variation of the circuit element due to the voltage variation when the value subtracted from the voltage is given as the operating voltage.

  Although not particularly described in the above embodiment, the table generation means 10 for generating the delay variation amount of the circuit element with respect to the voltage change amount as a reference table, and the current source model obtained by obtaining the current waveform when the circuit is switched. The wiring resistance network is extracted from the circuit layout data, the current source model is added to the extracted wiring resistance network, and a transient analysis is performed to obtain a dynamic voltage fluctuation waveform. Voltage fluctuation waveform and voltage change amount average value calculating means 20 for calculating the average value of the fluctuation waveform, and a case where a value obtained by subtracting the average value of the voltage fluctuation amount of the voltage fluctuation waveform from the ideal voltage value is given as an operating voltage. The delay variation calculation means 30 for calculating the delay variation of the element with reference to the reference table, and the calculated delay variation of the circuit element at the ideal voltage. If it has the total delay time calculation means 40 added to the delay value in the case of the analysis, it is possible to determine whether or not the target design circuit malfunctions due to the delay variation of the circuit element due to the power supply voltage variation. The object of the present invention can be achieved.

  In the above embodiment, the case where the average value of the voltage fluctuation amount of the voltage fluctuation waveform is the average voltage value in the waveform area of the voltage fluctuation waveform has been described. It may be an average value of the minimum fluctuation voltage.

  Further, although not particularly described in the above-described embodiment, the circuit of the first embodiment until the layout of the circuit element of the target circuit that does not malfunction (the malfunction occurs when the total delay time exceeds one clock cycle) is obtained. By verifying the circuit operation using the operation verification apparatus 1, circuit information including the layout of the circuit elements of the good target circuit is quickly and accurately obtained, and the semiconductor integrated circuit is designed based on the circuit information. By using the resist pattern patterned by the above, it is possible to manufacture a stable semiconductor integrated circuit that has a high yield and does not malfunction.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

   The present invention is a circuit operation verification apparatus that verifies delay variation of a circuit element due to voltage fluctuation of a power supply wiring when designing an LSI using an automatic placement and routing method of a standard element, and is designed using this circuit operation verification apparatus. Semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit using the obtained data, circuit operation verification method using the circuit operation verification apparatus, control program for causing a computer to execute the circuit operation verification method, and the program In the field of computer-readable readable recording media, in LSI design using automatic placement and routing of standard cells, the relationship between the amount of power supply voltage change due to switching and the delay change is accurately determined by circuit simulation, and is previously stored for each element type. By registering and registering, it is possible to achieve high performance without performing circuit simulation for each net. It is possible to perform a delay analysis considering power supply voltage fluctuation.

  In addition, the switching power source current waveform at the ideal power source is used as a current source model and applied to a separately extracted power source wiring resistor network to perform a transient analysis, thereby obtaining a power source voltage fluctuation waveform. The accuracy of a commercial CAD tool that calculates the delay by giving the peak voltage drop amount as the operating voltage by giving the voltage obtained by subtracting the average value of the power source voltage fluctuation amount obtained from the power supply voltage fluctuation waveform from the ideal voltage as the operating voltage. Can be improved.

  Furthermore, by referring to a table created in advance by circuit simulation, it is possible to perform delay analysis considering delay variation due to power supply voltage variation at a higher speed than performing analysis each time using circuit simulation. .

It is a block diagram which shows the principal part structural example of the circuit operation verification apparatus which concerns on embodiment of this invention. It is a block diagram which shows the principal part hardware structural example of the circuit operation verification apparatus of FIG. It is a circuit diagram which shows an example of an inverter element. It is a flowchart for demonstrating the process sequence of the table preparation means of FIG. It is a wave form diagram which shows the change of the input-output waveform with respect to the power supply voltage change of the inverter element shown in FIG. It is a figure which shows an example of the delay fluctuation reference table produced in the circuit simulation implementation part of FIG. 3 is a flowchart for explaining a processing procedure for obtaining an average value of a power supply voltage fluctuation waveform and a power supply voltage change amount in the power supply voltage fluctuation waveform and power supply voltage change amount average value calculating means of FIG. It is a wave form diagram which shows an example of the switching power supply current waveform computed by the transient analysis part of FIG. It is a top view which shows the mask layout result of the whole semiconductor integrated circuit containing a logic circuit. FIG. 10 is an equivalent circuit diagram for voltage change analysis by the current source and resistance of FIG. 9. It is a wave form diagram which shows an example of the switching power supply voltage waveform calculated by the transient analysis part of FIG. It is a figure which shows the example of a circuit for demonstrating the improvement effect by the circuit operation verification apparatus of embodiment of this invention. FIG. 13 is a diagram for comparing delays when the peak power supply voltage and the average power supply voltage are used for the circuit shown in FIG. 12. FIG. 13 is a diagram illustrating the delay estimation when using the average power supply voltage and the improvement rate of the delay estimation when using the peak power supply voltage for the circuit shown in FIG. 12.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit operation verification apparatus 10 Table preparation means 11 Circuit information and circuit simulation condition storage part for every element classification 12 Circuit simulation execution part 13 Reference table storage part
20 Voltage Fluctuation Waveform and Voltage Change Average Mean Calculation Unit 21 Wiring Resistance Extraction Unit 211 Resistance Extraction Data Storage Unit 22 Transient Analysis Unit 221 Switching Current Waveform Storage Unit 23 Voltage Fluctuation Waveform Storage Unit 24 Voltage Change Amount Average Value Calculation Unit 241 Clock cycle storage section 25 Average voltage fluctuation value storage section 30 Delay fluctuation amount calculation means 31 Reference table extraction section 32 Delay fluctuation amount / output transition time calculation section 33 Delay fluctuation amount storage section 40 Total delay time calculation means 41 Total delay time calculation Section 411 Timing analysis result storage section

Claims (43)

A circuit operation verification device that verifies a delay fluctuation amount when a circuit voltage is changed with respect to a circuit element constituting a semiconductor integrated circuit by an average power supply voltage fluctuation amount in consideration of a delay fluctuation due to noise,
A current source model is created by obtaining a current waveform when the target circuit is switched, a wiring resistance network is extracted from the layout data of the target circuit, and the current source model is added to the extracted wiring resistance network. A voltage fluctuation waveform and a voltage change amount average value calculating means for obtaining a dynamic voltage fluctuation waveform by performing a transient analysis and calculating an average value of the voltage fluctuation waveform or an average value of the voltage fluctuation amount of the voltage fluctuation waveform;
A table creating means for creating a delay variation amount of the circuit element for each voltage variation amount of the voltage variation waveform as a reference table;
When the average value of the voltage fluctuation waveform is used as the operating voltage or the value obtained by subtracting the average value of the voltage fluctuation amount from the ideal voltage value is given as the operating voltage, the delay fluctuation amount for each circuit element of the target circuit is calculated. A delay variation calculating means for calculating with reference to the reference table;
A circuit operation verification device having total delay time calculation means for calculating the total delay time of the target circuit by sequentially adding the calculated delay variation of the circuit element to the delay value when the timing analysis is performed at the ideal voltage . The voltage fluctuation waveform and the voltage change amount average value calculating means are:
A current source model is created by obtaining a power source current waveform when the target circuit is switched, a power supply wiring resistance network is extracted from the layout data of the target circuit, and the current source model is extracted from the extracted power supply wiring resistance network. The dynamic power supply voltage fluctuation waveform is obtained by performing transient analysis in addition, and the average value of the power supply voltage fluctuation waveform or the average value of the power supply voltage fluctuation amount of the power supply voltage fluctuation waveform is calculated. Circuit operation verification device. The voltage fluctuation waveform and the average value calculation means of the voltage change amount are:
A current source model is created by obtaining a ground current waveform when the target circuit is switched, a resistance network of the ground wiring is extracted from the layout data of the target circuit, and the current source model is extracted from the extracted resistance network of the ground wiring. A dynamic ground wiring voltage fluctuation waveform is obtained by performing transient analysis in addition, and an average value of the ground wiring voltage fluctuation waveform or an average value of the ground wiring voltage fluctuation amount of the ground wiring voltage fluctuation waveform is calculated. The circuit operation verification apparatus according to 1.   The circuit operation verification device according to claim 2, wherein the table creation unit creates a delay variation amount of the circuit element for each power supply voltage variation amount of the power supply voltage variation waveform as a reference table.   The circuit operation verification device according to claim 3, wherein the table creation unit creates a delay variation amount of the circuit element for each ground wiring voltage variation amount of the ground wiring voltage variation waveform as a reference table.   The delay fluctuation amount calculating means uses the average value of the power supply voltage fluctuation waveform as an operating voltage, or uses the value obtained by subtracting the average value of the power supply voltage fluctuation amount from the ideal power supply voltage value as the operating voltage. The circuit operation verification device according to claim 4, wherein the delay variation amount for each circuit element of the target circuit is calculated with reference to the reference table.   The delay fluctuation amount calculation means uses the average value of the ground wiring voltage fluctuation waveform as the operating voltage or gives the value obtained by subtracting the average value of the ground wiring voltage fluctuation amount from the ideal ground voltage value as the operating voltage. The circuit operation verification device according to claim 5, wherein the delay fluctuation amount for each circuit element of the target circuit is calculated with reference to the reference table.   7. The circuit operation verification according to claim 6, wherein the total delay time calculation means sequentially adds the calculated delay variation amount for each circuit element of the target circuit to a delay value when timing analysis is performed at an ideal power supply voltage. apparatus.   8. The circuit operation verification according to claim 7, wherein the total delay time calculation means sequentially adds the calculated delay variation amount for each circuit element of the target circuit to a delay value when timing analysis is performed at an ideal ground voltage. apparatus.   3. The voltage fluctuation waveform and voltage change amount average value calculating means further includes a wiring resistance network extraction unit that extracts a wiring resistance network from layout data of the target circuit using a parasitic circuit component extraction tool. 4. The circuit operation verification device according to 3.   The voltage fluctuation waveform and the voltage change amount average value calculating means connect the ideal power supply voltage output terminal or / and the ground wiring voltage output terminal to each logic gate of the target circuit, and obtain a switching current obtained by performing circuit simulation. The circuit operation verification apparatus according to claim 2, wherein a waveform is used as the current source model.   The voltage fluctuation waveform and voltage change amount average value calculating means adds the current source model to the extracted power supply wiring or / and ground wiring resistance network and performs a transient analysis to obtain the dynamic voltage fluctuation waveform. The circuit operation verification device according to claim 10, further comprising a transient analysis unit.   The voltage fluctuation waveform and the voltage fluctuation amount average value calculation means further include a voltage fluctuation waveform storage unit for storing a power supply voltage fluctuation waveform and / or a ground wiring voltage fluctuation waveform as the voltage fluctuation waveform. Circuit operation verification device.   The voltage fluctuation waveform and the voltage change amount average value calculating means time-integrates the voltage waveform per one clock cycle, and divides the time-integrated voltage waveform by a time required for one cycle, thereby obtaining the power supply voltage fluctuation waveform. 14. The circuit operation verification device according to claim 12, further comprising a voltage change amount average value calculation unit that calculates an average value of voltage change amounts of the ground wiring voltage fluctuation waveform.   15. The circuit operation verification device according to claim 14, wherein the voltage fluctuation waveform and voltage change amount average value calculation means includes an average voltage change value storage unit that stores an average value of the voltage change amount.   The circuit operation verification device according to claim 4, wherein the table creation unit includes a circuit information / circuit simulation condition storage unit that stores circuit information and circuit simulation conditions for each element type.   The circuit operation verification device according to claim 16, wherein the table creation unit includes a circuit simulation execution unit that creates the reference table by circuit simulation based on circuit information for each element type and the circuit simulation condition.   The circuit simulation execution unit, for each element type, an operation voltage change amount with respect to an ideal voltage as the circuit simulation condition, an input transition time and an output load capacitance value, a delay change amount per circuit element and an output transition 18. The circuit operation verification device according to claim 17, wherein time is obtained, and the obtained delay change amount and output transition time are created as the reference table and stored in the table storage unit.   The delay fluctuation amount calculating means is configured to determine, from the reference table, an average value of the voltage fluctuation waveform or a voltage fluctuation amount corresponding to the average value of the voltage fluctuation amount, an input transition time, and a delay fluctuation amount and an output transition time for the output load capacity The circuit operation verification apparatus according to claim 6, further comprising a reference table extraction unit for extracting the reference table.   20. The circuit operation verification device according to claim 19, wherein the delay variation calculation means includes a delay variation / output transition time calculator that calculates a delay variation and an output transition time of a circuit element with reference to the reference table. .   21. The circuit operation verification device according to claim 20, wherein the delay variation / output transition time calculation unit refers to the reference table using the output transition time of the previous circuit element as the input transition time of the next circuit element.   The circuit operation verification device according to claim 20 or 21, wherein the delay variation calculation means further includes a delay variation storage unit for storing the calculated delay variation.   The total delay time calculating means calculates the delay fluctuation amount considering the voltage fluctuation stored in the delay fluctuation amount storage section separately using a timing analysis method with a normal ideal voltage, and the timing analysis result storage section To obtain the delay time in consideration of the delay variation due to the voltage variation, and by performing this process for all the circuit elements of the target circuit, the total delay in consideration of the delay variation due to the voltage variation. The circuit operation verification device according to claim 22, further comprising a total delay time calculation unit for obtaining time.   The average value of the voltage fluctuation waveform is an average voltage value in a waveform area of the voltage fluctuation waveform as an average value of the voltage fluctuation amount, or an average value of a maximum fluctuation voltage and a minimum fluctuation voltage of the voltage fluctuation waveform. Item 4. The circuit operation verification device according to Item 1.   The circuit operation verification device according to claim 1, wherein the delay variation due to noise is a delay variation when the target circuit or a target circuit element included in the target circuit is switched.   The delay fluctuation amount calculating means has a reference table closest to the circuit simulation condition including the average value of the voltage fluctuation waveform of the target design circuit calculated by the voltage fluctuation waveform and the voltage change amount average value calculating means. The circuit simulation condition including the voltage change amount and the delay fluctuation amount at that time are read out, and the circuit simulation condition including the voltage change amount of the read reference table and the voltage fluctuation waveform and the voltage change amount average value calculation unit are calculated. 2. The circuit according to claim 1, wherein a delay variation amount of the circuit element with respect to a voltage change for each circuit element of the target design circuit is calculated by proportional calculation from a difference from a circuit simulation condition including an average value of a voltage variation waveform of the target design circuit. Operation verification device.   27. The circuit operation verification device according to claim 26, wherein the circuit simulation condition includes a voltage change amount, an input transition time, and an output additional capacitance.   A method for manufacturing a semiconductor integrated circuit, wherein a semiconductor integrated circuit is manufactured using a resist pattern patterned based on circuit information for which circuit operation verification processing has been completed using the circuit operation verification apparatus according to claim 1. A circuit operation verification method for verifying an amount of delay variation when a voltage changes for a circuit element constituting a semiconductor integrated circuit, based on an average voltage variation amount in consideration of delay variation due to noise,
The voltage fluctuation waveform and the voltage change amount average value calculating means obtain a current waveform when the target circuit is switched, create a current source model, extract a wiring resistance network from the layout data of the target circuit, and extract A voltage fluctuation waveform and a voltage change amount average value calculating step for calculating a dynamic voltage fluctuation waveform by adding the current source model to the resistance network of the wiring and performing a transient analysis, and calculating an average value of the voltage fluctuation waveform; ,
A table creating step for creating a delay variation amount of the circuit element for each voltage change amount as a reference table;
When the delay fluctuation amount calculating means gives the value obtained by subtracting the average value of the voltage fluctuation waveform from the ideal voltage value as the operating voltage, the delay fluctuation amount for each circuit element of the target circuit is referred to the reference table. A delay variation calculating step to calculate
A total delay time calculating step in which the total delay time calculating means calculates the total delay time of the target circuit by adding the calculated delay variation of the circuit element to a delay value when timing analysis is performed at an ideal voltage; A circuit operation verification method comprising: The voltage fluctuation waveform and voltage change amount average value calculating step calculates a power source current waveform when the target circuit is switched, creates a current source model, and extracts a resistance network of the power wiring from the layout data of the target circuit Then, a dynamic power supply voltage fluctuation waveform is calculated by adding the current source model to the extracted resistance network of the power supply wiring and performing a transient analysis to obtain an average value of the power supply voltage fluctuation waveform or the power supply voltage fluctuation waveform Calculate the average power supply voltage fluctuation amount of
The table creation step creates a delay variation amount of the circuit element for each power supply voltage variation amount of the power supply voltage variation waveform as a reference table,
In the delay fluctuation amount calculating step, the average value of the power supply voltage fluctuation waveform is used as the operating voltage, or a value obtained by subtracting the average value of the power supply voltage fluctuation amount from the ideal power supply voltage value is used as the operating voltage in the circuit element of the target circuit. For the given case, the delay variation amount for each circuit element of the target circuit is calculated with reference to the reference table,
30. The circuit operation verification method according to claim 29, wherein the total delay time calculation step sequentially adds the calculated delay fluctuation amount for each circuit element of the target circuit to a delay value when timing analysis is performed at an ideal power supply voltage. . The voltage fluctuation waveform and voltage change amount average value calculating step calculates a ground current waveform when the target circuit is switched, creates a current source model, and extracts a ground wiring resistance network from the layout data of the target circuit. Then, by adding the current source model to the extracted ground wiring resistance network and performing a transient analysis, a dynamic ground wiring voltage fluctuation waveform is calculated, and an average value of the ground wiring voltage fluctuation waveform or the ground wiring is calculated. Calculate the average value of the ground wiring voltage fluctuation amount of the voltage fluctuation waveform,
The table creation step creates a delay variation amount of the circuit element for each ground wiring voltage variation amount of the ground wiring voltage variation waveform as a reference table,
The delay fluctuation amount calculating step is performed when the average value of the ground wiring voltage fluctuation waveform is used as the operating voltage or a value obtained by subtracting the average value of the ground wiring voltage fluctuation quantity from the ideal ground voltage value is given as the operating voltage. The delay variation amount for each circuit element of the target circuit is calculated with reference to the reference table,
31. The circuit operation according to claim 29, wherein the total delay time calculating step sequentially adds the calculated delay fluctuation amount for each circuit element of the target circuit to a delay value when timing analysis is performed at an ideal ground voltage. Method of verification.   30. The power supply voltage fluctuation waveform and voltage change amount average value calculating step includes: a wiring resistance network extraction unit extracting a wiring resistance network from layout data of the target circuit using a parasitic circuit component extraction tool. 31. The circuit operation verification method according to any one of 31.   The voltage fluctuation waveform and the voltage change amount average value calculating step include a switching current waveform obtained by connecting the ideal power supply output terminal or / and the ground wiring voltage output terminal to each logic gate of the target circuit and performing circuit simulation. 33. The circuit operation verification method according to claim 29, wherein the circuit operation verification method is used as the current source model.   In the step of calculating the voltage fluctuation waveform and the voltage change amount average value, the transient analysis unit adds the current source model to the extracted resistance network of the power supply wiring and / or the ground wiring and performs a transient analysis to perform the dynamic analysis. The circuit operation verification method according to claim 32 or 33, wherein a voltage fluctuation waveform is obtained and the voltage fluctuation waveform is stored in a voltage fluctuation waveform storage unit.   In the voltage fluctuation waveform and voltage change amount average value calculating step, the voltage change amount average value calculating unit time-integrates the voltage waveform per clock cycle, and the time-integrated voltage waveform is calculated in a time required for one cycle. 35. The circuit operation verification method according to claim 34, wherein by dividing, an average value of a voltage change amount of the power supply voltage fluctuation waveform and / or ground wiring voltage fluctuation waveform is calculated and stored in an average voltage fluctuation value storage unit.   32. The table creation step further includes a circuit simulation execution step in which a circuit simulation execution unit creates the reference table by circuit simulation based on circuit information for each element type and the circuit simulation conditions. The circuit operation verification method according to any one of the above.   The circuit simulation execution step includes, for each element type, an operation voltage change amount with respect to an ideal voltage as the circuit simulation condition, a delay change amount per circuit element and an output transition with respect to an input transition time and an output load capacitance value. The circuit operation verification method according to claim 36, wherein time is obtained, and the obtained delay change amount and output transition time are created as the reference table and stored in the table storage unit.   In the delay fluctuation amount calculating step, the reference table extraction unit is configured to calculate, from the reference table, an average value of the voltage fluctuation waveform or a voltage change amount corresponding to an average value of the voltage fluctuation amount, an input transition time, and an output load capacity. 32. The circuit operation verification method according to claim 29, wherein the delay variation amount and the output transition time information are extracted.   39. The circuit according to claim 38, wherein in the delay variation calculation step, the delay variation / output transition time calculation section refers to the reference table with the output transition time of the previous circuit element as the input transition time of the next circuit element. Operation verification method.   In the delay variation calculation step, the delay variation / output transition time calculation unit refers to the reference table, calculates the delay variation and output transition time of the circuit element, and stores them in the delay variation storage unit. Item 40. The circuit operation verification method according to Item 38 or 39.   In the total delay time calculating step, the total delay time calculation unit separately calculates a delay fluctuation amount considering the voltage fluctuation stored in the delay fluctuation amount storage unit by using a timing analysis method with a normal ideal voltage. By adding to the delay time stored in the timing analysis result storage unit, the delay time for each circuit element taking into account the delay fluctuation due to voltage fluctuation is obtained, and this processing is performed for all the circuit elements of the target circuit. 41. The circuit operation verification method according to claim 40, wherein a total delay time in consideration of delay variation due to voltage variation is obtained.   A control program in which a processing procedure for causing a computer to execute each step of the circuit operation verification method according to any one of claims 29 to 41 is described.   43. A computer readable storage medium storing the control program according to claim 42.

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