JPH04309179A - Automatic correcting system for minimum delay time error - Google Patents

Abstract

PURPOSE:To obtain the automatic correcting system of minimum delay time error for a high-speed and large-scale logic circuit. CONSTITUTION:A path detecting means 14 is provided to detect a data path having the output terminal of a flip-flop on a logic circuit model as the start point and the input terminal of the flip-flop as the end point, a minimum delay time calculating means 15 is provided to calculate the minimum delay time of the data path calculated by the path detecting means 14, a limit value comparing means 17 is provided to compare the minimum delay time calculated by the minimum delay time calculating means 15 with a limit value decided in advance, a delay buffer inserting rule selecting means 19 is provided to select the kind and number of delay buffers to be inserted into the error path, which minimum delay time is judged lower than the limit value by the limit value comparing means 17, for guaranteeing the minimum delay time based on difference from the limit value concerning the error path, an error path display means 20 is provided to display the error path, and an exceptional path display means 21 is provided to display the error path out of a processing object.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to minimum delay time verification during logic circuit design, and in particular to verification of minimum delay time and correction of error paths in data paths of large-scale logic circuits intended to operate at high speed. The present invention relates to an automatic correction system for minimum delay time errors in logic circuits.

0002

[Prior Art] Conventionally, there has been no automatic correction system for minimum delay time errors in logic circuits.As a minimum delay time verification system, the minimum delay time for a data path in a logic circuit is calculated, and when an error path is discovered, , only displayed the error path. (For example, see Proceedings of the Information Processing Society of Japan's 35th National Conference, "Timing Analysis System for Large-Scale Circuits HEART," pages 2275-2276.)

[Problems to be Solved by the Invention] In the correction of error paths using the conventional minimum delay time verification system described above, when a large number of error paths are discovered in a complex and large-scale logic circuit, it is difficult to correct individual error paths. However, in order to guarantee the minimum delay time, it is difficult to manually consider the optimal combination of the type and number of delay buffers to be inserted into the error path. The type and number of delay buffers were uniform. This method of correcting the minimum delay time requires extremely high-speed operation and in designing large-scale logic circuits.
There is a problem in that it is not possible to guarantee a common minimum delay time for all error paths, and new measures are required to deal with contradictions caused by insertion.

[0003] The purpose of the present invention is to solve the above-mentioned problems.
An automatic correction system for minimum delay time errors for high-speed, large-scale logic circuits by finding the optimal combination of types and numbers of delay buffers to be inserted into error paths in order to guarantee the minimum delay time for each error path. Our goal is to provide the following.

0004

[Means for Solving the Problems] The minimum delay time error automatic correction system of the present invention provides data that is a path starting from the output terminal of a flip-flop on a logic circuit model and ending at the input terminal of the flip-flop. path detection means for detecting a path; minimum delay time calculation means for calculating the minimum delay time of the data path obtained from the path detection means; and a minimum delay time obtained from the minimum delay time calculation means. a limit value comparison means for comparing the minimum delay time with the limit value, and a limit value comparison means for comparing the minimum delay time with the limit value based on the difference between the error path and the limit value, which is a data path for which the minimum delay time is determined to be less than the limit value by the limit value comparison means; delay buffer insertion rule selection means for selecting the type and number of delay buffers to be inserted into the error path in order to ensure that the delay time is greater than the limit value; error path display means for displaying the error path; This configuration includes an exception path display means for displaying an error path that is not a target.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of an automatic minimum delay time error correction system for a logic circuit according to an embodiment of the present invention.

The minimum delay time error correction system for logic circuits of this embodiment includes a logic circuit model file 1, a logic circuit component library 2, a limit value library 3, a delay buffer insertion rule file 4, and a logic circuit model. loading means 5; logic circuit component loading means 6;
Limit value loading means 7, delay buffer insertion rule loading means 8, logic circuit model assembly means 9, logic circuit model table 10, and logic circuit component table 11
, a limit value table 12, a delay buffer insertion rule table 13, a path detection means 14, a minimum delay time calculation means 15, a path delay time table 16, a limit value comparison means 17, a difference storage table 18, It is configured to include a delay buffer insertion rule selection means 19, an error path display means 20, and an exception path display means 21.

[0008] Logic circuit model file 1 is a wiring configuration (hereinafter used as an expression of a combination of starting and ending points of wiring) for each wiring that connects each component in a logic circuit (hereinafter used as a general term for flip-flops and delay buffers). and the wiring delay time.

The logic circuit component library contains components that are connected by wiring in a logic circuit and the circuit configuration of components that can be used in a logic circuit (hereinafter, the connection status between terminals existing on the component and the connection between the terminals). (Used as a generic term for delay time) is stored.

The limit value library 3 stores limit values for minimum delay times for data paths.

The delay buffer insertion rule file 4 stores the type and number of delay buffers to be inserted into the error path based on the difference between the minimum delay time in the error path and the limit value.

The logic circuit model loading means 5 reads the wiring connection state between components in the logic circuit and the delay time information of each wiring from the logic circuit model file 1, and registers it in the logic circuit model table 10.

The logic circuit component loading means 6 reads, from the logic circuit component library 2, circuit configurations for components that are actually implemented in the logic circuit and components that can be mounted in the logic circuit, and registers them in the logic circuit component table 11.

The limit value loading means 7 reads the limit value of the minimum delay time for the data path of the logic circuit from the limit value library 3 and sets it in the limit value table 12.

Delay buffer insertion rule loading means 8
reads the type and number of delay buffers to be inserted into the error path based on the difference between the minimum delay time of the error path in the logic circuit and the limit value from the delay buffer insertion rule file 4, and sets it in the delay buffer insertion rule table 13. .

The logic circuit model assembling means 9 uses the wiring connection state information and delay time information for each wiring in the logic circuit stored in the logic circuit model table 10, and the information stored in the logic circuit component table 11 and mounted in the logic circuit. A logic circuit model is created based on the circuit configuration of the component, which also takes into account the connections within the component in the logic circuit, and is set in the logic circuit model table 10.

The path detecting means 14 finds a data path for each flip-flop input terminal from the logic circuit model table 10 and sets it in the path delay time table 16.

The minimum delay time calculation means 15 calculates the minimum delay time of the data path found by the path detection means 14 and sets it in the path delay time table 16.

The limit value comparing means 17 compares the minimum delay time information of the data path stored in the path delay time table 16 with the limit value of the minimum delay time for the data path stored in the limit value table 12. If the minimum delay time of the data path is smaller than the limit value, the corresponding data path is determined to be an error path, and the difference between the limit value and the minimum delay time of the path is registered in the difference storage table 18.

Delay buffer insertion rule selection means 19
is activated by the limit value comparison means 17 and is calculated based on the difference between the minimum delay time of the error path and the limit value from the set of rules for guaranteeing the minimum delay time error registered in the delay buffer insertion rule table 13. , select the rule to be applied to guarantee the minimum delay time error for the corresponding error path.

The error path display means 20 is activated by the delay buffer insertion rule selection means 19, and based on the information registered in the path delay time table 16, the error path display means 20 displays the path information of the error path, its delay time information, and stores the difference. The difference between the minimum delay time of the error path registered in the table 18 and the limit value and the delay buffer insertion rule selection means 19
Outputs the contents of the rule applied to guarantee the minimum delay time for the error path found in .

The exception path display means 21 is activated by the delay buffer insertion rule selection means 19 when the combination of delay buffers required for the minimum delay time to be larger than the limit value cannot be found, and the exception path display means 21 is activated by the delay buffer insertion rule selection means 19 and displays the path delay time table. Based on the information registered in the error path 16, the difference between the path information of the error path and its delay time information, and the minimum delay time and limit value of the error path registered in the difference storage table 18 is displayed.

Next, the operation will be explained.

FIG. 2 is a flowchart of processing in the automatic correction system for minimum delay time errors for logic circuits of this embodiment.

Logic circuit model loading step 50, circuit component loading step 51, and limit value loading step 5
2 and delay buffer insertion rule loading step 53
, a logic circuit model assembly step 54 , a data path end determination step 55 , a path detection step 56 ,
Minimum delay time calculation step 57, error path determination step 58, error width calculation step 59, delay buffer insertion rule selection step 60, delay buffer configuration loading step 61, delay buffer insertion rule confirmation step 62, exception error It consists of a path display step 63 and an error path display step 64.

Next, the operation of the system for automatically correcting the minimum delay time error for the logic circuit of this embodiment configured as described above will be explained.

When the automatic correction system for the minimum delay time error for the logic circuit of this embodiment is started, the logic circuit model loading means 5 loads the wiring connection state between components in the logic circuit and each wiring from the logic circuit model file 1. The delay time information is read out and loaded into the logic circuit model table 10, and control is transferred to the logic circuit component loading means 6 (step 50).

The logic circuit component loading means 6 to which control has been transferred from the logic circuit model loading means 5 retrieves circuit configurations for components mounted in the logic circuit and components that can be mounted in the logic circuit from the logic circuit component library 2. The data is read and loaded into the logic circuit component table 11, and control is transferred to the limit value loading means 7 (step 51).

The limit value load means 7 to which the control has been transferred from the logic circuit load means 6 reads the limit value for the minimum delay time of the data path of the logic circuit from the limit value file 3, loads it into the limit value table 12, Control is transferred to the delay buffer insertion rule loading means 8 (step 52
).

The delay buffer insertion rule loading means 8 to which control has been transferred from the limit value loading means 7 extracts an error path from the delay buffer insertion rule file 4 based on the difference between the minimum delay time of the error path in the logic circuit and the limit value. The type and number of delay buffers to be inserted are read, loaded into the delay buffer insertion rule table 13, and control is transferred to the logic circuit model assembly means 9 (step 53).

Delay buffer insertion rule loading means 8
The logic circuit model assembly means 9 to which control has been transferred from
The circuit configuration of the component that is the end point of the wiring connection information registered in the logic circuit model table 10 is read from the logic circuit component table 11, registered in the logic circuit model table 10, and control is transferred to the path detection means 14 (step 54 )
.

The path detection means 14 to which control has been transferred from the logic circuit model assembly means 9 determines whether an unanalyzed data path exists in the logic circuit model table 10, and
If there is no unanalyzed data path, the process ends (step 55). In the above judgment, if it is determined that there is an unanalyzed error path in the logic circuit model table 10, one data path is extracted from the logic circuit model table 10, and a logic circuit model representing the extracted data path is created. After setting the analyzed flag in the table 10, control is transferred to the minimum delay time calculation means 15 (step 56).

The minimum delay time calculation means 15 to which the control is transferred from the path detection means 14 calculates the minimum delay time for the data path taken out by the path detection means 14, and stores the calculated minimum delay time in the path delay time table 16. Then, control is transferred to the limit value comparison means (step 57).

The limit value comparison means 17 to which the control is transferred from the minimum delay time calculation means 15 is
The minimum delay time of the data path stored in the path delay time table 16 is compared with the minimum delay time limit value stored in the limit value table 12, and if the minimum delay time is greater than the limit value, the process is performed in step 55 (step 58).

If the minimum delay time is smaller than the limit value, the difference between the limit value and the minimum delay time is calculated, the calculated difference is registered in the difference storage table 18, and then control is transferred to the delay buffer insertion rule selection means 19 ( Step 59).

The delay buffer insertion rule selection means 19 to which control is transferred from the limit value comparison means 17 determines the minimum delay based on the difference between the limit value stored in the difference storage table 18 and the minimum delay time of the error path. In order to guarantee time, the type and number of delay buffers to be inserted into the error path are determined from the delay buffer insertion rule table 13 (step 60).

Next, the circuit configuration of the delay buffer to be inserted into the error path is determined from the logic circuit component table 11 (step 61). When a delay buffer is inserted, the minimum delay time is calculated using the minimum delay time calculating means 15, and the minimum delay time is compared with the limit value registered in the limit value table 12. If the minimum delay time is larger than the limit value, control is transferred to the error path display means 20, and if the minimum delay time is smaller than the limit value, the difference between the limit value and the minimum delay time is registered in the difference storage table 18. The value with the added content is registered in the difference storage table 18, and the process returns to step 60 (step 62).

In the processing from step 60 to step 62, if a delay buffer for which the minimum delay time becomes larger than the limit value cannot be found, it is assumed that it is impossible to guarantee the minimum delay time for the corresponding error path, and the path delay time is Based on the information registered in the table 16, the difference between the path information of the error path, the delay time information of the error path, and the minimum delay time and limit value of the error path registered in the difference storage table 18 is output. , the process returns to step 55. (Step 63).

Delay buffer insertion rule selection means 19
The error path display means 20 to which control has been transferred displays the path information of the error path, the delay time information of the error path, and the difference storage table 18 based on the information registered in the path delay time table 16. The difference between the minimum delay time of the error path and the limit value, and the contents of the rule to be applied to guarantee the minimum delay time for the error path, which are obtained by the delay buffer insertion rule selection means 19, are output, and the process is performed in step 55. (step 64).

[0040]

Effects of the Invention As explained above, the present invention achieves high speed processing by finding the optimal combination of the types and number of delay buffers to be inserted into error paths in order to guarantee the minimum delay time for each error path. It also has the effect of avoiding unnecessary insertion of delay buffers in guaranteeing minimum delay time errors for large-scale logic circuits, and preventing new problems (for example, occurrence of maximum delay time errors, etc.) caused by unnecessary insertion of delay buffers. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart illustrating processing for one embodiment of the present invention.

[Explanation of symbols]

1 Logic circuit model file 2 Logic circuit component library 3 Limit value library 4 Delay buffer insertion rule file 5
Logic circuit model loading means 6 Logic circuit component loading means 7 Limit value loading means 8 Delay buffer insertion rule loading means 9
Logic circuit model assembly means 10 Logic circuit model table 11 Logic circuit component table 12 Limit value table 13 Delay buffer insertion rule table 14
Path detection means 15 Minimum delay time calculation means 16 Path delay time table 17 Limit value comparison means 18 Difference storage table 19 Delay buffer insertion rule selection means 20
Error path display means 21 Exception path display means

Claims (1)

[Claims] 1. Path detection means for detecting a data path that is a path starting from an output terminal of a flip-flop on a logic circuit model and ending at an input terminal of the flip-flop; Minimum delay time calculation means for calculating the minimum delay time of the data path;
limit value comparison means for comparing the minimum delay time obtained from the minimum delay time calculation means with a predetermined limit value; and data for which the minimum delay time is determined to be less than the limit value from the limit value comparison means. Delay buffer insertion rule selection for selecting the type and number of delay buffers to be inserted into the error path to ensure that the minimum delay time is greater than the limit value based on the difference between the error path and the limit value. 1. A system for automatically correcting a minimum delay time error in a logic circuit, comprising: means for displaying the error path; and exception path display means for displaying the error path that is not to be processed.