JP2007323203A - Device and method for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and a method for designing a semiconductor integrated circuit which can replace a normal cell with a low power consumption cell in consideration of the margin of a cell arrangement area. <P>SOLUTION: In the device 1 for designing the semiconductor integrated circuit, a replacement cell candidate selection part 13 selects low power consumption cells as replacement cell candidates with respect to a normal cell extracted by a replacement object cell extraction part 12 as an object to be replaced with a low power consumption cell based on the analytic result of a timing analyzing part 11 to a netlist 200 designed in the normal cell, and a power consumption reduction effect analyzing part 14 ranks the low power consumption cells as replacement candidates in the order of the larger reduction quantity of power consumption due to replacement, and a replacement execution cell determination part 15 adds the increase quantity of a cell arrangement area in the order of the higher rank, and determines the low power consumption cell of a rank until it reaches cell arrangement area increase permissible quantity 140 as a replacement execution cell, and a cell replacement execution part 16 executes cell replacement based on the determination, and outputs a post-replacement netlist 300. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design apparatus and design method.

  Generally, in designing a large-scale semiconductor integrated circuit, a circuit function is realized by selecting and combining cells having a desired function from a cell library prepared in advance. In recent years, there is a strong demand for low power consumption for large-scale semiconductor integrated circuits designed in this way. Therefore, in many cases, a low power consumption cell is prepared in the cell library in addition to a normal cell so that the low power consumption cell can be used as necessary.

  Usually, such low power consumption cells often reduce power consumption by reducing the transistor size and the load driving power. Therefore, as one method of designing a semiconductor integrated circuit using such a low power consumption cell, after designing with a high power consumption cell having a large driving power at first, a timing margin is determined based on a timing verification result. A design method has been proposed in which only a certain path is replaced with a low power consumption cell with a small driving force (see, for example, Patent Document 1).

  On the other hand, some cells can reduce power consumption without reducing the load driving force. One of them is a flip-flop with a clock signal control function that stops input of a clock signal when an input signal and an output signal match (for example, refer to Patent Document 2).

  By using a flip-flop with a clock signal control function as a flip-flop having a low data transition rate of the input signal, power consumption accompanying a change in the clock signal can be greatly reduced.

  In addition to this, a cell with a high threshold transistor should be used in combination with an increase in power consumption due to an increase in leakage current due to a lower threshold of the transistor due to the recent lowering of the voltage of semiconductor integrated circuits. Thus, there has been proposed a semiconductor integrated circuit for reducing leakage current (see, for example, Patent Document 3).

  Therefore, in addition to the low power consumption low-power consumption cells, the above-mentioned flip-flops with clock signal control function and cells with high threshold transistors can be added to the low-power consumption cells for a wider variety of low power consumption measures. Can be taken.

  However, a cell having a flip-flop with a clock signal control function or a high threshold transistor tends to have a larger cell area than a normal cell. This is because a flip-flop with a clock signal control function requires a circuit for clock signal control, and in a cell having a high threshold transistor, it is necessary to increase the transistor size in order to ensure driving power. by.

  On the other hand, low power consumption cells with a small driving force tend to have a smaller cell area than ordinary cells. For this reason, low power consumption cells with a small driving force that do not have a concern about an increase in chip area have been used exclusively in reducing power consumption of a semiconductor integrated circuit by conventional cell replacement.

  However, in recent large-scale semiconductor integrated circuits, a large-capacity memory is often mounted together with a logic circuit designed using the above-described cell library. In such a memory-embedded semiconductor integrated circuit, the chip size is often determined by the arrangement of the memory area, and the area of the logic circuit area often has a margin.

  In recent large-scale semiconductor integrated circuits, a large number of input / output pins are often used. In such semiconductor integrated circuits, the chip size is determined by the arrangement area of pads for connecting the input / output pins. Sometimes. Even in such a semiconductor integrated circuit, there is a margin in the area of the logic circuit region.

  In other words, it can be said that a semiconductor integrated circuit having a sufficient area in the logic circuit region can be replaced with a low power consumption cell having a large cell area.

However, in the conventional reduction of power consumption of a semiconductor integrated circuit by cell replacement, there is a problem that a low power consumption cell is not selected in consideration of a cell arrangement area margin.
JP 2002-342400 A (page 8-9, FIG. 1) Japanese Patent No. 3580736 (Page 5-6, FIG. 1) JP-A-8-18021 (page 3-4, FIG. 3)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit design apparatus and design method capable of replacing a normal cell with a low power consumption cell in consideration of a cell layout area margin.

  According to one aspect of the present invention, a normal cell and a low power consumption cell having a cell area larger than that of the normal cell and having a driving force equivalent to that of the normal cell and less power consumption than the normal cell are included. A semiconductor integrated circuit design apparatus for designing a logic circuit using a cell library, a timing analysis means for analyzing a timing of a logic circuit based on inputted design information, and a logic circuit designed using a normal cell Based on the analysis result of the timing analysis means, the replacement target cell extraction means for extracting normal cells constituting a path having a timing margin as a target to be replaced with the low power consumption cell, and the replacement target cell extraction means Replacement cell candidate selection means for selecting the low power consumption cell corresponding to the selected cell as a replacement cell candidate, and the replacement target cell extraction A reduction amount of the power consumption of the low power consumption cells selected by the replacement cell candidate selection unit with respect to the power consumption of the cells extracted by the stage is calculated, and the replacement cell candidate selection unit calculates the reduction amount in descending order. The power consumption reduction effect analyzing means for generating a list in which the selected low power consumption cells are ranked, and the increase amount of the cell layout area of the logic circuit when the low power consumption cells are replaced. Replacement that sequentially adds from the top and determines the low power consumption cells in the rank until the added value reaches the upper limit of the cell layout area increase allowed for the logic circuit as replacement execution cells that actually perform replacement An execution cell determination unit and a cell replacement execution unit that executes replacement from the normal cell to the low power consumption cell based on the determination of the replacement execution cell determination unit. Apparatus for designing a semiconductor integrated circuit according to claim Rukoto is provided.

  Further, according to one embodiment of the present invention, based on a timing analysis result for a logic circuit designed using a normal cell, a cell constituting a path having a timing margin can be reduced in power consumption with less power consumption than the normal cell. A step of extracting a semiconductor integrated circuit design apparatus as an object to be replaced with a cell, and a low power consumption of the extracted cell, which has a cell area larger than that of the normal cell but has a driving force equivalent to that of the normal cell; The step of selecting a cell as a replacement cell candidate by the semiconductor integrated circuit design apparatus, and ranking the low power consumption cells selected as the replacement cell candidates in descending order of power consumption reduction for the extracted cells. The step of generating the list by the semiconductor integrated circuit design device and the cell arrangement of the logic circuit when the list is replaced with the low power consumption cell. The semiconductor integrated circuit design device adds the area increase amount in order from the top of the list, and the low consumption up to the rank when the added value reaches the upper limit of the cell layout area increase amount allowed for the logic circuit. A design method of a semiconductor integrated circuit, comprising: determining a power cell as a replacement execution cell that actually performs replacement;

  According to the present invention, it is possible to perform replacement with a low power consumption cell in consideration of a cell layout area margin, so that it is possible to design a semiconductor integrated circuit that ensures both driving power and reduction of power consumption. it can.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention.

  The semiconductor integrated circuit design apparatus 1 of the present embodiment includes a normal cell and a low power consumption cell having a cell area larger than that of the normal cell but having a driving force equivalent to that of the normal cell and less power consumption than the normal cell. A logic circuit is designed using a cell library 100 including

  The semiconductor integrated circuit design device 1 performs timing analysis based on the analysis result of the timing analysis unit 11 that performs timing analysis of the logic circuit based on the input design information and the timing analysis unit 11 for the logic circuit designed using the normal cell. A replacement target cell extraction unit 12 that extracts normal cells constituting a surplus path as a target to be replaced with low power consumption cells, and replacement that selects low power consumption cells corresponding to the extracted normal cells as replacement cell candidates The reduction amount of the power consumption of the low power consumption cell selected by the replacement cell candidate selection unit 13 with respect to the power consumption of the normal cell extracted by the cell candidate selection unit 13 and the replacement target cell extraction unit 12 is calculated, and the reduction Low power consumption for generating a list in which the low power consumption cells selected by the replacement cell candidate selection unit 13 are ranked in descending order of quantity. The increase amount of the cell arrangement area of the logic circuit when the effect analysis unit 14 is replaced with the low power consumption cell is added in order from the top of the above list, and the added value is allowed in the logic circuit. From the normal cell based on the determination of the replacement execution cell determination unit 15 and the replacement execution cell determination unit 15, which determines the low power consumption cells in the rank until reaching the increase allowable amount 140 as the replacement execution cell for actually executing the replacement. A cell replacement execution unit 16 that performs replacement with a low power consumption cell and outputs a post-replacement netlist 300 for the original netlist 200.

  The timing analysis unit 11 reads the net list 200 in which the cell connection information of the logic circuit is written, and based on the timing information 110 in which the output delay time due to the fan-out load and the wiring load of each cell is written, A path delay time is calculated, and whether the path delay time has a margin with respect to the timing constraint 120 is analyzed for each path.

  The power consumption reduction effect analysis unit 14 calculates the operation power consumption of the cell based on the transition probability 130 of the cell input data, and the state probability whether the cell input is “1” or “0”. Based on 140, the leakage power is calculated. Based on these calculation results, the power consumption reduction effect analysis unit 14 calculates a power consumption reduction amount when the normal cell is replaced with the low power consumption cell.

  Here, an example of a low power consumption cell included in the cell library 100 is shown in FIG.

  FIG. 2A shows an example of a circuit configuration of a flip-flop with a clock signal control function that is effective in reducing operation power consumption.

  In the flip-flop with the clock signal control function, the mismatch detection circuit 502 detects a mismatch between the values of the data input signal DIS and the data output signal DOS of the flip-flop circuit 501, and the values of the data input signal DIS and the data output signal DOS do not match. The clock control circuit 503 controls the input of the external clock signal ECLK so that the internal clock signal ICLK is input to the flip-flop circuit 501 only when.

  As a result, as shown in FIG. 2B, the internal clock signal ICLK input to the flip-flop circuit 501 is generated only when the values of the data input signal DIS and the data output signal DOS do not match, and the data input signal DIS Does not occur while the value of the data output signal DOS matches.

  As a result, power is consumed for each change of the external clock signal ECLK in the normal flip-flop, whereas power is consumed only in the flip-flop with the clock signal control function when the internal clock signal ICLK is generated. Therefore, when the transition rate of the data input signal DIS is low, the power consumption can be greatly reduced.

  Here, if the load driving power of the flip-flop circuit 501 is the same as that of a normal flip-flop, the load driving power can be changed to that of a normal flip-flop even if the normal flip-flop is replaced with a flip-flop having a clock signal control function. Can be kept equal. However, the area of the cell is increased by the addition of the mismatch detection circuit 502 and the clock control circuit 503 as compared with a normal flip-flop.

  Next, a method for designing a semiconductor integrated circuit with low power consumption using the semiconductor integrated circuit design apparatus 1 of the present embodiment will be described.

  FIG. 3 is a flowchart showing the flow of processing when designing a semiconductor integrated circuit with low power consumption by replacing a normal cell with a low power consumption cell using the semiconductor integrated circuit design apparatus 1.

  When starting the operation of replacing a normal cell with a low power consumption cell, first, the netlist 200 of the logic circuit designed using the normal cell is read into the semiconductor integrated circuit design apparatus 1 (step S01).

  For this netlist 200, the timing analysis unit 11 calculates a path delay time of a path that is synchronously designed based on the timing information 110, and whether the path delay time has a margin for the timing constraint 120. Are analyzed for each path (step S02).

  Based on the analysis result, the replacement target cell extraction unit 12 extracts a normal cell constituting a path having a timing margin as a target to be replaced with a low power consumption cell (step S03).

  Subsequently, the replacement cell candidate selection unit 13 selects a low power consumption cell corresponding to the extracted normal cell as a replacement cell candidate (step S04).

  The power consumption reduction effect analysis unit 14 analyzes the power consumption reduction effect on the replacement cell candidate low power consumption cell (step S05).

  For this purpose, the power consumption reduction effect analysis unit 14 first reduces the power consumption of the low power consumption cell selected by the replacement cell candidate selection unit 13 with respect to the power consumption of the normal cell extracted by the replacement target cell extraction unit 12. The amount is calculated, and a list in which the low power consumption cells selected by the replacement cell candidate selection unit 13 are ranked in descending order is generated (step S06).

  From this list, the replacement execution cell determination unit 15 selects a cell to actually perform replacement. At this time, the replacement execution cell determination unit 15 selects cells in order from the top of the above list within a range where the increase amount of the cell arrangement area of the logic circuit after replacement is within the cell arrangement area increase allowable amount 140 or less. For this purpose, the cell list order is expressed as n. First, n = 1 is set (step S07), and the area increase amount of the replacement candidate cells from the top of the list to the nth is added (step S08).

  The added area increase amount is compared with the cell arrangement area increase allowable amount 140 (step S09). If the cell arrangement area increase allowable amount 140 is not exceeded (NO), the value of n is increased by 1 (n = n + 1). (Step S10), the processing from step S08 is repeated.

  In the comparison in step S09, when the added area increase amount exceeds the cell arrangement area increase allowable amount 140 (YES), the replacement execution cell determination unit 15 ends the addition of the area increase amount of the replacement candidate cell, and one of them. The replacement candidate cells up to the previous rank are determined as the cells to be actually replaced (step S11).

  FIG. 4 shows an example of a list generated by the power consumption reduction effect analysis unit.

  In this list, the replacement candidate cells are given ranks in descending order of their power consumption reduction amounts P1, P2, P3,..., And are arranged in that order. Moreover, the area increase amount S1, S2, S3,... Of each replacement candidate cell is described.

  A value (S1 + S2 + S3 +... + Sn) obtained by adding this area increase amount from S1 in the first rank to Sn in the nth rank is (S1 + S2 + S3 +... + Sn) ≦ Smax with respect to the cell layout area increase allowable amount Smax. In some cases, the cell replacement execution cell determination unit 15 determines up to the replacement candidate cells ranked n as the cells that are actually to be replaced.

  Returning to FIG. 3, when the replacement execution cell determination unit 15 determines the cell to be replaced, the cell replacement execution unit 16 performs replacement from the normal cell to the low power consumption cell for the netlist 200. A post-replacement netlist 300 is created (step S12), and the process according to this flow is terminated.

  Such replacement of a normal cell with a low power consumption cell by the semiconductor integrated circuit design apparatus 1 of the present embodiment can be performed before or after execution of the layout of the semiconductor integrated circuit.

  FIG. 5 is a diagram showing an example of a design flow when replacing a normal cell with a low power consumption cell before executing the layout of the semiconductor integrated circuit.

  Before the layout is executed, the delay time due to the wiring load of the cell is a value estimated by the virtual wiring length. In this case, the timing analysis in the semiconductor integrated circuit design apparatus 1 is performed using the timing information 110A based on the virtual wiring length. .

  In the design flow shown in FIG. 5, the timing information 110A based on the net list 200 and the virtual wiring length is read, and the cell replacement is executed by the semiconductor integrated circuit design device 1 (step S21), which is output from the semiconductor integrated circuit design device 1 A layout is executed using the post-replacement netlist 300 (step S21).

  Therefore, in this flow, the replacement with the low power consumption cell has been completed at the time of layout, and it is not necessary to perform the layout correction for replacement with the low power consumption cell, and the layout correction amount can be reduced.

  On the other hand, FIG. 6 is a diagram showing an example of a design flow when replacing a normal cell with a low power consumption cell after executing the layout of the semiconductor integrated circuit.

  In this case, since the delay time due to the cell wiring load is a value calculated by the actual wiring length based on the layout result, the timing analysis in the semiconductor integrated circuit design device 1 is performed using the timing information 110B based on the actual wiring length.

  In the design flow shown in FIG. 6, the layout is first executed (step S31), the timing information 110B based on the actual wiring length is generated, the timing information 110B based on the actual wiring length and the netlist 200 are read to design the semiconductor integrated circuit. The device 1 performs cell replacement (step S32), and corrects the layout using the post-replacement netlist 300 output from the semiconductor integrated circuit design device 1 (step S33).

  In the case of this flow, the timing analysis in the semiconductor integrated circuit design device 1 is performed using the timing information 110B based on the actual wiring length. Therefore, the accuracy of the timing analysis is high, and the target cell to be replaced with the low power consumption cell can be extracted with high accuracy.

  According to the present embodiment, the replacement with the low power consumption cell in consideration of the margin of the cell arrangement area can be performed, so that the design of the semiconductor integrated circuit that achieves both the securing of the driving force and the reduction of the power consumption is achieved. It can be performed. Therefore, a flip-flop with a clock signal control function can be used as a low power consumption cell.

  Further, the replacement from the normal cell to the low power consumption cell according to the present embodiment can be executed before or after the layout of the semiconductor integrated circuit. If replacement is performed before layout, the amount of layout correction can be reduced, and if replacement is performed after layout, normal cells to be replaced with low power consumption cells can be accurately extracted.

  FIG. 7 is a block diagram showing an example of the configuration of a semiconductor integrated circuit design apparatus according to Embodiment 2 of the present invention.

  The semiconductor integrated circuit design device 2 according to the present embodiment is obtained by adding a cell type designation unit 21 to the semiconductor integrated circuit design device 1 according to the first embodiment. Therefore, in FIG. 7, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

  Based on the cell type designation information 160, the cell type designation unit 21 designates the type of cell to be extracted by the replacement target cell extraction unit 12 to the replacement target cell extraction unit 12.

  For example, if the cell type designation unit 21 designates the cell type as only a flip-flop, the replacement target cell extraction unit 12 extracts only the flip-flop as a target to be replaced with a low power consumption cell. If the cell type designation unit 21 designates flip-flop priority, the replacement target cell extraction unit 12 preferentially extracts the flip-flop as a target to be replaced with a low power consumption cell.

  FIG. 8 shows the changes made by the present embodiment with respect to the flowchart shown in FIG.

  When designing a semiconductor integrated circuit with low power consumption using the semiconductor integrated circuit design apparatus 2 of the present embodiment, after execution of the timing analysis of the flowchart shown in FIG. A process of designation (step S41) is added.

  As a result, the replacement target cell extraction unit 12 extracts only the specified type of cells from the normal cells constituting the path having a timing margin as a target to be replaced with the low power consumption cell (step S03).

  According to the present embodiment, since the cells to be replaced with the low power consumption cells are extracted only for the designated type of cells, the time required for extracting the cells is more than the target of extraction. Can be shortened.

1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention. The circuit diagram which shows the example of a circuit structure of the flip-flop with a clock signal control function. 1 is a flowchart showing an example of a method for designing a semiconductor integrated circuit by a semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention. The figure which shows the example of the list | wrist of a replacement candidate cell. The figure which shows the usage example of the semiconductor integrated circuit design apparatus which concerns on Example 1 of this invention. FIG. 5 is a diagram showing another example of use of the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention. FIG. 5 is a block diagram showing an example of the configuration of a semiconductor integrated circuit design apparatus according to Embodiment 2 of the present invention. The flowchart which shows the principal part of the design method of the semiconductor integrated circuit by the semiconductor integrated circuit design apparatus which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Semiconductor integrated circuit design apparatus 11 Timing analysis part 12 Replacement object cell extraction part 13 Replacement cell candidate selection part 14 Power consumption reduction effect analysis part 15 Replacement execution row cell determination part 16 Cell replacement execution part 21 Cell type designation part

Claims (5)

Logic circuit design using a cell library including a normal cell and a low power consumption cell having a cell area larger than that of the normal cell and having a driving force equivalent to that of the normal cell and less power consumption than the normal cell A semiconductor integrated circuit design apparatus for performing
Timing analysis means for performing timing analysis of the logic circuit based on the inputted design information;
A replacement target cell extracting means for extracting a normal cell constituting a path having a timing margin as a target to be replaced with the low power consumption cell based on an analysis result of the timing analysis means for a logic circuit designed using a normal cell; ,
Replacement cell candidate selecting means for selecting the low power consumption cell corresponding to the cell extracted by the replacement target cell extracting means as a replacement cell candidate;
A reduction amount of power consumption of the low power consumption cells selected by the replacement cell candidate selection unit is calculated with respect to power consumption of the cells extracted by the replacement target cell extraction unit, and the replacement is performed in descending order of the reduction amount. Power consumption reduction effect analysis means for generating a list in which the low power consumption cells selected by the cell candidate selection means are ranked;
The increase amount of the cell layout area of the logic circuit when replaced with the low power consumption cell is added in order from the top of the list, and the added value is the upper limit of the cell layout area increase amount allowed for the logic circuit Replacement execution cell determination means for determining the low power consumption cells in the ranks until reaching a replacement execution cell for actually executing replacement;
An apparatus for designing a semiconductor integrated circuit, comprising: cell replacement execution means for executing replacement from the normal cell to the low power consumption cell based on the determination by the replacement execution cell determination means. It further comprises cell type designation means for designating the type of cell to be replaced,
2. The semiconductor integrated circuit design apparatus according to claim 1, wherein the replacement target cell extracting unit selects only the cell of the type specified by the cell type specifying unit.   3. The semiconductor integrated circuit design apparatus according to claim 1, wherein the cell library includes a flip-flop with a clock signal control function as a low power consumption cell. Design of a semiconductor integrated circuit as a target to replace a cell constituting a path having a timing margin with a low power consumption cell having a lower power consumption than the normal cell based on a timing analysis result for a logic circuit designed using the normal cell. A device extracting step;
A step of selecting a semiconductor integrated circuit design device as a replacement cell candidate for a low power consumption cell having a cell area larger than that of the normal cell but having a driving force equivalent to that of the normal cell for the extracted cell;
The semiconductor integrated circuit design apparatus generates a list in which the low power consumption cells selected as the replacement cell candidates are ranked in descending order of the power consumption reduction amount for the extracted cells;
The amount of increase in the cell layout area of the logic circuit when replaced with the low power consumption cell is added by the semiconductor integrated circuit design device in order from the top of the list, and the added value is allowed to the logic circuit. And a step of determining, by the semiconductor integrated circuit design device, the low power consumption cells up to the rank when the upper limit of the cell layout area increase amount is reached as a replacement execution cell for actually executing replacement. A method for designing a semiconductor integrated circuit. The semiconductor integrated circuit design apparatus further includes a step of designating the type of cell to be replaced,
5. The cell according to claim 4, wherein when a cell configuring a path having a timing margin is extracted as a target to be replaced with the low power consumption cell, only the specified type of cell is selected as an extraction target. Design method of semiconductor integrated circuit.

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