JP2008149724A - Storage device and method for accessing storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device which can readily rewrite identification data and can properly complete writing data in a short period of time. <P>SOLUTION: An ID comparator 203 judges whether the ID data transmitted from a host computer match the identification data stored in a memory cell 201, and when they match, the comparator transmits access permission signals EN to an operation code decoder 204. The operation code decoder 204 performs an analysis of read/write command; in accordance with the command, changes the data transfer direction with respect to the memory cell 201; and requests an I/O controller 205 to change the high-impedance setting of a sinal line connected to a data terminal DT. An access to the address of the memory array 201 specified by the counter value of an address counter 202 is executed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to storage devices connected to each other by a bus, and more particularly to a technique for identifying a desired storage device from a plurality of storage devices connected by a bus.

  Various techniques have been proposed in which a desired storage device is selected from a plurality of memories (storage devices) included in the memory module and data is read or written. For example, in a plurality of storage devices that are bus-connected to data signal lines and clock signal lines, physical identification information is previously stored in the storage device using a pull-up resistor or the like, and the desired identification information is used using the identification information. A technology for accessing a storage device has been put into practical use. In this technology, a data string to be transmitted includes a start bit indicating the start of the data string and an end bit indicating the end of the data string. Access to each storage device is defined by a combination of the start bit, the end bit and the clock signal. It was.

  In addition to this, a technique using a chip select signal line for transmitting a chip select signal for selecting a storage device in addition to the data signal line and the clock signal line has been put into practical use. In this technique, only a storage device that has received a chip select signal among a plurality of storage devices becomes accessible, and writing to or reading from the storage device can be executed (see, for example, Patent Document 1).

JP-A-6-67973

  However, with the technology that makes a storage device have physical identification information using a pull-up resistor, etc., it is practically impossible to rewrite the identification information set in each storage device and is not suitable for recycling use. was there. In addition, since access to the storage device is defined by a combination of a start bit, an end bit, and a clock signal, data writing cannot be normally terminated if a power down occurs during access to the storage device. was there.

  Further, in the technology using the chip select signal lines, the number of chip select signal lines corresponding to the number of storage devices must be provided, which increases the number of signal lines and complicates the wiring design. . Furthermore, there is a problem that only one chip select signal line is used at the time of access, and the use efficiency of the signal line is poor.

  The present invention has been made to solve the above problems and demands, and an object thereof is to provide a storage device in which identification information can be easily rewritten. It is another object of the present invention to provide a storage device that can complete data writing normally in a short time.

  In order to solve the above problems, the first aspect of the present invention is initialized by a reset signal that is bus-connected to the clock signal line, the data signal line, and the reset signal line and that is input via the reset signal line. A non-volatile storage device is provided. The storage device according to the first aspect of the present invention has a storage area that is accessed sequentially, and can be written in a predetermined condition from the beginning position of the storage area to a predetermined position. A memory cell having an area in which identification information is stored in a non-rewritable manner is provided.

  According to the storage device of the first aspect of the present invention, the storage device is selected because the identification information is normally stored in a non-rewritable manner and has a memory cell that can be written under a predetermined condition. Therefore, a desired storage device can be selected without providing a signal line. Although the identification information is stored in a non-rewritable manner, the identification information can be easily rewritten because it can be written to the area where the identification information is written under a predetermined condition.

  The storage device according to the first aspect of the present invention further counts up a counter value in synchronization with a data bus connected to the data signal line and a clock signal input via the clock signal line, An address counter for designating a position to be accessed in the storage area of the memory cell and resetting a counter value to an initial value at the time of initialization, and being arranged between the memory cell and the data bus, and data for the memory cell Controlling the transfer direction and the data transfer direction of the data bus, and at the time of initialization, sets the data transfer direction to the memory cell as the data read direction and disconnects the connection with the data bus; and Input identification information connected to a data bus and input via the data bus and the input / output control device A comparison device that determines whether or not the identification information stored in the memory cell read through the access matches, and an access that permits access to the storage cell when the identification information is determined to match An allowable device may be provided.

  By providing the above configuration, only access to a desired storage device can be permitted. In particular, when a plurality of storage devices are provided, a desired storage device can be identified from the plurality of storage devices, and access such as reading and writing can be executed. In addition, when determining whether or not the identification information included in the storage device matches the input identification information, data writing to the storage cell cannot be performed, and the identification information stored in the storage cell Read-only property can be maintained.

  The storage device according to the first aspect of the present invention is further connected to the data bus and the comparison device, and the input identification information from the comparison device matches the identification information stored in the storage cell. When the determination result is received, the write / read command input via the data bus is analyzed, and the data transmission direction of the data bus is switched to the input / output control device based on the analysis result. And the input / output control unit cuts off a connection between the data transfer direction and the data bus at the time of initialization until the analysis of the write / read command by the instruction decoder is completed. The state may be maintained.

  With the above structure, data can be written to and read from the selected storage device. Further, since data writing or reading with respect to the memory cell can be prohibited until the analysis of the writing / reading command is completed, data writing or reading can be executed from a predetermined position of the memory cell.

  The storage device according to the first aspect of the present invention further includes a test terminal connected to a test mode signal line, a test mode control device connected to the test terminal, and determining whether or not a test mode signal is input. The predetermined condition may be at the time of detecting the input of the test mode signal. With such a configuration, data can be written to a memory cell region in which identification information is stored.

  In the storage device according to the first aspect of the present invention, the test mode control device outputs a test mode instruction to the instruction decoder when detecting the input of the test mode signal, and the instruction decoder The address counter is prohibited from counting up until the analysis of the test mode instruction is completed by the instruction decoder, and after the analysis of the test mode instruction, the instruction decoder writes to the input / output control device and the data The I / O controller may request the release of the bus, and may execute writing to the memory cell and releasing the data bus based on a request from the instruction decoder. The instruction decoder, after analyzing the test mode instruction, requests the input / output controller to read the memory cell and release the data bus. The input / output controller requests the instruction decoder. The memory cell may be read and the data bus released.

  With the above configuration, the instruction decoder can be activated without receiving a result indicating that the identification information matches from the comparison device, and the input / output control device can write / read data to / from the memory cell and the data bus Can be released. Since the address counter is not counted up until the analysis of the test mode instruction is completed by the instruction decoder, data can be written from the head position of the memory cell. As a result, rewriting of the identification information stored in the memory cell can be realized. Further, until the instruction decoder finishes analyzing the test mode instruction, the address counter is prohibited from counting up, so that data can be read from the head position of the memory cell.

  In the storage device according to the first aspect of the present invention, the storage cell may have a writable area for writing write data following the storage area in which the identification information is stored. Further, data may be written to the memory cell in 1-bit units. When such a configuration is provided, write data can be quickly written. Even when a reset signal is input during data writing, data writing can be completed without garbled data.

  According to a second aspect of the present invention, there is provided an ink cartridge comprising the storage device according to the first aspect of the present invention. In the ink cartridge according to the second aspect of the present invention, the ink cartridge may include a storage device having identification information different for each ink type corresponding to the ink type to be stored. With such a configuration, even when a plurality of ink cartridges are used, an ink cartridge that contains a predetermined ink type can be specified.

According to a third aspect of the present invention, a plurality of nonvolatile storage devices that are bus-connected to a clock signal line, a data signal line, and a reset signal line, and a memory through the clock signal line, the data signal line, and the reset signal line A storage system including a control device connected to the device is provided. The third aspect of the present invention is:
A clock signal generation circuit;
A reset signal generation circuit for generating a reset signal for initializing the storage device;
An identification information issuing circuit for issuing identification information corresponding to identification information of a desired storage device among the plurality of storage devices;
The control device comprising: a data sending circuit for sending a data string including the issued identification information and a read / write command to the data signal line in synchronization with the generated clock signal;
A data bus connected to the data signal line;
A storage area that has a storage area that is accessed sequentially, and that has an area from the beginning of the storage area to a predetermined position where data can be written under a predetermined condition and the identification information is stored in a non-rewritable state at other times. Cell,
A comparison device that is connected to the data bus and determines whether the identification information sent from the control device matches the identification information stored in the memory cell;
An input / output control device that is disposed between the data bus and the data bus and controls data transfer to the data bus and the storage cell;
The data bus is connected to the data bus and the comparison device, and when it is determined that the identification information sent from the control device by the comparison device matches the identification information stored in the memory cell, the data bus is Each of the storage devices including an instruction decoder that analyzes a write / read command input via the command and requests the input / output control device to switch the data transmission direction of the data bus based on the analysis result. It is characterized by.

  According to the storage system of the third aspect of the present invention, the storage system is selected because the storage cell is provided with an area in which the identification information is normally stored in a non-rewritable manner and can be written in a predetermined condition. A desired storage device can be selected from a plurality of storage devices without providing a signal line. Although the identification information is stored in a non-rewritable manner, the identification information can be easily rewritten because it can be written to the area where the identification information is written under a predetermined condition. In addition, when determining whether or not the identification information included in the storage device matches the input identification information, data writing to the storage cell cannot be performed, and the identification information stored in the storage cell Read-only property can be maintained. Furthermore, data can be written to and read from the selected storage device.

In the storage system according to the third aspect of the present invention,
The storage device further includes
The counter value is counted up in synchronization with the clock signal input via the clock signal line, the position to be accessed in the storage area of the storage cell is specified, and the counter value is reset to the initial value at initialization. With an address counter,
The input / output control device sets a data transfer direction to the memory cell at the time of initialization and interrupts data transfer to the data bus at the time of initialization until the analysis of the write / read command by the command decoder is completed. The state at the time of initialization may be maintained.

  With the above configuration, data writing or reading with respect to the memory cell can be prohibited until the analysis of the writing / reading command is completed, so that data writing or reading is executed from a predetermined position of the memory cell. be able to.

  In the storage system according to the third aspect of the present invention, the identification information issuing circuit of the control circuit issues common identification information common to all storage devices, and the comparison device of the storage device outputs the common identification information. You may own it. When such a configuration is provided, all storage devices can be selected as storage devices that are desired to be accessed. Therefore, when there is data to be commonly written to all the storage devices, data writing can be executed at the same time and the writing time can be shortened.

  In the storage system according to the third aspect of the present invention, the control circuit includes a power compensation circuit that supplies power for a predetermined period after power is shut down, and the reset signal generation circuit of the control circuit is provided when the control circuit is powered on. And generating a reset signal at least one of when the power is cut off, and when the data transmission circuit of the control circuit detects the generation of the reset signal during the transfer of the write data, the data transmission circuit currently writing is transmitted. Then, write priority data that can be written may be sent during a period when the power supply is compensated by the power supply compensation circuit.

  With the above configuration, even when the power is shut off, writing of data that should be prioritized, such as ink consumption data or ink remaining amount data, can be completed.

In the storage system according to the third aspect of the present invention,
A test control device having a test signal generation circuit that generates a test signal that enables writing to or reading from all the storage areas of the storage cells of the storage device instead of the control device,
The storage device further detects whether or not the test signal is input, and outputs a test mode instruction to the instruction decoder when detecting the input of the test mode signal.
A test mode control device for prohibiting counting up of the address counter until the analysis of the test mode instruction by the instruction decoder is completed;
The instruction decoder, after analyzing the test mode instruction, sets a data transfer direction for the storage cell to a write direction or a read direction for the input / output control device, and sets a data transfer direction for the data bus to a write direction or a read direction. Request to set the direction,
The input / output control device may set a data transfer direction for the memory cell to a write direction or a read direction, and may set a data transfer direction for the data bus to a write direction or a read direction.

  With the above configuration, the instruction decoder can be activated without receiving a result indicating that the identification information matches from the comparison device, and the input / output control device can write / read data to / from the memory cell and the data bus Can be released. In addition, since the address counter is not counted up until the analysis of the test mode instruction is completed by the instruction decoder, data can be written to or read from the entire area of the memory cell. Data can be written. As a result, rewriting of the identification information stored in the memory cell can be realized. Furthermore, data can be read from the head position of the memory cell.

  In the storage system according to the third aspect of the present invention, at the time of data writing in the test mode, the test control device uses the data signal configured from the top in the order of a write command, identification information, and write data. The identification information may be written to a predetermined position from the start position of the storage area in the storage cell of the storage device.

In the storage system according to the third aspect of the present invention, instead of the control device, an identification information search circuit that searches for identification information that matches the identification information stored in a storage cell of the storage device, and the identification When the identification information matching the identification information stored in the memory cell is acquired by the information search circuit, the identification information is next to the write data corresponding to the end position of the storage area of the storage cell in the storage device. A test control device having a data string sending circuit in a test mode for sending a data string having the data string to the data signal line;
The test control device may write the identification information from a start position of a storage area in a storage cell of the storage device to a predetermined position.

  With the above configuration, the identification information stored in the memory cell of the memory device can be rewritten without the test mode control device.

  In the storage system according to the third aspect of the present invention, the clock signal generation circuit in the control circuit generates a clock signal when sending a write command via the data sending circuit than when sending a read command. The interval may be increased. With such a configuration, the access time to the storage device can be shortened while securing the time required for data writing.

  In the storage system according to the third aspect of the present invention, the plurality of storage devices are further accommodated, the storage devices are serially connected, one end is grounded, and the other end is connected to the control circuit. A storage device detection comprising a module substrate on which device detection signal lines are arranged, wherein the control circuit determines whether or not all storage devices are arranged on the module substrate based on the value of the storage device detection signal line A circuit may be provided.

  With the above configuration, it is possible to detect whether or not the storage device is appropriately arranged on the module substrate. This aspect can be used, for example, to determine whether or not an ink cartridge for an ink jet printer is provided with the storage device and the ink cartridge is properly accommodated in the ink cartridge holder.

  In the storage system according to the third aspect of the present invention, the storage device detection circuit of the control circuit includes all the storage devices arranged on the module substrate when the storage device detection signal line indicates a ground voltage. It may be determined that

  In the storage system according to the third aspect of the present invention, the storage device detection circuit of the control circuit has at least one storage device on the module substrate when the storage device detection signal line indicates a voltage other than a ground voltage. It may be determined that they are not arranged.

  In the storage system according to the third aspect of the present invention, the storage device may be provided in an ink cartridge, and may store various data related to the ink type accommodated in the ink cartridge. With such a configuration, in a printer using a plurality of ink cartridges, a specific ink cartridge can be selected and unique information can be written.

According to a fourth aspect of the present invention, a desired memory is selected from a plurality of nonvolatile memory devices that are bus-connected to a clock signal line, a data signal line, and a reset signal line and each have unique identification information. A method for accessing a device is provided. The method according to the fourth aspect of the present invention comprises:
Output a reset signal to the reset signal line,
A data string including identification information of the storage device desired to be accessed and a read / write command is sent to a data signal line in synchronization with a clock signal. By providing such a configuration, it is possible to obtain the same effect as the aspect of the first invention.

  According to a fifth aspect of the present invention, there is provided a storage device including a storage cell having a storage area that is sequentially accessed and having an area in which identification information is stored from a leading position of the storage area to a predetermined position. An access request processing method in a storage device that shares a clock bus connected to a clock signal line, a data bus connected to a data signal line, and a reset bus connected to a reset signal line with another storage device provide. The access request processing method according to the fifth aspect of the present invention resets the counter value of the address counter to an initial value when a reset signal is detected on the reset bus, and stores the identification information sent to the data bus and the memory cell. If the identification information sent to the data bus matches the identification information stored in the memory cell, the read / write instruction sent to the data bus is determined. And controlling data transfer of the data bus and data transfer to the memory cell based on the analysis result, and writing data to a desired position of the memory cell according to the counter value of the address counter, or Data is read from the memory cell.

  By providing such a configuration, it is possible to obtain the same effects as those of the first and second aspects of the present invention.

  According to a sixth aspect of the present invention, there is provided a method for storing identification information from a head position of a storage area of a memory cell to a predetermined position in a nonvolatile memory device having memory cells accessed sequentially. The identification information storage method according to the sixth aspect of the present invention resets the counter value of the address counter to an initial value when a reset signal is detected and prohibits the counter value from being counted up in synchronization with the clock signal. Based on the transmitted write command, the data transfer direction of the data bus is set to the write direction and the data transfer direction to the memory cell is set to the write direction. After the setting of the data transfer direction is completed, the clock in the address counter The counter value is allowed to be counted up in synchronization with the signal, and the identification information is written from the start position of the storage area of the storage cell to a predetermined position according to the count value of the address counter, and then the data is written. .

  With the above configuration, the identification information and other data can be written in the test mode. In particular, identification information can be written from the beginning position of the storage area.

  According to a seventh aspect of the present invention, there is provided a method of reading data stored in a storage area of a storage cell from a head position in a nonvolatile storage device having storage cells that are sequentially accessed. In the data read method according to the seventh aspect of the present invention, when the reset signal is detected, the counter value of the address counter is reset to the initial value and the counter value is not allowed to be counted up in synchronization with the clock signal and is sent to the data bus. Based on the read command, the data transfer direction of the data bus is set to the read direction and the data transfer direction with respect to the memory cell is set to the read direction. After the setting of the data transfer direction is completed, the clock signal in the address counter is set. The counter value is allowed to be counted up in synchronization with the data, and the data stored in the storage area of the storage cell is read from the head position according to the count value of the address counter.

  With the above configuration, data can be read in the test mode.

  According to an eighth aspect of the present invention, there is provided a method for storing identification information from a start position of a storage area of a storage cell to a predetermined position in a nonvolatile storage device having storage cells that are sequentially accessed. The method according to the eighth aspect of the present invention searches for identification information that matches the identification information stored in the storage cell of the storage device, and identifies that matches the identification information stored in the storage cell. When the information is retrieved, the retrieved identification information and write command are sent to the storage device, and the identification information is next to the write data corresponding to the end position of the storage area of the storage cell in the storage device. The data string is sent to the storage device, data is written to the end position of the storage area of the storage cell according to the count value of the address counter, and then from the start position of the storage area of the storage cell to the predetermined position. The identification information is written in

  According to the method of the eighth aspect of the present invention, even if the identification information included in the storage device is not known, the identification information included in the storage device is found and the storage area of the storage cell is moved from the start position to the predetermined position. Identification information can be written in Therefore, after the storage device is recycled, new identification information and data can be easily written to the storage device, and the reuse of the storage device can be promoted.

Hereinafter, a storage system including a storage device according to the present invention will be described based on several embodiments with reference to the drawings in the following order.
A. B. Configuration of storage system according to first embodiment Configuration of storage device according to first example C.I. Operation of storage system in first embodiment Configuration of storage system and configuration of storage device according to second embodiment F. Writing identification information (identification data) to the storage device in the test mode according to the third embodiment Writing of identification information (identification data) to the storage device in the test mode according to the fourth embodiment

A. Configuration of the storage system according to the first embodiment:
A schematic configuration of the storage system according to the first embodiment will be described with reference to FIG. FIG. 1 is an explanatory diagram illustrating a configuration example of a storage system including a plurality of storage devices and a host computer according to the first embodiment.

  The storage system according to this embodiment includes a host computer 10 and five storage devices 20, 21, 22, 23, 24 that are arranged on the memory module substrate 200 and whose access is controlled by the host computer 10. I have. It is assumed that the storage devices 20, 21, 22, 23, and 24 are respectively provided in five color ink cartridges C1, C2, C3, C4, and C5 for an inkjet printer, as shown in FIG. The five color ink cartridges C1, C2, C3, C4, and C5 contain, for example, cyan, light cyan, magenta, light magenta, and yellow inks. In addition, the storage device in this embodiment is an EEPROM that holds the storage content in a nonvolatile manner and can rewrite the storage content.

  In FIG. 1, only the storage devices 20, 21, 22, 23, and 24 are shown for ease of explanation, but as described above, the storage devices 20, 21, 22, 23, and 24 is actually provided in the ink cartridges C1, C2, C3, C4, and C5.

  The data signal terminal DT, the clock signal terminal CT, and the reset signal terminal RT of each of the storage devices 20, 21, 22, 23, and 24 are respectively connected via the data bus DB, the clock bus CB, and the reset bus RB (FIG. 4). reference). The host computer 10 and the data bus DB, the clock bus CB, and the reset bus RB are connected via a data signal line DL, a clock signal line CL, and a reset signal line RL. These signal lines can be realized as, for example, a flexible feed cable (FFC). The power supply positive terminal VDDH of the host computer 10 and the power supply positive terminal VDDM of each storage device 20, 21, 22, 23, 24 are connected via a power supply line VDL. On the memory module substrate 200, a power supply negative signal line VSL for serially connecting the power supply negative terminals VSS of the storage devices 20, 21, 22, 23, and 24 is disposed. One end of the power supply negative signal line VSL is grounded, and the other end is connected to the cartridge out detection terminal COT of the host computer 10 via the cartridge out signal line COL.

  The host computer 10 is a control device having a clock signal generation circuit, a reset signal generation circuit, a power supply monitoring circuit, a power supply circuit, a power supply compensation circuit, a data storage circuit, and a control circuit for controlling each circuit, which are not shown in the figure, Controls access to the storage devices 20, 21, 22, 23, and 24. The host computer 10 is disposed on the main body side of the ink jet printer, for example, and acquires data such as ink consumption and ink cartridge mounting time and stores them in a data storage circuit.

  The control circuit of the host computer 10 accesses the storage devices 20, 21, 22, 23, 24 when the ink jet printer is turned on, the ink cartridge is replaced, the print job is finished, the ink jet printer is turned off, etc. To do. When accessing the storage devices 20, 21, 22, 23, and 24, the control circuit of the host computer 10 requests the reset signal generation circuit to generate the reset signal RST. Accordingly, the reset signal RST is also generated when a power failure or the power plug is removed. The power supply compensation circuit of the host computer 10 supplies power for a predetermined period (for example, 0.3 s) even when power supply is interrupted. As a result, even if the power supply during data writing is cut off due to a power failure or the power plug being disconnected, it is possible to complete the writing of data that should be prioritized during the predetermined period. For example, a capacitor is used as the power supply compensation circuit.

  The control circuit of the host computer 10 controls the output of the positive power supply by controlling the power supply circuit. The host computer 10 according to the present embodiment does not always supply power to the storage devices 20, 21, 22, 23, 24, and an access request to the storage devices 20, 21, 22, 23, 24 is generated. Only when this is the case, the positive power supply is supplied to the storage devices 20, 21, 22, 23 and 24.

  A data string transmitted from the host computer 10 will be described with reference to FIGS. FIG. 2 is an explanatory diagram showing an example of a data string transmitted from the host computer 10 at the normal time. FIG. 3 is an explanatory diagram showing an example of a data string transmitted from the host computer 10 in the test mode.

  The data string transmitted from the host computer 10 normally includes a 3-bit identification data portion, a 1-bit read / write command portion, and a 1- to 252-bit write / read data portion as shown in FIG. On the other hand, in the test mode, the data sequence transmitted from the host computer 10 includes a 1-bit write data portion and 1-bit to 256-bit write data portion as shown in FIG. Note that identification data is arranged in 3 bits from the top of the write data portion.

  When reading data from the storage devices 20, 21, 22, 23, 24, the clock signal generation circuit of the host computer 10 generates, for example, a clock signal SCK at intervals of 4 μS, and at the time of data writing, the clock signal SCK at intervals of 3 ms. Is generated.

B. Configuration of Storage Device According to First Embodiment Next, the internal configuration of the storage devices 20, 21, 22, 23, 24 will be described with reference to FIG. FIG. 4 is a block diagram showing an internal circuit configuration of the storage device 20. The internal configuration of each storage device 20, 21, 22, 23, 24 is the same except for stored identification information (identification data) and unique data. The internal structure of 20 will be described.

  The storage device 20 includes a memory array 201, an address counter 202, an ID comparator 203, an operation code decoder 204, an I / O controller 205, and a factory setting unit 206.

  The memory array 201 has a predetermined capacity, for example, a 256-bit storage area, the identification data is stored in the 3-bit storage area from the top, and the fourth-bit storage area from the top is an invalid area. As described above, normally, identification data is stored in the first 3 bits of the data string transmitted from the host computer 10, and a write / read command is stored in the fourth bit from the top. Therefore, data is not written unless the storage area is the fifth and subsequent bits from the beginning, and the storage area of the memory array 201 has such a configuration, so that the top 4 bits become a read-only storage area. The memory array 201 has an area for writing information that should be prioritized for writing, for example, ink consumption amount or ink remaining amount, from the fifth bit. With such a configuration, even when the power is shut off without operating the power switch, important data can be written to the memory array 201 within a period in which the power supply compensation circuit can compensate the power supply. .

  The address counter 202 is a circuit that increments the counter value in synchronization with the clock signal SCK supplied via the factory setting unit 206, and is connected to the memory array 201. The counter value and the storage area position (address) of the memory array 201 are associated with each other, and the write position or the read position in the memory array 201 can be designated by the counter value of the address counter 202. The address counter 202 is also connected to the reset signal terminal RT, and resets the counter value to the initial value when the reset signal RST is input. Here, the initial value may be any value as long as it is associated with the head position of the memory array 201, and generally 0 is used as the initial value.

  The ID comparator 203 is connected to the clock signal terminal CT, the data signal terminal DT, and the reset signal terminal RT, and is stored in the memory array 201 with the identification data included in the data string input via the data signal terminal DT. It is determined whether or not the identification data matches. Specifically, the ID comparator 203 acquires 3-bit data that is input after the reset signal RST is input, that is, identification data. The ID comparator 203 includes a 3-bit register (not shown) that stores identification data included in the data string, and a 3-bit register (not shown) that stores identification data acquired from the memory array 201 via the I / O controller 205. It is determined whether or not the identification data matches depending on whether or not the values of both registers match. The ID comparator 203 sends an access permission signal EN to the operation code decoder 204 when both identification data match. The ID comparator 203 clears the value of the register when the reset signal RST is input. Note that common identification data, for example, (1, 1, 1) is stored in the ID comparator 203 of the storage device 20 and all the other storage devices 21, 22, 23, 24. The common identification data is held by the ID comparators of the storage devices 20, 21, 22, 23, and 24, thereby simultaneously writing data to be written to the storage devices 20, 21, 22, 23, and 24 simultaneously. Can be executed.

  The operation code decoder 204 is connected to the I / O controller 205, the clock signal terminal CT, and the data signal terminal DT, and receives the fourth bit data input after the reset signal RST is input, that is, the write / read command. get. When the access permission signal EN is input, the operation code decoder 204 analyzes the acquired write / read command and sends a write process request or a read process request to the I / O controller 205. The operation code decoder 204 is also connected to the factory setting unit 206, and sends an analysis end notification to the factory setting unit 206 when the analysis of the write / read command is completed in the test mode.

  The I / O controller 205 is connected to the data signal terminal DT and the memory array 201. According to a request from the operation code decoder 204, the I / O controller 205 is connected to the data transfer direction to the memory array 201 and to the data signal terminal DT (connected to the data signal terminal DT. Switch the data transfer direction (for the signal line). The I / O controller 205 is also connected to the reset signal terminal RT and receives the reset signal RST. The I / O controller 205 includes a first buffer memory (not shown) that temporarily stores data read from the memory array 201 and write data to the memory array 201, and data from the data bus DB and the data bus DB. A second buffer memory (not shown) for temporarily storing data is provided.

  The I / O controller 205 is initialized by the input of the reset signal RST. At the time of initialization, the data transfer direction with respect to the memory array 201 is set to the read direction, and the signal line connected to the data signal terminal DT is set to high impedance. By doing so, data transfer to the data signal terminal DT is prohibited. This initialization state is maintained until a write process request or a read process request is input from the operation code decoder 204. Therefore, the data of the first 4 bits of the data string input via the data signal terminal DT after the reset signal is input is not written to the memory array 201, but on the other hand, the first 4 bits (of the 4th bit of the memory array 201) The data stored in (invalid data) is sent to the ID comparator 203. As a result, the first 4 bits of the memory array 201 are in a read-only state.

  The factory setting unit 206 is connected to the test signal terminal TT, the clock signal terminal CT, and the data signal terminal DT, and executes a test mode process when a test signal is input. The factory setting unit 206 transfers the received clock signal SCK as it is to the address counter 202 when there is no test signal input. When the test signal is input, the factory setting unit 206 clocks the address counter 202 until an analysis end notification is received from the operation code decoder 204. The signal SCK is not transferred. The factory setting unit 206 sends a test mode command to the operation code decoder 204. Note that a pull-down resistor is connected to the test signal terminal TT, and is normally an inactive terminal.

C. Operation of Storage System in First Embodiment The operation of the storage system in this embodiment will be described with reference to FIGS. FIG. 5 is a flowchart showing a processing routine executed by the host computer 10 when accessing the storage devices 20, 21, 22, 23 and 24. FIG. 6 is a flowchart showing a processing routine executed by each component circuit of the storage devices 20, 21, 22, 23, 24 when accessed by the host computer 10. FIG. 7 is a timing chart showing a temporal relationship among the reset signal RST, the clock signal SCK, the data signal CDA, and the address counter value at the time of data reading. FIG. 8 is a timing chart showing a temporal relationship among the reset signal RST, the clock signal SCK, the data signal CDA, and the address counter value at the time of data writing.

  The control circuit of the host computer 10 waits until the input value CO of the cartridge out signal line COL becomes 0 (No at Step S100). That is, when all the ink cartridges are correctly accommodated in the ink cartridge holder, the power supply negative signal line VSL is serially connected and grounded, so the input value CO of the cartridge out signal line COL is set to the ground voltage (for example, This is because it indicates about 0 volts). On the other hand, even if one ink cartridge is not correctly stored in the ink cartridge holder, the power supply negative signal line VSL is not serially connected and therefore is not grounded and corresponds to the circuit voltage of the control circuit. The value appears on the cartridge out signal line COL. However, in this embodiment, binarization is performed with reference to a predetermined threshold value in order to eliminate the influence of noise and the like. Therefore, the input value CO of the cartridge out signal line COL takes 0 or 1.

  When the input value CO of the cartridge out signal line COL is 0 (step S100: Yes), the control circuit of the host computer 10 stores the power supply voltage via the power supply line VDL as shown in FIGS. The power is supplied to the power supply positive terminal VDDM of the devices 20, 21, 22, 23, 24 (VDD = 1), and the reset signal generation circuit generates a reset / low signal (set to RST = 0) via the reset signal line RL. To the reset bus RB (step S110). That is, the power supply voltage is not supplied to the storage devices 20, 21, 22, 23, and 24 unless the ink cartridge is properly stored in the ink cartridge holder. Note that the reset signal RST is assumed to be active low, and the terms such as the generation and input of the reset signal RST used in this specification mean the reset low signal unless otherwise specified. To do.

  Subsequently, as shown in FIGS. 7 and 8, the host computer 10 sets the reset signal RST to high by setting the reset signal generation circuit to RST = 1 (step S120). The control circuit of the host computer 10 issues identification data (ID data) of the ink cartridge (storage devices 20, 21, 22, 23, 24) desired to be accessed (step S130). The issued ID data is transferred to the data bus DB via the data signal line DL in synchronization with the rising edge of the clock signal SCK as shown in FIGS. The control circuit of the host computer 10 determines whether or not the issued ID data is (1, 1, 1) (step S140). As described above, the ID data (1, 1, 1) is identification data stored in advance in the ID comparators of all the storage devices 20, 21, 22, 23, 24, and the issued ID data is ( In the case of (1, 1, 1), data can be written to all the storage devices 20, 21, 22, 23, 24 simultaneously.

  If the control circuit of the host computer 10 determines that ID data = (1, 1, 1) (step S140: Yes), it issues a write command (step S150). The issued write command is synchronized with the rising edge of the fourth clock signal SCK after the reset signal RST is switched from low to high as shown in FIGS. 7 and 8, via the data signal line DL. Transferred to the data bus DB. The control circuit of the host computer 10 requests the clock signal generation circuit to reduce the speed of the clock signal SCK, that is, to increase the generation interval of the clock signal SCK (step S160). The time required for writing data to the EEPROM is, for example, about 3 ms, and the time required for reading data is, for example, about 4 μs. Accordingly, when writing data, it takes about 1000 times as long as the time required for reading data. Therefore, in this embodiment, the storage devices 20, 21, 22, 23, and 24 are accessed at a high clock signal speed until the data write command is issued, and the clock signal speed is reduced during the data write process. Thus, the access time is shortened and reliable data writing is realized.

  When the control circuit of the host computer 10 determines that the issued ID data is not (1, 1, 1) (step S140: No), either the read command (Read) or the write command (Write) Is issued (step S170). The issued command is transferred to the data bus DB via the data signal line DL. If the issued command is a write command (step S170: Write), the control circuit of the host computer 10 delays the clock signal speed (step S160). On the other hand, when the issued command is a read command (step S170: Read), the clock signal speed is maintained.

  The control circuit of the host computer 10 issues a number of clock signal pulses corresponding to the address (position) of the memory array 201 that is desired to be written (step S180). That is, since the storage device 20 in this embodiment is a sequential access type storage device, the number of clock signal pulses corresponding to the address desired to be written is issued, and the counter value of the address counter 202 corresponds to a predetermined address. Must increment to the count value. Finally, the control circuit of the host computer 10 causes the reset signal generation circuit to generate a reset / low signal (set to RST = 0) and send it to the reset bus RB via the reset signal line RL to store the storage devices 20, 21. , 22, 23, 24 are completed. In this way, the access is completed by sending the reset signal RST (reset low signal), and the reset signal RST is also sent when the power is turned off. Therefore, even when the power is turned off during data writing, at least the writing is finished. The data writing process can be completed normally.

  Next, processing executed by the constituent circuits of the storage devices 20, 21, 22, 23, and 24 when accessed by the host computer 10 will be described with reference to FIG. In this description, the storage device 20 is representatively described.

  The factory setting unit 206 of the storage device 20 determines whether there is a test signal input (TEST = 1) or not (TEST = 0) (step S200). When the factory setting unit 206 determines that there is a test signal input (step S200: No), a factory setting process described later is executed separately.

  When the factory setting unit 206 determines that no test signal is input (step S200: Yes), each component device of the storage device 20 operates based on the various signals sent from the host computer 10 described above. Hereinafter, the operation of the storage device 20 will be described according to the signal output timing sent by the host computer 10 with reference to FIG. 7 and FIG.

  When the reset / low signal is input to the reset bus RB, the address counter 202 resets the counter value to the initial value (0) (step S210). Also, the ID comparator 203 and the I / O controller 205 are initialized. That is, the two registers in the ID comparator are cleared, and the I / O controller 205 sets the data transfer direction to the memory array 201 to the read direction and sets the signal line connected to the data signal terminal DT to high impedance to perform data transfer. Prohibit transfer.

  As described above, when the reset signal RST switches from low to high, the host computer 10 sends various data in synchronization with the rising edge of the clock signal SCK. Similarly, when the reset signal RST switches from low to high, the address counter 202 increments the counter value one by one from the initial value in synchronization with the rising edge of the clock signal SCK.

  The ID comparator 203 acquires the data sent to the data bus DB in synchronization with the rising edges of the three clock signals SCK after the reset signal RST is switched from low to high, that is, 3-bit ID data. Store in the first 3-bit register (step S220a). At the same time, the ID comparator 203 obtains data from the address of the memory cell 201 specified by the counter values 00, 01, 02 of the address counter 202, that is, obtains identification data stored in the memory cell 201. And stored in the second 3-bit register (step S220b).

  The ID comparator 203 determines whether or not the ID data (identification data) stored in the first and second registers match (step S230). Further, the ID comparator 203 also determines whether or not the common ID data held in advance matches the ID data stored in the first register. If the ID comparator 203 determines that the ID data do not match (step S230: No), the access to the memory array 201 by the host computer 10 is not permitted, and the access process in the storage device 20 ends. In such a case, access to any of the other storage devices 21, 22, 23, and 24 is permitted.

  On the other hand, if the ID comparator 203 determines that the ID data match (step S240), it sends an access permission signal EN to the operation code decoder 204. In such a case, only the storage device 20 among the plurality of storage devices 20, 21, 22, 23, 24, or all the storage devices 20, 21, 22, when the ID data is (1, 1, 1). , 23, and 24 are permitted to access the memory array. The operation code decoder 204 that has received the access permission signal EN receives the read / write command sent to the data bus in synchronization with the rising edge of the fourth clock signal SCK after the reset signal RST is switched from low to high. It is determined whether there is a write command acquired (step S240).

  If the operation code decoder 204 determines that the data is write data (step S240: Yes), it sends a write command to the I / O controller 205. The I / O controller 205 that has received the write command changes the data transfer direction to the memory cell 201 to the write direction, cancels the high impedance setting of the signal line connected to the data terminal DT, and allows data transfer ( Step S250). In this state, the write data sent to the data bus is one bit at a time in the address (position) of the memory array 201 specified by the counter value of the address counter 202 that is sequentially counted up in synchronization with the clock signal SCK. It is stored sequentially. Since the storage device 20 according to the present embodiment is sequentially accessed in this way, the write data sent from the host computer 10 is currently stored in the memory array 201 except for the data corresponding to the address desired to be rewritten. It has the same value (0 or 1) as the recorded data. That is, the data of the address that is not rewritten in the memory array 201 is overwritten with the same value.

  If the operation code decoder 204 determines that it is not write data (step S240: No), it sends a read command to the I / O controller 205. The I / O controller 205 that has received the read command changes the data transfer direction to the memory cell 201 to the read direction, cancels the high impedance setting of the signal line connected to the data terminal DT, and allows data transfer. (Step S260). In this state, data stored in the memory array 201 is sequentially read out in the order of addresses (positions) specified by the counter value of the address counter 202 that is sequentially incremented in synchronization with the clock signal SCK. The first buffer memory of the O controller 205 is sequentially overwritten.

  That is, only the data of the address read last (data at the address position designated by the host computer 10) is finally held in the second buffer memory of the I / O controller 205. The I / O controller 205 sends the read data held in the second buffer memory to the data bus DB via the data terminal DT and transfers it to the host computer 10.

  Finally, when a reset / low signal is input, the address counter 202, the ID comparator 203, and the I / O controller 205 are initialized, and the writing or reading of data is completed. Note that read or write data is determined in 1-bit units, and re-input of a reset / low signal is not an operation necessary for determining data. Further, as described above, since the reset signal RST is output even when the power is shut off, even if the power is accidentally shut down during the data writing, the data that has been written at that time In this embodiment, since data is written in 1-bit units, problems such as garbled data can be avoided for data that has been written.

  Further, when the power is shut off, the power supply compensation circuit compensates the power supply for a predetermined period, and when data is written, the data is sequentially written from the write priority data such as the remaining ink amount or the ink consumption amount. Therefore, even when writing to a plurality of storage devices 20, 21, 22, 23, 24 is necessary, writing of write priority data to all the storage devices can be completed.

D. Configuration of storage system and storage device according to second embodiment:
The internal configuration of the storage system and the storage device according to the second embodiment will be described with reference to FIGS. FIG. 9 is an explanatory diagram showing a configuration example of a storage system including a plurality of storage devices and a host computer according to the second embodiment. FIG. 10 is a block diagram showing the internal circuit configuration of the storage device according to the second embodiment.

  The storage system according to the second embodiment is characterized in that the storage devices 40, 41, 42, 43, and 44 constituting the system do not include the test signal terminal TT for TEST mode. Since the other configuration of the storage system is the same as the configuration of the storage system according to the first embodiment, the same reference numerals are given and the description thereof is omitted. The internal configuration of the storage device 40 will be described with reference to FIG. The storage device 40 does not include the test signal terminal TT, and does not include a circuit corresponding to the factory setting unit 206 included in the storage device 20 according to the first embodiment. That is, since the factory setting unit is a circuit necessary for writing the identification information and data to the storage device 40 by the method according to the third embodiment described later, the identification information and the data by the method according to the fourth embodiment. This circuit is unnecessary when writing. Therefore, in the second embodiment, the storage device 40 that does not include a circuit corresponding to the factory setting unit 206 is illustrated. Since the circuit configuration is the same as that of the storage device 20 according to the first embodiment except that the test signal terminal TT and the factory setting unit 206 are not provided, the same reference numerals are used and description thereof is omitted. To do. Furthermore, since the operations of the storage system and the storage device 40 according to the second embodiment are the same as the operations of the storage system and the storage device 20 according to the first embodiment, the description thereof is omitted.

E. Writing of identification data to the storage device in the test mode (factory setting process) according to the third embodiment Next, identification data for the storage devices 20, 21, 22, 23, and 24 in the test mode according to the third embodiment and the initial Write processing of write data will be described with reference to FIGS. FIG. 11 is a flowchart showing the flow of the test mode write process according to the third embodiment. FIG. 12 is a flowchart showing an example of the connection state between the test host computer and the storage device when executing the test mode write processing according to the third embodiment.

  The configuration of the storage device to which the write / read processing in the test mode according to the third embodiment can be applied is the same as the configuration of the storage device in the storage system according to the first embodiment. Omitted. Further, the process according to the third embodiment is performed with the storage device 20 attached to the ink cartridge when the ink cartridge is manufactured, or with the storage device 20 removed after the ink cartridge is collected, as shown in FIG. This can be executed by connecting the signal lines from the host computer 10 (or a dedicated test host computer) to the terminals CT, DT, RT, TT (probes) of the storage device 20 on a one-to-one basis.

  This processing starts after the TEST signal is sent from the host computer 100 to the storage device 20, that is, after the processing shifts to the factory setting processing in the flowchart shown in FIG. The factory setting unit 206 does not transfer the input clock signal SCK to the address counter 202, and prohibits the count up of the counter value in the address counter 202 (step S300). The factory setting unit 206 activates the operation code decoder 204 without the access permission signal EN from the ID comparator 203, and after the test signal is input, obtains data (command) first sent to the data bus DB. A mode command is sent to the operation code decoder 204 (step S310). The data string input to the data bus DB in the test mode is as shown in FIG. 3, and the command acquired by the operation code decoder 204 is a write command or a read command.

  The operation code decoder 204 analyzes the acquired command, sets the data transfer direction with respect to the memory array 201 to the write direction or the read direction with respect to the I / O controller 205, and sets the data bus DB and the I / O controller 205 A request is made to set the signal line connecting the two to a data transfer enabled state (step S320).

  When the command analysis is completed, the operation code decoder 204 notifies the factory setting unit 206 of the completion of the command analysis, and the factory setting unit 206 that has received this transfers the input clock signal SCK to the address counter 202. (Step S330). When the analysis result by the operation code decoder 204 is a write command (step S340: Write), the data sent to the data bus DB is sequentially written to the address specified by the counter value in the address counter 202 (step S350). . Therefore, data following the write command can be written from address 00 of the memory array 201, and the identification data is written into the 3 bits of the first area of the memory array 201 by giving the identification data to the 3-bit data following the write command. be able to.

  The test host computer 100 reads the data in the memory array 201 (step S360) and determines whether or not it matches the transmitted data (step S370). If the test host computer 100 determines that the two data match (step S370: Yes), the test host computer 100 determines that the writing is correctly completed and ends the factory setting process. On the other hand, if the test host computer 100 determines that the two data do not match (step S370: No), the data is written again.

  On the other hand, when the analysis result by the operation code decoder 204 is a write command (step S340: Read), the address counter 202 sequentially reads the data up to the address specified by the counter value, and the data at the specified address is stored. The data is sent to the host computer 10 via the data bus DB (step S380).

F. Writing of identification data to the storage device in the test mode (factory setting process) according to the fourth embodiment Next, the flow of the test mode writing process according to the fourth embodiment will be described with reference to FIG. 13 and FIG. FIG. 13 is a flowchart showing the flow of the test mode write process according to the fourth embodiment. FIG. 14 is an explanatory diagram showing an example of the connection relationship between the test host computer and the storage device when executing the test mode write processing according to the third embodiment. The configuration of the storage device to which the present embodiment can be applied is the same as the configuration of the storage device 40 according to the second embodiment, so that the same reference numerals are given and description thereof is omitted. As shown in FIG. 10, this processing is characterized in that the target storage device 40 does not need to include the factory setting unit 206 in order to invalidate the ID check by the test terminal TT and the ID comparator 203.

  Further, the process according to the fourth embodiment is performed with the storage device 20 attached to the ink cartridge at the time of manufacturing the ink cartridge, or with the storage device 20 removed after the ink cartridge is collected, as shown in FIG. It can be executed by connecting the signal lines from the host computer 10 (or a dedicated test host computer) to the terminals CT, DT, RT (probes) of the storage device 40 on a one-to-one basis.

  First, the test host computer 100 sequentially issues arbitrary ID data (step S400) and inputs it to the ID comparator 203 via the data bus DB until it matches the identification data of the memory array 201 (step S410: No). ). In this embodiment, since 3-bit data is used as ID data and identification data, there are eight combinations.

  The determination of whether or not the identification data and the ID data match in the test host computer 100 can be realized as follows, for example. First, when a write / read command is received from the ID comparator 203 under the condition that the access permission signal EN is not transferred, the I / O controller 205 sends all data strings of 1 or 0 to the data bus DB. The operation code decoder 204 is set so as to make a request. When the acquired read data is all 1 or all 0, the test host computer 100 determines that the transmitted ID data and the identification information of the storage device 400 do not match, and again stores the ID data in the storage device 400. Send to On the other hand, if the acquired read data is not all 1 or all 0, the test host computer 100 determines that the transmitted ID data matches the identification information of the storage device 400. Therefore, the test host computer 100 repeats the process of sending the ID data to the storage device 400 and acquiring the data sent to the data bus DB until the ID data matches the identification information of the storage device 400. Execute.

  When the test host computer 100 matches the identification data and ID data of the memory array 201 (step S410: Yes) and detects the access permission signal EN from the ID comparator 203, the test host computer 100 has the same capacity as the capacity of the memory array 201. Is written into the memory array 201 (S420). In this embodiment, since the memory array 201 has a capacity of 256 bits, data of a capacity of 252 bits from the fifth bit to the 256th bit which can be written is written. Subsequently, the test host computer 100 writes the data (identification data) having a 3-bit capacity of 257 to 259 bits into the memory array 201 (step S430). Since writing has already been completed up to the 256th bit in the address of the memory array 201, newly written data is written in the first 1st to 3rd bits of the memory array 201. As a result, identification data is written in the first 3 bits of the memory array 201.

  When determining whether the transmitted ID data matches the identification information of the storage device 400, the test host computer 100 may monitor the access permission signal EN of the ID comparator 203. This is because the access permission signal EN is sent to the ID comparator 203 when the ID data matches the identification information.

  According to this method, for example, even when the storage device 20 is taken out from the collected ink cartridge, the memory array 201 is overwritten without knowing what value the identification data of the storage device 400 is. New identification data can be written. Further, it is not necessary to include the factory setting unit 206 in the storage device 400, and the number of circuits constituting the storage device 400 can be reduced.

  As described above, according to the storage device 20 and the storage system according to the first to fourth embodiments, the identification data is transferred from the start position of the memory array of the storage devices 20, 21, 22, 23, 24 to the 3-bit area. Therefore, a desired storage device can be selected from the plurality of storage devices 20, 21, 22, 23, and 24. The area in which the identification data is stored is normally read-only, but can be written in the test mode, so that the identification data can be easily rewritten. For example, when the storage devices 20, 21, 22, 23, and 24 are provided in the ink cartridge as in this embodiment, the storage devices 20, 21, 22, 23, and 24 are removed from the used ink cartridge. , Making it easy to write identification data when reusing. As a result, the reuse of the storage devices 20, 21, 22, 23, and 24 can be promoted.

  The storage device and the storage system according to the present invention have been described above based on the embodiments. However, the embodiments of the present invention described above are for facilitating the understanding of the present invention and limit the present invention. is not. The present invention can be changed and improved without departing from the spirit and scope of the claims, and it is needless to say that the present invention includes equivalents thereof.

  In the above embodiment, the EEPROM is used as the storage device 20, but the storage device is not limited to the EEPROM as long as the storage data can be maintained in a nonvolatile manner and the storage data can be rewritten.

  In the above-described embodiment, the remaining ink data and the ink consumption data are illustrated as the priority write data, but other data may be used as the priority write data instead of or in addition to these data.

  In the above embodiment, the identification data is stored in the first 3 bits of the memory array 201. However, the capacity of the identification data can be appropriately changed depending on the number of storage devices to be identified. The capacity of the memory array 201 is not limited to 256 bits, and can be changed as appropriate according to the amount of data to be stored.

  In the above-described embodiment, the case where the five storage devices 20, 21, 22, 23, and 24 are provided in five independent ink cartridges (five colors) has been described. The present invention can also be applied to ink cartridges of colors to four colors or six colors or more.

  In the above embodiment, the storage device 20 according to this embodiment has been described as a storage device for storing ink cartridge information in an ink cartridge for an ink jet printer. However, the storage device 20 according to this embodiment is in another form. It goes without saying that it can be used. That is, in a system using a plurality of storage devices, identification data is stored in the first 3 bits of the memory array 201 in order to access a specific storage device, but the capacity of the identification data is that of the storage device to be identified. It can be changed appropriately depending on the number. The capacity of the memory array 201 is not limited to 256 bits, and can be changed as appropriate according to the amount of data to be stored.

It is explanatory drawing which shows the structural example of the storage system containing the some storage device and host computer which concern on 1st Example. It is explanatory drawing which shows an example of the data sequence transmitted from the host computer 10 at the time of normal. It is explanatory drawing which shows an example of the data sequence sent out from the host computer 10 at the time of test mode. It is a block diagram which shows the internal circuit structure of the memory | storage device 20 according to 1st Example. 3 is a flowchart showing a processing routine executed by the host computer 10 when accessing the storage devices 20, 21, 22, 23, 24. 4 is a flowchart showing a processing routine executed by each constituent circuit of the storage devices 20, 21, 22, 23, and 24 when accessed by the host computer 10. 6 is a timing chart showing a temporal relationship among a reset signal RST, a clock signal SCK, a data signal CDA, and an address counter value when reading data. 6 is a timing chart showing a temporal relationship among a reset signal RST, a clock signal SCK, a data signal CDA, and an address counter value at the time of data writing. It is explanatory drawing which shows the structural example of the storage system containing the some storage device and host computer which concern on 2nd Example. It is a block diagram which shows the internal circuit structure of the memory | storage device 40 concerning 2nd Example. It is a flowchart which shows the flow of the writing process at the time of the test mode according to 3rd Example. It is explanatory drawing which shows an example of the connection relation of the test host computer and memory | storage device at the time of implementing the test mode write-in process according to 3rd Example. It is a flowchart which shows the flow of the write process at the time of the test mode according to 4th Example. It is explanatory drawing which shows an example of the connection relation of the test host computer and memory | storage device at the time of implementing the test-mode write-in process according to 4th Example. It is explanatory drawing which shows an example in which the memory | storage device is applied to an ink cartridge in 1st Example.

Explanation of symbols

10. Host computer 100 ... Test host computer 100
20, 21, 22, 23, 24 ... storage device 40, 41, 42, 43, 44 ... storage device 200 ... memory module 201 ... memory array 202 ... address counter 203 ... ID comparator 204 ... Operation code decoder 205 ... I / O controller 206 ... Factory setting unit VDL ... Power supply voltage supply line VDDH ... Power supply positive terminal VDDM ... Power supply positive terminal CL ... Clock signal line DL ... Data signal line RL ... Reset signal line CB ... Clock bus DB ... Data bus RB ... Reset bus VSC ... Power supply negative signal line COL ... Cartridge out signal Line COT ... Cartridge out detection terminal CT ... Clock signal terminal DT ... Data signal terminal TT ... Test signal terminal RT ... Reset signal terminal SCK ... Clock signal CDA ... Data signal RST ... Set signal COO ... cartridge out signal

Claims (28)

A nonvolatile storage device that is bus-connected to a clock signal line, a data signal line, and a reset signal line and that is initialized by a reset signal input through the reset signal line,
A memory having a storage area that is accessed sequentially, and having an area in which writing can be performed under a predetermined condition and identification information is stored in a non-rewritable state under a non-predetermined condition from the start position of the storage area to a predetermined position. A storage device including a cell. The storage device according to claim 1 further includes:
A data bus connected to the data signal line;
The counter value is counted up in synchronization with the clock signal input via the clock signal line, the position to be accessed in the storage area of the storage cell is specified, and the counter value is reset to the initial value at initialization. An address counter;
The memory cell is arranged between the memory cell and the data bus, controls the data transfer direction to the memory cell and the data transfer direction of the data bus, and at initialization, sets the data transfer direction to the memory cell to the data read direction. An input / output control device for setting and disconnecting from the data bus;
Whether the input identification information connected to the data bus and input via the data bus matches the identification information stored in the memory cell read via the input / output control device. A comparison device for determining
A storage device comprising: an access permission device that permits access to the memory cell when it is determined that the identification information matches. The storage device according to claim 2 further includes:
When the determination result that the input identification information and the identification information stored in the memory cell match is received from the comparison device and connected to the data bus and the comparison device, A command decoder that analyzes a write / read command input via the command and requests the input / output control device to switch the data transmission direction of the data bus based on the analysis result;
The input / output control device maintains a data transfer direction to the memory cell and a connection cut-off state with the data bus at the time of initialization until analysis of a write / read command by the command decoder is completed. Storage device. The storage device according to claim 3 further includes:
A test terminal connected to the test mode signal line;
A test mode control device that is connected to the test terminal and determines whether or not a test mode signal is input;
The storage device according to claim 1, wherein the predetermined condition is when an input of a test mode signal is detected. The storage device according to claim 4.
When the test mode control device detects an input of the test mode signal, the test mode control device outputs a test mode command to the command decoder, and the address until the test decoder finishes analyzing the test mode command. Prohibit the counter from counting up,
The instruction decoder, after analyzing the test mode instruction, requests the input / output control device to write to the storage cell and release the data bus,
The input / output control device performs writing to the storage cell and releasing the data bus based on a request from the instruction decoder. The storage device according to claim 4.
When the test mode control device detects an input of the test mode signal, the test mode control device outputs a test mode command to the command decoder, and the address until the test decoder finishes analyzing the test mode command. Prohibit the counter from counting up,
The instruction decoder, after analyzing the test mode instruction, requests the input / output control device to read the memory cell and release the data bus,
The storage device according to claim 1, wherein the input / output control device executes reading from the storage cell and release of the data bus based on a request from the instruction decoder. The storage device according to any one of claims 1 to 6,
The storage cell has a writable area for writing write data following a storage area in which the identification information is stored. The storage device according to any one of claims 1 to 7,
A memory device, wherein data is written to the memory cell in 1-bit units.   An ink cartridge comprising the storage device according to any one of claims 1 to 8. The ink cartridge according to claim 9, wherein
The ink cartridge includes a storage device having identification information different for each ink type corresponding to the ink type to be stored. A plurality of nonvolatile storage devices bus-connected to the clock signal line, the data signal line and the reset signal line; and a control device connected to the storage device via the clock signal line, the data signal line and the reset signal line A storage system comprising:
The controller is
A clock signal generation circuit;
A reset signal generation circuit for generating a reset signal for initializing the storage device;
An identification information issuing circuit for issuing identification information corresponding to identification information of a desired storage device among the plurality of storage devices;
A data sending circuit for sending a data string including the issued identification information and read / write command to the data signal line in synchronization with the generated clock signal;
Each of the storage devices
A data bus connected to the data signal line;
A memory having a storage area that is accessed sequentially, and having an area in which writing can be performed under a predetermined condition and identification information is stored in a non-rewritable state under a non-predetermined condition from the start position of the storage area to a predetermined position. Cell,
A comparison device that is connected to the data bus and determines whether the identification information sent from the control device matches the identification information stored in the memory cell;
An input / output control device that is disposed between the data bus and the data bus and controls data transfer to the data bus and the storage cell;
The data bus is connected to the data bus and the comparison device, and when it is determined that the identification information sent from the control device by the comparison device matches the identification information stored in the memory cell, the data bus is And a command decoder that analyzes a write / read command input via the command and requests the input / output control device to switch a data transmission direction of the data bus based on the analysis result. The storage system of claim 11, wherein
The storage device further includes
The counter value is counted up in synchronization with the clock signal input via the clock signal line, the position to be accessed in the storage area of the storage cell is specified, and the counter value is reset to the initial value at initialization. With an address counter,
The input / output control device sets a data transfer direction to the memory cell at the time of initialization and interrupts data transfer to the data bus at the time of initialization until the analysis of the write / read command by the command decoder is completed. A storage system characterized by maintaining a state at the time of initialization. The storage system according to claim 11 or claim 12,
The identification information issuing circuit of the control circuit issues common identification information common to all storage devices,
A storage system, wherein the comparison device of the storage device holds the common identification information. The storage system according to any one of claims 11 to 13,
The control circuit includes a power compensation circuit that supplies power for a predetermined period after power is shut off,
The reset signal generation circuit of the control circuit generates a reset signal at least one of when the control circuit is turned on and when the power is turned off.
When the data transmission circuit of the control circuit detects generation of the reset signal during write data transfer, the data transmission circuit ends transmission of the data currently being written, and the power supply compensation circuit compensates for power supply. A storage system that sends write priority data that can be written to. The storage system of claim 12,
A test control device having a test signal generation circuit that generates a test signal that enables writing to or reading from all the storage areas of the storage cells of the storage device instead of the control device,
The storage device further detects whether or not the test signal is input, and outputs a test mode instruction to the instruction decoder when detecting the input of the test mode signal, and the test mode by the instruction decoder. Having a test mode control device for prohibiting counting up of the address counter until the analysis of the instruction is completed;
The instruction decoder, after analyzing the test mode instruction, sets a data transfer direction for the storage cell to a write direction or a read direction for the input / output control device, and sets a data transfer direction for the data bus to a write direction or a read direction. Request to set the direction,
2. The storage system according to claim 1, wherein the input / output control device sets a data transfer direction for the storage cell to a write direction or a read direction and sets a data transfer direction for the data bus to a write direction or a read direction. The storage system according to claim 15, wherein at the time of data writing in the test mode,
The test control device sends a data string configured in the order of a write command, identification information, and write data from the top to the data signal line, and starts at a predetermined position from the start position of the storage area in the storage cell of the storage device. The storage system, wherein the identification information is written before. The storage system according to any one of claims 11 to 14,
In place of the control device, an identification information search circuit for searching for identification information that matches the identification information stored in the storage cell of the storage device;
When the identification information search circuit searches for identification information that matches the identification information stored in the storage cell, the identification is performed after the write data corresponding to the end position of the storage area of the storage cell in the storage device. A test control device having a data string sending circuit in a test mode for sending a data string having information to the data signal line;
The test control device writes the identification information from a start position of a storage area in a storage cell of the storage device to a predetermined position. The storage system according to any one of claims 11 to 17,
The storage system according to claim 1, wherein the clock signal generation circuit in the control circuit makes the generation interval of the clock signal longer when the write command is transmitted through the data transmission circuit than when the read command is transmitted. The storage system according to any one of claims 11 to 18,
And a module substrate on which a plurality of storage devices are accommodated, the storage devices are serially connected, and a storage device detection signal line having one end grounded and the other end connected to the control circuit is disposed. ,
The storage system includes a storage device detection circuit that determines whether or not all storage devices are arranged on a module substrate based on a value of the storage device detection signal line. The storage system of claim 19,
The storage device detection circuit of the control circuit determines that all storage devices are arranged on the module substrate when the storage device detection signal line indicates a ground voltage. The storage system of claim 19,
The storage device detection circuit of the control circuit determines that at least one storage device is not disposed on the module substrate when the storage device detection signal line indicates a voltage other than a ground voltage. Storage system.   The storage system according to any one of claims 11 to 21, wherein the storage device is provided in an ink cartridge and stores various data related to the ink type stored in the ink cartridge. A featured storage system.   23. The storage system according to claim 11, wherein the control circuit supplies power to the storage device only when data is read from or written to the storage device. A storage system characterized by This is a method of accessing a desired storage device from a plurality of nonvolatile storage devices that are bus-connected to a clock signal line, a data signal line, and a reset signal line and each have unique identification information. And
Output a reset signal to the reset signal line,
A method of sending a data string including identification information of the storage device desired to be accessed and a read / write command to a data signal line in synchronization with a clock signal. A storage device having a storage area that is sequentially accessed and having a storage cell having an area in which identification information is stored from the start position of the storage area to a predetermined position, and is connected to a clock signal line An access request processing method in a storage device that shares a clock bus, a data bus connected to a data signal line, and a reset bus connected to a reset signal line with another storage device,
When a reset signal is detected on the reset bus, the counter value of the address counter is reset to the initial value.
Determining whether the identification information sent to the data bus matches the identification information stored in the memory cell;
If it is determined that the identification information sent to the data bus matches the identification information stored in the memory cell, the read / write command sent to the data bus is analyzed,
Controlling data transfer of the data bus and data transfer to the storage cell based on the analysis result;
A method of writing data to a desired position of the memory cell or reading data from the memory cell according to a counter value of an address counter. A method of storing identification information from a start position of a storage area of a storage cell to a predetermined position in a nonvolatile storage device having storage cells that are sequentially accessed,
When the reset signal is detected, the counter value of the address counter is reset to the initial value and the counter value counting up in synchronization with the clock signal is prohibited.
Based on a write command sent to the data bus, the data transfer direction of the data bus is set to the write direction and the data transfer direction to the memory cell is set to the write direction,
After completion of the setting of the data transfer direction, allowing the counter value to be counted up in synchronization with the clock signal in the address counter,
A method of writing identification information from a start position of a storage area of the storage cell to a predetermined position in accordance with a count value of the address counter, and subsequently writing data. A method of reading data stored in a storage area of a storage cell from a head position in a nonvolatile storage device having a storage cell accessed sequentially,
When the reset signal is detected, the counter value of the address counter is reset to the initial value and the counter value counting up in synchronization with the clock signal is prohibited.
Based on the read command sent to the data bus, the data transfer direction of the data bus is set to the read direction and the data transfer direction to the memory cell is set to the read direction,
After completion of the setting of the data transfer direction, allowing the counter value to be counted up in synchronization with the clock signal in the address counter,
A method of reading data stored in a storage area of the storage cell from a head position according to a count value of the address counter. A method of storing identification information from a start position of a storage area of a storage cell to a predetermined position in a nonvolatile storage device having storage cells that are sequentially accessed,
Search for identification information that matches the identification information stored in the storage cell of the storage device;
When searching for identification information that matches the identification information stored in the storage cell, the searched identification information and a write command are sent to the storage device,
Sending a data string having the identification information next to the write data corresponding to the end position of the storage area of the storage cell in the storage device to the storage device;
A method of writing data to the end position of the storage area of the storage cell according to the count value of the address counter, and subsequently writing the identification information from the start position of the storage area of the storage cell to a predetermined position.

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