JP2006121060A - Semiconductor device and its fabrication process, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a plurality of functions, and to provide its fabrication process. <P>SOLUTION: The semiconductor device comprises a thin-film integrated circuit, a first substrate having a sensor or an antenna, and a second substrate having an antenna, wherein the first substrate having a sensor or an antenna and the second substrate having an antenna are holding the thin-film integrated circuit between. When a plurality of antennas are provided and the communication frequency bands are different, a plurality of frequency bands can be received, and thereby the selection width of a reader/writer is widened. When a sensor and an antenna are provide, information detected by the sensor can be converted into a signal and delivered to the reader/writer through the antenna. Consequently, the semiconductor device has a added value higher than that of conventional semiconductor devices such as wireless chip. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device.

In recent years, technology development for transposing a thin film integrated circuit provided over an insulating substrate has been advanced. As such a technique, for example, a separation layer is provided between the thin film integrated circuit and the substrate, and the separation layer is removed using a gas containing a halogen to separate the thin film integrated circuit from the supporting substrate, and then There is a technique for transposing (see Patent Document 1).
JP-A-8-254686

However, according to Patent Document 1 described above, a release layer is formed on one surface of a substrate, a plurality of elements are formed on the release layer, and then the release layer is removed. Then, the plurality of elements are separated from the substrate, and a space is generated between the substrate and the plurality of elements. After that, a plurality of elements are bonded to the substrate, but the plurality of elements are as thin as several μm and very light. Therefore, before the plurality of elements are bonded to the substrate, the plurality of elements may be scattered from the substrate.

  Thus, an object of the present invention is to manufacture a semiconductor device while preventing scattering of a plurality of elements. It is another object to provide a semiconductor device having a plurality of functions and a manufacturing method thereof.

  One embodiment of the present invention includes a thin film integrated circuit, a first substrate having a sensor or an antenna, a second substrate having an antenna, a first substrate having a sensor or an antenna, and a second substrate having an antenna. The gist is that the semiconductor device sandwiches the thin film integrated circuit.

    In the semiconductor device, the thin film integrated circuit and the sensor, and the thin film integrated circuit and the antenna are electrically connected with conductive particles. The thin film integrated circuit and the sensor, and the thin film integrated circuit and the antenna each sandwich a resin having conductive particles. Furthermore, the first substrate and the second substrate have flexibility.

  In addition, according to one aspect of the present invention, after a peeling layer is formed on one surface of the first substrate, the peeling layer is selectively removed, and the first region where the peeling layer is provided and the peeling layer are provided. A second region that is not formed is formed. Subsequently, a base insulating layer is formed over the entire surface over the first region and the second region. Then, the base insulating layer is in contact with the separation layer in the first region, and is in contact with the first substrate in the second region. Next, a thin film integrated circuit including a plurality of thin film transistors is formed over the base insulating layer. Subsequently, an opening is formed in the insulating layer and the insulating layer formed in the thin film integrated circuit, and then the peeling layer is removed by introducing an etching agent into the opening. At this time, a space is generated between the substrate and the base insulating layer in the first region where the release layer is provided, but the substrate and the base insulating layer are in close contact with each other in the second region where the release layer is not provided. It remains. As described above, since the region where the first substrate and the base insulating layer are in close contact with each other is provided even after the peeling layer is removed, scattering of the thin film integrated circuit provided over the base insulating layer can be prevented. it can. After the separation layer is removed, the thin film integrated circuit and the second substrate having an antenna are integrated so that the conductive layer on the second substrate and the first conductive layer for connecting the thin film integrated circuit are in contact with each other. Make it. Next, the thin film integrated circuit and the substrate are peeled off from the first substrate. At this time, the second conductive layer for connection is exposed on the back surface. The gist is to bond the thin film integrated circuit and the third substrate having an antenna or sensor so that the conductive layer on the third substrate is in contact with the second conductive layer for connecting the thin film integrated circuit. And

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a peeling layer is selectively formed over a first substrate, a base insulating layer is formed in contact with the first substrate and the peeling layer, and the base insulating layer is formed. A plurality of thin film transistors are formed thereon, a first opening is formed so that the first substrate is exposed, and a second opening is formed so that a source region and a drain region of the plurality of thin film transistors are exposed. Forming a first conductive layer filling the first opening and a second conductive layer filling the second opening, forming a third opening so that the release layer is exposed, The plurality of thin film transistors and the first thin film transistors are connected so that the second conductive layer and the third conductive layer provided over the second substrate are connected to each other by introducing an etching agent into the opening 3 and removing the peeling layer. After bonding the two substrates, the plurality of thin film transistors are peeled off from the first substrate. A first conductive layer, as the fourth conductive layer provided on the third substrate is connected, wherein attaching the plurality of thin film transistors and the third substrate.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a peeling layer is selectively formed over a first substrate, a base insulating layer is formed so as to be in contact with the first substrate and the peeling layer, and base insulating is performed. A plurality of thin film transistors are formed on the layer, a first opening is formed so that the first substrate is exposed, and a second opening is formed so that a source region and a drain region of the plurality of thin film transistors are exposed. Forming a first conductive layer filling the first opening and a second conductive layer filling the second opening, and forming a third opening so that the release layer is exposed; An etching agent is introduced into the third opening to selectively remove the peeling layer, so that the second conductive layer and the third conductive layer provided on the second substrate are connected to each other. After bonding the thin film transistor and the second substrate, physical means (physical force) The plurality of thin film transistors are peeled from one substrate, and the plurality of thin film transistors and the third substrate are attached so that the first conductive layer and the fourth conductive layer provided over the third substrate are connected to each other. It is characterized by that.

  In the above manufacturing method, the first substrate is a glass substrate, a quartz substrate, a metal substrate having an insulating layer, a plastic substrate that can withstand the processing temperature of the manufacturing process, or the like. Further, as a peeling layer, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn) , Ruthenium (Ru), rhodium (Rh), lead (Pd), osmium (Os), iridium (Ir), silicon (Si), or an alloy material containing the element as a main component, or the element It is characterized by being formed of a layer made of a compound material containing as a main component. In addition, as the separation layer, a layer containing an oxide of the above element is formed by a sputtering method in an oxygen atmosphere. In addition, the peeling layer is formed using the above element, an alloy material containing the element as a main component, or a compound material containing the element as a main component, and a layer containing an oxide of silicon is formed thereon. It is characterized by. The etching agent is a gas or a liquid containing halogen fluoride.

  According to another aspect of the semiconductor device of the present invention, a first conductive layer provided over a first substrate, a base insulating layer covering the first conductive layer, and a first conductive layer provided over the base insulating layer A thin film transistor, a second thin film transistor, an interlayer insulating layer covering the first thin film transistor and the second thin film transistor, a second conductive layer and a third conductive layer provided on the interlayer insulating layer, and a second substrate The second conductive layer is connected to the source region and the drain region of the first thin film transistor through the opening provided in the interlayer insulating layer, and the base insulating layer The third conductive layer is connected to the first conductive layer through the opening provided in each of the interlayer insulating layers, and the third conductive layer is connected to the source region of the second thin film transistor through the opening provided in the interlayer insulating layer. And the drain region and the fourth conductivity Characterized in that it connects to.

  In addition, the first substrate and the second substrate have flexibility.

The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are each electrically connected by conductive particles. The first substrate and the base insulating layer, and the interlayer insulating layer and the second substrate are in contact with a resin having conductive particles.

  Further, the first conductive layer and the fourth conductive layer may function as an antenna. Furthermore, the first conductive layer may function as an antenna, and the fourth conductive layer may be electrically connected to the sensor.

  The second conductive layer has a region in contact with the first conductive layer and a region in contact with the interlayer insulating layer through a resin having conductive particles.

  In addition, each of the first thin film transistor and the second thin film transistor may include a sidewall insulating layer.

  The present invention prevents the scattering of a plurality of thin film transistors provided above the base insulating layer by removing the peeling layer while providing a region where the substrate and the base insulating layer are in close contact with each other. Manufacture can be performed easily.

  The semiconductor device of the present invention includes a thin film integrated circuit portion and a plurality of antennas. For this reason, even if one antenna is damaged, electromagnetic waves supplied from an external device can be received by another antenna, and thus durability can be improved. In addition, when the frequency bands communicated by a plurality of antennas are different, a plurality of frequency bands can be received, so that the selection range of the reader / writer is widened.

  The semiconductor device of the present invention includes a thin film integrated circuit portion, an antenna, and a sensor. For this reason, it is possible to record information after processing the information detected by the sensor in the thin film integrated circuit section. It is also possible to convert information detected by the sensor into a signal and output the signal to the reader / writer via the antenna. Therefore, a semiconductor device having higher added value than a conventional semiconductor device such as a wireless chip can be manufactured.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
A method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings.

First, release layers 101 to 104 are formed on one surface of a substrate 100 (see a cross-sectional view in FIG. 1A and a perspective view in FIG. 5A, and AB in FIG. 1A is FIG. 5). (Corresponding to AB in (A)).

As shown in FIG. 1A, a substrate 100 is a glass substrate, a quartz substrate, a metal substrate or a stainless steel substrate with an insulating layer formed on one surface, and a heat-resistant plastic substrate that can withstand the processing temperature in this step. Etc. are used. Since there is no restriction on the size and shape of the substrate 100 listed above, for example, if a substrate having a side of 1 meter or more and a rectangular shape is used, the productivity is remarkably improved. Can do. This advantage is a great advantage compared to the case of using a circular silicon substrate.

Further, the thin film integrated circuit provided over the substrate 100 is peeled off from the substrate 100 later. Therefore, a new thin film integrated circuit may be formed on the substrate 100 by reusing the substrate 100. As a result, cost can be reduced. Note that a quartz substrate is preferably used as the substrate 100 to be reused.

The peeling layers 101 to 104 are selectively formed by forming a thin film on one surface of the substrate 100 and then etching using a resist mask formed by a photolithography method. The release layers 101 to 104 are formed by a known means (sputtering method, plasma CVD method, etc.) tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni). , Elements selected from cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), lead (Pb), osmium (Os), iridium (Ir), silicon (Si) Alternatively, a single layer or a layer formed of an alloy material containing the element as a main component or a compound material containing the element as a main component is formed. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

In the case where the separation layers 101 to 104 have a single-layer structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is preferably formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

In the case where the separation layers 101 to 104 have a stacked structure, preferably, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as a first layer, and tungsten, molybdenum, or tungsten and molybdenum is formed as a second layer. An oxide, nitride, oxynitride or nitride oxide of the mixture is formed.

In the case where a stacked structure of a layer containing tungsten and a layer containing an oxide of tungsten is formed as the separation layers 101 to 104, a layer containing tungsten is formed, and a layer containing silicon oxide is formed thereon, thereby forming tungsten. The fact that a layer containing an oxide of tungsten is formed at the interface between the layer and the silicon oxide layer may be utilized. Further, the layer containing tungsten oxide may be formed by performing thermal oxidation treatment, oxygen plasma treatment, treatment with a solution having strong oxidizing power such as ozone water, or the like on the surface of the layer containing tungsten. The same applies to the case where a layer containing tungsten is formed and a layer containing tungsten nitride, oxynitride and nitride oxide is formed thereon, and after the layer containing tungsten is formed, nitriding is performed on the upper layer. A silicon layer, a silicon oxynitride layer, and a silicon nitride oxide layer may be formed.

The oxide of tungsten is represented by WOx, 2 ≦ x ≦ 3, when x is 2 (WO ₂ ), when x is 2.5 (W ₂ O ₅ ), when x is 2.75 (W ₄ O ₁₁ ), and x is 3 (WO ₃ ). In forming the tungsten oxide, the above-mentioned value of x is not particularly limited, and may be determined based on the etching rate. However, the layer having the best etching rate is a layer containing tungsten oxide (WOx, 0 <x <3) formed by a sputtering method in an oxygen atmosphere. Therefore, in order to shorten the manufacturing time, a layer containing a tungsten oxide is preferably formed as the separation layer by a sputtering method in an oxygen atmosphere.

Moreover, according to said process, although the peeling layers 101-104 are formed so that the board | substrate 100 may be touched, this invention is not restrict | limited to this process. A base insulating layer may be formed so as to be in contact with the substrate 100, and the peeling layers 101 to 104 may be provided so as to be in contact with the insulating layer.

Next, an insulating layer 105 serving as a base is formed so as to cover the separation layers 101 to 104. The insulating layer 105 is formed as a single layer or a stacked layer containing a silicon oxide or a silicon nitride by a known means (such as a sputtering method or a plasma CVD method). The silicon oxide material is a substance containing silicon (Si) and oxygen (O), and corresponds to silicon oxide, silicon oxynitride, silicon nitride oxide, or the like. The silicon nitride material is a substance containing silicon and nitrogen (N), and corresponds to silicon nitride, silicon oxynitride, silicon nitride oxide, or the like.

In the case where the base insulating layer 105 has a two-layer structure, for example, a silicon nitride oxide layer may be formed as a first layer and a silicon oxynitride layer may be formed as a second layer. When the underlying insulating layer has a three-layer structure, a silicon oxide layer is formed as the first insulating layer, a silicon nitride oxide layer is formed as the second insulating layer, and oxynitriding is performed as the third insulating layer A silicon layer may be formed. Alternatively, a silicon oxynitride layer may be formed as the first insulating layer, a silicon nitride oxide layer may be formed as the second insulating layer, and a silicon oxynitride layer may be formed as the third insulating layer. The base insulating layer functions as a blocking film that prevents impurities from entering the crystalline semiconductor layer formed later from the substrate 100.

Next, an amorphous semiconductor layer (eg, a layer containing amorphous silicon) is formed over the insulating layer 105. This amorphous semiconductor layer is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a known means (sputtering method, LPCVD method, plasma CVD method or the like). Subsequently, a known crystallization method (laser crystallization method, thermal crystallization method using an RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, and crystallization are promoted. A crystalline semiconductor layer is formed by crystallization by a combination of a thermal crystallization method using a metal element to be combined and a laser crystallization method). Thereafter, the obtained crystalline semiconductor layer is etched into a desired shape to form crystalline semiconductor layers 127 to 130.

As a specific example of a manufacturing process of the crystalline semiconductor layers 127 to 130, first, an amorphous semiconductor layer having a thickness of 66 nm is formed by a plasma CVD method. Next, after a solution containing nickel, which is a metal element for promoting crystallization, is held on the amorphous semiconductor layer, the amorphous semiconductor layer is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor layer. Thereafter, laser light is irradiated as necessary, and selective etching is performed using a resist mask formed by a photolithography method, so that crystalline semiconductor layers 127 to 130 are formed.

Note that when the crystalline semiconductor layers 127 to 130 are formed by a laser crystallization method, a continuous wave or pulsed gas laser or solid laser is used. As the gas laser, an excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti: sapphire laser, or the like is used. As the solid-state laser, a laser using a crystal such as YAG, YVO ₄ , YLF, or YAlO ₃ doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm is used.

In addition, when an amorphous semiconductor layer is crystallized using a metal element that promotes crystallization, it is possible to crystallize at a low temperature for a short time and the crystal orientation is aligned. Remains in the crystalline semiconductor layer, resulting in an increase in off-current and unstable characteristics. Therefore, an amorphous semiconductor layer functioning as a gettering site is preferably formed over the crystalline semiconductor layer. Since the amorphous semiconductor layer serving as a gettering site needs to contain an impurity element such as phosphorus or argon, it is preferably formed by a sputtering method in which argon can be contained at a high concentration. After that, heat treatment (RTA method or thermal annealing using a furnace annealing furnace) is performed to diffuse the metal element in the amorphous semiconductor layer, and then the amorphous semiconductor layer containing the metal element is removed. To do. Then, the content of the metal element in the crystalline semiconductor layer can be reduced or removed.

Next, the gate insulating layer 106 that covers the crystalline semiconductor layers 127 to 130 is formed. The gate insulating layer 106 is formed by a known method (plasma CVD method or sputtering method) as a single layer or a stack of layers containing silicon oxide or silicon nitride. Specifically, a layer containing silicon oxide, a layer containing silicon oxynitride, or a layer containing silicon nitride oxide is formed as a single layer or a stacked layer.

Next, a first conductive layer and a second conductive layer are stacked over the gate insulating layer 106. The first conductive layer is formed with a thickness of 20 to 100 nm by a known means (plasma CVD method or sputtering method). The second conductive layer is formed with a thickness of 100 to 400 nm by a known means. The first conductive layer and the second conductive layer include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used.

Examples of combinations of the first conductive layer and the second conductive layer include a tantalum nitride (TaN) layer and a tungsten (W) layer, a tungsten nitride (WN) layer and a tungsten layer, and a molybdenum nitride (MoN) layer. A molybdenum (Mo) layer etc. are mentioned. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the formation of the first conductive layer and the second conductive layer. In the case of a three-layer structure instead of a two-layer structure, a structure of a molybdenum layer, an aluminum layer, and a molybdenum layer may be employed.

Furthermore, instead of the stacked structure of the first conductive layer and the second conductive layer, a single conductive layer may be formed using the same material as the first conductive layer or the second conductive layer. Good.

Next, a resist mask is formed using a photolithography method, and an etching process for forming a gate electrode is performed, so that conductive layers (also referred to as gate electrode layers) 107 to 110 function as the gate electrode. Form.

Next, an impurity element imparting N-type conductivity is added to the crystalline semiconductor layers 128 and 130 at a low concentration by ion doping or ion implantation, so that N-type impurity regions 111 and 112 are formed. The impurity element imparting N-type may be an element belonging to Group 15, for example, phosphorus (P) or arsenic (As).

Subsequently, an impurity element imparting P-type is added to the crystalline semiconductor layers 127 and 129 to form P-type impurity regions 113 and 114. For example, boron (B) is used as the impurity element imparting P-type.

Next, an insulating layer is formed so as to cover the gate insulating layer 106 and the conductive layers 107 to 110. The insulating layer is formed by a known means (plasma CVD method or sputtering method) such as a layer containing an inorganic material of silicon, silicon oxide or silicon nitride (sometimes referred to as an inorganic layer), or an organic resin. A layer containing an organic material (sometimes referred to as an organic layer) is formed as a single layer or a stacked layer. Preferably, a layer made of an oxide of silicon is formed as the insulating layer.

Next, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction, and insulating layers in contact with the side surfaces of the conductive layers 107 to 110 (hereinafter referred to as sidewall insulating layers) 115 to 118. (See FIG. 1C). The sidewall insulating layers 115 to 118 are used as a doping mask for forming an LDD region later.

Note that in the etching step for forming the sidewall insulating layers 115 to 118, the gate insulating layer 106 is also etched to form gate insulating layers 119 to 122. The gate insulating layers 119 to 122 are layers that overlap with the conductive layers 107 to 110 and the sidewall insulating layers 115 to 118. Thus, the gate insulating layer 106 is etched because the etching rates of the materials of the gate insulating layer 106 and the sidewall insulating layers 115 to 118 are the same. In FIG. Show. Therefore, when the etching rates of the materials of the gate insulating layer 106 and the sidewall insulating layers 115 to 118 are different, the gate insulating layer 106 remains even after the etching process for forming the sidewall insulating layers 115 to 118. There is a case.

Subsequently, an impurity element imparting N-type is added to the crystalline semiconductor layers 128 and 130 using the sidewall insulating layers 115 to 118 as masks, and first N-type impurity regions (also referred to as LDD regions) 123 and 124 are added. And second N-type impurity regions 125 and 126 are formed. The concentration of the impurity element contained in the first N-type impurity regions 123 and 124 is lower than the concentration of the impurity element in the second N-type impurity regions 125 and 126.

Note that in order to form the first N-type impurity regions 123 and 124, the gate electrode has a stacked structure of two or more layers, and anisotropic etching is performed on the gate electrode to form a lower conductive layer constituting the gate electrode. There are a method using a layer as a mask and a method using a sidewall insulating layer as a mask. A thin film transistor formed using the former method is called a GOLD (Gate Overlapped Lightly Doped Drain) structure. In the present invention, either the former method or the latter method may be used. However, the use of the latter method using the sidewall insulating layer as a mask has an advantage that the LDD region can be reliably formed and the width of the LDD region can be easily controlled.

Through the above steps, N-type thin film transistors 131 and 132 and P-type thin film transistors 133 and 134 are completed.

The N-type thin film transistor 131 has an LDD structure, and includes an active layer including a first N-type impurity region 123 (also referred to as an LDD region), a second N-type impurity region 125, and a channel formation region 135, a gate insulating layer 120 and a conductive layer 108 functioning as a gate electrode.

The N-type thin film transistor 132 has an LDD structure, and includes an active layer including a first N-type impurity region 124 (also referred to as an LDD region), a second N-type impurity region 126, and a channel formation region 136, a gate insulating layer 122 and a conductive layer 110 functioning as a gate electrode.

The P-type thin film transistor 133 has a single drain structure, and includes an active layer including a P-type impurity region 113 and a channel formation region 137, a gate insulating layer 119, and a conductive layer 107 functioning as a gate electrode.

The P-type thin film transistor 134 has a single drain structure and includes an active layer including a P-type impurity region 114 and a channel formation region 138, a gate insulating layer 121, and a conductive layer 109 functioning as a gate electrode.

Next, an insulating layer is formed as a single layer or a stacked layer so as to cover the thin film transistors 131 to 134 (see FIG. 1E). The insulating layer covering the thin film transistors 131 to 134 is formed by a known means (coating method, droplet discharge method, CVD method, sputtering method, etc.), an inorganic material such as silicon oxide or silicon nitride, polyimide, polyamide, benzo A single layer or a stacked layer is formed using an organic material such as cyclobutene, acrylic, epoxy, or siloxane. Siloxane corresponds to a substance in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), for example. As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Further, a fluoro group may be used as a substituent. Furthermore, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

The cross-sectional structure shown in the figure shows the case where two insulating layers are stacked so as to cover the thin film transistors 131 to 134, and a layer containing silicon oxide is formed as the first insulating layer 141, and the second layer is formed. The insulating layer 142 is formed using siloxane. Further, a layer containing silicon nitride may be formed between the first insulating layer and the second insulating layer.

Note that before the insulating layers 141 and 142 are formed, or after one or both of the insulating layers 141 and 142 are formed, the crystallinity of the semiconductor layer is restored and the activity of the impurity element added to the semiconductor layer is increased. Heat treatment for the purpose of hydrogenation of the semiconductor layer is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

Next, the insulating layers 141 and 142 are etched by photolithography to expose the P-type impurity regions 113 and 114, the contact holes 143 to 150 that expose the second N-type impurity regions 125 and 126, and the substrate 100. Contact holes 151 and 152 to be formed are formed (see FIG. 2A).

Note that the contact holes 151 and 152 are formed so as not to contact the peeling layer. By forming the contact holes 151 and 152 at such positions, it is possible to avoid simultaneously removing the conductive layer filling the contact hole when the peeling layer is removed. As a result, defective elements can be reduced and the yield of the semiconductor device can be increased.

Subsequently, a conductive layer is formed so as to fill the contact holes 143 to 152, and the conductive layer is patterned to form conductive layers 155 to 162 (see FIG. 2B). Note that the side surfaces of the conductive layers 155 and 158 formed in this manner are not in contact with the separation layers 101 to 104 but are in contact with the insulating layers 141 and 142. This is to prevent the conductive layers 155 and 158 from being removed by the etching agent when the peeling layers 101 to 104 are removed by the etching agent.

The conductive layers 155 to 162 are formed of an element selected from titanium (Ti), aluminum (Al), and neodymium (Nd) by known means (plasma CVD method or sputtering method) or an alloy containing these elements as a main component. The material or compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon.

For example, the conductive layers 155 to 162 have a stacked structure of a barrier layer, an aluminum silicon (Al—Si) layer and a barrier layer, and a barrier layer, an aluminum silicon (Al—Si) layer, a titanium nitride (TiN) layer, and a barrier layer. Good. Note that the barrier layer corresponds to a layer formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the conductive layers 155 to 162 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. When a lower barrier layer is provided, good contact between aluminum or aluminum silicon and the crystalline semiconductor layer can be obtained. Titanium is a highly reducible element. Therefore, when a barrier layer made of titanium is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, this natural oxide film is reduced and crystalline. Good contact can be made with the semiconductor layer.

Next, the insulating layer 163 is formed as a single layer or a stacked layer so as to cover the conductive layers 155 to 162 (see FIG. 2C). The insulating layer 163 covering the conductive layers 155 to 162 can be formed using a method and a material similar to those of the insulating layer 142 covering the thin film transistor. Next, contact holes are formed in the insulating layer 163 that covers the conductive layers 155 to 162 to form conductive layers 164 and 165. The conductive layers 164 and 165 function as conductive layers for connection to external terminals.

Next, an insulating layer may be formed so as to cover the conductive layers 164 and 165. The insulating layer corresponds to a layer containing carbon such as DLC (diamond-like carbon), a layer containing silicon nitride, a layer containing silicon nitride oxide, a layer containing an organic material (preferably epoxy resin), or the like. Note that the insulating layer functions as a protective layer, and may not be formed if not necessary. Further, when a layer made of an organic material is formed as the insulating layer, the thickness of the insulating layer 163 can be increased. As a result, even after the separation layers 101 to 104 are removed, a plurality of layers on the substrate 100 can be formed. A weight is applied to the element, scattering from the substrate 100 is prevented, and further, a wound shape is not caused, and the element can be prevented from being broken or damaged.

Note that here, the element including the thin film transistors 131 and 133 completed through the above steps and the conductive layers 155 to 158 are collectively referred to as a first thin film integrated circuit 166, and the element including the thin film transistors 132 and 134, The layers 159 to 162, 164, and 165 are collectively referred to as a second thin film integrated circuit 167 (see a cross-sectional view in FIG. 2C and a perspective view in FIG. 5B). Note that in FIG. 2C, one each of the first thin film integrated circuit 166 and the second thin film integrated circuit 167 is shown, but in actuality, as shown in FIG. A plurality of thin film integrated circuits 166 and a plurality of second thin film integrated circuits 167 are arranged. Therefore, a layer in which a plurality of first thin film integrated circuits 166 and second thin film integrated circuits 167 are arranged is sometimes referred to as a layer having the first thin film integrated circuit 166 and the second thin film integrated circuit 167. .

Here, the first thin film integrated circuit 166 is provided with at least a communication circuit that processes electromagnetic waves received by the conductive layer 185 to be connected later. The second thin film integrated circuit 167 is provided with at least a communication circuit that processes electromagnetic waves received by the conductive layer 175 to be connected later. Note that the conductive layer 185 and the conductive layer 175 are illustrated as antennas that receive electromagnetic waves supplied from an external device.

In the case where the antenna formed using the conductive layer 185 and the antenna formed using the conductive layer 175 can receive the same frequency band, the respective conductive layers may be connected to the same thin film integrated circuit. In this case, it is preferable that the antenna formed of the conductive layer 185 and the antenna formed of the conductive layer 175 have the same shape.

In the case where the antenna formed using the conductive layer 185 and the antenna formed using the conductive layer 175 can receive different frequency bands, the conductive layers are connected to different thin film integrated circuits. In this case, the shape of the antenna formed of the conductive layer 185 and the shape of the antenna formed of the conductive layer 175 may be different. This increases the range of antenna selection.

Next, the insulating layers 105, 141, 142, and 163 are etched by photolithography so that part or all of the separation layers 101 to 104 are exposed to form openings 171 and 172 (FIG. 2D ) And a perspective view of FIG.

Next, an etchant is introduced into the openings 171 and 172 to remove the peeling layers 101 to 104 (see the cross-sectional view in FIG. 3A and the perspective view in FIG. 6B). For wet etching, the etchant is a mixture of hydrofluoric acid diluted with water or ammonium fluoride, a mixture of hydrofluoric acid and nitric acid, a mixture of hydrofluoric acid, nitric acid and acetic acid, a mixture of hydrogen peroxide and sulfuric acid, hydrogen peroxide And a mixture of ammonia water and water, a mixture of hydrogen peroxide, hydrochloric acid and water, or the like. In the case of dry etching, a gas containing a halogen atom or molecule such as fluorine or a gas containing oxygen is used. Preferably, a gas or liquid containing halogen fluoride or an interhalogen compound is used as an etchant. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride. Note that since the conductive layers 155 and 158 are provided so as not to be in contact with the separation layers 101 to 104, the conductive layers 155 and 158 are not etched by the etchant in this step.

Next, one surface of the layer including the first thin film integrated circuit 166 and the second thin film integrated circuit 167 is bonded to a substrate 179 provided with a conductive layer 175 (see a cross-sectional view in FIG. 3B). . Note that one surface of the layer including the first thin film integrated circuit 166 and the second thin film integrated circuit 167 is a surface where the conductive layers 164 and 165 and the openings 171 and 172 are exposed. At this time, the layer having the first thin film integrated circuit 166 and the second thin film integrated circuit 167 and the substrate 179 are bonded and integrated using the resin 181 including the conductive particles 180, and the second The conductive layers 164 and 165 included in the thin film integrated circuit 167 are brought into contact with the conductive layer 175 over the substrate 179 through the conductive particles 180. After that, the first thin film integrated circuit 166 and the second thin film integrated circuit 167 are completely separated from the substrate 100 (see the cross-sectional view in FIG. 3C and the perspective view in FIG. 7A).

A substrate 179 provided with a conductive layer 175 includes a film (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), a paper made of a fibrous material, a base film (polyester, polyamide, an inorganic vapor deposition film, Paper) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to sealing treatment with the object to be processed by thermocompression bonding. When performing the sealing treatment, the film is an adhesive layer provided on the outermost surface of the film or a layer provided on the outermost layer. (Not the adhesive layer) is melted by heat treatment and bonded by pressure.

Subsequently, the other surface of the layer including the first thin film integrated circuit 166 and the second thin film integrated circuit 167 is bonded to the substrate 189 provided with the conductive layer 185 (a cross-sectional view and a diagram in FIG. 3D). 7 (B) perspective view). Note that the other surface of the layer including the first thin film integrated circuit 166 and the second thin film integrated circuit 167 is a surface where the conductive layers 155 and 158 and the insulating layer 105 are exposed. The layer having the first thin film integrated circuit 166 and the second thin film integrated circuit 167 and the substrate 189 are bonded and integrated using a resin 191 containing conductive particles 190, and the first thin film integrated circuit is integrated. The conductive layers 155 and 158 included in 166 are brought into contact with the conductive layer 185 over the substrate 189 through the conductive particles 190.

Next, the layer in which the first thin film integrated circuit 166 and the second thin film integrated circuit 167 are integrated with the substrates 179 and 189 having conductive layers is divided using a slicing device, a laser irradiation device, or the like. (See the perspective view of FIG. 7C). Through the above-described steps, a wireless chip (wireless processor, wireless memory) including divided substrates 195 and 196 and a layer formed by the divided first thin film integrated circuit 166 and second thin film integrated circuit 167. A semiconductor device functioning as a wireless tag is completed.

  Note that in this embodiment, the layer including the first thin film integrated circuit 166 and the second thin film integrated circuit 167 and the substrates 179 and 189 having conductive layers are integrated, and then divided into wireless chips (wireless chips). Although a semiconductor device functioning as a processor, a wireless memory, and a wireless tag is formed, the invention is not limited to this process. The layer having the first thin film integrated circuit 166 and the second thin film integrated circuit 167 and the substrate 179 having a conductive layer are integrated and divided, and then the divided first thin film integrated circuit 166 and second thin film integrated circuit are integrated. A substrate having a conductive layer may be bonded to the layer having the circuit 167.

In this embodiment mode, a case where conductive layers 175 and 185 functioning as antennas are provided over divided substrates 195 and 196 is shown. The conductive layer functioning as an antenna is formed using a metal material containing aluminum, copper, or silver. For example, a copper or silver paste composition can be formed by screen printing, offset printing, or an ink jet printing method. Alternatively, an aluminum film may be formed by sputtering or the like and formed by etching. In addition, you may form using an electroplating method and an electroless-plating method.

  Note that, according to the above embodiment, the layer having the first thin film integrated circuit 166 and the second thin film integrated circuit 167 and the substrate 179 and 189 having the conductive layer are the resin 181 including the conductive particles 180 and 190. , 191. However, the present invention is not limited to this mode, and the layers having the first thin film integrated circuit 166 and the second thin film integrated circuit 167 are bonded to the substrates 179 and 189 by further using the bumps 194a to 194d. It is also possible (see FIG. 24).

Note that the conductive layers 175 and 185 over the substrates 179 and 189 are covered with the protective insulating layers 193a and 193b, and openings are formed in the protective insulating layers 193a and 193b at the portions where the bumps 194a to 194d and the conductive particles are in contact. Is provided.

  Next, FIG. 14 shows a configuration of the wireless chip 900 shown in the present embodiment. The wireless chip of this embodiment includes a thin film integrated circuit 901 and antennas 902a and 902b.

    The thin film integrated circuit 901 includes the first thin film integrated circuit 166 and the second thin film integrated circuit 167 shown in FIGS. 3 to 7, and includes an arithmetic processing circuit portion 903, a memory portion 904, and communication circuit portions 905a and 905b. The power supply circuit unit 907 is provided. The memory unit 904 includes one or both of a read-only memory and a rewritable memory. The memory unit 904 includes static RAM (Static RAM), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, and the like, and records information received from outside via the antennas 902a and 902b as needed. be able to. The memory unit 904 may be divided into a first memory unit 910 for storing signals received via the antennas 902a and 902b and a second memory unit 911 for recording information written from the reader / writer device. it can. Further, a read-only memory unit may be provided by a mask ROM or a programmable ROM.

  The first memory unit 910 is preferably composed of a flash memory or the like that allows sequential writing and does not lose data. In addition, it is preferable to apply a storage element having a floating gate structure, which can be written only once.

  Note that the memory portion 904 may be configured by a storage element having a floating gate structure in which data can be sequentially written and data is not lost. In particular, it is preferable to use a memory element having a floating gate structure, which can be written only once. The wireless chip having this configuration has only a function of reading information stored in the memory unit. By simplifying the function, the wireless chip can be reduced in size. In addition, power can be saved.

  The communication circuit units 905a and 905b include demodulation circuits 912a and 912b and modulation circuits 913a and 913b, respectively. The demodulation circuits 912a and 912b demodulate signals input via the antennas 902a and 902b, respectively, and output the signals to the arithmetic processing circuit unit 903. The signal includes information to be stored in the memory unit 904. Information read from the memory unit 904 is output to the modulation circuits 913a and 913b through the arithmetic processing circuit unit 903, respectively. The modulation circuits 913a and 913b modulate this signal into a signal capable of wireless communication, and output the signal to an external device via the antennas 902a and 902b, respectively.

  The antennas 902a and 902b receive electromagnetic waves supplied from an external device called a reader / writer and generate necessary power in the power supply circuit unit 907. The antennas 902a and 902b may be appropriately designed according to a frequency band for communication. As the frequency band of electromagnetic waves, a long wave band up to 135 kHz, a short wave band of 6 to 60 MHz (typically 13.56 MHz), an ultra high frequency band of 400 to 950 MHz, a microwave band of 2 to 25 GHz, and the like can be used. As the long wave band or short wave band antenna, an antenna using electromagnetic induction by a loop antenna is used. In addition, a mutual inductive action (electromagnetic coupling method) or an electrostatic induction action (electrostatic coupling method) may be used. Power is generated by the power supply circuit unit 907 via an antenna. In addition, the arithmetic processing circuit portion 903, the memory portion 904, and the communication circuit portions 905a and 905b are operated using the power. Note that the antenna 902a may be provided as a data communication antenna and the antenna 902b may be provided separately as a power supply antenna.

When the antenna 902a and the antenna 902b can receive the same frequency band, the signal may be demodulated and modulated by one communication circuit unit (for example, the communication circuit unit 905a). However, in this case, it is preferable that the antenna 902a and the antenna 902b have the same shape.

In the case where the antennas 902a and 902b can receive different frequency bands, the antennas 902a and 902b are preferably connected to different communication circuit portions 905a and 905b. In this case, the shapes of the antenna 902a and the antenna 902b may be different.

  According to this embodiment mode, by removing the peeling layer while providing a region where the substrate and the base insulating layer are in close contact with each other, the thin film integrated circuit provided above the base insulating layer is prevented from being scattered, and the thin film integrated circuit Can be easily manufactured.

  In addition, the semiconductor device of this embodiment includes a thin film integrated circuit portion and a plurality of antennas. For this reason, even if one antenna is damaged, electromagnetic waves supplied from an external device can be received by another antenna, and thus durability can be improved. Further, when the frequency bands communicated by a plurality of antennas are different, a plurality of frequency bands can be received, so that transmission / reception can be performed with reader / writers of different styles.

(Embodiment 2)
According to the above embodiment, the peeling layers 101 to 104 are completely removed by the etching agent (see FIG. 3A). However, the present invention is not limited to this mode, and the peeling layers 101 to 104 may be selectively removed (see FIG. 4A). After that, a substrate 179 provided with a conductive layer 175 is provided on the layer having the first thin film integrated circuit 166 and the second thin film integrated circuit 167, integrated with the substrate, and then physical means (physical force) Thus, the layer including the first thin film integrated circuit 166 and the second thin film integrated circuit 167 and the substrate 179 provided with the conductive layer 175 may be separated from the substrate 100 (see FIG. 4C). ). When the layer including the first thin film integrated circuit 166 and the second thin film integrated circuit 167 is peeled from the substrate 100 by physical means (physical force), the peeling layers 101 to 104 may remain on the substrate 100. There are two cases where the peeling layers 101 to 104, the first thin film integrated circuit 166, and the second thin film integrated circuit 167 are peeled from the substrate 100, and this embodiment shows the latter case (FIG. 4 ( C)). The physical means (physical force) corresponds to means for applying stress from the outside, such as wind pressure of a gas blown from a nozzle, ultrasonic waves, or the like.

As described above, the peeling layers 101 to 104 are not completely removed by the etching agent, but by selectively removing the peeling layers 101 to 104 and using physical means (physical force) in combination, The scattering of the thin film integrated circuit can be prevented and the time for removing the peeling layers 101 to 104 can be shortened in a short time, so that productivity can be improved.

(Embodiment 3)
In this embodiment, an example in which a substrate having a sensor is bonded instead of one of the substrate 179 having a conductive layer or the substrate 189 having a conductive layer in Embodiments 1 and 2 is described.

  Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor is typically formed of an element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

  8 is a cross-sectional view of a semiconductor device in which a sensor, a photosensor as a representative example, is provided instead of the substrate 189 having the conductive layer of Embodiment 1. FIG. On the substrate 251, a photodiode 250 formed of the first electrode 252, the light receiving layer 253, and the second electrode 254 is formed. Further, the photodiode 250 is covered with an interlayer insulating layer 255, and a connection conductive layer 256 connected to the first electrode through the interlayer insulating layer 255, and a connection connected to the second electrode. A conductive layer 257 is formed. The first thin film integrated circuit 166 and the second thin film integrated circuit are formed so that the conductive layers 155 and 158 of the second thin film integrated circuit and the conductive layers 256 and 257 on the substrate 251 are in contact with the conductive particles 190, respectively. The layer having 167 and the substrate 251 are bonded to each other. In addition to the sensor, a sensor circuit may be provided on the substrate 251. Note that although a photodiode is used in FIG. 8, a phototransistor can be used instead. Furthermore, instead of the optical sensor, an element for detecting temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics can be provided as appropriate. Further, instead of the conductive layers 256 and 257 for connection, conductive layers constituting the sensor may be in contact with the conductive layers 155 and 158.

Next, FIG. 9 illustrates a structure of a wireless chip 900 including a thin film integrated circuit 901, a sensor portion 908, and an antenna 902. The sensor unit 908 detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor unit 908 includes a sensor 906 and a sensor circuit 909 that controls the sensor 906. The sensor 906 is formed of an element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 909 detects a change in impedance, reactance, inductance, voltage, or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the arithmetic processing circuit unit 903.

  The thin film integrated circuit 901 includes an arithmetic processing circuit unit 903, a memory unit 904, a communication circuit unit 905, and a power supply circuit unit 907. The memory unit 904 can record external information received via the sensor unit 908 and the antenna 902 as needed. The memory unit 904 can be divided into a first memory unit 910 that stores a signal detected by the sensor unit 908 and a second memory unit 911 that records information written from the reader / writer device.

  The first memory unit 910 is preferably composed of a flash memory or the like that enables sequential writing and records no data in order to record information detected by the sensor unit 908. In addition, it is preferable to apply a storage element having a floating gate structure, which can be written only once.

  The communication circuit unit 905 includes a demodulation circuit 912 and a modulation circuit 913. The demodulation circuit 912 demodulates a signal input via the antenna 902 and outputs the demodulated signal to the arithmetic processing circuit unit 903. The signal includes a signal for controlling the sensor unit 908 and information stored in the memory unit 904. Further, a signal output from the sensor circuit 909 and information read from the memory unit 904 are output to the modulation circuit 913 through the arithmetic processing circuit unit 903. The modulation circuit 913 modulates this signal into a signal capable of wireless communication, and outputs the signal to an external device via the antenna 902.

  Electric power necessary for operating the arithmetic processing circuit unit 903, the sensor unit 908, the memory unit 904, and the communication circuit unit 905 is supplied via the antenna 902.

  In accordance with this embodiment mode, the peeling layer is removed while providing a region where the substrate and the base insulating layer are in close contact with each other, thereby preventing scattering of the thin film integrated circuit provided above the base insulating layer and including the thin film integrated circuit. A semiconductor device can be manufactured easily.

  The semiconductor device of the present invention includes a thin film integrated circuit portion, an antenna, and a sensor. For this reason, it is possible to record information after processing the information detected by the sensor in the thin film integrated circuit section. It is also possible to convert information detected by the sensor into a signal and output the signal to the reader / writer via the antenna. Therefore, a semiconductor device having higher added value than a conventional semiconductor device such as a wireless chip can be manufactured.

(Embodiment 4)
Although the semiconductor device functioning as a wireless chip has been described in the above embodiment, the present invention is not limited to this embodiment. Therefore, in this embodiment, a semiconductor device different from the above structure is described.

  First, a semiconductor device of the present invention in which a plurality of functions are integrated will be described (see FIGS. 18A and 18B). A plurality of thin film integrated circuits 601 to 604 are bonded to a substrate 600 provided with a conductive layer. The conductive layer on the substrate 600 and the connecting conductive layer on one surface included in each of the thin film integrated circuits 601 to 604 are bonded using a resin 644 including conductive particles 645. Each of the thin film integrated circuits 601 to 603 functions as one or more selected from a central processing unit (CPU, Central Processing Unit), a memory, a network processing circuit, a disk processing circuit, an image processing processor, a sound processing processor, and the like. . The thin film integrated circuit 604 can be provided with the thin film integrated circuit formed in any of Embodiments 1 to 3. Here, an example having one antenna and a thin film integrated circuit is shown. The connection conductive layer on the other surface of the thin film integrated circuit 604 and the connection conductive layer 606 of the substrate 605 having a conductive layer such as an antenna are bonded using a resin 646 containing conductive particles 647.

  Next, a semiconductor device of the present invention having a display portion will be described (see FIGS. 19A and 19B. AB in FIG. 19A corresponds to AB in FIG. 19B). .) Thin film integrated circuits 624 and 625 are bonded on the substrate 620, and thin film integrated circuits 628 and 629 are bonded on the connection films 641 and 642. As the thin film integrated circuits 624 and 625, the thin film integrated circuit formed in any of Embodiments 1 to 3 can be provided. Here, an example having one antenna and a thin film integrated circuit is shown.

The connection conductive layer on the back surface of the display portion 623 and the thin film integrated circuit 624 is connected through a conductive layer 631 on the substrate 620. The connection conductive layer on the surface of the thin film integrated circuit 624 is bonded to the connection conductive layer 639 of the substrate 626 having a conductive layer such as an antenna with a resin 637 containing conductive particles 638.

The thin film integrated circuit 624 and the thin film integrated circuit 628 are connected to each other through the conductive layer 634 on the substrate 620 and the conductive layer 635 on the connection film 641. For the connection of these conductive layers, a resin 654 containing conductive particles 655 is used. Further, the substrate 620 and the counter substrate 621 are bonded by a sealant 630.

  Next, a semiconductor device of the present invention functioning as an IC card will be described (see FIGS. 20A and 20B). A thin film integrated circuit 611 is bonded onto the substrate 610. The thin film integrated circuit formed in any of Embodiments 1 to 3 can be provided. Here, an example having a sensor and a thin film integrated circuit is shown. The conductive layer 612 over the substrate 610 and the connection conductive layer on the back surface of the thin film integrated circuit 611 are bonded using a resin 651 containing conductive particles 652. In addition, the connection conductive layer on the surface of the thin film integrated circuit 611 is bonded using a connection conductive layer 659 of the substrate 615 including the sensor element 616 and a resin 657 including conductive particles 658.

The thin film integrated circuit included in the semiconductor device of the present invention is small, thin, and lightweight. A semiconductor device including a plurality of systems (see FIG. 18), a semiconductor device having a display function (see FIG. 19), an IC card ( By using each of them in FIG. 20), further higher functionality and higher added value can be realized.

In this embodiment, a method for forming a fine conductive layer will be described (see FIG. 10).

First, the separation layers 101 to 104, the insulating layer 105, the crystalline semiconductor layers 127 to 130, the gate insulating layer 106, and the conductive layers 271 and 272 are formed over the substrate 100 having an insulating surface. Next, resist masks 273 to 276 are formed over the conductive layers 271 and 272 using a photomask (see FIG. 10A).

Next, the resist masks 273 to 276 are etched by a known etching process such as an oxygen plasma process to form new resist masks 283 to 286 (see FIG. 10B). The resist masks 283 to 286 that have undergone the above steps can be finer than the limit that can be formed by a photolithography method.

Next, by performing etching using the resist masks 283 to 286, fine conductive layers 107 to 110 can be manufactured (see FIG. 10C). The conductive layers 107 to 110 function as gate electrodes.

As a different method from the above, first, the separation layers 101 to 104, the insulating layer 105, the crystalline semiconductor layers 127 to 130, the gate insulating layer 106, the conductive layers 271 and 272, a resist are formed over the substrate 100 having an insulating surface. Masks 273 to 276 are formed (see FIG. 10A).

Next, the conductive layers 271 and 272 are etched using the resist masks 273 to 276 to form conductive layers 263 to 266 (see FIG. 11A).

Subsequently, without removing the resist masks 273 to 276, only the side surfaces of the conductive layers 263 to 266 in the stacked body of the resist masks 273 to 276 and the conductive layers 263 to 266 are selectively etched (FIG. 11B). reference). As such an etching method, isotropic dry etching or wet etching may be used. Then, similarly to the above method, fine conductive layers 107 to 110 with different limits that can be formed by photolithography can be formed (see FIG. 11C). The conductive layers 107 to 110 function as gate electrodes.

  A fine thin film transistor having a channel length of 0.5 μm or less can be formed by any of the above methods. If the thin film transistor is fine, it can be highly integrated accordingly, so that a semiconductor device with high performance elements can be manufactured. In addition, since the width of the channel formation region is narrowed, high-speed operation is realized.

  Since the wireless chip supplies power from an antenna, it is difficult to stabilize the power and it is necessary to suppress power consumption as much as possible. If the power consumption of the wireless chip increases, it is necessary to input electromagnetic waves strongly. Therefore, the power consumption of the reader / writer increases, adverse effects on other devices and the human body, and the communication distance between the wireless chip and the reader / writer is limited. Inconvenience occurs.

  Therefore, the present invention relates to N-type thin film transistors 242, 244 including lower gate electrodes 232, 234 and upper gate electrodes 236, 238, lower gate electrodes 231, 233, and upper gate electrodes 235, 237, respectively. A semiconductor device using P-type thin film transistors 241 and 243 each including two gate electrodes is provided (see FIG. 12).

  In order to suppress power consumption, a method of applying a bias voltage to the lower gate electrodes 231 to 234 is effective. Specifically, a negative bias for the lower gate electrodes 232 and 234 of the N-type thin film transistors 242 and 244 is effective. By applying the voltage, the threshold voltage can be increased and the leakage current can be reduced. In addition, by applying a positive bias voltage, the threshold voltage can be lowered and current can easily flow through the channel formation region. Accordingly, the thin film transistors 242 and 244 can be operated at higher speed or at a lower voltage.

  By applying a positive bias voltage to the lower gate electrodes 231 and 233 of the P-type thin film transistors 241 and 243, the threshold voltage can be increased and the leakage current can be reduced. Further, by applying a negative bias voltage, the threshold voltage can be lowered and current can easily flow through the channel formation region. Accordingly, the thin film transistors 241 and 243 can be operated at higher speed or at a lower voltage.

  As described above, by controlling the bias voltage applied to the lower gate electrode, the threshold voltage of the thin film transistors 241 to 244 is changed to reduce the leakage current, thereby suppressing the power consumption of the wireless chip itself. Can do. Therefore, even if complicated processing such as encryption processing is performed, the power supply does not become unstable, and the power supply is stabilized. Further, it is not necessary to input electromagnetic waves, and the communication distance with the reader / writer can be improved.

Note that application of a bias voltage to the thin film transistors 241 to 244 may be controlled by providing a dedicated control circuit.

  A cross-sectional structure of the capacitor transistor used in the semiconductor device of the present invention is described (see FIG. 13A). In the capacitor transistor 301, the source electrode and the drain electrode are connected to each other. That is, the source region 304 and the drain region 305 are connected by the conductive layer 303. Therefore, when the capacitor transistor 301 is turned on, a capacitor is formed between the gate electrode and the channel formation region. Such a cross-sectional structure of the capacitor transistor 301 is not different from that of a normal thin film transistor. An equivalent circuit diagram is represented as shown in FIG.

  However, in the above structure, since the gate insulating film is used to form the capacitor, the capacitance value may be affected by the fluctuation of the threshold voltage of the capacitor transistor 301. Therefore, a capacitor transistor 301 to which an impurity element is added may be used in the region 302 that overlaps with the gate electrode (see FIG. 13C). Since the capacitor transistor having the above structure can form a capacitor regardless of the threshold voltage of the transistor, it is possible to prevent the influence of variations in the threshold voltage of the transistor. An equivalent circuit diagram in this case is represented as shown in FIG.

Next, an example of the layout of the wireless chip described in Embodiments 1 and 2 is described with reference to FIG. First, an overall layout of one wireless chip is described (see FIG. 26A). The wireless chip is formed in separate layers by a first antenna 201, an element group 214 constituting a power supply unit and a logic unit, and a second antenna (not shown). Specifically, The first antenna 201 is formed on the element group 214. A part of a region where the element group 214 is formed and a part of a region where the first antenna 201 is formed overlap. In the configuration shown in the drawing, the width of the wiring constituting the first antenna 201 is designed to be 150 μm, the width between the wirings is designed to be 10 μm, and the number of windings is 15 turns. Further, the first antenna 201 is not limited to the wound shape as shown in FIG. The shape of the first antenna 201 may be a curved shape (see FIG. 27A) or a straight shape (see FIG. 27B).

Although not shown, the second antenna is provided on the opposite side of the first antenna via the element group 214. Similarly to the first antenna, the second antenna can have any of a rolled shape, a curved shape, and a straight shape.

Next, a layout of the element group 214 included in the power supply portion and the logic portion will be described (see FIG. 26B). The rectifier circuit 202 and the storage capacitor 203 constituting the power supply unit are provided in the same region. The logic unit includes a demodulation circuit 204, a clock generation / correction circuit 205, each code recognition and determination circuit 206, a memory controller 207, and a modulation circuit 208 including a modulation resistor. The demodulation circuit 204 and each code recognition / determination circuit 206 are provided in two locations. The mask ROM 211 and the memory controller 207 are provided adjacent to each other. The clock generation / correction circuit 205 and each code recognition / determination circuit 206 are provided adjacent to each other. The demodulation circuit 204 is provided between the clock generation / correction circuit 205 and each code recognition / determination circuit 206. Also, a detection capacitor 212 for the logic unit and a detection capacitor 213 for the power source unit are provided. A modulation circuit 208 including a modulation resistor is provided between the detection capacitor 212 and the detection capacitor 213.

The mask ROM 211 is used to create memory contents in the memory in the manufacturing process. Here, a power line connected to a high potential power supply (also referred to as VDD) and a power supply line connected to a low potential power supply (also referred to as VSS) are used. Two power supply lines are provided, and the memory content stored in the memory cell is determined by which power supply line the transistor included in each memory cell is connected to.

FIG. 15A illustrates an example of a sensor portion that is a detection portion in a wireless chip that detects ambient brightness or the presence or absence of light irradiation. The sensor unit 908 includes a sensor 906 and a sensor circuit 909. The sensor 906 is formed of a photodiode, a phototransistor, or the like. The sensor circuit 909 includes a sensor drive circuit 952, a detection circuit 953, and an A / D conversion circuit 954.

  FIG. 15B is a circuit diagram illustrating the detection circuit 953. When the reset TFT 955 is turned on, a reverse bias voltage is applied to the sensor 906. Here, an operation in which the potential of the negative terminal of the sensor 906 is charged to the potential of the power supply voltage is referred to as “reset”. Thereafter, the reset TFT 955 is turned off. At that time, due to the electromotive force of the sensor 906, the potential state changes with time. That is, the potential of the negative terminal of the sensor 906 that has been charged to the potential of the power supply voltage gradually decreases due to the charge generated by the photoelectric conversion. When the bias TFT 957 is turned on after a certain time has elapsed, a signal is output to the output side through the amplification TFT 956. In this case, the amplification TFT 956 and the bias TFT 957 operate as a so-called source follower circuit. Although FIG. 15B shows an example in which the source follower circuit is formed of an n-channel TFT, it can of course be formed of a p-channel TFT. A power supply voltage Vdd is applied to the amplification side power supply line 958. The bias-side power supply line 959 is given a reference potential of 0 volts. The drain side terminal of the amplification TFT 956 is connected to the amplification side power supply line, and the source side terminal is connected to the drain terminal of the bias TFT 957. The source side terminal of the bias TFT 957 is connected to the bias side power line 959. A bias voltage Vb is applied to the gate terminal of the bias TFT 957, and a bias current Ib flows through the TFT. The bias TFT 957 basically operates as a constant current source. The input voltage Vin is applied to the gate terminal of the amplifying TFT 956, and the source terminal becomes the output terminal. The input / output relationship of this source follower circuit is Vout = Vin−Vb. This output voltage Vout is converted into a digital signal by the A / D conversion circuit 954. The digital signal is output to the arithmetic processing circuit unit 903.

  FIG. 16 shows an example in which an element for detecting capacitance is provided in the sensor 906. The element for detecting the capacitance includes a pair of electrodes. An object to be detected such as a liquid or a gas is filled between the electrodes. By detecting a change in capacitance between the pair of electrodes, for example, the state of the contents sealed in the container is determined. Further, it is possible to detect a change in humidity by interposing a polyimide, acrylic or other hygroscopic dielectric material between a pair of electrodes and reading a minute change in electric resistance.

  The sensor circuit 909 has the following configuration. A pulse generator (oscillation circuit) 960 generates a measurement reference signal and inputs the signal to the electrode of the sensor 906. The voltage at this time is also input to the voltage detection circuit 961. The reference signal detected by the voltage detection circuit 961 is converted into a voltage signal indicating an effective value by the conversion circuit 963. A current flowing between the electrodes of the sensor 906 is detected by a current detection circuit 962. The signal detected by the current detection circuit 962 is converted by the conversion circuit 964 into a current signal indicating an effective value. The arithmetic circuit 966 calculates electric parameters such as impedance or admittance by performing arithmetic processing on the voltage signal output from the conversion circuit 963 and the current signal output from the conversion circuit 964. The output of the voltage detection circuit 961 and the output of the current detection circuit 962 are input to the phase comparison circuit 965. The phase comparison circuit 965 outputs the phase difference between the two signals to the arithmetic circuit 967. The arithmetic circuit 967 calculates the capacitance using the output signals of the arithmetic circuit 966 and the phase comparison circuit 965. Then, the signal is output to the arithmetic processing circuit unit 903.

  FIG. 17 is a flowchart for explaining the operation of the data management device 401 and the wireless chip 900. The data management device 401 transmits control signals such as a sensor activation signal, a data read signal, and a data write signal. The wireless chip 900 receives the control signal. The wireless chip 900 identifies a control signal with an arithmetic processing circuit. Then, it is determined which operation is to be performed among the operation of measuring and recording the data by operating the sensor unit 908, the operation of reading the data recorded in the memory unit, and the operation of writing the data to the memory unit. In the operation of measuring and recording data, the sensor circuit is operated, the sensor signal is read, binarized via the sensor circuit, and recorded in the memory unit. In the operation of writing data, the data transmitted from the data management device 401 is written into the memory unit 904. In the operation of reading the data recorded in the memory unit, the operation of reading the data in the memory unit 904 and transmitting it to the data management device 401 is performed. The power necessary for the operation of the circuit is assumed to be performed simultaneously with the signal transmission or at any time.

  Next, a system for transmitting and receiving information detected by the sensor of the wireless chip (hereinafter referred to as sensor detection information) to and from the reader / writer will be described with reference to FIG. FIG. 25 illustrates an example of a wireless chip 900 that is a semiconductor device of the present invention and a reader / writer 920 that transmits and receives information from and to the wireless chip 900. The reader / writer 920 includes an antenna 921, a communication circuit unit 922 including a transmitter 923, a demodulation circuit 924, and a modulation circuit 925. In addition, an arithmetic processing circuit unit 926 and an external interface unit 927 are provided. In order to encrypt and transmit the control signal, an encryption / decryption circuit unit 928 and a memory unit 929 may be provided. The power supply circuit unit 930 supplies power to each circuit, and supplies the power supplied from the external power supply 931 to each circuit.

  Information detected by the sensor unit 908 of the wireless chip 900 is processed by the arithmetic processing circuit unit 903 and then held in the memory unit 904. A signal 942 transmitted as a radio wave via the modulation circuit 925 of the reader / writer 920 is converted into an AC electrical signal by electromagnetic induction in the antenna 902 of the wireless chip 900. The demodulation circuit 912 of the communication circuit unit 905 demodulates the alternating electrical signal and transmits it to the arithmetic processing circuit unit 903. The arithmetic processing circuit unit 903 calls the sensor detection information held in the memory unit 904 in accordance with the input signal. Then, a signal is sent from the arithmetic processing circuit unit 903 to the modulation circuit 913, and the modulation circuit 913 modulates the signal into an AC electrical signal. Then, the AC electrical signal 941 is transmitted to the antenna 921 of the reader / writer 920 via the antenna 902.

  The AC electrical signal received by the antenna 921 of the reader / writer 920 is demodulated by the demodulation circuit 924 of the communication circuit unit 922 and transmitted to the arithmetic processing circuit unit 926 and the external interface unit 927. The sensor detection information is displayed on an information processing device 932 such as a display or a computer connected to the external interface unit 927.

  The semiconductor device manufactured according to the present invention can be used in a wide range. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 21A), packaging Containers (wrapping paper, bottles, etc., see FIG. 21 (B)), recording media (DVD software, video tape, etc., see FIG. 21 (C)), vehicles (bicycles, etc., see FIG. 21 (D)), It can be used in personal items (such as bags and glasses, see FIG. 21E), foods, plants, animals, human bodies, clothing, household goods, electronic devices, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like. Moreover, it can be used for plants, animals, human bodies and the like.

  The semiconductor device of the present invention is fixed to an article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing semiconductor devices for banknotes, coins, securities, bearer bonds, certificates, and the like. Further, by providing semiconductor devices in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. Even if the semiconductor device of the present invention that realizes small size, thinness, and light weight is mounted on an article, the design is not impaired. In addition, the selection range of the reader / writer is widened by providing a plurality of antennas. Furthermore, by having a sensor, it is possible to manage the state of the article.

  Further, by applying the semiconductor device of the present invention to an object management or distribution system, it is possible to increase the functionality of the system. For example, the reader / writer 295 is provided on the side surface of the portable terminal including the display portion 294 and the semiconductor device 296 is provided on the side surface of the article 297 (see FIG. 22A). In this case, when the semiconductor device 296 is held over the reader / writer 295, the display unit 294 displays information such as the raw material and origin of the article 297 and the history of distribution process. Another example is the case where a reader / writer 295 is provided on the side of the belt conveyor (see FIG. 22B). In this case, the inspection of the article 297 can be easily performed.

  A typical usage pattern of the semiconductor device having the sensor of the present invention will be described with reference to FIG.

  As shown in FIG. 23A, a semiconductor device 502 having a temperature sensor is embedded in an animal 501 and information obtained by measuring the temperature of the animal is recorded in a memory portion of the semiconductor device. By providing a reader / writer 505 in equipment provided near the animal such as the tub 503 or the bait box 504, and periodically reading information recorded by the reader / writer, it is possible to easily manage the health condition of the animal. it can.

  Further, as shown in FIG. 23B, a semiconductor device 512 having a gas sensor is provided in a food 511 that is easily spoiled to detect spoilage gas emitted from the food. The reader / writer provided on the side of the display shelf or belt conveyor reads the information recorded on the semiconductor device periodically to control the freshness of the food and to easily select the food that has started to rot. Is possible.

  In addition, as shown in FIG. 23C, in order to control the flower bud formation of long-day plants and short-day plants, a semiconductor device 522 having an optical sensor is provided in a place where light such as a leaf of a plant 521 is exposed, and sunlight is provided. The time is recorded in a memory in the semiconductor device. By periodically reading the recorded information with a reader / writer and controlling the illumination time, the flowering time and shipping time of the flower can be easily controlled.

  Further, as shown in FIGS. 23D and 23E, semiconductor devices 532 and 542 having sensors such as a temperature sensor and a pressure sensor are provided on the surface or inside of the human body, and the pulse rate, heart rate, body temperature, Biological information such as blood pressure, electrocardiogram, and electromyogram is recorded in a memory in the semiconductor device. FIG. 23D is a diagram in which a pulse is measured by attaching a semiconductor device having a pressure sensor to the arm 531. FIG. 23E is a diagram in which an electrocardiogram is measured by attaching a semiconductor device having a pressure sensor near the heart of a human body 541. Since the semiconductor device of the present invention is thin and small, it can read biological information without restraining the human body. Further, by regularly reading the recorded information with a reader / writer, it is possible to manage the health state and exercise state of the human body and to prevent and predict diseases. In addition, a home medical monitoring system or the like can be obtained by obtaining biological information read by a reader / writer using a network such as the Internet.

8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining operation | movement of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the usage pattern of the semiconductor device of this invention. It is a figure explaining the usage pattern of the semiconductor device of this invention. It is a figure explaining the usage pattern of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention. It is a figure explaining the structure of the semiconductor device of this invention.

Claims (25)

Selectively forming a release layer on the first substrate;
Forming a first insulating layer in contact with the first substrate and the release layer;
Forming a plurality of thin film transistors on the first insulating layer;
Forming a second insulating layer on the first insulating layer;
Forming a first opening in the first insulating layer and the second insulating layer so that a part of the first substrate is exposed;
Forming a second opening in the second insulating layer so as to expose a source region and a drain region of the plurality of thin film transistors;
Forming a first conductive layer filling the first opening and a second conductive layer filling the second opening;
Forming a third opening in the first insulating layer and the second insulating layer so that a part of the release layer is exposed;
An etching agent is introduced into the third opening to remove the release layer, and the second conductive layer is connected to the third conductive layer provided on the second substrate. After laminating a plurality of thin film transistors and the second substrate, peeling the plurality of thin film transistors from the first substrate,
A plurality of thin film transistors and the third substrate are bonded to each other so that the first conductive layer and a fourth conductive layer provided over a third substrate are connected to each other. Manufacturing method. Selectively forming a release layer on the first substrate;
Forming a first insulating layer in contact with the first substrate and the release layer;
Forming a plurality of thin film transistors on the first insulating layer;
Forming a second insulating layer on the first insulating layer;
Forming a first opening in the first insulating layer and the second insulating layer so that a part of the first substrate is exposed;
Forming a second opening in the second insulating layer so as to expose a source region and a drain region of the plurality of thin film transistors;
Forming a first conductive layer filling the first opening and a second conductive layer filling the second opening;
Forming a third opening in the first insulating layer and the second insulating layer so that a part of the release layer is exposed;
An etchant is introduced into the third opening to selectively remove the release layer so that the second conductive layer and the third conductive layer provided on the second substrate are connected to each other. In addition, after bonding the plurality of thin film transistors and the second substrate, the plurality of thin film transistors is peeled from the first substrate by physical means,
A plurality of thin film transistors and the third substrate are bonded to each other so that the first conductive layer and a fourth conductive layer provided over a third substrate are connected to each other. Manufacturing method. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a layer containing tungsten or molybdenum is formed as the separation layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a layer containing an oxide of tungsten or molybdenum is formed as the separation layer by a sputtering method in an oxygen atmosphere. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a layer containing tungsten or molybdenum is formed as the separation layer, and a layer containing silicon oxide is formed thereover. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a layer containing silicon is formed as the insulating layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the etching agent is a gas or a liquid containing halogen fluoride.   3. The method for manufacturing a semiconductor device according to claim 1, wherein the third conductive layer and the fourth conductive layer function as an antenna.   3. The method for manufacturing a semiconductor device according to claim 1, wherein the third conductive layer functions as an antenna, and the fourth conductive layer is electrically connected to a sensor.   A thin film integrated circuit; a first substrate having a sensor; and a second substrate having an antenna. The thin film integrated circuit is sandwiched between the first substrate having the sensor and the second substrate having the antenna. A semiconductor device which is characterized by being made. 11. The thin film integrated circuit and the sensor provided on the first substrate, and the antenna provided on the thin film integrated circuit and the second substrate are electrically connected by conductive particles. A semiconductor device characterized by comprising: 11. The first substrate having the thin film integrated circuit and the sensor, and the second substrate having the thin film integrated circuit and the antenna sandwich a resin having conductive particles. Semiconductor device.   A thin film integrated circuit; a first substrate having an antenna; and a second substrate having an antenna. The thin film integrated circuit is sandwiched between the first substrate having the antenna and the second substrate having the antenna. A semiconductor device which is characterized by being made. 14. The thin film integrated circuit and the antenna provided on the first substrate, and the thin film integrated circuit and the antenna provided on the second substrate are electrically connected by conductive particles. A semiconductor device. 14. The thin film integrated circuit and the first substrate having the antenna, and the thin film integrated circuit and the second substrate having the antenna sandwich a resin having conductive particles. Semiconductor device.   14. The semiconductor device according to claim 10, wherein the first substrate and the second substrate have flexibility. A first conductive layer provided on the first substrate;
A first insulating layer covering the first conductive layer;
A first thin film transistor and a second thin film transistor provided on the first insulating layer; a second insulating layer covering the first thin film transistor and the second thin film transistor;
A second conductive layer and a third conductive layer provided on the second insulating layer;
A fourth conductive layer provided on the second substrate;
The second conductive layer is connected to a source region and a drain region of the first thin film transistor through a first opening provided in the second insulating layer, and the first conductive layer and the first insulating layer Connecting to the first conductive layer through a second opening provided in each of the second insulating layers;
The third conductive layer is connected to a source region and a drain region of the second thin film transistor through a third opening provided in the second insulating layer, and is connected to the fourth conductive layer. A semiconductor device comprising: 18. The method according to claim 17, wherein the first conductive layer and the second conductive layer, and the third conductive layer and the fourth conductive layer are electrically connected by conductive particles, respectively. A semiconductor device. 18. The semiconductor according to claim 17, wherein the first substrate and the first insulating layer, and the second insulating layer and the second substrate sandwich a resin having conductive particles. apparatus. 18. The semiconductor device according to claim 17, wherein the first substrate and the second substrate have flexibility. 18. The semiconductor device according to claim 17, wherein the first conductive layer and the fourth conductive layer function as an antenna. 18. The semiconductor device according to claim 17, wherein the first conductive layer functions as an antenna, and the fourth conductive layer is electrically connected to a sensor. 18. The semiconductor according to claim 17, wherein the second conductive layer includes a region in contact with the first conductive layer through a resin having conductive particles and a region in contact with the second insulating layer. apparatus. 18. The semiconductor device according to claim 17, wherein the first thin film transistor and the second thin film transistor each include a sidewall insulating layer. An electronic apparatus comprising the semiconductor device according to any one of claims 10 to 24.

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