JP2006080465A - Manufacturing method of semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cut a tape stuck to the surface of a thin-type wafer in accordance with the size of a wafer without breaking the wafer and to laminate the wafer and a supporting substrate via an adhesive tape without breaking the thin type wafer. <P>SOLUTION: An adhesive tape 31 which is larger than the thin type wafer 41 is stuck to the surface thereof. A blade 101 of a tape cutter is abutted to a peripheral edge of a wafer holding stand 102 keeping it oblique as if falling to the wafer 41 side. In the state, the blade 101 of the tape cutter is moved along the peripheral edge of the wafer holding stand 102, thus cutting the adhesive tape 31. Thereafter, the supporting substrate 32 is stuck to the adhesive tape 31. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a thin power semiconductor element such as an insulated gate bipolar transistor (hereinafter referred to as IGBT).

  2. Description of the Related Art Conventionally, an integrated circuit (IC) in which a large number of transistors, resistors, and the like are connected to form an electric circuit and integrated on a single chip has been frequently used as a main part of computers and communication devices. Among such ICs, those including power semiconductor elements are called power ICs. One of power semiconductor elements is an insulated gate bipolar transistor (hereinafter referred to as IGBT).

  The IGBT is a power element in which a MOSFET (insulated gate field effect transistor) having high-speed switching characteristics and voltage driving characteristics and a bipolar transistor having low on-voltage characteristics are configured on a single chip. The range of applications has expanded from industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), or switching power supplies to consumer equipment fields such as microwave ovens, rice cookers, and strobes. Further, IGBTs having a lower on-voltage using a new chip structure have been developed, and reductions in the loss and efficiency of application devices using the IGBT have been achieved.

  The IGBT has a punch-through (hereinafter referred to as PT) type, non-punch-through (hereinafter referred to as NPT) type, and field stop (hereinafter referred to as FS) type, and an n-channel vertical double type. A diffusion structure is the mainstream. Therefore, in this specification, an n-channel IGBT is described as an example, but the same applies to a p-channel IGBT.

The PT-type IGBT is formed using an epitaxial wafer obtained by epitaxially growing an n ⁺ buffer layer and an n ⁻ active layer on a p ⁺ semiconductor substrate. Therefore, for example, in a device with a withstand voltage of 600 V, the thickness of the active layer is about 70 μm, but the total thickness including the p ⁺ semiconductor substrate is about 200 to 300 μm. In the PT type IGBT, the depletion layer in the n ⁻ active layer reaches the n ⁺ buffer layer.

FIG. 8 is a cross-sectional view showing the configuration of a half cell of an NPT type IGBT having a shallow p ⁺ collector layer with a low dose. As shown in FIG. 8, an n ⁻ semiconductor substrate made of, for example, an FZ wafer is used as an active layer 1, and ap ⁺ base region 2 is selectively formed on the surface side thereof. An n ⁺ emitter region 3 is selectively formed on the surface layer of the base region 2. A gate electrode 5 is formed on the substrate surface via a gate oxide film 4.

The emitter electrode 6 is in contact with the emitter region 3 and the base region 2 and is insulated from the gate electrode 5 by the interlayer insulating film 7. A p ⁺ collector layer 8 and a collector electrode 9 are formed on the back surface of the substrate. In the case of the NPT type, the thickness of the active layer 1 is thicker than that of the PT type, but the entire element is significantly thinner than the PT type element. Moreover, since the FZ substrate is used without using the epitaxial substrate, the cost is low.

FIG. 9 is a cross-sectional view showing the configuration of a half cell of the FS type IGBT. As shown in FIG. 9, the element structure on the substrate surface side is the same as the NPT type element shown in FIG. On the back side of the substrate, an n ⁺ buffer layer 10 is provided between the n ⁻ active layer 1 and the p ⁺ collector layer 8. In the case of the FS type, the thickness of the active layer 1 is about 70 μm (withstand voltage 600 V system), which is the same as that of the PT type, and the thickness of the entire element is about 100 to 200 μm.

  Recently, in order to further reduce the total loss, an attempt has been made to thin the wafer and reduce the device thickness as much as possible. For example, in the case of an element having a withstand voltage of 600 V, the thickness of the FS type IGBT is assumed to be about 70 μm. When the breakdown voltage class is lowered, the thickness of the element is further reduced. As a manufacturing method of the FS type IGBT having such a thickness or a device similar thereto, a method of polishing an FZ wafer is known as described below.

FIG. 10 (FIGS. 10-1 to 10-5) is a diagram showing a manufacturing process of an FS type IGBT using a conventional FZ wafer. As shown in FIGS. 10-1 to 10-5, first, on the surface side of the n-FZ wafer to be the active layer 1, a base region, an emitter region, a gate oxide film made of SiO ₂ , a gate electrode, BPSG, etc. A surface-side element structure 11 having an interlayer insulating film made of, an emitter electrode made of an Al—Si film, etc., and an insulating protective film made of a polyimide film or the like is formed (FIG. 10-1).

  Next, the back surface of the wafer is ground by means such as back grinding or etching, so that the wafer has a desired thickness, for example, 70 μm (FIG. 10-2). In the case of etching, although it is not strictly grinding, in this specification, since means for thinning the wafer is not questioned, grinding including etching is performed.

  Then, for example, phosphorus (P), which is an n-type impurity, and boron (B), which is a p-type impurity, are ion-implanted from the back surface of the wafer, and heat treatment (annealing) is performed at 350 to 500 ° C. in an electric furnace. Layer 10 and collector layer 8 are formed (FIG. 10-3). Next, a plurality of metals such as aluminum (Al), titanium (Ti), nickel (Ni), and gold (Au) are vapor-deposited on the back surface of the wafer, that is, the surface of the collector layer 8 to form the collector electrode 9 (FIG. 10-4).

  Finally, the dicing tape 12 is attached to the collector electrode 9 side to perform dicing, and the wafer is cut into a plurality of chips 13 (FIG. 10-5). Then, the collector electrode 9 of each chip 13 is soldered to a fixing member, and an aluminum wire electrode is fixed to the electrode of the surface side element structure portion 11 by a wire bonding apparatus.

  However, when an element having a thickness of, for example, about 70 μm is manufactured by the above-described conventional method, the wafer is easily cracked because the back grind on the back surface of the wafer or the etched wafer is thin. Further, when a metal film serving as a collector electrode is deposited on the back surface of the wafer, the metal film has a tensile stress when viewed from the film forming side, that is, the back surface side of the substrate, so that the wafer is warped (see FIG. Example 1), the wafer is easily broken (see FIG. 3, Conventional Example 1 in FIG. 3).

  Therefore, the present applicant first joins the wafer and the support substrate via an adhesive tape that can be peeled off by heating and foaming, and then performs the back surface processing of the wafer in that state, and then peels the wafer from the support substrate. A method has been filed (Japanese Patent Application No. 2003-138805). A process for manufacturing an FS type IGBT according to this method will be described with reference to FIGS. 11 (FIGS. 11-1 to 11-3) and 12 (FIGS. 12-1 to 12-4).

  First, the surface side element structure 22 is formed on the surface side of the n-FZ wafer 21 (FIG. 11-1). Next, the surface (the lower surface in FIG. 11-2) of the surface-side element structure 22 is joined to the support substrate 32 via the adhesive tape 31 (FIG. 11-2). Adhesive tape has a foaming agent part made of a foam tape-type sheet that can be peeled off by foaming on both sides of a PET tape base material, and heat-resistant peelable when the adhesive is cured by UV light irradiation. Each is provided with a UV tape layer made of a unique UV tape sheet.

  A foaming agent portion of the adhesive tape 31 is attached to the wafer 21. The support substrate 32 is made of a wafer (ceramics, quartz, glass, or the like) that transmits UV light, and the UV tape layer of the adhesive tape 31 is attached to the support substrate 32. Next, with the support substrate 32 bonded, the back surface of the wafer (the upper surface in FIG. 11-3) is ground by back grinding, wet etching, or the like, so that the thickness of the entire wafer including the surface side element structure 22 is desired. (Fig. 11-3).

Next, for example, phosphorus, which is an n-type impurity, and boron, which is a p-type impurity, are ion-implanted into the back surface of the wafer 21. Thereafter, annealing is performed by irradiating the back surface of the wafer with a laser to form an n ⁺ layer 23 serving as a buffer layer and a p ⁺ layer 24 serving as a collector layer (FIG. 12-1). Here, for example, a YAG third harmonic (YAG3ω) pulse laser (wavelength: 355 nm, half-value width: 100 to 500 ns, frequency: 500 Hz) is used as the laser, and a single irradiation area is about 1 mm square and 50%. Irradiate with ~ 90% overlap.

By using the third harmonic of YAG, the deep n ⁺ layer 23 can be formed. Further, only the p ⁺ layer 24 and the n ⁺ layer 23 on the back surface of the wafer can be activated by laser annealing, and heat treatment can be performed regardless of the heat-resistant temperature of the adhesive tape 31.

  Next, a plurality of metal films such as aluminum, titanium, nickel and gold are formed on the entire back surface of the wafer to form a back electrode 25 serving as a collector electrode (FIG. 12-2). Here, it is appropriate to deposit a metal film by a low temperature sputtering method. The reason for this is that the heat resistance temperature of the adhesive tape 31 is approximately 100 ° C. or less for a high-rigidity UV tape type sheet, 200 ° C. or less for a heat resistant UV tape type sheet, and 150 ° C. or less for a heated foam tape type sheet. Therefore, it is desirable that the temperature during film formation is 100 ° C. or lower.

  Then, for example, the wafer 21 or the support substrate 32 is heated while being sucked, and the foaming agent 44 contained in the foaming agent portion of the adhesive tape 31 is foamed to adhere at the interface with the insulating protective film of the surface side element structure portion 22. The tape 31 is peeled off (FIG. 12-3). After removing the adhesive tape 31 and the support substrate 32, the dicing tape 26 is attached to the back surface of the wafer and cut into a plurality of chips 27 (FIG. 12-4).

  Thereafter, although not shown, each chip 27 is soldered to a fixing member such as a wiring board via the back electrode 25. An aluminum wire electrode is fixed to the electrode on the wafer surface side of each chip 27 by an ultrasonic wire bonding apparatus. Further, the adhesive tape 31 is irradiated with UV light (FIG. 12-3), the adhesive tape 31 is peeled off from the support substrate 32, and the support substrate 32 is reused. Note that the UV tape layer of the adhesive tape 31 may be attached to the wafer 21, and the foaming agent portion of the adhesive tape 31 may be attached to the support substrate 32. In this case, after the support substrate 32 is peeled off by foaming, the wafer 21 may be peeled off by irradiation with UV light.

In the case of manufacturing an NPT type IGBT instead of the FS type IGBT, an ion implantation step of an n type impurity (phosphorus) for forming the n ⁺ layer 23 may be omitted. In that case, the laser used for laser annealing on the backside of the wafer is a short half-width XeF pulse laser (wavelength: 351 nm, half-width: for example 14 ns), XeCl pulse laser (wavelength: 308 nm, half-width: for example 49 ns), all A solid YAG2ω laser (wavelength: 532 nm, half width: 100 ns, for example) may be used. By using these lasers, only the p ⁺ layer 24 can be activated.

  According to this method, since the support substrate is bonded to the wafer, there is almost no warping of the wafer even after grinding of the back surface of the wafer (see FIG. 2, Conventional Example 2 (with support substrate)). Moreover, after forming a collector electrode by vapor-depositing a metal film on the back surface of the wafer, the wafer can be prevented from cracking (see FIG. 3, Conventional Example 2 with support substrate).

  However, when a wet process such as wet etching is performed in a state where the wafer 21 is attached to the support substrate 32 via the adhesive tape 31 described above, the chemical solution may enter from the periphery of the wafer 21. In this case, the foaming function of the portion of the foaming agent portion 43 where the chemical solution has entered is lost. FIG. 13 is a diagram schematically showing a state of the foaming agent portion 43 on the tape base material 42 constituting the adhesive tape 31 after the wafer 21 is peeled off. In the region excluding the end of the foaming agent portion 43 (foaming normal region 431), the foaming agent 44 is normally foamed. On the other hand, as a result of the loss of the foaming function due to the intrusion of the chemical solution, there is a region (foam failure region 432) having a width of about 100 to 200 μm where the foaming agent 44 is not foamed.

  Originally, if there is no defective foam region 432, as shown in FIGS. 14 and 15, when the wafer 21 (thin wafer 41) is peeled off by foaming, the thin wafer 41 is not cracked or chipped. Can be peeled off from the adhesive tape 31. On the other hand, when the poorly foamed region 432 exists at the periphery of the foaming agent portion 43, the glue of the adhesive tape 31 extends and sticks to the thin wafer 41 in the poorly foamed region 432.

  Therefore, when the foaming agent part 43 is foamed by heating, the thin wafer 41 is easily peeled off from the adhesive tape 31 in the normal foaming region 431 excluding the peripheral edge of the thin wafer 41, but the peripheral part of the thin wafer 41 is bonded. It is not easy to peel off from the tape 31. In such a state, if the thin wafer 41 is forcibly separated, a defective portion 411 such as a chip or a crack is generated in the thin wafer 41 as shown in FIG. Then, as shown in FIG. 17, wafer fragments 412 remain in the foaming agent portion 43.

  Therefore, after the grinding process such as back grinding and wet etching is completed, a method is effective in which the thin wafer and the support substrate are bonded together via an adhesive tape, and the process on the back side of the wafer such as an ion implantation process is performed in that state. . A process for manufacturing an FS type IGBT according to this method will be described with reference to FIG. 18 (FIGS. 18-1 to 18-4).

  First, the surface-side element structure 22 is formed on the surface side of the n-FZ wafer 21 (FIG. 18-1). Next, the back surface of the wafer (the upper surface in FIG. 18-2) is ground by back grinding, wet etching, or the like, so that the entire thickness of the wafer including the surface-side element structure portion 22 becomes a desired thickness (FIG. 18-). 2). Hereinafter, the thinned wafer 21 is referred to as a thin wafer 41. Subsequently, the foaming agent portion 43 of the adhesive tape 31 is attached to the thin wafer 41 and the UV tape layer 45 of the adhesive tape 31 is attached to the support substrate 32 (or vice versa), whereby the support substrate 32 is interposed via the adhesive tape 31. The surface of the surface side element structure part 22 is joined to (FIG. 18-3).

Next, in the same manner as in FIGS. 12A to 12B, the n ⁺ layer 23, the p ⁺ layer 24, and the back electrode 25 are formed on the back surface of the thin wafer 41. And the foaming agent 44 contained in the foaming agent part 43 of the adhesive tape 31 is foamed, and the adhesive tape 31 is peeled off at the interface with the insulating protective film of the surface side element structure part 22 (FIG. 18-4). The subsequent steps are the same as in FIG. 12-4. In the case of manufacturing an NPT type IGBT, an n-type impurity (phosphorus) ion implantation step for forming the n ⁺ layer 23 is omitted.

  According to this method, since the wet process is not performed after the adhesive tape 31 is attached, the foaming failure portion 432 does not exist in the foaming agent portion 43 of the adhesive tape 31. Therefore, the thin wafer 41 can be peeled off from the adhesive tape 31 without the thin wafer 41 being cracked or chipped due to foaming.

  By the way, in the manufacturing process shown in FIG. 11 (FIGS. 11-1 to 11-3) and FIG. 12 (FIGS. 12-1 to 12-4), after the adhesive tape 31 is attached to the wafer 21, the adhesive tape 31 is used. Need to be cut off. FIG. 19 is a cross-sectional view showing a state when the adhesive tape 31 is cut, and FIG. 20 is a plan view thereof. As shown in FIG. 19, when the adhesive tape 31 is cut, the blade 101 of the tape cutter is in a state in which the blade tip faces outward with the center of the wafer 21 as the center position.

  In order to make the adhesive tape 31 smaller than the wafer 21, the blade 101 of the tape cutter is brought into contact with the chamfered peripheral edge of the wafer 21 in an inclined state toward the wafer 21 side. As shown, the blade 101 of the tape cutter may be moved. At this time, since the thickness of the wafer 21 is about 500 to 630 μm, the edge of the wafer 21 is not chipped or the wafer 21 is not broken.

  As a method similar to such a tape cutting method, beveling is formed on the peripheral edge of the wafer, and the tape attached to the wafer is moved by inclining the tape cutter along the inclination direction of the beveling. A method of cutting has been proposed (see, for example, Patent Document 1). Also, as a method of cutting the tape so that the tape is larger than the wafer, a method of cutting the tape along the groove by inserting the blade edge of the tape cutter into the groove provided on the table that supports the wafer is proposed. (For example, see Patent Document 2).

Japanese Patent Laying-Open No. 2002-57208 (FIG. 14) Japanese Patent Laying-Open No. 2003-209082 (FIG. 4)

  In the manufacturing process shown in FIG. 18 (FIGS. 18-1 to 18-4), the adhesive tape 31 is applied after the wafer 21 is thinned. As shown in FIG. 21, the thickness of the wafer 21 before grinding is 500 μm. And the part of the width | variety 1200 micrometers along the periphery of the wafer 21 inclines so that thickness may become thin about 150 micrometers. Therefore, as shown in FIG. 22, by grinding the back surface of the wafer, the thickness of the thin wafer 41 becomes 70 μm, and the portion having a width of 500 μm along the periphery thereof has a sharp pointed shape. Therefore, as shown in FIG. 23, when the tape 101 is brought into contact with the peripheral edge of the thin wafer 41 and the adhesive tape 31 is cut, the edge of the thin wafer 41 is chipped or the thin wafer 41 is broken. There is a problem.

  The present invention provides a method for manufacturing a semiconductor device, in which a tape is attached to the surface of a thin wafer and the tape can be cut according to the size of the wafer in order to eliminate the above-described problems caused by the prior art. For the purpose. Another object of the present invention is to provide a method for manufacturing a semiconductor element, in which a thin wafer and a supporting substrate can be bonded together with an adhesive tape.

  In order to solve the above-described problems and achieve the object, the semiconductor device manufacturing method according to the first aspect of the present invention is such that a tape larger than the wafer is attached to the surface of the thin wafer, and the blade is inclined so as to fall down on the wafer side. The tape is cut along a wafer holding table holding the wafer by a tape cutter in a state where the wafer is held.

  According to the first aspect of the present invention, since the tape is cut along the wafer holding table instead of cutting along the peripheral edge of the thin wafer, the peripheral edge of the thin wafer is sharply pointed even if the wafer is thin. The tape can be cut without breaking the thin wafer. Therefore, after the tape is cut, the thin wafer and the support substrate can be bonded together.

  Further, in order to solve the above-described problems and achieve the object, a method for manufacturing a semiconductor element according to the invention of claim 2 is to attach an adhesive tape larger than the support substrate on the surface of the support substrate, and After the adhesive tape is cut along the periphery of the support substrate, a thin wafer is attached to the adhesive tape. According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the second aspect, wherein the thin wafer is previously thinned by grinding.

  According to the invention of claim 2 or 3, since the tape is not cut along the periphery of the thin wafer, but the tape is cut along the periphery of the support substrate, even if the wafer is thin, the periphery of the thin wafer is also obtained. Even if the edge is sharp, the thin wafer will not break. Therefore, after the tape is cut, the thin wafer and the support substrate can be bonded together.

  According to the semiconductor element manufacturing method of the present invention, the tape attached to the surface of the thin wafer can be cut according to the size of the wafer without breaking the wafer. In addition, the thin wafer and the support substrate can be bonded via an adhesive tape without breaking the thin wafer. Therefore, a thin wafer can be easily manufactured. In particular, there is an effect that a semiconductor element having a thickness of 100 μm or less and good device characteristics can be easily manufactured.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a state when the adhesive tape is cut according to the first embodiment. As shown in FIG. 1, the first embodiment is characterized by a method of cutting an adhesive tape 31 attached to a thin wafer 41. The manufacturing process is the same as the manufacturing process shown in FIG. 18 (FIGS. 18-1 to 18-4), for example, and a duplicate description is omitted.

  In the step shown in FIG. 18C, the cutting method of the adhesive tape 31 is as follows. For example, a thin wafer 41 having a thickness of 70 μm and an adhesive tape 31 attached is placed on the wafer holder 102 so that the thin wafer 41 faces downward. The wafer holder 102 is slightly larger than the size of the thin wafer 41. Preferably, the peripheral portion of the surface of the wafer holder 102 on the side on which the thin wafer 41 is placed is chamfered, for example, in a curved shape.

  Then, the blade 101 of the tape cutter is brought into contact with the chamfered peripheral edge of the wafer holder 102 in a state where the blade tip is directed outward and the thin wafer 41 is inclined obliquely. In this state, for example, as indicated by an arrow in FIG. 20, the adhesive tape 31 is cut by moving the blade 101 of the tape cutter along the peripheral edge of the wafer holder 102. Instead of the wafer holder 102, a thick silicon wafer or the like may be used as the holder.

  In this way, since the blade 101 of the tape cutter does not contact the peripheral edge of the thin wafer 41, it is possible to prevent the peripheral edge of the thin wafer 41 from being broken or the thin wafer 41 from being broken. In the manufacturing process shown in FIG. 18 (FIGS. 18-1 to 18-4), since the adhesive tape 31 is attached to the thin wafer 41 after the wet process at the time of back grinding, the chemical solution at the time of the wet process is used. It is possible to prevent a phenomenon in which the glue of the adhesive tape 31 extends and sticks to the thin wafer 41 due to the influence. Therefore, the thin wafer 41 can be peeled from the adhesive tape 31 without the thin wafer 41 being cracked or chipped.

  FIG. 2 shows the relationship between the amount of warpage of the wafer after forming the back electrode and the thickness of the wafer after back grinding for a wafer having a diameter of 6 inches manufactured according to the manufacturing method of the first embodiment (Example 1). It is a figure which shows the result of having investigated. Here, the amount of warpage is the difference in height between the center and the periphery of the wafer. From FIG. 2, in Example 1, even when the thickness of the wafer after back grinding is reduced to 70 μm, the warpage amount of the wafer after forming the back electrode is the limit value of the warpage amount when cracking occurs after the back electrode formation. It was found to be much smaller than 5.5 mm (in the case of a 6-inch diameter wafer) and almost zero.

  For comparison, a wafer having a diameter of 6 inches (conventional example 1) manufactured according to the method shown in FIG. 10, and FIGS. 11 (FIGS. 11-1 to 11-3) and 12 (FIGS. 12-1 to 12) are used. FIG. 2 also shows the results of examining the same for a wafer with a diameter of 6 inches (conventional example 2) manufactured according to the method shown in -4). Conventional Example 1 has no support substrate. Conventional Example 2 and Example 1 are those with a support substrate. The amount of warpage of Conventional Example 2 was almost the same as that of Example 1. On the other hand, in Conventional Example 1, since there is no support substrate, when the thickness of the wafer after back grinding is 90 μm or less, the warpage amount of the wafer after forming the back electrode is 5.5 mm (the limit value of cracking). (In the case of a wafer having a diameter of 6 inches).

  FIG. 3 is a diagram showing the results of examining the relationship between the cracking rate of the wafer after forming the back electrode and the thickness of the wafer after back grinding for Example 1. For comparison, FIG. 3 also shows the results of examining the same for Conventional Example 1 and Conventional Example 2. As shown in FIG. 3, in Example 1 and Conventional Example 2, even when the thickness of the wafer after back grinding is reduced to 70 μm, the cracking rate is extremely small, almost zero. On the other hand, in Conventional Example 1, the crack rate when the thickness of the wafer after back grinding is 70 μm is as high as 95%.

Embodiment 2. FIG.
FIG. 4 is a cross-sectional view showing a state when the adhesive tape is cut according to the second embodiment. As shown in FIG. 4, the second embodiment has a feature in a method of attaching and cutting an adhesive tape 31 to a support substrate 32. The manufacturing process is the same as the manufacturing process shown in FIG. 18 (FIGS. 18-1 to 18-4), for example, and a duplicate description is omitted.

  In the step shown in FIG. 18C, the cutting method of the adhesive tape 31 is as follows. For example, the adhesive tape 31 is attached to a glass support substrate 32 having a thickness of 630 μm. Although not particularly limited, in the illustrated example, the UV tape layer 45 is attached to the support substrate 32 side. Then, the blade 101 of the tape cutter is brought into contact with the peripheral edge of the support substrate 32 in a state where the blade tip is directed outward and the support substrate 32 is tilted obliquely. In this state, for example, as indicated by an arrow in FIG. 20, the adhesive tape 31 is cut by moving the blade 101 of the tape cutter along the peripheral edge of the support substrate 32. Thereafter, as shown in FIG. 5, the separator 46 of the adhesive tape 31 is peeled off, and a thin wafer 41 having a thickness of 70 μm, for example, is attached to the foaming agent portion 43 of the adhesive tape 31.

  By doing so, it is not necessary to cut the adhesive tape 31 by applying the blade 101 of the tape cutter to the peripheral edge of the thin wafer 41. Can be prevented from cracking. Further, similarly to the first embodiment, the adhesive on the adhesive tape 31 can be prevented from extending and sticking to the thin wafer 41 due to the influence of the chemical solution at the time of the wet treatment, so that the thin wafer 41 is cracked or chipped. The thin wafer 41 can be peeled from the adhesive tape 31 without any problem.

  Regarding a wafer having a diameter of 6 inches manufactured according to the manufacturing method of the second embodiment (referred to as Example 2), the relationship between the amount of warpage of the wafer after forming the back electrode and the wafer thickness after back grinding, and the wafer after forming the back electrode The results of examining the relationship between the cracking rate and the wafer thickness after back grinding are shown in FIGS. 2 and 3, respectively. The result of Example 2 was the same as Example 1.

Embodiment 3 FIG.
6 (FIGS. 6-1 to 6-3) and FIG. 7 (FIGS. 7-1 to 7-2) are views showing a manufacturing process of the FS type IGBT according to the third embodiment. First, the back surface of the n-FZ wafer is ground by back grinding, wet etching, or the like to obtain a thin wafer 41 having a desired thickness, for example, 70 μm (FIG. 6-1). Next, in the same manner as in FIGS. 10-3 to 10-4, the n ⁺ layer 23, the p ⁺ layer 24, and the back electrode 25 are formed on the back surface of the thin wafer 41 (FIG. 6-2).

  In the third embodiment, when the heat treatment (annealing) after the ion implantation is performed, the surface-side element structure portion 22 is not formed. Therefore, this heat treatment can be performed at a high temperature of about 1000 ° C., for example. Therefore, since the implanted dopant can be sufficiently activated, a deep diffusion layer can be formed on the back surface side of the thin wafer 41.

  Next, the foaming agent portion 43 of the adhesive tape 31 is attached to the back electrode 25 of the thin wafer 41, and the UV tape layer 45 of the adhesive tape 31 is attached to the support substrate 32 (or vice versa). Then, the support substrate 32 is bonded (FIG. 6-3). At that time, when the adhesive tape 31 is cut with the adhesive tape 31 larger than that attached to the thin wafer 41, the cutting method of the first embodiment described above is followed. On the other hand, when the adhesive tape 31 is cut in a state where the larger adhesive tape 31 is attached to the support substrate 32, the cutting method of the second embodiment described above is followed.

Next, the surface-side element structure 22 is formed on the surface side of the thin wafer 41 with the support substrate 32 attached (FIG. 7-1). And the foaming agent 44 contained in the foaming agent part 43 of the adhesive tape 31 is foamed, and the adhesive tape 31 is peeled off at the interface with the back electrode 25 (FIG. 7-2). The subsequent steps are the same as in FIG. 12-4. In the case of manufacturing an NPT type IGBT, an n-type impurity (phosphorus) ion implantation step for forming the n ⁺ layer 23 is omitted.

  In addition, you may form the back surface electrode 25 after the peeling process from the support substrate 32 shown to FIGS. 7-2 instead of forming in the step before bonding with the support substrate 32 shown to FIGS. 6-2. At this time, as shown in FIG. 7B, after the thin wafer 41 is once peeled off from the support substrate 32, the support substrate is attached again to the front surface side element structure portion 22 of the thin wafer 41, and in this state, the back electrode 25 After that, the support substrate may be peeled off again.

  In the above, the present invention is not limited to the manufacture of FS type IGBTs, but can also be applied to the manufacture of NPT type IGBTs, reverse blocking IGBTs, semiconductor elements having a MOS (metal-oxide-semiconductor) structure, ICs, and the like. In addition, it is effective when the objects bonded through the adhesive tape 31 having the foaming agent portion 43 are separated by foaming. In addition, the present invention is not limited to the adhesive tape 31 used in the embodiment, and when cutting a tape attached to a thin wafer, such as a tape attached to a wafer when performing back grinding or the like in the state of a thin wafer. It is effective for. Further, the present invention is not limited to the FZ wafer but can be applied to the case of using an epitaxial wafer.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a power IC including a power semiconductor device, and in particular, a general-purpose inverter, AC servo, uninterruptible power supply (UPS), switching power supply, etc. It is suitable for power ICs used in industrial fields and consumer equipment fields such as microwave ovens, rice cookers or strobes.

3 is a cross-sectional view showing a state when the adhesive tape is cut according to Embodiment 1. FIG. It is a characteristic view showing the result of investigating the relationship between the amount of wafer warpage after the formation of the back electrode and the thickness of the wafer after back grinding. It is a characteristic view which shows the result of having investigated the relationship between the wafer crack rate after back surface electrode formation, and the wafer thickness after back grinding. It is sectional drawing which shows a mode when an adhesive tape is cut | disconnected by Embodiment 2. FIG. 9 is a cross-sectional view showing a state where a wafer and a support substrate are bonded together in Embodiment 2. FIG. FIG. 10 is a diagram showing a manufacturing process in the third embodiment. FIG. 10 is a diagram showing a manufacturing process in the third embodiment. FIG. 10 is a diagram showing a manufacturing process in the third embodiment. FIG. 7 is a diagram showing a continuation of the manufacturing process shown in FIGS. 6-1 to 6-3. FIG. 7 is a diagram showing a continuation of the manufacturing process shown in FIGS. 6-1 to 6-3. It is sectional drawing which shows the structure of NPT type IGBT. It is sectional drawing which shows the structure of FS type IGBT. It is a figure which shows the conventional manufacturing process. It is a figure which shows the conventional manufacturing process. It is a figure which shows the conventional manufacturing process. It is a figure which shows the conventional manufacturing process. It is a figure which shows the conventional manufacturing process. It is a figure which shows a part of conventional manufacturing process. It is a figure which shows a part of conventional manufacturing process. It is a figure which shows a part of conventional manufacturing process. It is a figure which shows the continuation of the manufacturing process shown to FIGS. It is a figure which shows the continuation of the manufacturing process shown to FIGS. It is a figure which shows the continuation of the manufacturing process shown to FIGS. It is a figure which shows the continuation of the manufacturing process shown to FIGS. It is a schematic diagram for demonstrating the foaming state of an adhesive tape. It is a figure which shows the mode of the wafer peeled from the adhesive tape when there is no foaming defect area | region. It is a figure which shows the mode after wafer peeling of the adhesive tape when there is no foaming defect area | region. It is a figure which shows the mode of the wafer peeled from the adhesive tape in case there exists a foaming poor area | region. It is a figure which shows the mode after wafer peeling of the adhesive tape in case there exists a foaming defect area | region. It is a figure which shows the conventional manufacturing process. It is a figure which shows the conventional manufacturing process. It is a figure which shows the conventional manufacturing process. It is a figure which shows the conventional manufacturing process. It is sectional drawing which shows a mode when cut | disconnecting an adhesive tape. It is a top view which shows a mode when cut | disconnecting an adhesive tape. It is sectional drawing which expands and shows the wafer peripheral part before back surface grinding. It is sectional drawing which expands and shows the wafer peripheral part after back surface grinding. It is sectional drawing which shows a mode when cut | disconnecting an adhesive tape.

Explanation of symbols

31 Adhesive tape 32 Support substrate 41 Thin wafer 101 Tape cutter blade 102 Wafer holder

Claims (3)

  A tape that is larger than the wafer is attached to the surface of the thin wafer, and the tape is cut along a wafer holding table that holds the wafer by a tape cutter in a state where the blade is inclined so as to fall on the wafer side. A method for manufacturing a semiconductor device.   An adhesive tape larger than the support substrate is applied to the surface of the support substrate, the adhesive tape is cut along the periphery of the support substrate by a tape cutter, and then a thin wafer is attached to the adhesive tape. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 2, wherein the thin wafer is thinned by grinding in advance.

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