JP4525048B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to an IC (integrated circuit), a MOSFET (MOS field effect transistor), an asymmetrical normal IGBT (insulated gate bipolar transistor) having a reverse breakdown voltage significantly lower than a forward breakdown voltage, and a reverse equivalent to a forward breakdown voltage. The present invention relates to a method for manufacturing a semiconductor device such as a symmetric reverse blocking IGBT having a withstand voltage, and more particularly to a method for manufacturing a semiconductor device including a thin semiconductor substrate.

In recent years, ICs formed by integrating a large number of transistors, resistors, and the like on a single chip are frequently used in important parts of computers and communication devices. Among such ICs, those including power elements are called power ICs.
The IGBT is a power element in which high-speed switching and voltage driving characteristics of a MOSFET and low on-voltage characteristics of a bipolar transistor are configured on a single chip. IGBTs have been increasingly applied to industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), and switching power supplies, as well as consumer devices such as microwave ovens, rice cookers, and strobes.
Furthermore, development to the next generation is also progressing, and a device having a lower on-voltage using a new chip structure has been developed, and the loss and the efficiency of the applied device have been reduced.
IGBT structures include a punch-through type (PT type), a non-punch-through type (NPT type), a field stop type (FS type), and the like. Almost all IGBTs currently mass-produced have an n-channel vertical double diffusion structure except for a p-channel type for some audio power amplifiers. Therefore, here, an n-channel IGBT will be described as an example.

A punch-through IGBT (hereinafter referred to as PT-IGBT) has a p ⁺ substrate and an n ⁻ layer (n-type active layer: n ⁻ drift layer 81 and p base layer 82 formed by epitaxial growth on the p ⁺ substrate. And an expensive epitaxial substrate provided with an n ⁺ layer (n buffer layer) formed by epitaxial growth between the p ⁺ substrate and the n ⁻ layer, and a depletion layer in the active layer is an n buffer. It is a structure that reaches the layer, and is the basic structure of the mainstream in IGBT. For example, for a withstand voltage of 600V, an active layer thickness of about 70 μm is sufficient, but when including a p ⁺ substrate, the total thickness of the epitaxial substrate is 200 μm to 300 μm.
Therefore, without using an expensive epitaxial substrate, using an inexpensive FZ substrate, non-punch-through type IGBT which adopts a shallow p ⁺ collector layer of low dose which attained the cost of the chip (hereinafter, NPT-IGBT This is a structure in which the depletion layer does not reach the p ⁺ collector layer) and a field stop type IGBT (hereinafter referred to as FS-IGBT. This is a structure in which a buffer layer is provided and the extension of the depletion layer is stopped by this buffer layer. ) Has been developed.

FIG. 6 is a cross-sectional view of an essential part of an NPT-IGBT having a shallow p ⁺ collector layer with a low dose. Here, a cross-sectional structure of a ½ cell is shown.
Since NPT-IGBT using a low dose shallow p ⁺ collector layer 89 (low implantation p ⁺ collector) does not use a thick epitaxial substrate (p ⁺ substrate), the total substrate thickness is much larger than that of PT-IGBT. getting thin. In this structure, since the hole injection rate can be controlled by controlling the impurity concentration and thickness of the p ⁺ collector layer 89, high-speed switching is possible without performing lifetime control. However, since the thickness of the n-type active layer (n ⁻ drift layer 81) is thicker than that of PT-IGBT, the on-voltage is slightly higher than that of PT-IGBT. However, since an inexpensive FZ substrate (a silicon substrate manufactured by the floating zone method) is used without using an epitaxial substrate as described above, the cost of the chip can be reduced.

In the figure, 83 is an n ⁺ emitter layer, 84 is a gate oxide film, 85 is a gate electrode, 86 is an interlayer insulating film, 87 is an emitter electrode, and 90 is a collector electrode.
FIG. 7 shows a cross-sectional structure of an FS-IGBT having a low dose, shallow p ⁺ collector layer and an n buffer layer. Here, a cross-sectional structure of a ½ cell is shown.
The basic structure is the same as that of PT-IGBT, but the total thickness of the substrate is set to 100 μm to 200 μm according to the withstand voltage using an FZ substrate without using an epitaxial substrate. Similar to PT-IGBT, the active layer has a withstand voltage of 600 V and is set to about 70 μm, and the entire region of the active layer is depleted. Therefore, an n ⁺ layer (n buffer layer 88) is provided under the active layer. On the collector side, a low dose shallow p ⁺ diffusion layer (p ⁺ collector layer 89) is used as the low injection collector. Thereby, lifetime control is unnecessary like NPT-IGBT. In addition, for the purpose of further reducing the on-voltage, there is a combination of this FS-IGBT and a trench IGBT gate structure in which a narrow and deep groove (trench) is formed on the chip surface and a MOSFET is formed on the side surface of the trench. Recently, the total thickness has been reduced by optimizing the design.

In recent years, matrix converters that perform direct AC-AC conversion without using a DC intermediate circuit have been in the spotlight. Unlike conventional inverters, a DC intermediate circuit (capacitor) is unnecessary, and there is an advantage that power harmonics (electromagnetic noise) are reduced. However, since the input is AC, the semiconductor switch is required to have a reverse breakdown voltage. Since the conventional IGBT does not have reverse blocking capability, when the conventional IGBT is used, it is necessary to connect a reverse blocking diode in series with the conventional IGBT.
FIG. 8 is a cross-sectional view of a main part of a reverse blocking IGBT having a separation layer. Here, a cross-sectional structure of a ½ cell is shown.
The basic structure is formed in contact with p ⁺ isolation layer 91 (also serves the p ⁺ collector layer) for holding the reverse breakdown voltage to chip around the NPT-IGBT of FIG. 6 to p ⁺ collector layer 89.

Since the reverse blocking IGBT does not require a conventional reverse blocking series diode, the on-loss can be halved, which greatly contributes to the improvement of the conversion efficiency of the matrix converter. A high-performance reverse-blocking IGBT can be manufactured by combining a technology for forming a deep junction of 100 μm or more from the substrate surface and a technology for manufacturing an ultrathin wafer having a thickness of 100 μm or less.
However, in order to realize a thin IGBT having a substrate thickness of 100 μm or less (around 70 μm), a process of back grinding the back surface of a thick wafer of about 500 μm, a process of ion implantation from the back surface, and a heat treatment of the back surface are required. Therefore, there are many problems in the manufacturing process such as warping of the wafer. In the figure, 92 is a metal film formed on the p ⁺ isolation layer, and 93 is an insulating film of a protective film.
FIG. 9 is a diagram showing the steps of the semiconductor device manufacturing method (conventional example 1) according to the first conventional example, and FIG. 9 (a) to FIG. It is. Here, the FS-IGBT in FIG. 7 is taken as an example of the semiconductor device.
Step (1) On the surface side of the n-type thick wafer 51 (FZ-N substrate), as shown in FIG. 7, a gate oxide film 84 (here, SiO ₂ ) and polycrystalline silicon (here, Poly-Si) ) Is deposited and processed, and an interlayer insulating film 86 (here, BPSG: boron phosphorous glass) is deposited on the surface and processed to form an insulated gate structure. Subsequently, after forming the p-type base layer 82 (p ⁺ ) shown in FIG. 7 on the thick wafer 51, the p-type base layer 82 is formed, and then the n-type emitter layer 83 is formed in the p-type base layer 82. Form. Note that the FZ-N substrate is an n-type wafer manufactured in a floating zone (FZ).

Next, an emitter electrode 87 made of an aluminum / silicon film is formed in contact with the n-type emitter layer 83. The aluminum / silicon film is then heat-treated at a low temperature of about 400 ° C. to 500 ° C. in order to realize stable bonding and low resistance wiring. Further, an insulating protective film made of the polyimide film 54 is formed so as to cover the surface. The diffusion layer 53 is composed of the p-type base layer 82 and the n-type emitter layer 83 of FIG. 7, and the surface electrode 53 is the gate oxide film 84, gate electrode 85, interlayer insulating film 86 and emitter electrode 87 of FIG. The surface structure 55 includes a p-type base layer 82, an n-type emitter layer 83, a surface electrode 53, and a polyimide film 54 serving as a protective film.
In this way, the surface structure 55 of the FS-IGBT chip is formed on the thick wafer 51, and the thick wafer 51 has a large number of cells shown in FIG. In the figure, reference numeral 56 denotes a thick wafer formed up to the surface structure 55, 57 denotes the surface of the thick wafer 56 (the surface of the polyimide film), and 58 denotes the back surface of the thick wafer (FIG. 5A).

Next, the process proceeds to the back surface manufacturing process.
Step (2) From the back surface 58 side, the thick wafer 56 is back grinded (ground), and then etched to remove the processing strain layer to form a thin wafer 61. Etching is performed using wet nitric acid solution having good mass productivity. Reference numeral 59 in the figure is the back surface of the thin wafer (FIG. 5B).
Step (3) Next, in order to form an n-type buffer layer (n ⁺ layer 62) and the high-concentration p-type collector layer (p ⁺ layer 63), an ion implantation from the rear surface 59. In this example, n ⁺ layer 62 is implanted with phosphorus, and p ⁺ layer 63 is implanted with boron. Subsequently, heat treatment (annealing) is performed in an electric furnace. The heat treatment is performed at a low temperature of 350 ° C. to 500 ° C. where the surface electrode 53 is not melted ((c) in the figure). Step (4) Next, a back electrode 64 (collector electrode) is vapor-deposited on the high-concentration p-type collector layer (p ⁺ layer 63) by a combination of metal films such as an aluminum layer, a titanium layer, a nickel layer, and a gold layer. (Fig. 4D).
Step (5) Next, the thin wafer 61 is diced into chips (FIG. 5E).
Step (6) After that, although not shown, in order to connect the surface electrode 64 (emitter electrode, gate pad connected to the gate electrode) and the external lead-out terminal (lead terminal), an aluminum wire is bonded to the surface electrode 64 by ultrasonic wire bonding. The other back surface electrode 64 (collector electrode) is fixed by an apparatus and connected to a fixing member such as a cooling base through a solder layer (not shown).

In this method, since the thickness of the wafer after back grinding is thin, cracking occurs. In particular, in the vapor deposition step of step (4), the back electrode 64 formed on the back surface 59 acts in a shrinking direction with respect to the thin wafer 56, and the thin wafer warps the back electrode 64 side greatly in a concave shape due to this tensile stress.
FIG. 10 is a diagram showing the thickness of the thin wafer after the back grinding and etching are finished, and the amount of warpage of the thin wafer after the back electrode deposition. Conventional example 1 (black circle) in the figure shows the amount of warpage of the wafer. Conventional examples 2 and 3 show the case of the steps shown in FIGS.
The amount of warpage of the wafer after the back electrode deposition becomes larger as the thickness of the wafer is reduced, and reaches 11 mm at 70 μm.

FIG. 11 is a diagram showing the thickness of the wafer and the cracking rate of the wafer after the back grinding and etching are completed. Here, the thickness of the wafer indicates the thickness of the thin wafer 1a (the thickness of the wafer without the surface electrode 3 and the polyimide film 4). The black circles in the figure are the steps in FIG. 9 after the back electrode deposition, and the white circles are after the back grinding and etching are completed. In addition, the crack after back grinding and an etching were also included in the crack rate after back electrode vapor deposition.
From FIG. 11, the thinner the wafer, the greater the cracking rate of the thin wafer and the higher the manufacturing cost. When the thickness is 70 μm, the cracking rate after the back electrode deposition is 90% or more. As described above, when the thin wafer 61 is processed in the process of the conventional example 1 shown in FIG. 9, the crack rate of the wafer is large and the manufacturing cost is increased.
In order to solve this, for example, as shown in Patent Document 1, it is effective to fix the wafer to a glass substrate as a support substrate via an adhesive sheet, and to proceed with the process up to the back electrode deposition in that state. Become. Here, the case where the adhesive sheet is composed of a foam tape and a UV tape, the foam tape on the wafer side, and the UV tape on the glass substrate side will be described.

FIG. 12 is a diagram showing the steps of a semiconductor device manufacturing method (conventional example 2) according to a second conventional example, and FIG. 12 (a) to FIG. It is. The process (1) is the same as the process (1) of the conventional example 1, and the process (2) of the conventional example 1 and the processes after the process of FIG. 9 (b) are different.
Step (2) The thick wafer 56 on which the surface structure 55 is formed is reversed and fixed to the glass substrate 71 via the adhesive sheet 74. The adhesive sheet 74 includes a foam tape 73 and a UV tape 72. The foam tape 73 is disposed on the thick wafer 56 side, and the UV tape 72 is disposed on the glass substrate 71 side ((b) in the figure).
Step (3) Next, the thickness of the thick wafer 56 is reduced from the back surface 58 side by a back grinding or etching step, and the total thickness is set to a thin wafer 61 having a desired thickness. For example, in the case of a 600V element, it is about 70 μm ((c) in the figure).
Step (4) Next, ion implantation is performed from the back surface 59 in order to form an n-type buffer layer (n ⁺ layer 62) and a high-concentration p-type collector layer (p ⁺ layer 63). For example, the n ⁺ layer 62 is implanted with phosphorus, and the p ⁺ layer 63 is implanted with boron. Subsequently, the surface layer is annealed by laser irradiation to activate the impurities after ion implantation. Laser annealing is YAG third harmonic (YAG3ω) pulse laser (wavelength = 355 nm, half-value width = 100 ns to 500 ns, frequency = 500 Hz, one irradiation area is approximately 1 mm square, and irradiation is performed with 50% to 90% overlap. ). By using YAG3ω, a deep n ⁺ layer 62 of about 10 μm can be formed (for example, Patent Document 2).

Further, according to the laser annealing of YAG3ω, only the p ⁺ layer 63 and the n ⁺ layer 62 formed on the surface layer of the wafer can be activated, and the adhesive sheet 74 is not heated. Therefore, heat treatment can be performed at a high temperature regardless of the heat resistant temperature of the adhesive sheet 75. Also, from YAG second harmonic (YAG2ω) pulse laser (wavelength = 532 nm, half-width = 100 ns to 500 ns, frequency = 1 kHz, one irradiation area is about 1 mm square and irradiated with 50% to 90% overlap) Laser annealing may be performed (for example, Patent Document 3) (FIG. 4D).
Step (5) Next, a metal deposition film is formed on the high-concentration p-type collector layer (p ⁺ layer 63) to form a back electrode 64 (collector electrode). Here, the back electrode 64 is formed of a laminated metal film made of a metal such as an aluminum layer, a titanium layer, a nickel layer, or a gold layer. The vapor deposition at this time is preferably performed by a low temperature sputtering method. This is because the heat resistance temperature of the adhesive sheet 74 is approximately 100 ° C. or lower for a high-rigidity UV tape, 200 ° C. or lower for a heat resistant UV tape, and 150 ° C. or lower for a heat-foamed foam tape. This is because it is desirable that the temperature is 100 ° C. or less ((e) in the figure).
Step (6) Next, the thin wafer 61 on which the back electrode 64 is formed is heated to about 100 ° C. to be foamed and peeled from the foam tape 73. Thereafter, on the glass substrate 71 side, the UV tape 72 to which the foam tape 73 is fixed is peeled off from the glass substrate 71 by the irradiation of the ultraviolet rays 75 ((f) in the figure).
Step (7) Next, the thin wafer 61 is inverted, the back electrode 64 of the thin wafer 61 is attached to the dicing tape 76, and the thin wafer 61 on which the back electrode 64 is formed is diced into chips (FIG. g)).
Step (8) The subsequent processing such as wire bonding (not shown) is performed in the same manner as in FIG.

Although the FS-IGBT process has been described here, the n-type buffer layer (n ⁺ layer 62) is not formed by removing the process of forming the n ⁺ layer 62 in the above process (4). This is an IGBT process.
In the manufacture of the NPT-IGBT, since the n ⁺ layer 62 is not formed, the laser is a short half width XeF pulse laser (wavelength = 351 nm, half width = 14 ns) or XeCl pulse laser (wavelength = 308 nm, half width = 49 ns). The p ⁺ layer 63 is activated by using it.
According to the manufacturing method of FIG. 12, since the thin wafer 61 is stuck to the glass substrate 71 until the back electrode is formed, the wafer does not warp as shown in the conventional example 2 of FIG. do not do.
The manufacturing method of FIG. 12 has the following problems.

When the adhesive sheet 74 on the glass substrate 71 and the thin wafer 61 are peeled off by foam peeling, the tensile stress and foaming force of the backside metal vapor deposition film are used. However, when the glass substrate 71 and the thick wafer 51 are fixed via the adhesive sheet 74, the side surface of the adhesive sheet 74 is exposed, and this exposed side surface is used to remove the processed layer after grinding the thick wafer 51. The foaming agent of the foamed tape 73 constituting the adhesive sheet 74 is deteriorated by wet etching with a hydrofluoric acid solution of the above, and the peeling action is lowered to make peeling difficult.
Further, the side surface of the UV tape 72 constituting the adhesive sheet 74 is also melted by this wet etching, and the residue becomes particles, and gas is generated by the wet etching to contaminate the thin wafer 61, or a post process. Contaminates the vacuum equipment used in
Further, when the thick wafer 56 and the glass substrate 71 are fixed through the adhesive sheet 74, the thick wafer 61 and the glass substrate 71 are hard as shown in FIG. The air bubbles 81 are generated between the thick wafer 61 and the adhesive sheet 74 and between the glass substrate 71 and the adhesive sheet 74. Due to the bubbles 81, the thin wafer after grinding expands in a process in which the bubbles 81 are subjected to heat such as a vapor deposition process, and cracks are generated. Further, the back surface of the thin wafer undulates with the bubbles 81, and it becomes difficult to ensure the flatness of the thin wafer. The bubble 81 has a size of about 100 μm near the center and the edge, and the number of bubbles is about five (four are shown in the figure). Also, smaller bubbles are observed on the entire surface.

Next, a method for fixing a wafer and a glass substrate using a UV curable resin and a release layer instead of the adhesive sheet 74 will be described. The release layer is used to release the UV curable resin layer, and the release layer is peeled off by heating.
FIG. 13 is a diagram showing the steps of another method for manufacturing a semiconductor device according to the third conventional example (conventional example 3). FIG. 13 (a) to FIG. It is sectional drawing. Step (1) Same as Conventional Examples 1 and 2, except that UV curable resin layer 73 and release layer 72 are used instead of adhesive sheet 74 in Step (2) and FIG. .
Step (2) The thick wafer 56 on which the surface structure 55 is formed is inverted, the thick wafer 56 is inverted, and the UV curable resin layer 78 and the UV curable resin layer 78 are used to release the glass through the release layer 77. It adheres to the substrate 71.

First, a release liquid is applied onto the glass substrate 71 and solidified at room temperature to form a release layer 77 fixed to the glass substrate 71. Subsequently, a UV curable resin solution is applied onto the release layer 77. Thereafter, the surface 57 side of the thick wafer 56 is placed on the UV curable resin layer 78, and the UV curable resin liquid 78 is formed by irradiating ultraviolet rays to form the UV curable resin layer 78. The release layer 77 and the thick wafer 56 are fixed via the layer 78. The diameter of the glass substrate 71 is made about 4 mm larger than the diameter of the thick wafer 56 so that the stripping solution or UV curable resin solution to be applied is applied in the glass substrate 71 (FIG. 2B).
Step (3) Next, the total thickness of the wafer is changed to a thin wafer 61 having a desired thickness (for example, 70 μm, etc.) by the back grinding and etching steps ((c) in the figure).
Step (4) Next, in order to form an n-type buffer layer (n ⁺ layer 62) and the high-concentration p-type collector layer (p ⁺ layer 63), an ion implantation from the rear surface 59. For example, the n ⁺ layer 62 is implanted with phosphorus, and the p ⁺ layer 63 is implanted with boron. Subsequently, annealing is performed by laser irradiation. Laser annealing is the same as in FIG. 12, and the description is omitted ((d) in FIG. 12).
Step (5) Next, a metal vapor deposition film to be the back electrode 64 is formed on the high-concentration p-type collector layer (p ⁺ layer 63). Here, a back metal film made of metal of an aluminum layer, a titanium layer, a nickel layer, and a gold layer is formed. The vapor deposition at this time is preferably performed by a low temperature sputtering method. This is because the heat-resistant temperature of the UV curable resin layer 78 (UV resin layer) is approximately 200 ° C. or lower, and it is desirable that the temperature during film formation is 100 ° C. or lower ((e) in the figure). .
Step (6) Next, the thin wafer 61 on which the back electrode 64 is formed is peeled off. The peeling layer 77 is heated and peeled together with the UV curable resin layer 78 while being fixed to the glass substrate 71 by irradiating infrared light 79 from the glass substrate 71. A part of the UV curable resin layer 78 (not shown) attached to the thin wafer 61 side is attached with another strong adhesive sheet (not shown) on the UV curable resin layer 78 and peeled off the other adhesive sheet. By doing so, it can be peeled off (figure (f)).
Step (7) Next, the thin wafer 61 on which the back electrode 65 is formed is diced into chips (FIG. 5G).
Step (8) The subsequent wire bonding is the same as described above.

With this method, as shown in Conventional Example 3 in FIG. 10, no warpage occurs and wafer cracking does not occur. Further, the UV curable resin layer 73 enters the uneven surface formed on the front surface side of the thin wafer 61, and the pattern transfer in which the unevenness on the front surface generated when the thick wafer 56 is thinned is reflected on the back surface side does not occur.
However, when this method is used, since the glass substrate 71 is larger than the wafer, the grinding dust of the wafer due to back grinding remains on the periphery of the glass substrate 71. Even if the wafer is etched or cleaned, it is difficult to remove the grinding dust from the glass substrate 71. Further, the UV curable resin layer 78 is not etched by wet etching, but the glass substrate 71 is etched as shown in FIG. Then, the peeling layer 77 is altered by etching, and the altered substance adheres to the thin wafer 61 to cause contamination.

Moreover, the outer peripheral part of the glass substrate 71 is etched and a shape changes. The state is shown below.
FIG. 15 is a view showing a state in which the glass substrate is etched in the etching process. FIG. 15A shows a state after back grinding, FIG. 15B shows a state after wet etching, and FIG. These are the A section enlarged views of the figure (b).
After wet etching, the periphery of the glass substrate 71 is etched and the shape is greatly deformed as shown in part B of FIG. 5C, and the glass substrate 71 cannot be reused. Here, as a wet etching, a case where a so-called rotational etching method is adopted in which a glass substrate is rotated and an etching solution is dropped at the center to perform etching is employed. In this rotational etching, the upper periphery of the glass substrate 71 is used as an etching solution. Because of the exposure, the periphery of the upper portion of the glass substrate 71 is etched.
Japanese Patent Application No. 2002-302137 JP 2003-59856 A Japanese Patent Application No. 2003-179725

As described above, in the method in which the entire process is performed without attaching the wafer to the glass substrate, the wafer is cracked because the thickness of the wafer after back grinding is thin. In particular, in the vapor deposition process, the wafer cracking rate increases and the manufacturing cost increases as the wafer thickness decreases due to the tensile stress caused by the metal film on the back surface.
Further, since the annealing process is performed at a low temperature of about 350 ° C. to 500 ° C. so as not to affect the surface structure 55, the p ⁺ layer 63 (in this embodiment, boron is dosed at 1 × 10 ¹⁵ cm ^{−). 2/50} keV at an implantation) the activation rate of only about 2%, NPT-IGBT and FS-IGBT, the injection of positive holes is not performed sufficiently even in the reverse blocking IGBT. Therefore, it is difficult to realize good device characteristics.
In addition, in the FS-IGBT, there is an influence of a defect of the field stop layer (n ⁺ layer 62), and sufficient hole injection is not performed.

In the method of attaching the thick wafer 56 before back grinding to the glass substrate 71 using the adhesive tape 74, the annealing step is performed with a laser, and the surface layer is annealed at a sufficiently high temperature. Hole injection is performed sufficiently as large as about 80%. In the FS-IGBT, the field stop layer defect is repaired by annealing, and sufficient hole injection is performed.
However, in this method, the side surface of the adhesive sheet 74 is exposed, and the foam forming the adhesive sheet 74 is melted by wet etching with hydrofluoric acid solution for removing the processed layer after the back grinding of the thick wafer 56. The foaming agent of the tape 73 is deteriorated and the peeling action is lowered to make peeling difficult.
Further, the side surface of the UV tape 72 constituting the adhesive sheet 74 is also melted by this wet etching, and the residue becomes particles, and gas is generated by the wet etching to contaminate the wafer or to be used in a subsequent process. Contaminating manufacturing equipment such as vacuum equipment.

Further, the adhesion between the thick wafer 56 and the glass substrate 71 and the adhesive sheet 74 is not necessarily good, and bubbles 81 are generated between the thick wafer 56 and the adhesive sheet 74, and between the glass substrate 71 and the adhesive sheet 74. Due to the bubbles 81, the thin wafer 61 after grinding is broken, or the back surface of the thin wafer 61 is waved, making it difficult to ensure the flatness of the back surface of the wafer.
Further, in the method using the UV curable resin layer 78 and the release layer 77, as in the case of the adhesive sheet 74, since the annealing process is performed with a laser, the activation rate of the p ⁺ layer 63 is increased by about 80%. Injection is sufficient. In the FS-IGBT, defects in the field stop layer (n ⁺ layer 62) are repaired by annealing, and sufficient hole injection is performed.
However, in this method, it is necessary to make the size of the glass substrate 71 larger than that of the thick wafer 61, and the grinding dust of the wafer due to back grinding remains on the periphery of the glass substrate 71. Even if the wafer is etched or cleaned, it is difficult to remove the grinding dust from the glass substrate 71. In addition, after wet etching, the periphery of the glass substrate 71 is etched and the shape is greatly deformed as shown in part B of FIG. 3C, and the glass substrate 71 cannot be reused.

Further, the UV curable resin layer 78 is not etched by wet etching, but the glass substrate 71 is etched, so that it is difficult to reuse the glass substrate 71. Further, the peeling layer 77 is altered by etching, and the altered substance adheres to the thin wafer 61 to contaminate the thin wafer 61 and also the manufacturing apparatus.
The object of the present invention is to solve the above-mentioned problems, prevent wafer cracking in the process after thinning the wafer, prevent contamination of the wafer and the manufacturing apparatus, and a low-cost semiconductor that can reuse the glass substrate It is to provide a method for manufacturing an apparatus.

In order to achieve the above object, in the method of manufacturing a semiconductor device formed from a thin semiconductor substrate having a processing step on the back surface, the back surface side of the thick semiconductor substrate in which the surface structure (including the surface electrode) is formed on the front surface side Forming a thin semiconductor substrate by thinning, a step of bonding the surface of the thin semiconductor substrate and a support substrate through a fixing layer, a step of performing ion implantation and heat treatment on the back surface of the thin semiconductor substrate, forming a back electrode of the thin semiconductor substrate, and sequentially includes manufacturing method the step of removing the sticking layer from said thin semiconductor substrate and the supporting substrate.
Moreover, in the manufacturing method of the semiconductor device formed from the thin semiconductor substrate which has a processing process in the back surface, from the back surface side of the thick semiconductor substrate in which the surface structure (including the surface electrode) is formed on the front surface side

Forming a thin semiconductor substrate by thinning; performing ion implantation and heat treatment on a back surface of the thin semiconductor substrate; bonding the surface of the thin semiconductor substrate to a support substrate through a fixing layer; forming a back electrode on a thin semiconductor substrate, and sequentially includes manufacturing method the step of removing the sticking layer from said thin semiconductor substrate and the supporting substrate.

Also, in a method of manufacturing a semiconductor device formed from a thin semiconductor substrate having a processing step on the back surface, a thin semiconductor substrate is formed by thinning from the back surface side of a thick semiconductor substrate having a surface structure excluding the surface electrode on the front surface side. A step of performing ion implantation and heat treatment on the back surface of the thin semiconductor substrate, a step of bonding the surface of the thin semiconductor substrate and the support substrate through a first fixing layer, and a back electrode on the thin semiconductor substrate Forming the first fixing layer, peeling the first fixing layer from the thin semiconductor substrate and the supporting substrate, bonding the back surface of the thin semiconductor substrate and the supporting substrate through the second fixing layer, and the thin forming a surface electrode on the semiconductor substrate, the manufacturing method steps sequentially including for peeling the second pinned layer from said thin semiconductor substrate and the supporting substrate.
The step of forming a thin semiconductor substrate by thinning it from the back surface of the thick semiconductor substrate may be a step of grinding the surface and a step of etching.

Moreover, the pinned layer, the first, may the second pinned layer is formed as a multilayer fixed layer composed of a plurality of types of fixed layer to peel under different conditions.
The multilayer fixing layer may be formed of a UV curable resin layer and a release layer that is peeled off by heating.
The multilayer fixing layer may be formed of a foam layer that is foamed and peeled off by heating and a UV layer that is peeled off by ultraviolet irradiation.
The foamed layer and the UV layer are laminated into a sheet to form an adhesive sheet, the adhesive sheet is sandwiched between the thin semiconductor substrate and the support substrate, and a cylindrical body (roller) is placed on the thin semiconductor substrate. The cylindrical body is preferably rotated and moved from one end of the thin semiconductor substrate to the other end, and the adhesive tape is adhered to each other by bringing the thin semiconductor substrate and the support substrate into close contact with each other. At this time, if it is performed in a vacuum, the influence of particles and the like can be removed, and the attachment can be made more effective.

Further, the foamed layer and the UV layer are laminated in a sheet shape to form an adhesive sheet, the adhesive sheet is sandwiched between the thin semiconductor substrate and the support substrate, and the entire area on the thin semiconductor substrate is pressurized to each other. It is good to stick together. At this time, if it is performed in a vacuum, the influence of particles and the like can be removed, and the attachment can be made more effective.
As described above, when a thick semiconductor substrate is back-ground and etched to form a thin semiconductor substrate, and then the thin semiconductor substrate is attached to the support substrate via the fixing layer, the thin wafer has good flexibility, and the fixing layer and the thin semiconductor Almost no bubbles are generated between the substrate and the support substrate. Therefore, bubbles are expanded in the process of applying heat in the subsequent process, the thin semiconductor substrate is not cracked, and the surface is not rough, and the flatness of the wafer surface is kept good. In addition, the on-voltage characteristics can be improved. Further, since the support substrate is not etched, it can be reused.

If the adhesive layer is an adhesive sheet, the cylinder is rolled and moved in a vacuum on a thin semiconductor substrate to push out bubbles to the outer periphery of the wafer, reducing the size of the remaining bubbles and increasing the number. Therefore, it is possible to further reduce the wafer cracking rate and improve the device characteristics.
In addition, when the fixing layer is an adhesive sheet, by pressing the thin semiconductor substrate in a vacuum, the bubbles are pushed out to the outer periphery of the thin semiconductor substrate, and the number of remaining bubbles can be reduced and the number can be reduced. It is possible to reduce the cracking rate of the semiconductor substrate and improve the device characteristics (ON voltage).
Further, when the fixing layer is a UV curable resin layer and a release layer, the thickness is thinner than that of the adhesive tape, and the phenomenon that the pattern on the front side of the semiconductor substrate is transferred to the back surface can be reduced.

Further, since the peeling layer does not touch the etching solution, it does not change in quality and does not contaminate the semiconductor substrate or the manufacturing apparatus.
Also, if ion implantation and heat treatment (annealing) are performed before the thin semiconductor substrate is attached to the support substrate, the annealing temperature can be increased, and the activation rate of the impurities implanted into the back surface can be increased, resulting in device characteristics. Can be improved.
In addition, when a thin semiconductor substrate is attached to a supporting substrate when forming the back electrode and the front electrode, warping of the thin semiconductor substrate can be greatly reduced, and the cracking rate of the thin semiconductor substrate can be reduced.

According to the present invention, by sticking a thin semiconductor substrate (thin wafer) after back grinding and etching to a support substrate (glass substrate), generation of bubbles is suppressed, and cracking of the thin semiconductor substrate is prevented. It is possible to ensure the flatness of the back surface.
Further, by increasing the annealing temperature after ion implantation, the activation rate of impurities can be improved and good device characteristics (low on-voltage) can be obtained.
Further, since the support substrate (glass substrate) is not etched, it can be reused.

In the best mode for carrying out the present invention, a thick wafer on which a surface structure is formed is thinned by grinding (back grinding) and etching (wet etching), and the thin wafer is bonded to a support substrate (glass substrate) ( A back surface treatment (formation of p ⁺ layer, n ⁺ layer, back electrode, etc.) is performed by attaching via an adhesive tape, a UV curable resin layer and a release layer.

FIG. 1 is a diagram showing the steps of a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and FIGS. Here, FS-IGBT will be described as an example of the semiconductor device.
The steps (1) and (2) are the same as the steps (1) and (2) of the conventional example 1 and the steps of FIGS. 9A and 9B, and the steps (3) and thereafter are different. Further, in the step (2) of the conventional example 2 and the step of FIG. 12 (b), the thick wafer is fixed to the glass substrate through the adhesive sheet, but in this embodiment (FIG. 1), the back grind and the wet etching are performed. FIG. 12 is different from FIG. 12 in that a thin wafer is fixed to a glass substrate through an adhesive sheet.
Step (1) The surface structure 5 is formed on the surface side of the thick wafer 1. This surface structure is the same as the surface structure 55 of FIG. Similar to FIG. 11, the surface structure 5 includes a diffusion layer 2, a surface electrode 3, and a polyimide film 4. The surface structure 5 will be described in more detail. A gate electrode 85 made of gate oxide film 84 (here, SiO ₂ ) and polycrystalline silicon (here, Poly-Si) in FIG. 7 is deposited and processed, and an interlayer insulating film 86 (here, BPSG) is formed on the surface. Deposit and process to form an insulated gate structure. Subsequently, after forming a p-type base layer 82 (p ⁺ ) on the thick wafer 1, an n-type emitter layer 83 (n ⁺ ) is formed in the p-type base layer 82. The p-type base layer 82 (p ⁺ ) and the n-type emitter layer 83 (n ⁺ ) are the diffusion layer 2.

  Next, the surface electrode 4 (emitter electrode) made of an aluminum / silicon film is formed so as to be in contact with the n-type emitter layer 83. The aluminum / silicon film is then heat-treated at a low temperature of about 400 ° C. to 500 ° C. in order to realize stable bonding and low resistance wiring. Further, an insulating protective film made of the polyimide film 4 is formed so as to cover the surface. The cell portion of the FS-IGBT chip completed in this way is shown in FIG. A large number of these cells are formed on the thick wafer 1. At this stage, the surface side process is complete. The cell portion is not shown in the thick wafer 1. Reference numeral 6 denotes a thick wafer on which the surface structure 5 has been formed, reference numeral 7 denotes the front surface, and reference numeral 8 denotes the back surface thereof ((a) in the figure). In addition, the formation process of the said polyimide film 4 may be after the back surface grinding demonstrated below. In this case, the surface structure of the step (1) includes the surface electrode 4 but does not include the polyimide film 4. However, the polyimide film 4 is also included after the step (2).

Next, the process proceeds to the back surface manufacturing process.
Step (2) From the back surface 8 side, the thick wafer 1 is back grinded (ground), and then the back surface is wet-etched with a highly productive hydrofluoric acid solution to remove the processing strain layer, and a thin wafer 1a is formed. Form. Reference numeral 9 denotes a back surface after the wet etching, and reference numeral 11 denotes a thin wafer having a surface structure formed thereon ((b) in the figure).
Step (3) Next, the thin wafer 11 is fixed through the glass substrate 21 and the adhesive sheet 24 with the back surface 9 facing up and the front surface 7 facing down. The adhesive sheet 24 is composed of at least two layers of a UV tape 22 that is peeled off by ultraviolet rays and a foam tape 23 that is peeled off by heating. The foam tape 23 is fixed to the thin wafer 11 side, and the UV tape 22 is fixed to the glass substrate 21 side. The The foam tape 23 and the UV tape 22 are fixed to the surface 7 and the glass substrate 21 at room temperature, respectively. Further, the configuration of these tapes 22 and 23 may be reversed so that the foam tape 23 is fixed to the glass substrate 21 side and the UV tape 22 is fixed to the thin wafer 11 side. At this time, after the foam tape 23 to which the thin wafer 11 and the UV tape 22 are fixed is peeled off from the glass substrate 21, the UV tape 23 fixed to the thin wafer 11 is irradiated with ultraviolet rays, The foamed tape 22 may be peeled from the thin wafer 11 ((c) in the figure).
Step (4) Next, ion implantation is performed from the back surface 9 in order to form an n-type buffer layer (n ⁺ layer 12) and a high-concentration p-type collector layer (p ⁺ layer 13). For example, n ⁺ layer 12 is phosphorus, p ⁺ layer 13 implanting boron. Subsequently, the surface layer of the back surface 9 is annealed by laser irradiation. The feature of laser annealing is that only the surface layer of the surface irradiated with laser is annealed at a high temperature of about 1000 ° C., and the temperature of the surface not irradiated with laser can be kept at room temperature. Here, the laser is a YAG third harmonic (YAG3ω) pulse laser (wavelength = 355 nm, full width at half maximum = 100 ns to 500 ns, frequency = 500 Hz, with a single irradiation area of about 1 mm square and 50% to 90% overlap. A deep n ⁺ layer 12 of about 10 μm is formed.

Further, according to the laser annealing of YAG3ω, only the p ⁺ layer and the n ⁺ layer formed on the surface layer of the wafer can be activated, and the adhesive sheet is not heated. Therefore, heat treatment can be performed at a high temperature regardless of the heat resistant temperature of the adhesive sheet 24. Also, from YAG second harmonic (YAG2ω) pulse laser (wavelength = 532 nm, half-width = 100 ns to 500 ns, frequency = 1 kHz, one irradiation area is about 1 mm square and irradiated with 50% to 90% overlap) Laser annealing may be performed ((d) in the figure).
Step (5) Next, a metal vapor deposition film is formed as the back electrode 14 on the high-concentration p-type collector layer (p ⁺ layer 13). Here, the metal vapor deposition film is made of an aluminum layer, a titanium layer, a nickel layer, or a gold layer. This vapor deposition is preferably performed by a low temperature sputtering method. That is, the heat resistance temperature of the adhesive sheet 24 is approximately 100 ° C. or less for a high-rigidity UV tape, 200 ° C. or less for a heat resistant UV tape, and 150 ° C. or less for a foam tape that is heated and fired. It is because it is desirable that is below 100 degreeC. Reference numeral 15 denotes a back surface structure comprising an n ⁺ layer 12, a p ⁺ layer 13 and a back electrode 14 (FIG. 5E).
Step (6) Next, the thin wafer 11 on which the back electrode 14 is formed is foamed and peeled from the foaming tape 23 by heating. Thereafter, the glass substrate 21 side is irradiated with ultraviolet rays 25 to peel off the UV tape 22 to which the foaming tape 23 is fixed from the glass substrate 21. In the figure, a state before the UV tape 22 and the foamed tape 23 are peeled from the glass substrate 21 is depicted ((f) in the figure).
Step (7) Next, the thin wafer 11 on which the back surface structure 15 is formed is inverted, the back electrode 14 of the thin wafer 11 is attached to the dicing tape 26, and the thin wafer 11 on which the back electrode 14 is formed is diced into chips. (FIG. (G)).
Step (8) The subsequent processes such as wire bonding are the same as in the conventional method.

Although the FS-IGBT process has been described here, the NPT-IGBT process can be performed by removing the process of forming the n ⁺ layer 12 in the process (4) (by not forming the buffer layer).
In the manufacture of NPT-IGBT, since the n ⁺ layer 12 is not formed, the laser is a short half width XeF pulse laser (wavelength = 351 nm, half width = 14 ns) or XeCl pulse laser (wavelength = 308 nm, half width = 49 ns). Use to activate the p ⁺ layer.
According to this manufacturing method, since the wet etching process is performed before the fixing process using the adhesive sheet 24, the adhesive sheet 24 is not wet-etched. Therefore, the adhesive sheet as shown in FIG. The foaming agent of the foaming tape 23 constituting 24 does not lose its function, and the UV tape 22 is not melted by wet etching to generate particles or gas, and the thin wafer 11 and the manufacturing apparatus are not contaminated.

Further, when the thin wafer 11 is bonded to the glass substrate 21 via the adhesive sheet 24 in the step (3) and FIG. 1C, the thin wafer 11 is elastic and has a flexure so that it can be bonded. The sheet 24 and the thin wafer 11 are in close contact with each other by applying pressure, and the generation of the bubbles 81 as shown in FIG. 14 is suppressed. As a result, bubbles having a size of about 100 μm were not generated, and the number of bubbles smaller than that was greatly reduced. As a result, wafer cracking is reduced and the manufacturing cost can be reduced.
Further, when the pressurization is stopped, the adhesive sheet 24 swells in the vertical direction, so that the adhesive sheet 24 sandwiched between the thin wafer 11 and the glass substrate 21 acts in a close contact direction. Therefore, coupled with the reduction of the bubbles, the flatness of the back surface of the thin wafer 11 can be ensured in a good state.

For example, when the thin wafer 11 in the case where the silicon thickness is 70 μm and the glass substrate 21 having a thickness of 630 μm are bonded together with the adhesive sheet 24, the flatness of the back surface 9 of the thin wafer 11 is ± 3 μm to ± 5 μm. The flatness of the back surface 59 is improved by about half compared to the case where the conventional thick wafer 56 is attached when the thickness is 500 μm. As a result, the junction of the n ⁺ layer 12 and p ⁺ layer 13 and n ⁺ buffer layer is a p ⁺ collector layer formed on the back surface 9 side can flatly accurately formed, also the back electrode 14 can formed flat Device characteristics can be improved.
Further, since the glass substrate 21 is not exposed to the hydrofluoric acid solution, it can be reused without any change in shape, so that the manufacturing cost can be reduced.
Here, a specific method for attaching the adhesive sheet 24 will be described.

FIG. 2 is a diagram illustrating a method of attaching an adhesive sheet. This step is the step (3) of the first embodiment and the step of FIG. 1 (c), and is an attaching method that does not generate bubbles.
In a vacuum of about 10 Pa, an adhesive sheet 24 is pasted (foam tape 23 on the thin wafer 11 side and UV tape 22 on the glass substrate 21 side). The silicon thickness from a height of about 10 mm on the glass substrate 21. Is dropped and placed on the thin wafer 11. Several support plates 41 are arranged on the glass substrate 21 in the region where the thin wafer 11 is fixed (FIG. 1A).
Next, the support plate 41 is removed while the roller 42 is advanced (FIGS. 5B and 5C). When the roller 42 is pressed while rotating and passes over the thin wafer 11, since the force by the roller 42 is applied, the bubbles 81 shown in FIG. 14 escape to the outside of the thin wafer 11. Since the thin wafer 11 has a bend, it adheres well to the adhesive sheet 24. Further, when the pressure is released, the adhesive sheet 24 and the thin wafer 11 try to adhere further, so the thin thin wafer 11 is well bonded. Thereby, the flatness of the back surface 9 of the thin wafer can be set to ± 3 μm. Even if the force by the roller 42 is applied to the foam tape 23, the thin wafer 11 can be easily foamed and peeled off from the foam tape (for example, in the case of Nitto Denko 3195MS, a temperature of 120 ° C. to 130 ° C. is applied). Can do. The glass substrate 21 and the UV tape 22 (for example, UB-3083D, UB-5133D, UB-2153D manufactured by Nitto Denko) can be easily peeled off by irradiation with ultraviolet rays (UV irradiation of about 500 mJ).

FIG. 3 is a diagram illustrating another method of attaching the adhesive sheet. This step is the step of step (3) and FIG. 1 (c), and is an attaching method that does not generate bubbles.
By pressing the thin wafer 11 and the glass substrate 21 up and down in a vacuum of about 10 Pa through the adhesive sheet 24 (100 to 200 N / cm ² ), bubbles act on the outside of the thin wafer 11 so as to be instantaneously removed. . The thin wafer 11 is attracted and fixed to the wafer support 43 with the surface 7 facing down, and the glass substrate 21 is placed on the glass substrate support. Since the thin wafer 11 has flexibility, the thin wafer 11 is well bonded to the adhesive sheet 24 to improve adhesion. In addition, the adhesive sheet 24 comes into close contact with the thin wafer 11 and the glass substrate 21 when the applied pressure is removed. Thereby, the flatness of the back surface 9 of the thin wafer 11 can be set to ± 3 μm. The thin wafer 11 can be easily heated from the foam tape (for example, by applying a temperature of 120 ° C. to 130 ° C. in 3195MS manufactured by Nitto Denko) by applying a vertical force to the foam tape 23 in a vacuum. Foam can be peeled off. The glass substrate 21 and the UV tape 22 (for example, UB-3083D, UB-5133D, UB-2153D manufactured by Nitto Denko) can also be easily peeled by irradiation with ultraviolet rays (UV irradiation of about 500 mJ).

  In addition, when the adhesive sheet 24 is pasted on the glass substrate 21 or the thin wafer 11 at the initial stage, the effect of dust or dust can be prevented by performing the pasting operation in a vacuum.

FIGS. 4A and 4B are diagrams showing the steps of the semiconductor device manufacturing method according to the second embodiment of the present invention. FIGS. The difference from the first embodiment (FIG. 1) is that the UV curable resin layer 28 and the release layer 27 are used in place of the adhesive tape 24 in the step (3). Therefore, the steps after step (3) will be described.
Step (3) The thin wafer 11 is fixed to the glass substrate 21 through the UV curable resin layer 28 and the release layer 27 with the back surface 9 side facing up.
First, a release liquid is applied on the glass substrate 21 and solidified at room temperature to form a release layer 27 fixed to the glass substrate 21. Subsequently, a UV curable resin liquid is applied onto the release layer 27. Thereafter, the surface 7 side of the thin wafer 11 is placed on the UV curable resin liquid, and the UV curable resin layer 28 is formed by irradiating the ultraviolet rays to cure the UV curable resin layer. The release layer 27 and the surface 7 of the thin wafer 11 are fixed through the mold resin layer 28. The diameter of the glass substrate 21 is made about 4 mm larger than the diameter of the thin wafer 11 so that the stripping solution or UV curable resin solution to be applied is applied in the glass substrate 21 (FIG. 3C).
Step (4) Next, ion implantation is performed from the back surface 9 in order to form an n-type buffer layer (n ⁺ layer 12) and a high-concentration p-type collector layer (p ⁺ layer 13). For example, the n ⁺ layer 12 is implanted with phosphorus, and the p ⁺ layer 13 is implanted with boron. Subsequently, the surface layer of the back surface 9 is annealed by laser irradiation as in FIG. 1 ((d) in FIG. 1).
Step (5) Next, a metal vapor deposition film to be the back electrode 14 is formed on the high concentration p-type collector layer (p ⁺ layer 13). Here, a back metal film made of metal of an aluminum layer, a titanium layer, a nickel layer, and a gold layer is formed. The vapor deposition at this time is preferably performed by a low temperature sputtering method. This is because the heat-resistant temperature of the UV curable resin layer 28 (UV resin layer) is approximately 200 ° C. or lower, and it is desirable that the temperature during film formation is 100 ° C. or lower ((e) in the figure). .
Step (6) Next, the thin wafer 11 on which the back electrode 64 is formed is peeled off. The release layer 27 is heated and peeled together with the UV curable resin layer 28 while being fixed to the glass substrate 21 by irradiating infrared light 29 from the glass substrate 21. A part of the UV curable resin layer 28 (not shown) attached to the thin wafer 11 side is attached with another adhesive sheet (not shown) having a high strength on the UV curable resin layer 28, and the other adhesive sheet is peeled off. By doing so, it can be peeled off (figure (f)).
Step (7) Next, the thin wafer 11 on which the back structure 15 is formed is inverted, the back electrode 14 of the thin wafer 11 is attached to the dicing tape 26, and the thin wafer 11 on which the back electrode 14 is formed is diced into chips. (FIG. (G)).
Step (8) The subsequent processes such as wire bonding are the same as in the conventional method.

Also in this second embodiment, the fixing process for fixing the thin wafer 11 and the glass substrate 21 with the UV curable resin layer 28 and the release layer 27 is after the wet etching process. 27 is not wet-etched, so that the peeling layer 27 is not altered as described above, and the peeling is performed smoothly. Further, the thin wafer 11 is not contaminated by the altered material. Further, since the glass substrate 21 is not exposed to the wet etching hydrofluoric acid solution, it can be reused without contamination and shape change, and thus the manufacturing cost can be reduced.
Furthermore, since the combined thickness of the UV curable resin layer 28 and the release layer 27 can be reduced compared to the adhesive sheet 24, the pattern transfer to the back side of the surface side pattern due to the back grinding generated in the case of the adhesive sheet 24 is possible. Is less likely to occur.

  Further, by using the UV curable resin layer 28 and the release layer 27, the flatness of the back surface 9 of the thin wafer can be about ± 2 μm.

FIG. 5 is a diagram showing the steps of the semiconductor device manufacturing method according to the third embodiment of the present invention, and FIG. 5 (a) to FIG. The difference from the first embodiment (FIG. 1) is that the surface electrode 3 and the polyimide film 4 are not formed on the thick wafer 1, and the surface electrode is formed after the thin wafer 1a is attached to the glass substrate 21. 3 and the polyimide film 4 are formed, and then the thin wafer 11 (thin wafer with a back surface structure) is removed from the glass substrate 21, and the front surface 7 and the glass substrate 21 are turned over to attach the adhesive tape 24a (UV tape 22a and foam tape 23a). And the back electrode 14 is formed on the back surface 9.
Step (1) Deposit and process a gate electrode 85 made of the gate oxide film 84 (here, SiO ₂ ) and polycrystalline silicon (here, Poly-Si) in FIG. An interlayer insulating film 86 (here, BPSG) is deposited and processed to form an insulated gate structure. Subsequently, after forming a p-type base layer 82 (p ⁺ ) on the thick wafer 1, an n-type emitter layer 83 (n ⁺ ) is formed in the p-type base layer 82 (FIG. 1A).

Next, the process proceeds to the back surface manufacturing process.
Step (2) From the back surface 8 side, the thick wafer 1 is back-ground (ground), and then wet etching is performed to remove the processing strain layer to form a thin wafer 1a. Etching is performed by wet etching using a hydrofluoric acid solution ((b) in the figure).
Step (3) Next, in order to form n ⁺ buffer layer (n ⁺ layer 12)) and the high-concentration p-type collector layer (p ⁺ layer 13), an ion implantation from the back 9. For example, phosphorus is implanted into the n ⁺ layer 12 and boron is implanted into the p ⁺ layer 13. Subsequently, high-temperature heat treatment (annealing) is performed in an electric furnace or the like. The heat treatment temperature is a low temperature of 800 ° C. to 1000 ° C. ((c) in the figure).
Here, the process proceeds to the surface manufacturing process again.
Step (4) Next, the thin wafer 1a is fixed with the glass substrate 21 and the adhesive sheet 24 with the front surface 7a facing up and the back surface 9 facing down (FIG. 4D).
Step (5) Next, a surface electrode 3 (emitter electrode) made of an aluminum / silicon film is formed so as to be in contact with the n-type emitter layer. The aluminum / silicon film is then heat-treated at a low temperature of about 400 ° C. to 500 ° C. in order to realize stable bonding and low resistance wiring. Further, an insulating protective film made of the polyimide film 4 is formed so as to cover the surface (FIG. 5E).

Here, the process proceeds to the back surface manufacturing process again.
Step (6) Next, the thin wafer 11 (thin wafer with a surface structure) is removed from the glass substrate 21, and the glass substrate 21 and the adhesive sheet 24a (foam tape) with the back surface 9 of the thin wafer 11 facing up and the front surface 7 facing down. 23a and UV tape 22a). Next, on the high-concentration p-type collector layer (p ⁺ layer 13), a back electrode 14 is formed by vapor deposition using a combination of metal films such as an aluminum layer, a titanium layer, a nickel layer, and a gold layer (FIG. )).
Step (7) Next, the thin wafer 11 is peeled off from the foam tape 23a by foam peeling. Thereafter, the glass substrate side 21 peels off the UV tape 22a to which the foam tape 23a is fixed by the irradiation of the ultraviolet rays 25a from the glass substrate 21 ((g) in the figure).
Step (8) Next, the thin wafer 11 on which the back surface structure 15 is formed is reversed, the back electrode 14 of the thin wafer 11 is attached to a dicing tape 26, and the thin wafer 11 on which the back electrode 14 is formed is diced into chips. (FIG. (H)).
Step (9) The subsequent processes such as wire bonding are the same as in the conventional method.

In this manufacturing method, annealing after ion implantation is performed at a high temperature of 900 ° C. to 1100 ° C. using an electric furnace without using a laser, so that the activation rate of the n ⁺ layer 12 and the p ⁺ layer 13 is 80 to 80 ° C. It can be 90%. In both the FS-IGBT and the field stop layer, defects are recovered and a high activation rate of 90% or more can be obtained. In addition, since the heat treatment time can be made longer than in laser annealing, the thickness of the p-type collector layer (p ⁺ layer 13) can be made about twice that of laser annealing, and the on-voltage can be reduced. Further, since the laser annealing can be batch-processed compared to the single wafer type, the lead time can be shortened and the manufacturing cost can be reduced. Furthermore, an expensive laser device is not required, and high-temperature annealing can be performed in an inexpensive electric furnace.
In this method, the step of forming the surface electrode 3 and the polyimide film 4 made of an aluminum / silicon film is performed after these ion implantation and heat treatment steps. The bonding process of the glass substrate 21 is performed twice, but the amount of warpage of the wafer after the formation of the front surface electrode 3, the polyimide film 4 and the back surface electrode 14 is about 4 mm, and the thin wafer 11 and glass when the silicon thickness is 70 μm. The board | substrate 21 can be bonded together easily. In addition, since the flexible thin wafer 11 is fixed to the glass substrate 21, the adhesiveness is good and fixing with few bubbles is possible. The peeling method is the same as described above. When the adhesive tapes 24 and 24a are used, the flatness of the back surface 9 of the thin wafer 11 is about ± 3 μm to ± 5 μm. Instead of the adhesive tapes 24 and 24a, the UV curable resin layer 28 and When the release layer 27 is used, the flatness of the back surface 9 of the thin wafer 11 can be about ± 2 μm.

In each of the above embodiments, since the amount of warpage of the thin wafer after backside vapor deposition can be suppressed, cracks after the grinding process hardly occur.
As described above, a semiconductor device using a thin wafer having good device characteristics with low on-voltage can be manufactured by ensuring good flatness and increasing the activation of holes.

It is a figure which shows the process by the manufacturing method of the semiconductor device of 1st Example of this invention, (a) to (g) is principal part manufacturing process sectional drawing shown to process order The figure which shows the method of sticking the adhesive sheet The figure which shows another method of sticking the adhesive sheet It is a figure which shows the process by the manufacturing method of the semiconductor device of 2nd Example of this invention, (a) to (g) is principal part manufacturing process sectional drawing shown to process order It is a figure which shows the process by the manufacturing method of the semiconductor device of 3rd Example of this invention, (a) to (h) is principal part manufacturing process sectional drawing shown to process order Cross-sectional view of the principal part of an NPT-IGBT having a low p ⁺ collector layer with a low dose Cross-sectional structure diagram of FS-IGBT having a low dose shallow p ⁺ collector layer and n buffer layer Cross-sectional view of the main part of a reverse blocking IGBT having a separation layer It is a figure which shows the process by the manufacturing method of the semiconductor device of the 1st prior art example, (a) to (e) is principal part manufacturing process sectional drawing shown in process order Diagram showing thin wafer thickness after back grinding and etching and thin wafer warpage after back electrode deposition Diagram showing thin wafer thickness and thin wafer crack rate after back grinding and etching It is a figure which shows the process by the manufacturing method of the semiconductor device of the 2nd prior art example, (a) to (g) is principal part manufacturing process sectional drawing shown to process order It is a figure which shows the process by the manufacturing method of the semiconductor device of the 3rd prior art example, (a) to (g) is principal part manufacturing process sectional drawing which showed process order Diagram explaining the generation of bubbles Diagram explaining that glass substrate changes shape by etching

Explanation of symbols

1 Thick wafer (silicon)
1a Thin wafer (silicon)
2 Diffusion layer 3 Surface electrode 4 Polyimide film 5 Surface structure 6 Thick wafer (with surface structure)
7 Surface (after polyimide film formation)
7a Surface (before surface electrode formation)
8 Back side (thick wafer)
9 Back side (thin wafer)
11 Thin wafer (with surface structure)
12 n ⁺ layer 13 p ⁺ layer 14 Back electrode 21 Glass substrate 22, 22a UV tape 23, 23a Foam tape 24, 24a Adhesive sheet 25, 25a Ultraviolet 26 Dicing tape 27 Release layer 28 UV curable resin layer 29 Infrared 41 Support plate 42 Roller 43 Wafer support 44 Glass substrate support

Claims (10)

In a manufacturing method of a semiconductor device formed from a thin semiconductor substrate having a processing step on the back surface, a thin semiconductor substrate is formed by thinning from the back surface side of a thick semiconductor substrate having a surface structure formed on the front surface side, and the thin a step of bonding the semiconductor substrate surface and the supporting substrate through the fixing layer, and performing ion implantation and heat treatment on the back surface of the thin semiconductor substrate, forming a back electrode of the thin semiconductor substrate, the fixed A method of manufacturing a semiconductor device , comprising: sequentially separating layers from the thin semiconductor substrate and the supporting substrate . In a manufacturing method of a semiconductor device formed from a thin semiconductor substrate having a processing step on the back surface, a thin semiconductor substrate is formed by thinning from the back surface side of a thick semiconductor substrate having a surface structure formed on the front surface side, and the thin Performing ion implantation and heat treatment on the back surface of the semiconductor substrate, bonding the surface of the thin semiconductor substrate and a support substrate through a fixing layer, forming a back electrode on the thin semiconductor substrate, and fixing A method of manufacturing a semiconductor device , comprising: sequentially separating layers from the thin semiconductor substrate and the supporting substrate . In a manufacturing method of a semiconductor device formed from a thin semiconductor substrate having a processing step on the back surface, a step of forming a thin semiconductor substrate by thinning from a back surface side of a thick semiconductor substrate in which a surface structure excluding a surface electrode is formed on the front surface side A step of performing ion implantation and heat treatment on the back surface of the thin semiconductor substrate, a step of bonding the surface of the thin semiconductor substrate and the support substrate through a first fixing layer, and forming a back electrode on the thin semiconductor substrate A step of peeling the first fixing layer from the thin semiconductor substrate and the supporting substrate, a step of bonding the back surface of the thin semiconductor substrate and the supporting substrate through a second fixing layer, and the thin semiconductor substrate A method of manufacturing a semiconductor device comprising: sequentially forming a surface electrode on the substrate; and peeling the second fixing layer from the thin semiconductor substrate and the support substrate . The method of manufacturing a semiconductor device according to the pinned layer any of claims 1 or 2, characterized in that it is formed as a multilayer fixed layer composed of a plurality of types of fixed layer to peel under different conditions. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first and second fixing layers are formed as a multi-layer fixing layer including a plurality of types of fixing layers that are peeled off under different conditions. The semiconductor device according to any one of claims 1 to 5, and step step of grinding the surface to form a thin semiconductor substrate is thinned from the back surface of the thick semiconductor substrate, characterized in that the step of etching Manufacturing method. The multilayered pinned layer, a UV-curable resin layer, a method of manufacturing a semiconductor device according to any one of claims 4 or 5, characterized in that it is formed by the peeling layer is peeled off by heating. The multilayered pinned layer, a method of manufacturing a semiconductor device according to any one of claims 4 or 5, characterized in that it is formed by a UV layer is peeled off by the foam layer and the ultraviolet radiation which foams peeled off by heating. The foam layer and the UV layer are laminated in a sheet form to form an adhesive sheet, the adhesive sheet is sandwiched between the thin semiconductor substrate and the support substrate, and the thin semiconductor substrate is pressed by a cylindrical body, the cylinder 9. The semiconductor according to claim 8 , wherein a body is rotated and moved from one end to the other end of the thin semiconductor substrate, and the adhesive tape is bonded to each other by bringing the thin semiconductor substrate and the support substrate into close contact with each other. Device manufacturing method. The foamed layer and the UV layer are laminated into a sheet to form an adhesive sheet, the adhesive sheet is sandwiched between the thin semiconductor substrate and the support substrate, and the entire area on the thin semiconductor substrate is pressed to attach each other. the method of manufacturing a semiconductor device according to claim 8, wherein the keying.

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