JP2005302885A - Semiconductor circuit board and semiconductor circuit - Google Patents

Semiconductor circuit board and semiconductor circuit Download PDF

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JP2005302885A
JP2005302885A JP2004114367A JP2004114367A JP2005302885A JP 2005302885 A JP2005302885 A JP 2005302885A JP 2004114367 A JP2004114367 A JP 2004114367A JP 2004114367 A JP2004114367 A JP 2004114367A JP 2005302885 A JP2005302885 A JP 2005302885A
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semiconductor circuit
substrate
noise
integrated circuit
noise countermeasure
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JP3763312B2 (en
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Takashi Okano
貴史 岡野
Masaya Nishimura
政弥 西村
Shuhei Kawamura
周平 川村
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Daikin Industries Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform noise countermeasures for a semiconductor circuit board and further to enable to reduce a development cost. <P>SOLUTION: The semiconductor circuit board comprises a control board 1 and a semiconductor circuit 2 connected to the corresponding control board 1. The semiconductor circuit 2 has a board 21, an integrated circuit group 22, and noise countermeasure means 23, 231. These are constituted separate from the control board 1. The integrated circuit group 22 contains an integrated circuit serving as a noise generating source, for example, a fast switching element 221, and a transmission/reception circuit 222. The board 21 is a multilayer lamination board, to shift a frequency of noises generated from the integrated circuit group 221 to a side of a high frequency. The noise countermeasure means 23 is connected between the integrated circuit group 22 and the control board 1, and in particular, a filter damping the high frequency of noises suffices. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体回路基板及び半導体回路に関し、例えば設計技術に適用することができる。   The present invention relates to a semiconductor circuit substrate and a semiconductor circuit, and can be applied to, for example, design technology.

空調機器等には、その動作を制御するために、例えば半導体回路基板が設けられている。従来の半導体回路基板は、集積回路群とその制御回路、電源回路等を同一の基板上に形成していた。集積回路群は、例えば高速スイッチング素子や送信/受信回路等を含む。制御回路は、例えばマイクロプロセッサ等を含み、集積回路群を制御する。電源回路は、集積回路群に電源を供給する。   In order to control the operation of an air conditioner or the like, for example, a semiconductor circuit board is provided. In a conventional semiconductor circuit board, an integrated circuit group and its control circuit, power supply circuit and the like are formed on the same board. The integrated circuit group includes, for example, a high-speed switching element and a transmission / reception circuit. The control circuit includes, for example, a microprocessor and controls the integrated circuit group. The power supply circuit supplies power to the integrated circuit group.

なお、放射ノイズをシミュレーションする技術が特許文献1に開示されている。また、フェライトビーズやコイル等のインダクタと、バイパスコンデンサとを用いることで、電源から発生するノイズを低減する技術が非特許文献1に紹介されている。電子機器の構造を多層積層基板にすることで、電子機器からのノイズの発生を低減する技術が非特許文献2に紹介されている。   A technique for simulating radiation noise is disclosed in Patent Document 1. Non-Patent Document 1 introduces a technique for reducing noise generated from a power supply by using an inductor such as a ferrite bead or a coil and a bypass capacitor. Non-Patent Document 2 introduces a technique for reducing the generation of noise from an electronic device by making the structure of the electronic device a multilayer laminated substrate.

特開平6−309420号公報JP-A-6-309420 「トランジスタ技術」,CQ出版,2001年10月号,p202“Transistor Technology”, CQ Publishing, October 2001, p202 宮崎誠一著,「ノイズ対策Q&A101問」,システム総研,p88−89Seiichi Miyazaki, “Noise Countermeasure Q & A 101 Questions”, Systems Research Institute, p. 88-89

近年では、空調機器等の高性能化に伴い、半導体回路基板での処理速度、例えば高速スイッチング素子のスイッチング速度が高速化されている。一方、処理速度の高速化に伴って、高速スイッチング素子などから不要ノイズが発生する。不要ノイズは、半導体回路基板内の他の回路や、空調機器等の周辺に配置された装置に影響を及ぼす可能性がある。   In recent years, the processing speed of a semiconductor circuit board, for example, the switching speed of a high-speed switching element has been increased with the improvement in performance of air conditioners and the like. On the other hand, unnecessary noise is generated from a high-speed switching element or the like with an increase in processing speed. Unnecessary noise may affect other circuits in the semiconductor circuit board and devices arranged around the air conditioner and the like.

そこで、例えば上記した非特許文献1や非特許文献2で紹介される技術によって、ノイズが低減される。しかし、従来の半導体回路基板では、同一の基板上に各回路が形成されていたため、半導体回路基板ごとにノイズ対策を施す必要があった。このため、開発コストがかかる等の問題が生じていた。   Therefore, for example, noise is reduced by the technique introduced in Non-Patent Document 1 and Non-Patent Document 2 described above. However, in the conventional semiconductor circuit substrate, since each circuit is formed on the same substrate, it is necessary to take measures against noise for each semiconductor circuit substrate. For this reason, problems such as high development costs have arisen.

また、従来の半導体回路基板に対するノイズ対策は、半導体回路基板の設計の後段で行われることが多かった。このため、必要とされるノイズ対策を効率良く施すことができなかった。   Further, noise countermeasures for conventional semiconductor circuit boards are often performed after the design of the semiconductor circuit board. For this reason, the necessary noise countermeasures could not be efficiently taken.

本発明は、上述の事情に鑑みてなされたものであり、半導体回路基板に対してノイズ対策を効率良く行うこと、更には開発コスト及び部品コストを低減することが目的とされる。   The present invention has been made in view of the above-described circumstances, and an object of the present invention is to efficiently take measures against noise on a semiconductor circuit board and further reduce development costs and component costs.

この発明の請求項1にかかる半導体回路基板は、制御基板(1)と、前記制御基板に接続される半導体回路(2)とを備え、前記半導体回路は、基板(21)と、前記基板上に搭載される集積回路群(22)と、前記基板上に搭載されるノイズ対策手段(23)と
を有し、前記集積回路群は、ノイズ発生源となる集積回路(221)を含み、前記制御基板から分離して構成される。
According to a first aspect of the present invention, a semiconductor circuit board includes a control board (1) and a semiconductor circuit (2) connected to the control board, and the semiconductor circuit includes the board (21) and the board. An integrated circuit group (22) mounted on the substrate and a noise countermeasure means (23) mounted on the substrate, the integrated circuit group including an integrated circuit (221) serving as a noise generation source, It is configured separately from the control board.

この発明の請求項2にかかる半導体回路基板は、請求項1記載の半導体回路基板であって、前記ノイズ対策手段(23)を介して前記集積回路群(22)と前記制御基板(1)とが接続される。   A semiconductor circuit board according to a second aspect of the present invention is the semiconductor circuit board according to the first aspect, wherein the integrated circuit group (22), the control board (1), and the control board (1) are arranged via the noise countermeasure means (23). Is connected.

この発明の請求項3にかかる半導体回路基板は、請求項1または請求項2記載の半導体回路基板であって、前記基板(21)は、前記集積回路群(22)が搭載される第1層基板(31)と、前記第1層基板に対して内層であって、互いに異なる固定電位が供給されるパターンが形成される複数の第2層基板(32,33)とを含む多層積層基板である。   A semiconductor circuit substrate according to a third aspect of the present invention is the semiconductor circuit substrate according to the first or second aspect, wherein the substrate (21) is a first layer on which the integrated circuit group (22) is mounted. A multi-layer laminated substrate including a substrate (31) and a plurality of second layer substrates (32, 33) formed with patterns that are inner layers with respect to the first layer substrate and are supplied with different fixed potentials. is there.

この発明の請求項4にかかる半導体回路基板は、請求項1乃至請求項3記載のいずれか一つに記載の半導体回路基板であって、前記ノイズ対策手段(23)は、前記集積回路群(22)から発生するノイズの高周波成分を減衰させる。   A semiconductor circuit board according to a fourth aspect of the present invention is the semiconductor circuit board according to any one of the first to third aspects, wherein the noise countermeasure means (23) includes the integrated circuit group ( 22) attenuates the high-frequency component of the noise generated from step 22).

この発明の請求項5にかかる半導体回路基板は、請求項1乃至請求項4のいずれか一つに記載の半導体回路基板であって、前記ノイズ対策手段(23)はフィルタである。   A semiconductor circuit board according to a fifth aspect of the present invention is the semiconductor circuit board according to any one of the first to fourth aspects, wherein the noise countermeasure means (23) is a filter.

この発明の請求項6にかかる半導体回路基板は、請求項1記載の半導体回路基板であって、前記半導体回路は、前記基板(21)上に搭載される第2のノイズ対策手段(231)を更に有し、前記基板(21)は、前記集積回路群(22)が搭載される第1層基板(31)と、前記第1層基板に対して内層であって、互いに異なる固定電位が供給されるパターンが形成される複数の第2層基板(32,33)とを含む多層積層基板であって、前記第2のノイズ対策手段を介して前記集積回路群と前記固定電位が供給される前記パターンとが接続される。   A semiconductor circuit board according to a sixth aspect of the present invention is the semiconductor circuit board according to the first aspect, wherein the semiconductor circuit includes second noise countermeasure means (231) mounted on the substrate (21). Further, the substrate (21) is a first layer substrate (31) on which the integrated circuit group (22) is mounted, and is an inner layer with respect to the first layer substrate, and is supplied with different fixed potentials. And a plurality of second layer substrates (32, 33) on which a pattern to be formed is formed, and the integrated circuit group and the fixed potential are supplied via the second noise countermeasure means. The pattern is connected.

この発明の請求項7にかかる半導体回路基板は、請求項6記載の半導体回路基板であって、前記ノイズ対策手段(23)は、前記固定電位が供給される前記パターンと接続される。   A semiconductor circuit board according to a seventh aspect of the present invention is the semiconductor circuit board according to the sixth aspect, wherein the noise countermeasure means is connected to the pattern to which the fixed potential is supplied.

この発明の請求項8にかかる半導体回路基板は、請求項6または請求項7記載の半導体回路基板であって、前記ノイズ対策手段(23)及び前記第2のノイズ対策手段(231)は、前記集積回路群(22)から発生するノイズの高周波成分を減衰させる。   A semiconductor circuit board according to an eighth aspect of the present invention is the semiconductor circuit board according to the sixth or seventh aspect, wherein the noise countermeasure means (23) and the second noise countermeasure means (231) A high frequency component of noise generated from the integrated circuit group (22) is attenuated.

この発明の請求項9にかかる半導体回路基板は、請求項6乃至請求項8のいずれか一つに記載の半導体回路基板であって、前記ノイズ対策手段(23)及び前記第2のノイズ対策手段(231)はフィルタである。   A semiconductor circuit board according to a ninth aspect of the present invention is the semiconductor circuit board according to any one of the sixth to eighth aspects, wherein the noise countermeasure means (23) and the second noise countermeasure means. (231) is a filter.

この発明の請求項10にかかる半導体回路基板は、請求項1乃至請求項9のいずれか一つに記載の半導体回路基板であって、前記集積回路(221)は高速スイッチング素子を含む。   A semiconductor circuit board according to a tenth aspect of the present invention is the semiconductor circuit board according to any one of the first to ninth aspects, wherein the integrated circuit (221) includes a high-speed switching element.

この発明の請求項11にかかる半導体回路は、制御基板(1)に接続可能な半導体回路(2)であって、基板(21)と、前記基板上に搭載される集積回路群(22)と、前記基板上に搭載されるノイズ対策手段(23)とを有し、前記集積回路群は、ノイズ発生源となる集積回路(221)を含み、前記制御基板から分離して構成される。   A semiconductor circuit according to an eleventh aspect of the present invention is a semiconductor circuit (2) connectable to the control board (1), the board (21), and an integrated circuit group (22) mounted on the board. And the noise countermeasure means (23) mounted on the substrate, and the integrated circuit group includes an integrated circuit (221) serving as a noise generation source and is configured separately from the control substrate.

この発明の請求項12にかかる半導体回路は、請求項11記載の半導体回路であって、前記ノイズ対策手段(23)を介して前記集積回路群(22)と前記制御基板(1)とが接続可能である。   A semiconductor circuit according to a twelfth aspect of the present invention is the semiconductor circuit according to the eleventh aspect, wherein the integrated circuit group (22) and the control board (1) are connected via the noise countermeasure means (23). Is possible.

この発明の請求項13にかかる半導体回路は、請求項11または請求項12記載の半導体回路であって、前記基板(21)は、前記集積回路群(22)が搭載される第1層基板(31)と、前記第1層基板に対して内層であって、互いに異なる固定電位が供給されるパターンが形成される複数の第2層基板(32,33)とを含む多層積層基板である。   A semiconductor circuit according to a thirteenth aspect of the present invention is the semiconductor circuit according to the eleventh or twelfth aspect, wherein the substrate (21) is a first layer substrate on which the integrated circuit group (22) is mounted ( 31) and a plurality of second layer substrates (32, 33) which are inner layers with respect to the first layer substrate and are provided with patterns to which different fixed potentials are supplied.

この発明の請求項14にかかる半導体回路は、請求項11乃至請求項13記載のいずれか一つに記載の半導体回路であって、前記ノイズ対策手段(23)は、前記集積回路群(22)から発生するノイズの高周波成分を減衰させる。   A semiconductor circuit according to a fourteenth aspect of the present invention is the semiconductor circuit according to any one of the eleventh to thirteenth aspects, wherein the noise countermeasure means (23) is the integrated circuit group (22). Attenuates high frequency components of noise generated from

この発明の請求項15にかかる半導体回路は、請求項11乃至請求項14のいずれか一つに記載の半導体回路であって、前記ノイズ対策手段(23)はフィルタである。   A semiconductor circuit according to a fifteenth aspect of the present invention is the semiconductor circuit according to any one of the eleventh to fourteenth aspects, wherein the noise countermeasure means (23) is a filter.

この発明の請求項16にかかる半導体回路は、請求項11記載の半導体回路であって、前記基板(21)上に搭載される第2のノイズ対策手段(231)を更に有し、前記基板(21)は、前記集積回路群(22)が搭載される第1層基板(31)と、前記第1層基板に対して内層であって、互いに異なる固定電位が供給されるパターンが形成される複数の第2層基板(32,33)とを含む多層積層基板であって、前記第2のノイズ対策手段を介して前記集積回路群と前記固定電位が供給される前記パターンとが接続される。   A semiconductor circuit according to a sixteenth aspect of the present invention is the semiconductor circuit according to the eleventh aspect, further comprising second noise countermeasure means (231) mounted on the substrate (21). 21) includes a first layer substrate (31) on which the integrated circuit group (22) is mounted and a pattern that is an inner layer with respect to the first layer substrate and that is supplied with different fixed potentials. A multilayer laminated substrate including a plurality of second layer substrates (32, 33), wherein the integrated circuit group and the pattern to which the fixed potential is supplied are connected via the second noise countermeasure means. .

この発明の請求項17にかかる半導体回路は、請求項16記載の半導体回路であって、前記ノイズ対策手段(23)は、前記固定電位が供給される前記パターンと接続される。   A semiconductor circuit according to a seventeenth aspect of the present invention is the semiconductor circuit according to the sixteenth aspect, wherein the noise countermeasure means (23) is connected to the pattern to which the fixed potential is supplied.

この発明の請求項18にかかる半導体回路は、請求項16または請求項17記載の半導体回路であって、前記ノイズ対策手段(23)及び前記第2のノイズ対策手段(231)は、前記集積回路群(22)から発生するノイズの高周波成分を減衰させる。   A semiconductor circuit according to an eighteenth aspect of the present invention is the semiconductor circuit according to the sixteenth or seventeenth aspect, wherein the noise countermeasure means (23) and the second noise countermeasure means (231) are the integrated circuit. A high frequency component of noise generated from the group (22) is attenuated.

この発明の請求項19にかかる半導体回路は、請求項16乃至請求項18のいずれか一つに記載の半導体回路であって、前記ノイズ対策手段(23)及び前記第2のノイズ対策手段(231)はフィルタである。   A semiconductor circuit according to a nineteenth aspect of the present invention is the semiconductor circuit according to any one of the sixteenth to eighteenth aspects, wherein the noise countermeasure means (23) and the second noise countermeasure means (231). ) Is a filter.

この発明の請求項20にかかる半導体回路は、請求項11乃至請求項19のいずれか一つに記載の半導体回路であって、前記集積回路(221)は高速スイッチング素子を含む。   A semiconductor circuit according to a twentieth aspect of the present invention is the semiconductor circuit according to any one of the eleventh to nineteenth aspects, wherein the integrated circuit (221) includes a high-speed switching element.

この発明の請求項1にかかる半導体回路基板によれば、ノイズ発生源となる集積回路を含む集積回路群と、制御基板とを分離することにより、ノイズ対策手段によるノイズ除去で制御基板へのノイズの伝搬が低減される。しかも、ノイズ対策手段が施された半導体回路を後付けして、半導体回路基板を設計することができるので、半導体回路基板に対してノイズ対策を効率良く行うことができ、開発コストも低減される。   According to the semiconductor circuit board of claim 1 of the present invention, by separating the integrated circuit group including the integrated circuit serving as a noise generation source from the control board, noise to the control board can be removed by noise removal by the noise countermeasure means. Propagation is reduced. In addition, since the semiconductor circuit board can be designed by retrofitting the semiconductor circuit to which the noise countermeasure means is applied, the noise countermeasure can be efficiently performed on the semiconductor circuit board, and the development cost is reduced.

この発明の請求項2にかかる半導体回路基板によれば、集積回路群で発生したノイズが、制御基板へと至る前に、ノイズ対策手段によりその伝搬が妨げられる。   According to the semiconductor circuit board of claim 2 of the present invention, the noise generated in the integrated circuit group is prevented from propagating by the noise countermeasure means before reaching the control board.

この発明の請求項3にかかる半導体回路基板によれば、半導体回路で発生するノイズの周波数が高周波側へとシフトする。よって、ノイズ対策手段が除去する対象は、ノイズの高周波成分とすれば足りる。よって、ノイズ対策手段の設計が容易となる。   According to the semiconductor circuit substrate of the third aspect of the present invention, the frequency of noise generated in the semiconductor circuit is shifted to the high frequency side. Therefore, it is sufficient that the noise removal means removes a high-frequency component of noise. Therefore, the noise countermeasure means can be easily designed.

この発明の請求項4にかかる半導体回路基板によれば、半導体回路から高周波ノイズが伝搬しない。   According to the semiconductor circuit substrate of the fourth aspect of the present invention, high frequency noise does not propagate from the semiconductor circuit.

この発明の請求項5にかかる半導体回路基板によれば、フィルタはノイズを除去することができるので、請求項1乃至請求項4のいずれか一つに記載の態様で用いることができる。   According to the semiconductor circuit substrate of claim 5 of the present invention, the filter can remove noise, and therefore can be used in the aspect described in any one of claims 1 to 4.

この発明の請求項6にかかる半導体回路基板によれば、半導体回路で発生するノイズの周波数が高周波側へとシフトする。よって、ノイズ対策手段及び第2のノイズ対策手段が除去する対象は、ノイズの高周波成分とすれば足りる。よって、ノイズ対策手段の設計が容易となる。また、第2のノイズ対策手段により、集積回路群から、固定電位が供給されるパターンへのノイズの伝搬が更に低減される。   According to the semiconductor circuit board of the sixth aspect of the present invention, the frequency of noise generated in the semiconductor circuit is shifted to the high frequency side. Therefore, the object to be removed by the noise countermeasure means and the second noise countermeasure means may be a high frequency component of noise. Therefore, the noise countermeasure means can be easily designed. Further, the second noise countermeasure means further reduces the noise propagation from the integrated circuit group to the pattern to which the fixed potential is supplied.

この発明の請求項7にかかる半導体回路基板によれば、固定電位が供給されるパターンから制御基板へのノイズの伝搬が低減される。   According to the semiconductor circuit board of claim 7 of the present invention, noise propagation from the pattern to which the fixed potential is supplied to the control board is reduced.

この発明の請求項8にかかる半導体回路基板によれば、半導体回路で、ノイズの周波数を高周波側へとシフトさせ、ノイズ対策手段及び第2のノイズ対策手段でノイズの高周波成分を減衰させ、半導体回路からのノイズ伝搬が抑制される。   According to the semiconductor circuit board of claim 8 of the present invention, in the semiconductor circuit, the frequency of the noise is shifted to the high frequency side, and the high frequency component of the noise is attenuated by the noise countermeasure means and the second noise countermeasure means. Noise propagation from the circuit is suppressed.

この発明の請求項9にかかる半導体回路基板によれば、フィルタはノイズを除去することができるので、請求項6乃至請求項8のいずれか一つに記載の態様で用いることができる。   According to the semiconductor circuit substrate of the ninth aspect of the present invention, the filter can remove noise, and therefore can be used in the aspect described in any one of the sixth to eighth aspects.

この発明の請求項10にかかる半導体回路基板によれば、高速スイッチング素子はノイズ発生源となるので、請求項1乃至請求項9のいずれか一つに記載の態様で用いることができる。   According to the semiconductor circuit board of the tenth aspect of the present invention, the high-speed switching element serves as a noise generation source, so that it can be used in any one of the first to ninth aspects.

この発明の請求項11にかかる半導体回路によれば、ノイズ発生源となる集積回路を含む集積回路群と、制御基板とを分離することにより、ノイズ対策手段によるノイズ除去で制御基板へのノイズの伝搬が低減される。しかも、接続されるべき制御基板を種々採用しつつも、当該制御基板にノイズ対策は不要である。よって、半導体回路を後付けして、例えば半導体回路基板を設計する態様で用いることができる。   According to the semiconductor circuit of the eleventh aspect of the present invention, by separating the integrated circuit group including the integrated circuit serving as a noise generation source and the control board, noise removal to the control board can be performed by noise removal by the noise countermeasure means. Propagation is reduced. Moreover, while adopting various control boards to be connected, noise countermeasures are not required for the control boards. Therefore, the semiconductor circuit can be retrofitted and used, for example, in a mode of designing a semiconductor circuit substrate.

この発明の請求項12にかかる半導体回路によれば、集積回路群で発生したノイズが、制御基板へと至る前に、ノイズ対策手段によりその伝搬が妨げられる。   According to the semiconductor circuit of the twelfth aspect of the present invention, the noise generated in the integrated circuit group is prevented from propagating by the noise countermeasure means before reaching the control board.

この発明の請求項13にかかる半導体回路によれば、半導体回路で発生するノイズの周波数が高周波側へとシフトする。よって、ノイズ対策手段が除去する対象は、ノイズの高周波成分とすれば足りる。よって、ノイズ対策手段の設計が容易となる。   According to the semiconductor circuit of the thirteenth aspect of the present invention, the frequency of noise generated in the semiconductor circuit is shifted to the high frequency side. Therefore, it is sufficient that the noise removal means removes a high-frequency component of noise. Therefore, the noise countermeasure means can be easily designed.

この発明の請求項14にかかる半導体回路によれば、半導体回路から高周波ノイズが伝搬しない。   According to the semiconductor circuit of the fourteenth aspect of the present invention, high frequency noise does not propagate from the semiconductor circuit.

この発明の請求項15にかかる半導体回路によれば、フィルタはノイズを除去することができるので、請求項11乃至請求項14のいずれか一つに記載の態様で用いることができる。   According to the semiconductor circuit of the fifteenth aspect of the present invention, since the filter can remove noise, the filter can be used in any one of the eleventh to fourteenth aspects.

この発明の請求項16にかかる半導体回路によれば、半導体回路で発生するノイズの周波数が高周波側へとシフトする。よって、ノイズ対策手段及び第2のノイズ対策手段が除去する対象は、ノイズの高周波成分とすれば足りる。よって、ノイズ対策手段の設計が容易となる。また、第2のノイズ対策手段により、集積回路群から、固定電位が供給されるパターンへのノイズの伝搬が更に低減される。   According to the semiconductor circuit of the sixteenth aspect of the present invention, the frequency of noise generated in the semiconductor circuit is shifted to the high frequency side. Therefore, the object to be removed by the noise countermeasure means and the second noise countermeasure means may be a high frequency component of noise. Therefore, the noise countermeasure means can be easily designed. Further, the second noise countermeasure means further reduces the noise propagation from the integrated circuit group to the pattern to which the fixed potential is supplied.

この発明の請求項17にかかる半導体回路によれば、固定電位が供給されるパターンから制御基板へのノイズの伝搬が低減される。   According to the semiconductor circuit of the seventeenth aspect of the present invention, the propagation of noise from the pattern to which the fixed potential is supplied to the control board is reduced.

この発明の請求項18にかかる半導体回路によれば、半導体回路で、ノイズの周波数を高周波側へとシフトさせ、ノイズ対策手段及び第2のノイズ対策手段でノイズの高周波成分を減衰させ、半導体回路からのノイズ伝搬が抑制される。   According to the semiconductor circuit of the eighteenth aspect of the present invention, in the semiconductor circuit, the frequency of the noise is shifted to the high frequency side, and the high frequency component of the noise is attenuated by the noise countermeasure means and the second noise countermeasure means. Noise propagation from the is suppressed.

この発明の請求項19にかかる半導体回路によれば、フィルタはノイズを除去することができるので、請求項16乃至請求項18のいずれか一つに記載の態様で用いることができる。   According to the semiconductor circuit of the nineteenth aspect of the present invention, since the filter can remove noise, the filter can be used in any one of the sixteenth to eighteenth aspects.

この発明の請求項20にかかる半導体回路によれば、高速スイッチング素子はノイズ発生源となるので、請求項1乃至請求項9のいずれか一つに記載の態様で用いることができる。   According to the semiconductor circuit of the twentieth aspect of the present invention, the high-speed switching element serves as a noise generation source, and therefore can be used in the aspect described in any one of the first to ninth aspects.

図1は、本発明にかかる半導体回路基板の構造を概念的に示す斜視図である。半導体回路基板は、制御基板1と、当該制御基板1に接続される半導体回路2とを備える。制御基板1は、例えばマイクロプロセッサを有し、半導体回路2を制御する。半導体回路2は、基板21、集積回路群22及びノイズ対策手段23,231を有し、制御基板1から分離して構成される。集積回路群22及びノイズ対策手段23,231は、基板21上に搭載される。   FIG. 1 is a perspective view conceptually showing the structure of a semiconductor circuit board according to the present invention. The semiconductor circuit board includes a control board 1 and a semiconductor circuit 2 connected to the control board 1. The control board 1 has a microprocessor, for example, and controls the semiconductor circuit 2. The semiconductor circuit 2 includes a substrate 21, an integrated circuit group 22, and noise countermeasure means 23 and 231, and is configured separately from the control substrate 1. The integrated circuit group 22 and the noise countermeasure means 23 and 231 are mounted on the substrate 21.

集積回路群22は、ノイズ発生源となる集積回路、例えば高速スイッチング素子221を含む。その他、送信/受信回路222等の他の集積回路を含んでもよい。上記したように半導体回路2は制御基板1から分離して構成されるので、集積回路群22も制御基板1から分離して構成される。   The integrated circuit group 22 includes an integrated circuit that becomes a noise generation source, for example, a high-speed switching element 221. In addition, other integrated circuits such as the transmission / reception circuit 222 may be included. Since the semiconductor circuit 2 is configured separately from the control board 1 as described above, the integrated circuit group 22 is also configured separately from the control board 1.

図2は、基板21の構成を示す斜視図である。基板21は、多層積層基板であって、基板31,32,33,34をこの順に積層して有する。図2では、各基板に形成されるパターンが明確になるように、便宜的に各基板が積層方向に分離して示されている。   FIG. 2 is a perspective view showing the configuration of the substrate 21. The board | substrate 21 is a multilayer laminated board, Comprising: The board | substrates 31, 32, 33, and 34 are laminated | stacked in this order. In FIG. 2, for the sake of convenience, each substrate is shown separated in the stacking direction so that the pattern formed on each substrate is clear.

基板31は、基板21の最外層であり、集積回路群22及びノイズ対策手段23,231が搭載されている。基板31には、集積回路群2以外の回路が形成されてもよい。また、ノイズ対策手段23、231は、そのいずれか一方もしくは両方が、基板34に搭載されてもよい。   The substrate 31 is the outermost layer of the substrate 21 and has the integrated circuit group 22 and noise countermeasure means 23 and 231 mounted thereon. Circuits other than the integrated circuit group 2 may be formed on the substrate 31. In addition, one or both of the noise countermeasure units 23 and 231 may be mounted on the substrate 34.

基板32,33は、基板21に対して内層であり、互いに異なる固定電位が供給されるパターンがそれぞれ形成され、例えば相互に隣接する。図2では、当該パターンが、基板31側の基板32,33の表面にそれぞれ形成されている。基板32に形成されるパターンは、例えばグランドに接続され、基板33に形成されるパターンは、例えば外部電源に接続される。   The substrates 32 and 33 are inner layers with respect to the substrate 21 and are respectively formed with patterns to which different fixed potentials are supplied, and are adjacent to each other, for example. In FIG. 2, the pattern is formed on the surfaces of the substrates 32 and 33 on the substrate 31 side. The pattern formed on the substrate 32 is connected to, for example, the ground, and the pattern formed on the substrate 33 is connected to, for example, an external power source.

各基板は積層されるので、各基板に形成された回路は相互に接続されて、基板21は、通信機能等の所定の機能を有する。   Since the substrates are stacked, the circuits formed on the substrates are connected to each other, and the substrate 21 has a predetermined function such as a communication function.

上述した多層積層基板によれば、基板32,33に形成されるパターンを電極として、その電極が絶縁層を挟みこんでコンデンサが形成される。これにより、例えば高速スイッチング素子221で発生したノイズを高周波側へとシフトすることができる。よって、ノイズ対策手段23,231が除去する対象は、ノイズの高周波成分とすれば足りるので、ノイズ対策手段23,231の設計が容易となる。   According to the multilayer laminated substrate described above, a capacitor is formed by using the pattern formed on the substrates 32 and 33 as an electrode and sandwiching the insulating layer between the electrode. Thereby, for example, noise generated in the high-speed switching element 221 can be shifted to the high frequency side. Therefore, the noise countermeasure means 23, 231 need only be a high-frequency component of noise, so that the noise countermeasure means 23, 231 can be easily designed.

たとえ基板21が多層積層基板でないとしても、ノイズ対策手段23,231によって、半導体回路2からの高周波ノイズの伝搬が抑制される。   Even if the substrate 21 is not a multilayer laminated substrate, the noise countermeasures 23 and 231 suppress the propagation of high-frequency noise from the semiconductor circuit 2.

図3は、図1及び図2で示される半導体回路基板を概念的に示すブロック図である。ノイズ対策手段23は、例えばフェライトビーズやチップインダクタであって、集積回路群22と制御基板1との間に接続される。図3では、集積回路群22のうち高速スイッチング素子221がノイズ対策手段23に接続されている。ノイズ対策手段23を介して高速スイッチング素子221と制御基板1とを接続する配線は、たとえば信号線111と電源線112を含む。   FIG. 3 is a block diagram conceptually showing the semiconductor circuit substrate shown in FIGS. The noise countermeasure means 23 is, for example, a ferrite bead or a chip inductor, and is connected between the integrated circuit group 22 and the control board 1. In FIG. 3, the high-speed switching element 221 in the integrated circuit group 22 is connected to the noise countermeasure means 23. The wiring connecting the high-speed switching element 221 and the control board 1 via the noise countermeasure means 23 includes, for example, a signal line 111 and a power line 112.

ノイズ対策手段23は、上記したように基板21が多層積層基板である場合には、特にノイズの高周波を減衰させるフィルタであれば足りる。そして、ノイズ対策手段23は、集積回路群22と制御基板1との間に接続されるので、集積回路群22で発生したノイズは制御基板1へと至る前に除去される。換言すれば、半導体回路2からの低周波ノイズの発生を抑制しつつも、半導体回路2からの高周波ノイズの伝搬が妨げられる。   As described above, when the substrate 21 is a multi-layer laminated substrate, the noise countermeasure unit 23 may be a filter that attenuates high frequency noise. Since the noise countermeasure means 23 is connected between the integrated circuit group 22 and the control board 1, noise generated in the integrated circuit group 22 is removed before reaching the control board 1. In other words, the propagation of the high frequency noise from the semiconductor circuit 2 is hindered while the generation of the low frequency noise from the semiconductor circuit 2 is suppressed.

ノイズ対策手段231は、例えばフェライトビーズやチップインダクタ等のフィルタであって、集積回路群22と、基板32上に形成される固定電位が供給されるパターンとの間に接続される。図3では、集積回路群22のうち高速スイッチング素子221がノイズ対策手段231に配線114により接続されている。また、基板32上に形成される固定電位が供給されるパターンが、符号113を用いて示されている。   The noise countermeasure means 231 is a filter such as a ferrite bead or a chip inductor, for example, and is connected between the integrated circuit group 22 and a pattern to be supplied with a fixed potential formed on the substrate 32. In FIG. 3, the high-speed switching element 221 in the integrated circuit group 22 is connected to the noise countermeasure means 231 by the wiring 114. A pattern supplied with a fixed potential formed on the substrate 32 is indicated by reference numeral 113.

また、ノイズ対策手段23は、基板32上に形成される固定電位が供給されるパターンに接続される。   Further, the noise countermeasure means 23 is connected to a pattern formed on the substrate 32 and supplied with a fixed potential.

図2では、ノイズ対策手段23,231が、基板32上に形成される固定電位が供給されるパターンに接続されることが、破線によって示されている。   In FIG. 2, the broken line indicates that the noise countermeasure means 23 and 231 are connected to a pattern formed on the substrate 32 and supplied with a fixed potential.

ノイズ対策手段231についても、上記したように基板21が多層積層基板である場合には、特にノイズの高周波を減衰させるフィルタであれば足りる。そして、ノイズ対策手段231は、集積回路群22と固定電位が供給されるパターンとの間に接続されるので、当該パターンへのノイズの伝搬を低減する。   As the noise countermeasure means 231, when the substrate 21 is a multilayer laminated substrate as described above, a filter that attenuates the high frequency of noise is sufficient. And since the noise countermeasure means 231 is connected between the integrated circuit group 22 and the pattern to which the fixed potential is supplied, the noise propagation to the pattern is reduced.

上述の内容によれば、ノイズ発生源となる高速スイッチング素子221を含む集積回路群22と、制御基板1とを分離することにより、ノイズ対策手段23によるノイズ除去で制御基板1への高周波ノイズの伝搬が低減できる。更に、基板21に上述の構成の多層積層基板を採用することにより、半導体回路2での低周波ノイズの発生も低減できる。しかも、ノイズ対策手段が施された半導体回路2を後付けして、半導体回路基板を設計することができるので、半導体回路基板に対してノイズ対策を効率良く行うことができ、開発コストも低減される。   According to the above-described content, the integrated circuit group 22 including the high-speed switching element 221 serving as a noise generation source is separated from the control board 1, so that noise removal by the noise countermeasure unit 23 removes high-frequency noise to the control board 1. Propagation can be reduced. Furthermore, the use of the multilayer laminated substrate having the above-described configuration as the substrate 21 can reduce the occurrence of low-frequency noise in the semiconductor circuit 2. In addition, since the semiconductor circuit board can be designed by retrofitting the semiconductor circuit 2 provided with noise countermeasure means, noise countermeasures can be efficiently performed on the semiconductor circuit board, and the development cost can be reduced. .

本実施の形態では、制御基板1と半導体回路2とを備える半導体回路基板について説明したが、半導体回路2が単独で構成されてもよい。この場合、半導体回路2は、半導体回路2を制御可能な外部回路、例えば制御基板1に接続可能である。よって、半導体回路2は、後付けして例えば半導体回路基板を設計する態様で用いることができる。   In the present embodiment, the semiconductor circuit board including the control board 1 and the semiconductor circuit 2 has been described. However, the semiconductor circuit 2 may be configured alone. In this case, the semiconductor circuit 2 can be connected to an external circuit that can control the semiconductor circuit 2, for example, the control board 1. Therefore, the semiconductor circuit 2 can be used in a mode of retrofitting and designing a semiconductor circuit substrate, for example.

本発明にかかる半導体回路基板を概念的に示す斜視図である。1 is a perspective view conceptually showing a semiconductor circuit board according to the present invention. 多層積層基板である基板21を概念的に示す斜視図である。It is a perspective view which shows notionally the board | substrate 21 which is a multilayer laminated substrate. 半導体回路基板を概念的に示すブロック図である。1 is a block diagram conceptually showing a semiconductor circuit board.

符号の説明Explanation of symbols

1 制御基板
2 半導体回路
21 基板
22 集積回路群
23,231 ノイズ対策手段
31〜33 基板
221 高速スイッチング素子(集積回路)
DESCRIPTION OF SYMBOLS 1 Control board 2 Semiconductor circuit 21 Board | substrate 22 Integrated circuit group 23,231 Noise countermeasure means 31-33 Board | substrate 221 High-speed switching element (integrated circuit)

Claims (20)

制御基板(1)と、
前記制御基板に接続される半導体回路(2)と
を備え、
前記半導体回路は、
基板(21)と、
前記基板上に搭載される集積回路群(22)と、
前記基板上に搭載されるノイズ対策手段(23)と
を有し、
前記集積回路群は、ノイズ発生源となる集積回路(221)を含み、前記制御基板から分離して構成される、半導体回路基板。
A control board (1);
A semiconductor circuit (2) connected to the control board,
The semiconductor circuit is:
A substrate (21);
An integrated circuit group (22) mounted on the substrate;
Noise countermeasure means (23) mounted on the substrate,
The integrated circuit group includes a semiconductor circuit board including an integrated circuit (221) serving as a noise generation source and separated from the control board.
前記ノイズ対策手段(23)を介して前記集積回路群(22)と前記制御基板(1)とが接続される、請求項1記載の半導体回路基板。   The semiconductor circuit board according to claim 1, wherein the integrated circuit group (22) and the control board (1) are connected via the noise countermeasure means (23). 前記基板(21)は、
前記集積回路群(22)が搭載される第1層基板(31)と、
前記第1層基板に対して内層であって、互いに異なる固定電位が供給されるパターンが形成される複数の第2層基板(32,33)と
を含む多層積層基板である、請求項1または請求項2記載の半導体回路基板。
The substrate (21)
A first layer substrate (31) on which the integrated circuit group (22) is mounted;
The multi-layer laminated substrate including a plurality of second layer substrates (32, 33) which are inner layers with respect to the first layer substrate and are formed with patterns to which different fixed potentials are supplied. The semiconductor circuit board according to claim 2.
前記ノイズ対策手段(23)は、前記集積回路群(22)から発生するノイズの高周波成分を減衰させる、請求項1乃至請求項3記載のいずれか一つに記載の半導体回路基板。   The semiconductor circuit board according to any one of claims 1 to 3, wherein the noise countermeasure means (23) attenuates a high-frequency component of noise generated from the integrated circuit group (22). 前記ノイズ対策手段(23)はフィルタである、請求項1乃至請求項4のいずれか一つに記載の半導体回路基板。   The semiconductor circuit board according to any one of claims 1 to 4, wherein the noise countermeasure means (23) is a filter. 前記半導体回路は、
前記基板(21)上に搭載される第2のノイズ対策手段(231)を
更に有し、
前記基板(21)は、
前記集積回路群(22)が搭載される第1層基板(31)と、
前記第1層基板に対して内層であって、互いに異なる固定電位が供給されるパターンが形成される複数の第2層基板(32,33)と
を含む多層積層基板であって、
前記第2のノイズ対策手段を介して前記集積回路群と前記固定電位が供給される前記パターンとが接続される、請求項1記載の半導体回路基板。
The semiconductor circuit is:
Further comprising second noise countermeasure means (231) mounted on the substrate (21);
The substrate (21)
A first layer substrate (31) on which the integrated circuit group (22) is mounted;
A multi-layer laminated substrate including a plurality of second layer substrates (32, 33) which are inner layers with respect to the first layer substrate and are formed with patterns to which different fixed potentials are supplied;
The semiconductor circuit substrate according to claim 1, wherein the integrated circuit group and the pattern to which the fixed potential is supplied are connected via the second noise countermeasure unit.
前記ノイズ対策手段(23)は、前記固定電位が供給される前記パターンと接続される、請求項6記載の半導体回路基板。   The semiconductor circuit board according to claim 6, wherein the noise countermeasure means is connected to the pattern to which the fixed potential is supplied. 前記ノイズ対策手段(23)及び前記第2のノイズ対策手段(231)は、前記集積回路群(22)から発生するノイズの高周波成分を減衰させる、請求項6または請求項7記載の半導体回路基板。   The semiconductor circuit board according to claim 6 or 7, wherein the noise countermeasure means (23) and the second noise countermeasure means (231) attenuate high-frequency components of noise generated from the integrated circuit group (22). . 前記ノイズ対策手段(23)及び前記第2のノイズ対策手段(231)はフィルタである、請求項6乃至請求項8のいずれか一つに記載の半導体回路基板。   9. The semiconductor circuit board according to claim 6, wherein the noise countermeasure means (23) and the second noise countermeasure means (231) are filters. 前記集積回路(221)は高速スイッチング素子を含む、請求項1乃至請求項9のいずれか一つに記載の半導体回路基板。   The semiconductor circuit substrate according to any one of claims 1 to 9, wherein the integrated circuit (221) includes a high-speed switching element. 制御基板(1)に接続可能な半導体回路(2)であって、
基板(21)と、
前記基板上に搭載される集積回路群(22)と、
前記基板上に搭載されるノイズ対策手段(23)と
を有し、
前記集積回路群は、ノイズ発生源となる集積回路(221)を含み、前記制御基板から分離して構成される、半導体回路。
A semiconductor circuit (2) connectable to the control board (1),
A substrate (21);
An integrated circuit group (22) mounted on the substrate;
Noise countermeasure means (23) mounted on the substrate,
The integrated circuit group includes an integrated circuit (221) serving as a noise generation source, and is configured to be separated from the control board.
前記ノイズ対策手段(23)を介して前記集積回路群(22)と前記制御基板(1)とが接続可能である、請求項11記載の半導体回路。   12. The semiconductor circuit according to claim 11, wherein the integrated circuit group (22) and the control board (1) are connectable via the noise countermeasure means (23). 前記基板(21)は、
前記集積回路群(22)が搭載される第1層基板(31)と、
前記第1層基板に対して内層であって、互いに異なる固定電位が供給されるパターンが形成される複数の第2層基板(32,33)と
を含む多層積層基板である、請求項11または請求項12記載の半導体回路。
The substrate (21)
A first layer substrate (31) on which the integrated circuit group (22) is mounted;
The multi-layer laminated substrate including a plurality of second layer substrates (32, 33) which are inner layers with respect to the first layer substrate and are formed with patterns to which different fixed potentials are supplied. The semiconductor circuit according to claim 12.
前記ノイズ対策手段(23)は、前記集積回路群(22)から発生するノイズの高周波成分を減衰させる、請求項11乃至請求項13記載のいずれか一つに記載の半導体回路。   The semiconductor circuit according to any one of claims 11 to 13, wherein the noise countermeasure means (23) attenuates a high-frequency component of noise generated from the integrated circuit group (22). 前記ノイズ対策手段(23)はフィルタである、請求項11乃至請求項14のいずれか一つに記載の半導体回路。   15. The semiconductor circuit according to claim 11, wherein the noise countermeasure means (23) is a filter. 前記基板(21)上に搭載される第2のノイズ対策手段(231)を
更に有し、
前記基板(21)は、
前記集積回路群(22)が搭載される第1層基板(31)と、
前記第1層基板に対して内層であって、互いに異なる固定電位が供給されるパターンが形成される複数の第2層基板(32,33)と
を含む多層積層基板であって、
前記第2のノイズ対策手段を介して前記集積回路群と前記固定電位が供給される前記パターンとが接続される、請求項11記載の半導体回路。
Further comprising second noise countermeasure means (231) mounted on the substrate (21);
The substrate (21)
A first layer substrate (31) on which the integrated circuit group (22) is mounted;
A multi-layer laminated substrate including a plurality of second layer substrates (32, 33) which are inner layers with respect to the first layer substrate and are formed with patterns to which different fixed potentials are supplied;
The semiconductor circuit according to claim 11, wherein the integrated circuit group and the pattern to which the fixed potential is supplied are connected via the second noise countermeasure unit.
前記ノイズ対策手段(23)は、前記固定電位が供給される前記パターンと接続される、請求項16記載の半導体回路。   17. The semiconductor circuit according to claim 16, wherein the noise countermeasure means (23) is connected to the pattern to which the fixed potential is supplied. 前記ノイズ対策手段(23)及び前記第2のノイズ対策手段(231)は、前記集積回路群(22)から発生するノイズの高周波成分を減衰させる、請求項16または請求項17記載の半導体回路。   18. The semiconductor circuit according to claim 16, wherein the noise countermeasure means (23) and the second noise countermeasure means (231) attenuate high frequency components of noise generated from the integrated circuit group (22). 前記ノイズ対策手段(23)及び前記第2のノイズ対策手段(231)はフィルタである、請求項16乃至請求項18のいずれか一つに記載の半導体回路。   19. The semiconductor circuit according to claim 16, wherein the noise countermeasure means (23) and the second noise countermeasure means (231) are filters. 前記集積回路(221)は高速スイッチング素子を含む、請求項11乃至請求項19のいずれか一つに記載の半導体回路。
20. The semiconductor circuit according to any one of claims 11 to 19, wherein the integrated circuit (221) includes a high speed switching element.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007102366A2 (en) 2006-03-01 2007-09-13 Daikin Industries, Ltd. Device and connecting method
JP2009099876A (en) * 2007-10-19 2009-05-07 Yokogawa Electric Corp Shield case unit

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09232790A (en) * 1996-02-26 1997-09-05 Fuji Electric Co Ltd Shield of circuit on printed board
JPH1154861A (en) * 1997-08-04 1999-02-26 Sony Corp Wiring board
JPH11261180A (en) * 1998-03-11 1999-09-24 Murata Mfg Co Ltd Electro-magnetic shielding circuit board and electronic equipment using the same
JP2001102789A (en) * 1999-09-30 2001-04-13 Toshiba Corp High-frequency shield circuit structure
JP2002076537A (en) * 2000-08-23 2002-03-15 Otari Kk Printed wiring board reduced in electromagnetic interference and electronic equipment using it
JP2002184933A (en) * 2000-12-15 2002-06-28 Mitsubishi Electric Corp Semiconductor device
JP2003163466A (en) * 2001-11-29 2003-06-06 Sharp Corp Multilayer printed circuit board and multilayer printed circuit board device provided with the printed circuit board

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09232790A (en) * 1996-02-26 1997-09-05 Fuji Electric Co Ltd Shield of circuit on printed board
JPH1154861A (en) * 1997-08-04 1999-02-26 Sony Corp Wiring board
JPH11261180A (en) * 1998-03-11 1999-09-24 Murata Mfg Co Ltd Electro-magnetic shielding circuit board and electronic equipment using the same
JP2001102789A (en) * 1999-09-30 2001-04-13 Toshiba Corp High-frequency shield circuit structure
JP2002076537A (en) * 2000-08-23 2002-03-15 Otari Kk Printed wiring board reduced in electromagnetic interference and electronic equipment using it
JP2002184933A (en) * 2000-12-15 2002-06-28 Mitsubishi Electric Corp Semiconductor device
JP2003163466A (en) * 2001-11-29 2003-06-06 Sharp Corp Multilayer printed circuit board and multilayer printed circuit board device provided with the printed circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007102366A2 (en) 2006-03-01 2007-09-13 Daikin Industries, Ltd. Device and connecting method
US8013691B2 (en) 2006-03-01 2011-09-06 Daikin Industries, Ltd. Device and connecting method for connecting power-supply terminals to a power-supply bus based on noise intensities
JP2009099876A (en) * 2007-10-19 2009-05-07 Yokogawa Electric Corp Shield case unit

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