JP4671333B2 - Multilayer printed circuit board and electronic equipment - Google Patents

Multilayer printed circuit board and electronic equipment Download PDF

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JP4671333B2
JP4671333B2 JP2005078497A JP2005078497A JP4671333B2 JP 4671333 B2 JP4671333 B2 JP 4671333B2 JP 2005078497 A JP2005078497 A JP 2005078497A JP 2005078497 A JP2005078497 A JP 2005078497A JP 4671333 B2 JP4671333 B2 JP 4671333B2
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circuit board
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昌朗 白橋
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Ricoh Co Ltd
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Description

本発明は、電子機器に用いられる多層プリント回路基板に係わり、特に、放射ノイズを低減した高品質な多層プリント回路基板とそれを用いた電子機器に関するものである。   The present invention relates to a multilayer printed circuit board used for electronic equipment, and more particularly to a high quality multilayer printed circuit board with reduced radiation noise and an electronic equipment using the same.

近年の電子機器の小型化に伴い、電子機器に搭載されるプリント回路基板に形成される回路が高密度化し、その動作が高速化している。その結果、プリント回路基板から放出される電磁波が、周囲の電子機器の動作に悪影響を及ぼす電磁波妨害(EMI)が問題となっている。   With the recent miniaturization of electronic devices, the density of circuits formed on a printed circuit board mounted on the electronic devices has increased, and the operation has been accelerated. As a result, electromagnetic interference (EMI), in which electromagnetic waves emitted from the printed circuit board adversely affect the operation of surrounding electronic devices, is a problem.

例えば、特許文献1に記載のように、ICやLSIなどの集積回路素子が搭載されたプリント回路基板を有する電子機器では、搭載されている集積回路素子の高速スイッチング動作に伴ってながれる高周波電流が、電磁ノイズを発生することは良く知られている。   For example, as described in Patent Document 1, in an electronic apparatus having a printed circuit board on which an integrated circuit element such as an IC or LSI is mounted, a high-frequency current flowing along with a high-speed switching operation of the mounted integrated circuit element is high. It is well known that electromagnetic noise is generated.

プリント基板が発生する電磁ノイズは、その低減のため適切な処置を行わないと、そのプリント基板を含む電子機器自身に、あるいは、他の電子機器における誤動作の原因となり得る。   Electromagnetic noise generated by a printed circuit board may cause malfunctions in the electronic device including the printed circuit board or in other electronic devices unless appropriate measures are taken to reduce the electromagnetic noise.

このような電磁ノイズの中で、特に大きく比重を占めるのは、コモンモードノイズだと言われる、回路の寄生容量や寄生相互インダクタンスによって流れる電流や電源供給線に流れ込む高周波電流による放射である。   Among such electromagnetic noises, what occupies a large specific gravity is radiation caused by a high-frequency current flowing into a power supply line or a current flowing due to circuit parasitic capacitance or parasitic mutual inductance, which is said to be common mode noise.

これらの電磁ノイズに対しては、その発生機構が複雑なため、その発生源に近い場所での有効な対策方法がなかった。そのため、従来は、この種の電磁ノイズに対し、電子機器全体を金属個体で覆って電磁遮断を行う対策がとられている。   For these electromagnetic noises, the mechanism for their generation is complicated, so there has been no effective countermeasures at locations close to their sources. For this reason, conventionally, countermeasures have been taken against electromagnetic interference of this type by covering the entire electronic device with a metal object.

また、高周波電源電流による放射とグランド層と電源層のプレーン共振によるノイズ発生を防ぐために、その発生源であるLSIなどの回路素子の近傍にデカップリングコンデンサを配置することがよく行われている。   In order to prevent radiation due to high-frequency power supply current and noise generation due to plane resonance between the ground layer and the power supply layer, a decoupling capacitor is often disposed in the vicinity of a circuit element such as an LSI that is the generation source.

これは、プリント基板に搭載されたIC/LSIのスイッチング動作に伴って電源層に流れる高周波電流を、そのIC/LSI近傍でデカップリングコンデンサを介してグランド層にバイパスさせるとともに、IC/LSIのスイッチング動作に伴うIC/LSIの電源端子部の電圧変動を抑制するためのものである。   This is because the high frequency current flowing in the power supply layer in accordance with the switching operation of the IC / LSI mounted on the printed circuit board is bypassed to the ground layer through the decoupling capacitor in the vicinity of the IC / LSI and the switching of the IC / LSI is performed. This is to suppress the voltage fluctuation of the power supply terminal portion of the IC / LSI accompanying the operation.

さらに、グランド層と電源層、および、搭載される集積回路素子から形成されるLC回路の共振周波数で発生する放射ノイズが問題となっている。   Furthermore, there is a problem of radiation noise generated at the resonance frequency of the LC circuit formed from the ground layer, the power supply layer, and the integrated circuit element mounted.

特開2001−24334号公報JP 2001-24334 A

解決しようとする問題点は、従来の技術では、グランド層と電源層、および、搭載される集積回路素子から形成されるLC回路の共振周波数で発生する放射ノイズに対しては有効に対応できない点である。   The problem to be solved is that the conventional technology cannot effectively cope with the radiation noise generated at the resonance frequency of the LC circuit formed from the ground layer, the power supply layer, and the integrated circuit element mounted thereon. It is.

本発明の目的は、これら従来技術の課題を解決し、多層プリント回路基板の品質を向上させることである。   An object of the present invention is to solve these problems of the prior art and improve the quality of a multilayer printed circuit board.

上記目的を達成するため、本発明の多層プリント回路基板は、(1)複数の回路素子を搭載し、グランド層と信号層と回路素子に電源電圧を供給するための電源層とがそれぞれ絶縁材を介して積層された多層プリント回路基板であって、電源層とグランド層とが互いに対向する領域を、回路素子の最高動作周波数の1/4波長以下の長さを一辺とする同一面積の正方形で均等に分割した均等分割領域として形成し、すべての各均等分割領域は、高周波インピーダンスを高めるように且つループを作らないようにパターニングされ、隣接した均等分割領域と接続されることを特徴とする。また(2)均等分割領域と隣接した均等分割領域とを、ローパスフィルタの電子回路部品で接続する構成とすることを特徴とする。 In order to achieve the above object, a multilayer printed circuit board according to the present invention includes: (1) a plurality of circuit elements, and a ground layer, a signal layer, and a power supply layer for supplying a power supply voltage to the circuit elements, respectively; A multilayer printed circuit board laminated with a power source layer and a ground layer facing each other in a square of the same area with one side having a length equal to or less than ¼ wavelength of the maximum operating frequency of the circuit element in forming a uniformly divided areas obtained by equally dividing all the equally divided areas are patterned so as not to create and loop to increase the high frequency impedance is connected to the equally divided areas adjacent to said Rukoto . Or a (2) equally divided area adjacent to the equally divided areas, characterized in that a configuration of connecting with the electronic circuit components of the low-pass filter.

本発明によれば、電源およびグランド層を均等分割することにより、集積回路素子の高速スイッチング動作に伴って流れる高周波電源電流の他の領域への流れ込みを抑え、かつグランド層と電源層および搭載される集積回路素子から形成されるLC回路の共振周波数をEMI規制の対象周波数以上にシフトさせることにより、多層プリント回路基板から発生する放射ノイズを低減することができる。また、回路素子の最高動作周波数の1/4波長以下の長さを一辺とする正方形で分割することにより、集積回路素子の高速スイッチング動作に伴って流れる高周波電源電流により発生する放射ノイズが、共振により増幅されることを防ぐことができ、多層プリント回路基板から発生する放射ノイズを低減することができる。   According to the present invention, the power supply and the ground layer are equally divided to suppress the flow of the high-frequency power supply current that flows along with the high-speed switching operation of the integrated circuit element into other regions, and the ground layer and the power supply layer are mounted. By shifting the resonance frequency of the LC circuit formed from the integrated circuit element to a frequency higher than the target frequency of EMI regulation, radiation noise generated from the multilayer printed circuit board can be reduced. In addition, by dividing the square with a length of 1/4 wavelength or less of the maximum operating frequency of the circuit element into one side, the radiated noise generated by the high frequency power supply current that flows along with the high-speed switching operation of the integrated circuit element is resonant. Can be prevented, and radiation noise generated from the multilayer printed circuit board can be reduced.

以下、図を用いて本発明を実施するための最良の形態例を説明する。図1は、本発明に係わる多層プリント回路基板の断面構成例を示す側断面図であり、図2は、本発明に係わる多層プリント回路基板における均等分割領域の第1の接続構成例を示す上面図、図3は、本発明に係わる多層プリント回路基板における均等分割領域の第2の接続構成例を示す上面図である。   The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a side sectional view showing a cross-sectional configuration example of a multilayer printed circuit board according to the present invention, and FIG. 2 is a top view showing a first connection configuration example of equally divided regions in the multilayer printed circuit board according to the present invention. 3 and 3 are top views showing a second connection configuration example of equally divided regions in the multilayer printed circuit board according to the present invention.

図1に示すように、本例の多層プリント回路基板は、グランド層と信号層および回路素子に電源電圧を供給するための電源層とがそれぞれ絶縁材を介して積層された構成となっている。   As shown in FIG. 1, the multilayer printed circuit board of this example has a configuration in which a ground layer, a signal layer, and a power supply layer for supplying a power supply voltage to circuit elements are laminated via an insulating material. .

このような構成からなる多層プリント回路基板においては、ICやLSIなどの集積回路素子が搭載され、これらの集積回路素子は、電磁放射ノイズの発生源となる。本例では、図2および図3に示す構成とすることで、このような多層プリント回路基板に搭載された集積回路素子から流出する放射ノイズを、電源層で抑制するものである。   In the multilayer printed circuit board having such a configuration, integrated circuit elements such as ICs and LSIs are mounted, and these integrated circuit elements become sources of electromagnetic radiation noise. In this example, the configuration shown in FIGS. 2 and 3 is used to suppress radiation noise flowing out from the integrated circuit element mounted on the multilayer printed circuit board in the power supply layer.

電磁ノイズ放射は、一般にノーマルモードとコモンモードに分割され、その放射エネルギーは、ノーマルモード放射の場合は周波数の2乗の関数として表され、コモンモードノード放射の場合には周波数に比例する。いずれの場合であっても、周波数が高いほど放射レベルが大きくなる。   Electromagnetic noise radiation is generally divided into normal mode and common mode, and its radiant energy is expressed as a function of the square of frequency in the case of normal mode radiation, and is proportional to the frequency in the case of common mode node radiation. In any case, the higher the frequency, the higher the radiation level.

本例の多層プリント回路基板では、電源層およびグランド層(以下、電源層とグランド層を合わせてプレーンと言う)を分割し、分割した各領域を、高周波ノイズが流出しないように接続することで、ノイズの原因となる高周波電源電流を封じ込める。   In the multilayer printed circuit board of this example, the power supply layer and the ground layer (hereinafter, the power supply layer and the ground layer are collectively referred to as a plane) are divided, and the divided areas are connected so that high-frequency noise does not flow out. Contain high-frequency power supply current that causes noise.

このようにプレーンに流入する放射ノイズレベルを抑えることで、ICや、LSIから発生する周波数電源電流の基板外部への流出を阻止することができる。   By suppressing the radiation noise level flowing into the plane in this way, it is possible to prevent the frequency power source current generated from the IC or LSI from flowing out of the substrate.

例えば、図2に示す多層プリント回路基板8においては、プレーン4(電源層とグランド層)は、互いに対向する領域を、同一形状かつ同一面積で均等に分割した均等分割領域で形成され、本図2ではプレーン4は9個の同じ面積に分割されている。   For example, in the multilayer printed circuit board 8 shown in FIG. 2, the plane 4 (the power supply layer and the ground layer) is formed by equally divided regions obtained by equally dividing regions facing each other into the same shape and the same area. In plane 2, plane 4 is divided into nine equal areas.

そして、これら分割された各プレーン4は、同一電源電圧であるので相互に接続されている必要がある。本例では、隣接する領域とは1箇所でのみ接続している。このように1箇所でのみ接続するのは、ノイズを発生させる要因であるループを作らないようにするためであり、高周波ノイズをその1箇所の接続個所でカットするようにしている。   Since the divided planes 4 have the same power supply voltage, they need to be connected to each other. In this example, it is connected only at one place with the adjacent region. In this way, the connection is made only at one place so as not to create a loop that is a factor that generates noise, and high-frequency noise is cut at the one connection place.

図2では、このような接続に、電源配線パターン1を用いている。特に、この電源配線パターン1は、高周波インピーダンスが高いようにパターンニングされている。そのため、一方の領域(プレーン4)に発生した高周波ノイズは、他の接続されている領域(プレーン4)に流れることは無い。   In FIG. 2, the power supply wiring pattern 1 is used for such connection. In particular, the power supply wiring pattern 1 is patterned so as to have a high frequency impedance. Therefore, the high frequency noise generated in one region (plane 4) does not flow to the other connected region (plane 4).

また、図3に示す多層プリント回路基板8aにおいては、プレーン4間を、VIA2を介して、電子回路部品のローパスフィルタ3を用いて接続している。このローパスフィルタ3は、高周波ノイズを通さないので、一方の領域に発生した高周波ノイズは、他の接続されている領域に流れることは無い。   Further, in the multilayer printed circuit board 8a shown in FIG. 3, the planes 4 are connected to each other through the VIA 2 using the low-pass filter 3 as an electronic circuit component. Since the low-pass filter 3 does not pass high-frequency noise, high-frequency noise generated in one region does not flow to the other connected region.

さらに、図2および図3に示す多層プリント回路基板においては、分割するプレーン4の領域の大きさを、搭載しているICやLSIなどの集積回路素子の最高動作周波数の1/4波長分より短い長さを1辺とする正方形としている。   Further, in the multilayer printed circuit board shown in FIGS. 2 and 3, the size of the area of the plane 4 to be divided is a quarter wavelength of the maximum operating frequency of the integrated circuit element such as an IC or LSI mounted. It is a square with a short length as one side.

このように、分割するプレーン4の領域の大きさを、搭載しているICやLSIなどの集積回路素子最高動作周波数の1/4波長分より短い長さを1辺とする正方形に分割することにより、各領域に流入する高周波電流の共振によるノイズレベルの増幅が発生しないようにすることができ、領域ごとにノイズレベルを抑えることができる。   In this way, the size of the area of the plane 4 to be divided is divided into squares each having a length shorter than a quarter wavelength of the maximum operating frequency of an integrated circuit element such as an IC or LSI that is mounted. Thus, amplification of noise level due to resonance of the high-frequency current flowing into each region can be prevented, and the noise level can be suppressed for each region.

以上、図1〜図3を用いて説明したように、本例の多層プリント回路基板8,8aは、複数の回路素子を搭載し、グランド層と信号層と回路素子に電源電圧を供給するための電源層とがそれぞれ絶縁材を介して積層された構成であり、さらに、電源層とグランド層とが互いに対向する領域(プレーン4)を、同一形状かつ同一面積で均等に分割した均等分割領域で形成し、各均等分割領域を、他の均等分割領域と一箇所でのみ接続する構成とすることを特徴とする。そして、均等分割領域間を、高周波インピーダンスを高めるようにパターニングされた電源配線パターン1で接続する構成、あるいは、ローパスフィルタ3で接続する構成とする。さらに、均等分割領域(プレーン4)を、回路素子の最高動作周波数の1/4波長以下の長さを一辺とする正方形で分割して形成する構成とする。   As described above with reference to FIGS. 1 to 3, the multilayer printed circuit boards 8 and 8 a of this example are equipped with a plurality of circuit elements to supply a power supply voltage to the ground layer, the signal layer, and the circuit elements. The power supply layers are laminated with insulating materials interposed therebetween, and the region (plane 4) where the power supply layer and the ground layer face each other is equally divided into the same shape and the same area. And each equal divided area is connected to another equal divided area only at one location. And it is set as the structure connected by the power supply wiring pattern 1 patterned so that high frequency impedance may be raised between equal division | segmentation areas, or the structure connected by the low-pass filter 3. FIG. Further, the equally divided region (plane 4) is formed by being divided into squares each having a length equal to or shorter than a quarter wavelength of the maximum operating frequency of the circuit element.

このように、電源およびグランド層を均等分割(プレーン4)し、各プレーン4の高周波インピーダンスを高めるようにパターニングされた電源配線パターン1、もしくは、ローパスフィルタ3で接続する構成とすることにより、集積回路素子の高速スイッチング動作に伴って流れる高周波電源電流の他の領域への流れ込みを抑え、かつグランド層と電源層および搭載される集積回路素子から形成されるLC回路の共振周波数をEMI規制の対象周波数以上にシフトさせることができ、多層プリント回路基板から発生する放射ノイズを低減することができる。   As described above, the power supply and ground layers are equally divided (plane 4), and the power supply wiring pattern 1 or the low-pass filter 3 patterned so as to increase the high-frequency impedance of each plane 4 is connected. Suppressing the flow of the high-frequency power supply current that flows along with the high-speed switching operation of the circuit element into the other region, and the resonance frequency of the LC circuit formed from the ground layer, the power supply layer, and the integrated circuit element to be mounted is subject to EMI regulations The frequency can be shifted to more than the frequency, and radiation noise generated from the multilayer printed circuit board can be reduced.

さらに、回路素子の最高動作周波数の1/4波長以下の長さを一辺とする正方形で分割することにより、集積回路素子の高速スイッチング動作に伴って流れる高周波電源電流により発生する放射ノイズが、共振により増幅されることを防ぐことができ、多層プリント回路基板から発生する放射ノイズを低減することができる。   Furthermore, by dividing the square with a length of 1/4 wavelength or less of the maximum operating frequency of the circuit element into one side, the radiation noise generated by the high-frequency power supply current that flows along with the high-speed switching operation of the integrated circuit element is resonant. Can be prevented, and radiation noise generated from the multilayer printed circuit board can be reduced.

また、このような多層プリント回路基板を用いることで、電子機器の性能の向上を図ることができる。   Further, by using such a multilayer printed circuit board, the performance of the electronic device can be improved.

尚、本発明は、図1〜図3を用いて説明した例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能である。   In addition, this invention is not limited to the example demonstrated using FIGS. 1-3, In the range which does not deviate from the summary, various changes are possible.

本発明に係わる多層プリント回路基板の断面構成例を示す側断面図である。It is a sectional side view which shows the cross-sectional structural example of the multilayer printed circuit board concerning this invention. 本発明に係わる多層プリント回路基板における均等分割領域の第1の接続構成例を示す上面図である。It is a top view which shows the 1st connection structural example of the equal division | segmentation area | region in the multilayer printed circuit board concerning this invention. 本発明に係わる多層プリント回路基板における均等分割領域の第2の接続構成例を示す上面図である。It is a top view which shows the 2nd connection structural example of the equally divided area | region in the multilayer printed circuit board concerning this invention.

符号の説明Explanation of symbols

1:電源配線パターン、2:VIA、3:ローパスフィルタ、4:プレーン(正方形に均等分割)、8,8a:多層プリント配線基板。   1: power supply wiring pattern, 2: VIA, 3: low-pass filter, 4: plane (equally divided into squares), 8, 8a: multilayer printed wiring board.

Claims (3)

複数の回路素子を搭載し、グランド層と信号層と前記回路素子に電源電圧を供給するための電源層とがそれぞれ絶縁材を介して積層された多層プリント回路基板であって、
前記電源層と前記グランド層とが互いに対向する領域を、前記回路素子の最高動作周波数の1/4波長以下の長さを一辺とする同一面積の正方形で均等に分割した均等分割領域として形成し、
すべての各均等分割領域は、高周波インピーダンスを高めるように且つループを作らないようにパターニングされ、隣接した均等分割領域と接続されることを特徴とする多層プリント回路基板。
A multilayer printed circuit board having a plurality of circuit elements mounted thereon, wherein a ground layer, a signal layer, and a power supply layer for supplying a power supply voltage to the circuit elements are laminated via insulating materials,
A region where the power supply layer and the ground layer are opposed to each other is formed as an equally divided region that is equally divided by a square of the same area with one side having a length equal to or less than ¼ wavelength of the maximum operating frequency of the circuit element. ,
All the equally divided areas are and patterned so as not to create a loop to increase the high frequency impedance is connected to the equally divided areas adjacent multilayer printed circuit board according to claim Rukoto.
請求項1に記載の多層プリント回路基板であって、
前記均等分割領域と隣接した均等分割領域とを、ローパスフィルタの電子回路部品で接続することを特徴とする多層プリント回路基板。
The multilayer printed circuit board according to claim 1,
A multilayer printed circuit board, wherein the equally divided region and the adjacent equally divided region are connected by an electronic circuit component of a low-pass filter.
請求項1もしくは請求項のいずれかに記載の多層プリント回路基板を用いたことを特徴とする電子機器。 Electronic device characterized by using the multilayer printed circuit board according to claim 1 or claim 2.
JP2005078497A 2005-03-18 2005-03-18 Multilayer printed circuit board and electronic equipment Expired - Fee Related JP4671333B2 (en)

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KR100914440B1 (en) 2007-09-28 2009-08-28 삼성전기주식회사 Printed circuit board having stepped conduction layer
JP5336913B2 (en) * 2009-04-15 2013-11-06 三菱電機株式会社 Multilayer printed wiring board
KR101109190B1 (en) 2010-06-04 2012-01-30 삼성전기주식회사 A printed circuit board and a method of manufacturing the same
KR20160011867A (en) * 2014-07-23 2016-02-02 엘에스산전 주식회사 Inverter assembly without galvanic isolation

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745962A (en) * 1993-07-28 1995-02-14 Fujitsu Ltd Pattern against radio interference waves on multilayer printed-circuit board
JPH07111387A (en) * 1993-10-13 1995-04-25 Ricoh Co Ltd Multilayer printed wiring board
JPH1056245A (en) * 1996-06-04 1998-02-24 Mitsubishi Electric Corp Printed wiring board
JPH11340629A (en) * 1998-05-25 1999-12-10 Mitsubishi Electric Corp Printed wiring board with laminated structure
JP2001025334A (en) * 1999-05-10 2001-01-30 Kouyuumaru:Kk Fishing hook
JP2001267702A (en) * 2000-03-14 2001-09-28 Fuji Xerox Co Ltd Printed wiring board
JP2002368355A (en) * 2001-06-04 2002-12-20 Mitsubishi Electric Corp Printed wiring board
JP2003163466A (en) * 2001-11-29 2003-06-06 Sharp Corp Multilayer printed circuit board and multilayer printed circuit board device provided with the printed circuit board

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745962A (en) * 1993-07-28 1995-02-14 Fujitsu Ltd Pattern against radio interference waves on multilayer printed-circuit board
JPH07111387A (en) * 1993-10-13 1995-04-25 Ricoh Co Ltd Multilayer printed wiring board
JPH1056245A (en) * 1996-06-04 1998-02-24 Mitsubishi Electric Corp Printed wiring board
JPH11340629A (en) * 1998-05-25 1999-12-10 Mitsubishi Electric Corp Printed wiring board with laminated structure
JP2001025334A (en) * 1999-05-10 2001-01-30 Kouyuumaru:Kk Fishing hook
JP2001267702A (en) * 2000-03-14 2001-09-28 Fuji Xerox Co Ltd Printed wiring board
JP2002368355A (en) * 2001-06-04 2002-12-20 Mitsubishi Electric Corp Printed wiring board
JP2003163466A (en) * 2001-11-29 2003-06-06 Sharp Corp Multilayer printed circuit board and multilayer printed circuit board device provided with the printed circuit board

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