JP2005149445A - Method for designing terminal block layout in electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform the layout processing of substrate terminal blocks for forming wiring patterns, which do not use interlayer connection vias of backplane substrates to the utmost, in the designing of an electronic device comprising a plurality of substrates and backplane substrates connected through the substrates and connectors. <P>SOLUTION: After fetching the terminal information of each substrate and the information of connection between each substrate (S1) and performing a tentative layout of each substrate terminal (S2), a terminal layout is determined by giving priorities to ready-made substrates where a plurality of inserted substrates and pin assignment are established (S3 to S6). Consequently, the terminal layout is automatically determined which increases the number of horizontal wiring in wiring rat nests at the backplane substrates and reduces the number of wiring crossings. Also, when there is a balanced transmission net (S7), ground pins are assigned to vicinities of balanced transmission pins by further shifting the substrate terminal assigned to connector pins once in the unidirection and assigning ground pins to vacant connector pins (S8). Also, terminal layout results determined in this way are automatically fed back to a circuit diagram of each substrate (S9). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention efficiently allocates a board terminal group for reducing the number of layers of a backplane board in an electronic device including a plurality of printed boards and a backplane printed board connected to the board via a connector. Related to the method (design method and apparatus) to be performed.

  The sub-board connected to the main board (corresponding to the backplane board of the present invention) via the connector is regarded as one component, and the signal pin assignment is determined so that the connection line vector in the same unit is as much as possible. A method of reducing the number of layers has been proposed by creating a wiring pattern that uses as few interlayer connection vias as possible on the main board connected to the sub board. JP-A-8-6972 is cited as a related to this proposal.

JP-A-8-6972

  In the above prior art, in order to reduce the number of wiring layers, pin assignment is optimized simply by considering one board as a component, and a ready-made board (pin assignment) is used as a part of the board inserted into the backplane. The method of optimally assigning pins is not taken into consideration under the restriction that the same type of board is included) and the restriction that a plurality of boards of the same type are inserted into one backplane board. In addition, to avoid electrical problems such as reflection and crosstalk with respect to the pins of the balanced transmission net on the backplane board, pin assignment is optimized under the restriction that a ground pin is placed in the vicinity. There is no consideration on how to do it.

  The purpose of the present invention is to place a ground pin near a pin of a balanced transmission net on the backplane board, such as a restriction that the same board is inserted into the backplane board, a part of the board includes a ready-made board, or the like. A terminal group assignment design method for an electronic device that automatically determines the assignment of board terminal groups that reduce the number of backplane board layers by creating a wiring pattern that uses as little an interlayer connection path as possible while simultaneously considering the restrictions such as placement, and It is to provide such a device.

  To achieve the above object, the present invention provides a terminal group assignment design method for an electronic device configured by connecting each of a plurality of printed boards to a backplane printed board through a connector, A first step of tentatively assigning the terminal group of each printed circuit board to each connector pin group based on the terminal group information of the circuit board, the connection information between the terminal groups between the printed circuit boards, and the mounting information of the printed circuit board for the backplane And each of the terminal groups including the other printed circuit boards in preference to the same printed circuit board or the ready-made printed circuit board in which the pin assignment is fixed in the terminal group of each printed circuit board temporarily allocated in the first step. And a second step of automatically determining allocation to the connector pin group by wiring rats nest on the printed circuit board for the backplane. .

  Further, the present invention further includes a third step of assigning a ground pin to an empty connector pin by shifting the terminal group assigned in the second step in a predetermined direction when a balanced transmission net is present. It is characterized by having.

  In addition, the present invention includes a step of feeding back the terminal group assignment result determined in the second or third step to a circuit diagram of each printed circuit board.

  Further, the present invention is a terminal group assignment design device for an electronic device configured by connecting each of a plurality of printed circuit boards to a backplane printed circuit board through a connector, the terminal group information of each printed circuit board, First means for tentatively assigning each terminal group of each printed circuit board to each connector pin group based on connection information between terminal groups between the printed circuit boards and backplane printed circuit board mounting information; and the first means In the terminal group of each printed circuit board that is temporarily assigned in step 1, assign the terminal group to each connector pin group including the other printed circuit board in preference to the same printed circuit board or the ready-made printed circuit board in which the pin assignment is fixed. And a second means for automatically determining by wiring rats nest on the printed circuit board for backplane.

  The present invention further includes a third means for shifting the terminal group assigned by the second means in a predetermined direction and assigning a ground pin to an empty connector pin when a balanced transmission net is present. It is characterized by having.

  Further, the present invention captures terminal group information on the circuit diagram of each printed circuit board, connection information between each printed circuit board terminal group and mounting information of the printed circuit board for the backplane, and generates a wiring ratsnest of the printed circuit board for the backplane. The number of horizontal wirings of the wiring rats nest is increased, and the board terminal group is automatically assigned so that the number of wiring intersections is reduced.

  According to the present invention, when there are a plurality of identical printed circuit boards in a printed circuit board inserted into one printed circuit board for backplane, or there is a ready-made printed circuit board (pin assignment has been confirmed) in a part of the printed circuit board. In order to avoid electrical problems such as reflection and crosstalk with respect to the balanced transmission net pins of the printed circuit board for the backplane, even if there are restrictions such as placing ground pins in the vicinity of the backplane It is possible to efficiently allocate the board terminal group to the connector pins for reducing the number of layers of the printed board for plane.

  Embodiments of an optimum terminal assignment apparatus and method according to the present invention will be described with reference to the drawings. FIG. 2A shows a backplane printed circuit board (hereinafter referred to as a backplane board) 20 to be subjected to the optimum terminal group assignment according to the present invention and a printed circuit board (hereinafter referred to as a printed circuit board) connected thereto via connectors 2A to 2D. It is called a board | substrate.) It is an electronic device unit outline figure comprised from 21-24. In a large-scale system such as a communication system, it is difficult to realize all functions with one board. Therefore, the functions are usually distributed to a plurality of boards 21 to 24, and the plurality of boards 21 to 24 are backplane boards. In many cases, the system is configured by connecting using the network 20. FIG. 2B shows an example of a wiring pattern of the backplane substrate 20 in a state where the printed boards 21 to 24 are removed from the state of FIG. The backplane board 20 has wiring patterns 25 to 28 between connector pins into which the boards are inserted in order to connect signals of the boards 21 to 24.

  In normal electronic device design, each of the boards 21 to 24 to be inserted into the backplane board 20 and the backplane board 20 are often designed in parallel, and in this case, the assignment of each board terminal to a connector pin is required. If done well, wiring of the backplane substrate 20 can be facilitated, and as a result, the number of wiring layers can be reduced. However, considering the case where a plurality of the same substrates are inserted into one backplane substrate 20 or the case where a ready-made substrate is inserted, it is a time-consuming operation to consider the assignment of substrate terminals to connector pins. For example, when 21 and 24 are the same board, the connector pin assignment of the connector 2A to which the board 21 is connected and the connector 2D to which the board 24 is connected must be the same, and the number of wiring layers of the backplane board 20 The optimum terminal allocation method is found while simultaneously considering the condition of reducing the number of terminals. Alternatively, for example, when the board 22 is an off-the-shelf board, an optimum terminal assignment method is found while simultaneously considering the condition that the pin assignment of the connector 2B cannot be changed and the condition that the number of wiring layers of the backplane board 20 is reduced. It is such work. In addition, since the backplane board 20 generally has a long wiring, it is necessary to perform balanced transmission if high-speed signal transmission is performed. In this case, in order to reduce high-frequency reflection and crosstalk as much as possible, It is also necessary to consider the arrangement of ground pins near the balanced transmission net pins. However, it is difficult to optimize the assignment of each board terminal to the connector pin while simultaneously considering all these constraints, and there is a problem that much time is required for the examination.

  Hereinafter, an embodiment of an optimum terminal assignment apparatus and method according to the present invention for solving this problem will be described in detail. FIG. 3 is a diagram showing an embodiment of the system configuration of the terminal optimum allocation device. This system includes a logic information file 35 of an electronic device for each board terminal group connection information 35b corresponding to each board circuit diagram 35a and backplane board logic information, and connector component information 37a including a connector shape and a connector pin arrangement position. Based on the backplane board mounting information file 37 such as the connector arrangement information 37b including the backplane board shape and the connector arrangement position on the backplane, the central processing unit 31 optimizes each board terminal group to the connector pin group. Assignment is determined, and the result is automatically fed back to the terminal group assignment information of each board circuit diagram 39a (same as 35a). The result can be confirmed on the display device 32. The keyboard / mouse 33 is used for designating input information files 35, 37, 39 of the system, and the printer 34 is used for printing terminal group assignment results. In the circuit diagram 35a, it is only necessary to input logical information of at least the terminal group portion of the substrate, and it is not always necessary to complete the input of all logical information.

  Next, a detailed terminal group optimal assignment process using this system will be described using the flowchart shown in FIG. First, in step S1, circuit information (35a in FIG. 3) for each board and connection information (35b in FIG. 3) between board terminal groups corresponding to logic information of the backplane board are input. FIG. 4 shows an example of circuit boards A to C inserted into the backplane board 20. Each of the circuit diagrams 41 to 43 includes components (A1, A2; B1, B2; C1, C2) constituting a circuit, net groups (netA1 to netA12; netB1 to netB12; netC1 to netC12) connected to the component pins, and It is comprised from a board | substrate terminal group (A1-A6; B1-B6; C1-C6). Here, the board terminal name represents the connector type and pin number to which the terminal group should be assigned. For example, the board terminal A1 means a board terminal assigned to the first pin of the connector type A. In FIG. 4, each component name (part name, net name, board terminal name) is expressed by a different name, but generally a local name (for example, the same name for board A and board B) in each board. Even if there is a net name and the same terminal name, they are the same potential, that is, they are not regarded as being connected but are regarded as different. Therefore, global information defining the connection between the board terminals is required separately, which is the board terminal group connection information (35a in FIG. 3). For example, the backplane board 20 formed by inserting the board A, the board B, the board C, and the board A in order from the left into the backplane board having four connectors as shown in FIG. 5 will be described as an example. Since these connector types need to correspond to each board terminal, in this example, connector 1 and connector 4 are type A connectors into which board A can be inserted, connector 2 is a type B connector into which board B can be inserted, The connector 3 is a type C connector into which the substrate C can be inserted. FIG. 6 shows an example of logical connection information (connection information between board terminals) of the backplane board 20. This example is an example in which four boards of board A, board B, board C and board A having the board circuit diagram shown in FIG. 4 are inserted into connectors 1 to 4 of the backplane board 20 of FIG. In this example, connection information (35b in FIG. 3) between the board terminal groups of net1 to net9 is provided as backplane logical information. Here, net1 is a net having connections to terminal A1 (netA1) of board A, terminal B4 (netB4) of board B, terminal C1 (netC1) of board C, and terminal A4 (netA4) of board D. Yes. In this example, an electrical condition such as balanced transmission of net2 and net3 is instructed. In the central processing unit 31, the board circuit information 35a shown in FIG. 4 and the connection information 35b between the board terminal groups shown in FIG. 6 are taken into the backplane board 20 shown in FIG.

  In the central processing unit 31, in the next step S2, connector component information (37a in FIG. 3) further including the connector shape and connector pin arrangement position, and connector arrangement information including the backplane board shape and the connector arrangement position on the backplane. (37b in FIG. 3) processing for fetching backplane board mounting information and temporarily assigning board terminal groups to connector pin groups based on this and each board or backplane board logic information 35 already fetched in S1. Do. An example of the temporary allocation processing result is shown in FIG. This assigns the terminal groups A1 to A6 of the circuit board A circuit diagram to the 1st to 6th pins of the connector 1 and the connector 4, respectively, and assigns the terminal groups B1 to B6 of the circuit board B circuit diagram to the 1st to 6th pins of the connector 2, respectively. Similarly, the terminal groups C1 to C6 of the circuit board C circuit diagram are assigned to the 1st to 6th pins of the connector 3 in accordance with the circuit board terminal names (connector type + pin number) in the circuit diagram of FIG. This is a process of assigning groups to connector pin groups. 7 represents the wiring rats nests (net1 to net9) indicating the connection relationship between the board terminal groups. Since there are many intersections of the wiring rats nests, it is assumed that the wiring is performed as it is. The wiring pattern as shown in FIG. 1 is required, and an interlayer connection via for layer switching is required, and at least two wiring layers are required. The processing after step S3 solves the problem of the increase in the wiring layer.

  In the central processing unit 31, in step S3, first, terminal allocation is fixed (priority terminal group allocation is performed) to determine a reference board. For example, when a plurality of identical substrates are connected in a substrate connected to a backplane substrate, the decision rule is the one with the largest number of inserted substrates. Further, if there is a ready-made substrate, the substrate having the largest number of connection terminals is selected. In the following example, a case will be described as an example where all are newly designed boards and a plurality of identical boards are connected (FIG. 6). In FIG. 6, since the board A is inserted into the connector 1 and the connector 4, the board A is determined as a reference board in step S3.

  In the central processing unit 31, next, in step S4, the terminal groups of the other boards connected to the terminals of the reference board A are preferentially taken out in the order of the terminal groups A1 to A6 of the reference board A. The terminal group assignment method at this time will be described with reference to FIGS. The terminal that is preferentially connected to the terminal A1 of the reference board A inserted into the connector 1 and the connector 4 in FIG. 7 is B4 when the connector 2 is focused, and C4 when the connector 3 is focused. This is expressed as C4-A1-B4 (91) as shown in FIG. Similarly, terminals preferentially connected to the terminal groups A2 to A6 are C2-A2-B5 (92), C6-A3-B6 (93), C1-A4-B1 (94), C5-A5-B2 ( 95), C3-A6-B3 (96) and its connection relation. That is, in the order of the terminals A1 to A6 of the reference board A, the connection relationship (91 to 96) with the terminals of other boards connected to the terminals A1 to A6 is preferentially obtained. Next, paying attention to the terminals connected between the remaining substrates B and C, C1-B4 (97), C5-B5 (98), and C3-B6 (99) are obtained.

  In the central processing unit 31, the board terminal groups are reassigned (reassigned) in order from the first pin of each connector in the combination of 91 to 99 obtained in this way in step S5. This is shown in FIGS. 10 will be used for explanation. First, the 1st pin of each connector is determined by 91 combinations. That is, the terminal C4 is connected to the first pin of the connector 3 into which the substrate C is inserted, the terminal A1 is connected to the first pin of the connector 1 and the connector 4 into which the reference substrate A is inserted, and the connector 2 into which the substrate B is inserted. The terminal B4 is assigned to the first pin. Next, the second pin of each connector is determined by the combination of 92, that is, the terminal C2 is connected to the second pin of the connector 3 into which the board C is inserted, and the second pin of the connector 1 and the connector 4 into which the reference board A is inserted. The terminal A2 is assigned to the pin, and the terminal B5 is assigned to the second pin of the connector 2 into which the board B is inserted. It is assumed that the connection state between the terminals does not change at the time of assignment. Allocation is similarly performed for the combinations of 93 to 96, and allocation of the 3rd to 6th pins is determined. Next, in step S6, it is determined whether there is a terminal whose terminal assignment has not been determined. If there is a terminal that has not been determined, the assignment has been determined for the board including the terminal that has not been determined. The processing from step S3 to step S5 is repeated under the condition that the terminal does not move. In this embodiment, all terminals of the reference board A, board B, and board C are determined in the first loop (all terminals appear in FIG. 9). As a result, the assignment of the board terminal group to the connector pin group and the connection rats nest as shown in FIG. 10 are obtained.

  In the central processing unit 31, the next step S7 is a process of determining whether a balanced transmission instruction is present in the logical information of the backplane board. In this embodiment, pins 1 and 8 of connector 1 to connector 4 in FIG. 10 are vacant pins, and net2 and net3 are defined as balanced transmission nets as shown in FIG. Step S8 of assigning a ground pin in the vicinity of the pin of the transmission net is executed. In step S8, for example, all terminals constituting the balanced transmission net are shifted in one direction. In other words, the A2 terminal is the 2 → 3 pin, the B5 terminal is the 2 → 3 pin, the C5 terminal is the 5 → 7 pin, and the ground is assigned to the empty 2nd pin. Next, by repeatedly shifting other terminals affected by this in the same direction, a ground pin can be arranged in the vicinity of the pin of the net, and high frequency reflection and crosstalk in balanced transmission can be reduced as much as possible. It becomes possible.

  FIG. 11 shows the result of the optimum terminal assignment and the wiring rats nest of the backplane board obtained in this way, and the number of horizontal wirings is increased compared to the connection rats nest before the terminal optimization assignment in FIG. The number of wiring intersections is decreasing.

  FIG. 12 shows a result of wiring with respect to the connection rats nest of the backplane substrate after this terminal optimization. Compared to FIG. 8, FIG. 12 is improved so that wiring can be made in one layer without using vias.

  In the central processing unit 31, the last step S9 is a process of reflecting the terminal assignment result determined in this way on the circuit diagram of each board. Looking at the result after the terminal optimization (FIG. 11), since the terminal A1 of the board A is assigned to the first pin of the connector 1 and the connector 4 (both are type A), this is defined as A1 → A1. Is assigned to the third pin of the connector 1 and the connector 4, so that A2 → A3. Similarly, A3 → A4, A4 → A5, A5 → A7, and A6 → A8 are changed. The result is fed back to the circuit diagram 41 of the substrate A in FIG. 4 to obtain a circuit diagram 131 in FIG. Focusing on the board B, since the terminal B4 is assigned to the first pin of the connector 2 (type B), this is assigned to B4 → B1, and the B5 terminal is assigned to the third pin of the connector 2, so that B5 → B3, Similarly, B6 → B4, B1 → B5, B2 → B7, and B3 → B8 are changed. This result is fed back to the circuit diagram 42 of the substrate B in FIG. 4 to obtain the circuit diagram 132 in FIG. Further, if attention is paid to the board C in the same manner, the terminal C4 is assigned to the first pin of the connector 3 (type C), so this is C4 → C1, and the terminal C2 is assigned to the third pin of the connector 3. Therefore, C2 → C3, and similarly C6 → C4, C1 → C5, C5 → C7, and C3 → C8. The result is fed back to the circuit diagram 43 of the substrate C in FIG. 4 to obtain the circuit diagram 133 in FIG. Thus, by automatically feeding back the optimized terminal information to the original circuit diagram, each circuit designer changes the terminal assignment, so that the work of correcting the circuit diagram can be omitted.

  As described above, according to the embodiment of the present invention, when there are a plurality of identical substrates in a substrate to be inserted into one backplane substrate, or a part of the substrate is a ready-made substrate (the pin assignment has been confirmed). ), Or to avoid electrical problems such as reflection and crosstalk with respect to the balanced transmission net pins on the backplane board, even if there are restrictions such as placing ground pins in the vicinity. Further, it is possible to efficiently allocate the board terminal group to the connector pin group for reducing the number of layers of the backplane board.

It is a flowchart for demonstrating one Embodiment of the terminal group optimal allocation process which concerns on this invention. It is drawing for demonstrating the structure and backplane board | substrate of an electronic device unit which concern on this invention. It is a schematic block diagram which shows one Embodiment of the system configuration | structure of the terminal group optimal allocation apparatus which concerns on this invention. It is drawing for demonstrating an example of the board | substrate circuit diagram inserted in the backplane board | substrate which concerns on this invention. It is drawing for demonstrating an example of the connector arrangement | positioning on the backplane board | substrate which concerns on this invention. It is drawing for demonstrating an example of the logical connection information of the backplane board | substrate which concerns on this invention. It is drawing for demonstrating the terminal allocation state after each board | substrate terminal group is provisionally allocated to the backplane board | substrate which concerns on this invention, and the state of a connection rats nest. It is drawing for demonstrating the wiring result of the backplane board | substrate in the state before the terminal group allocation optimization which concerns on this invention. It is drawing for demonstrating the process of the terminal group allocation process which concerns on this invention. It is drawing for demonstrating the terminal allocation state and connection rats nest state of the backplane board | substrate after the terminal group allocation improvement which concerns on this invention. FIG. 11 is a diagram for explaining a terminal allocation state and a connected rats nest state after optimal allocation of terminal groups in consideration of balanced transmission from FIG. 10. It is drawing for demonstrating the wiring result in the backplane board | substrate in the state after the terminal group allocation optimization which concerns on this invention. It is drawing for demonstrating the result of having fed back the terminal group allocation result based on this invention to each board | substrate circuit diagram.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Backplane board | substrate, 21-24 ... Board | substrate inserted in a backplane board | substrate, 31 ... Central processing unit, 32 ... Display apparatus, 33 ... Keyboard / mouse, 34 ... Printer, 35 ... Logical information file, 35a, 39a ... Board circuit diagram file, 35b ... Board terminal group connection information file, 37 ... Backplane board mounting information file, 37a ... Connector component information file, 37b ... Connector arrangement information file, 39 ... Allocation result output file, 41-43 ... Board circuit diagram example inserted into connector, 91 to 99... Straight line representing connection relation between each board terminal group, 131 to 133.

Claims (3)

A terminal group assignment design method for an electronic device configured by connecting each of a plurality of printed circuit boards to a backplane printed circuit board through a connector,
Based on the terminal group information of each printed circuit board, the connection information between the terminal groups between the printed circuit boards, and the mounting information of the printed circuit board for backplane, the provisional assignment of the terminal groups of each printed circuit board to the connector pin groups is performed. 1 step,
Each connector pin of the terminal group including other printed circuit boards in preference to the same printed circuit board or the ready-made printed circuit board in which the pin assignment is fixed in the terminal group of each printed circuit board temporarily allocated in the first step And a second step of automatically determining allocation to groups by wiring rats nest on a printed circuit board for backplane.   Further, when there is a balanced transmission net, there is provided a third step in which the terminal group assigned in the second step is shifted in a predetermined direction and a ground pin is assigned to an empty connector pin. The electronic device terminal group allocation design method according to claim 1. 2. The terminal group assignment design method for an electronic device according to claim 1, further comprising a fourth step of feeding back the terminal group assignment result determined in the second step to a circuit diagram of each printed circuit board.

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