JP2007004303A - Design support method for printed circuit board, design support system for printed circuit board, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the design support method of a printed circuit board, the design support system of a printed circuit board, and a program for efficiently carrying out designing satisfactorily and in parallel. <P>SOLUTION: This design support method of a printed circuit board for supporting the designing of one printed circuit board by a plurality of designers comprises: an instruction information preparation step for preparing instruction information including at least information on a design region for which each of a plurality of designers is responsible and the layout of wiring on the basis of layout/wiring data acquired by executing the layout design of electronic components; an instruction information storage step for storing the instruction information in a database; and an instruction information notification step for notifying client terminal equipment to be used by the plurality of designers that the instruction information has been prepared. Thus, it is possible for each designer to perform designing by recognizing the instruction information. Therefore, it is possible to efficiently carry out the designing of a printed circuit board with satisfactory design quality in parallel by reducing interference among those designers. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a printed circuit board design support method and design support system suitable for designing a printed circuit board by a plurality of persons, and a program suitable for this system.

  In order to shorten the design period, a design method has been proposed in which one design object is distributed to a plurality of CAD apparatuses and work is performed in parallel. For example, Patent Document 1 discloses a simultaneous and parallel design method in which the content of a design object is divided into a plurality of parts by function and each part is assigned to each CAD device as an independent design operation.

  However, in the design of a printed circuit board, it is difficult to divide into a plurality of independent parts because a large number of wirings and parts forming a circuit are required to be densely and laid out. For example, as a result of designing a wiring in a certain part, interference and inconsistency may occur between adjacent parts to which the wiring is connected. For this reason, it is difficult to proceed with the design independently for each part.

  On the other hand, a design method is also known in which the same design object is accessed by a plurality of CAD devices or terminal devices without dividing the design object. For example, Patent Document 2 discloses a method of setting priorities for each CAD device, and Patent Document 3 discloses that a terminal device that first makes a design / edit request to a target object excludes other terminal devices. A method for designing and editing is disclosed. According to these methods, multiple designers under the main designer design a printed circuit board that is one design target in a team format, and automatically eliminate interference and contradictions between multiple designers. Thus, it becomes possible to design simultaneously.

JP 2002-117078 A JP 08-235233 A JP 2003-186914 A

  However, in parallel design, in many cases, there is a difference in the level of proficiency between designers and there is an information gap with respect to the design concept. And the contradiction has not been resolved. Further, detailed adjustments between designers and correction of design mistakes are performed for each of these interferences and contradictions, resulting in a reduction in design efficiency.

  The present invention has been made in view of the above-described problems, and a printed circuit board design support method, a printed circuit board design support system, and a program capable of efficiently and concurrently performing a high-quality design. The purpose is to provide.

  As a result of intensive studies to solve the above problems, the present inventor has come up with various aspects of the invention described below.

  A printed circuit board design support method according to the present invention is a printed circuit board design support method for supporting the design of one printed circuit board by a plurality of designers. An instruction information creating step for creating instruction information including information on a design area and / or wiring layout which each of the plurality of designers is in charge of based on data, and instruction information for storing the instruction information in a database A storage step; and an instruction information notification step of notifying the client terminal devices used by the plurality of designers that the instruction information has been created.

  A printed circuit board design support system according to the present invention is a printed circuit board design support system that supports the design of a single printed circuit board by a plurality of designers. Instruction information creating means for creating instruction information including information on a design area and / or wiring layout which each of the plurality of designers is in charge of based on data, and instruction information for storing the instruction information in a database And storing means and instruction information notifying means for notifying client terminal devices used by the plurality of designers that the instruction information has been created.

  A program according to the present invention is a program for allowing a computer to support the design of one printed circuit board by a plurality of designers, and for causing the computer to design information that serves as a basis for designing the printed circuit board and the layout design of electronic components. Procedures for displaying arrangement / wiring data including information on a display device, and dividing the printed circuit board into a plurality of design areas, assigning one or more design areas for each designer, and different designers For the assigned adjacent design areas, the procedure for allowing the user to input the first instruction information whose design order is different from each other, and the wiring to be connected via three or more component pins of different electronic components The second instruction information for instructing the connection order of the user and the third instruction information for instructing the wiring to secure the wiring route in preference to the other wiring. A procedure for causing the user to input, a procedure for causing the user to input fourth instruction information for designating at least one of a wiring design position and a wiring layer, and storing the first to fourth instruction information in a database And an instruction information notification procedure for notifying client terminal devices used by the plurality of designers that the first to fourth instruction information has been created. .

  According to the present invention, each designer can confirm instruction information including information related to the design area and / or the layout of the wiring each is in charge of. For this reason, each designer advances the design according to this instruction information to reduce the occurrence of interference between designers and inconsistencies in design / editing, and to perform high-quality design efficiently and concurrently. Is possible. In particular, by confirming the instruction information for designing the wiring on the printed circuit board such as the design order of the design area, the wiring connection order, the wiring for preferentially securing the route, the wiring position and the wiring layer, etc. on the client terminal device Therefore, it is possible to make a high-quality design more easily.

  In addition, since a designer who uses a client terminal device can design without requiring special learning, it is possible to reduce differences in design time, design quality, and the like between designers depending on the level of proficiency. Furthermore, at the time of the final inspection after the design, if it is possible to directly compare the designed wiring pattern with the instruction information created in image information or text format, the inspection can be performed quickly and accurately. The period can be shortened.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a printed circuit board design support system 100 according to an embodiment of the present invention.

  The printed circuit board design support system 100 includes a server CAD device 10 and a plurality of client terminal devices 11 to 13, and the server CAD device 10 and the client terminal devices 11 to 13 communicate with each other via a predetermined network 55. is there. The number of client terminal devices is not limited, but in the present embodiment, there are three.

  The server CAD device 10 includes a computer (CPU) and the like, and exhibits a CAD (computer-aided design) function for performing component placement design and wiring design for a printed circuit board. The program executed by the CPU is stored in the storage medium drive 53, for example. The server CAD device 10 stores design information 21 necessary for the design of the printed circuit board, the server CAD device 10 and the client terminal devices 11 to 13 inputted based on the circuit design drawing, the component library, the wiring specifications, the design constraint conditions, and the like. The information is transmitted to and received from the database 20 storing the arrangement / wiring data 28 edited using the data, instruction information 41 (details will be described later), and the like. Further, the server CAD device 10 takes in the design information 21, the arrangement / wiring data 28, the instruction information 41 and the like as a display device 52 that displays as image information, the input device 51 including a keyboard and a mouse, and programs and data. Information and the like are also transmitted and received between the storage medium drive 53 and the instruction information processing apparatus 30.

  Here, the functional configuration of the instruction information processing apparatus 30 will be described. FIG. 2 is a functional block diagram showing a functional configuration of the instruction information processing apparatus 30. The instruction information processing apparatus 30 includes an interface unit 39 that mediates exchange of information with the server CAD apparatus 10, a process for controlling the server CAD apparatus 10 to output data to the display device 52, and a process for storing data in the database 20. And a server CAD control unit 40 that performs processing for notifying the client terminal device of the update state of the instruction information 41, and an instruction information creating unit 31 that creates the instruction information 41. The interface unit 39 can be omitted when the program specifications of the server CAD device 10 and the instruction information processing unit 30 are the same.

  Each of the above-described units constituting the instruction information processing apparatus 30 is configured by, for example, a computer (CPU) and a program executed by the computer (CPU). This program is stored in the storage medium drive 53, for example.

  The instruction information creation unit 31 divides the printed circuit board into a plurality of design areas, assigns a design area to each designer who is in charge of each client terminal device, and creates instruction information that instructs the design order for each design area. Design area instruction creation unit 32 that performs connection, connection order instruction creation unit 33 that creates instruction information for instructing the connection order for wiring to be connected via three or more component pins, and wiring that should secure a wiring route with priority A priority wiring instruction creating unit 34 for creating instruction information for instructing, a wiring route instruction creating unit 35 for creating instruction information such as a wiring position or a wiring layer on the printed circuit board, and a wiring mode instruction in a text format A sentence format instruction creating unit 36 for creating instruction information to be provided is provided.

  The server CAD control unit 40 controls the server CAD device 10 to operate the preparation information display unit 47 and the instruction information creation unit 31 that display the design information 21 and the placement and routing data 28 on the display device 52. 41 includes an instruction information storage unit 48 that stores 41 in the database 20 managed by the server CAD device 10 and an instruction information notification unit 49 that notifies the client terminal devices 11 to 13 that the instruction information 41 has been created.

  In the printed circuit board design support system 100 according to the present embodiment, the main designer S operates the server CAD device 10 and uses the instruction information processing device 30 to classify design areas and design positions (layouts) of wiring. The instruction information 41 etc. regarding etc. is created. At this time, the main designer S can create the instruction information 41 while referring to the design information 21 and the placement / wiring data 28 of the database 20 displayed on the display device 52. Thereafter, the instruction information processing apparatus 30 stores the created instruction information 41 in the database 20 and notifies the client terminal apparatuses 11 to 13 that the instruction information 41 has been created.

  The client terminal devices 11 to 13 can refer to the instruction information 41 stored in the database 20 managed by the server CAD device 10 via the network 55 using the instruction information reference units 14 to 16 provided respectively. it can. Similarly, the client terminal devices 11 to 13 can also refer to the design information 21 stored in the database 20. Therefore, the designers A to C who use each of the client terminal devices 11 to 13 can design the printed circuit board by editing the placement / wiring data 28 with reference to the instruction information 41 and the design information 21. .

  Therefore, according to the printed circuit board design support system 100 having the above-described configuration, the designers A to C operating the client terminal devices 11 to 13 use the instruction information 41 created by the skilled main designer S. By referring to the layout / wiring data 28, it is possible to efficiently edit the arrangement / wiring data 28 while reducing the interference and contradiction of the editing contents generated between the designers. That is, by using the printed circuit board design support system 100 by the designers A to C, component placement design and wiring design of one printed circuit board can be performed simultaneously and efficiently. Further, it is preferable that the main designer S can be set in an environment in which the placement / wiring data 28 can be edited in the same manner as the other designers A to C.

  Next, the processing operation of the instruction information processing apparatus 30 will be described. FIG. 3 is a flowchart illustrating processing using the instruction information processing apparatus 30 according to the first embodiment. In addition, the blocks (31 and 40) surrounded by a broken line in FIG. 3 represent processing using the instruction information creation unit 31 and the server CAD control unit 40, respectively. Here, in the database 20, as the design information 21 input at the stage of design preparation, for example, the outer shape of the printed circuit board, the configuration of the wiring layer, the component placement region, the wiring prohibited region, the component height limited region, etc. Board information 23, electronic component external dimensions necessary for component layout design, component information 24 related to the shape and dimensions of lead pads attached to electronic components, connection information 25 related to wiring connections between electronic components, and vias Wiring specification information 26 relating to design restrictions such as holes, wiring widths, wiring intervals, and the like, and wiring layer attributes are stored in advance. Furthermore, it is assumed that the layout / wiring data 28 and the like in which the main designer S uses the server CAD device 10 and preferentially places and designs the main electronic components based on the design information 21 are stored in the database 20. .

  In addition, the main electronic components that are preferentially placed and designed in the actual parts placement design are referred to as QFP (quad flat package) and BGA (ball grid array), which are highly integrated circuits, etc., which have many pins and a large number of wiring connections. Dumping whose placement position is determined by restrictions on high-frequency circuits, such as package ICs, large capacitors whose placement positions are limited due to large size and placement height, coils and crystal oscillator parts A resistor, a bypass capacitor disposed near the IC and stabilizing the power supply to the IC, a termination resistor, and a connector for electrical connection to the outside of the printed circuit board.

  First, in step S101, the server CAD control unit 40 causes the display device 52 to display the layout / wiring data 28 on which the layout design of the main electronic components has been performed and the image information of the design information 21 in a superimposed manner. FIG. 4 shows an outline of the entire printed circuit board as an example of the display contents. In this schematic display, QFP 62, SOP (small outline package) 63, bypass capacitor 65, large capacitor 66 and connector 67, which are the main electronic components that are preferentially placed in placement / wiring data 28, are printed circuit boards. 60, the SOP 64 and the bypass capacitor 65 are arranged on the back surface. That is, FIG. 4 shows that the electronic component with the pattern is arranged on the back surface. Further, this display includes a broken line 61 indicating a wiring connection state between component pins based on the connection information 25 of the design information 21 called ratsnest. This ratsnest is displayed as a line segment connecting the component pins of the electronic component. That is, as shown in FIG. 4, the server CAD control unit 40 superimposes the design information 21 and the placement / wiring data 28 and displays them on the display device 52 as the image information 101. These component arrangements were previously designed by the main designer S and stored in the database 20 as the arrangement / wiring data 28.

In step S103, the main designer S operates the design area instruction creation unit 32 to divide the printed circuit board into a plurality of design areas and create design area instruction information 42 such as assigning to a plurality of designers. The design area instruction information 42 includes
(1) Instruction information that divides a printed circuit board into a number of design areas that can be assigned one or more design areas for each designer of the client terminal devices 11 to 13 and designates a designer in charge for each design area; And (2) Instruction information indicating the order of designing for each design area is included. When designating the design order, if any one of the design areas is designated as the first design area, the first design area is designated as the design order 1 of the first designer, and the first design area is designated as the first design area. By designating any one design area that is not adjacent to one design area as the design order 1 of the second designer, it is possible to prevent design work from occurring simultaneously when the design areas between different designers are adjacent. To reduce interference between the two. At this time, the main designer S considers the functional blocks of the circuit, the number of wirings, etc., and considers the capabilities of the designers A to C of the client terminal devices 11 to 13 to efficiently design the printed circuit board. It is preferable to divide the design area that can be completed earliest and assign it to the designers A to C.

  FIG. 5 is a diagram showing the contents of the created design area instruction information 42. The actual state of creation of the design area instruction information 42 is based on the image information 101 displayed on the display device 52 by the main designer S in step S101 and interactively classifies the area into the printed circuit board 60 using the input device 51. The figure of the line 70 is created and the printed circuit board is divided into a plurality of design areas. Then, in each design area, a figure of the tag 71 is created in which the names of designers (A to C) in charge of the design area and the design order (1 to 3) of the design area are entered. In the example shown in FIG. 5, the wiring area of the printed circuit board is divided into eight design areas consisting of A1 to A3, B1 to B3, and C1 to C2, and assignment to designers A to C is shown. Yes.

  Here, the instruction content indicated by the tag 71 will be described. For example, the design area in which B2 is written in the tag is assigned to the designer B, and indicates that the design area to be designed is the second of the three design areas assigned to the designer B. Therefore, the designer A is instructed to assign the three design areas and design the design areas A1, A2, and A3 in order, and the designer B is assigned the three design areas and the design area B1. , B2, and B3 are instructed in order. Similarly, the designer C is assigned two design areas and instructs to design the design areas C1 and C2 in order.

  Further, the design order of each design area is determined by the main designer S with the intention of reducing the interference generated during the design work among the designers. In the example shown in FIG. 5, the design area A1 of the design order 1 is assigned to the designer A as the first design area, and as an arbitrary one design area that is not adjacent to the first design area that is the design area A1. Design area B1 is assigned as design order 1 of designer B. The main designer S may set the design area B1 and the design area B2 interchangeably.

  When such setting is made by the main designer S, the designer A starts design from the design area A1 in accordance with the design order instruction. Further, the designer B who is in charge of designing the adjacent design area B3 starts designing from the design area B1 according to the design order instruction information. That is, the area designed by the designer A and the area designed by the designer B are not adjacent to each other. Therefore, the designer A can preferentially design the wiring that straddles the boundary between the design area A1 and the design area B3 without considering interference and contradiction with the designer B. Thereafter, when the designer B designs the design region B3, the design of the wiring over the boundary between the design region A1 and the design region B3 by the designer A has already been completed up to this boundary. Therefore, when designing the design region B3, the designer B considers the position of the end of the wiring to the boundary where the designer A has finished designing. That is, the designer B performs wiring design so that the end of the predetermined wiring in the design area B3 is connected to the end of the wiring already designed by the designer A. For this reason, the wiring design in the design region B3 can be efficiently executed without interfering with the wiring design by the designer A. The main designer S sets the same design order relationship at the boundary between the design area B1 and the design area C2 and at the boundary between the design area C1 and the design area A3.

  By instructing the design order of the design areas in this way, it is possible to reduce the occurrence of interference and contradictions between designers and to perform quick and efficient placement / wiring design. Note that this design area does not determine the editing exclusivity of the responsible designers A to C or the editing exclusivity of other designers. Therefore, the design contents of the design area assigned to other designers are differently designed. It is possible for a person to edit.

  Thus, the design area instruction information 42 created in step S103 is image information including the area division line 70, the graphic of the tag 71, and their position data, and is the image information displayed on the display device 52 in step S101. 101 is the image information to be overlaid on 101.

  In the next step S105 to step S111, the main designer S operates the instruction information creation unit 31 to instruct the connection order of the wiring in each part of the printed circuit board, the order of the priority wiring, the position of the wiring route, Instruction information relating to the wiring layout, such as instructions for the wiring layer and instructions regarding the wiring itself and the mutual form of the wiring, is created. That is, in these steps, the main designer S creates instruction information common to all the designers A to C in charge of the client terminal devices 11 to 13 without depending on the design area. In the present embodiment, such accurate instruction information is transmitted to the designers A to C of the client terminal devices 11 to 13, thereby enabling a quick and reliable design of a printed circuit board.

  In step S105, the main designer S operates the connection order instruction creating unit 33 to create the connection order instruction information 43. The connection order instruction information 43 is information for instructing the connection form or connection order of signal wirings to be connected via three or more component pins. If this connection order is not appropriate, problems such as time delay and increased noise occur in signal transmission of high-speed bus wiring and high-frequency clock wiring, and the printed circuit board may not operate normally.

  FIG. 6 is a diagram illustrating an example of creating the connection order instruction information 43. FIG. 6A shows the image information 101 displayed in step S101 enlarged in the substantially central part of the printed circuit board 60 shown in FIG. The ratsnest based on the connection information 25 of the four signal buses connecting the three electronic components 81, 82, and 83 is automatically displayed as a virtual wiring of the line segment that connects the component pins 609 of each electronic component in the shortest time. ing. That is, for example, a ratsnest 84 that connects between the component pins 609 of the electronic component 81 and the electronic component 83 and a ratsnest 85 that connects between the component pins 609 of the electronic component 83 and the electronic component 82 are drawn. Each wiring is a wiring that passes through three component pins 609. However, the correct connection order according to the regulations on the circuit diagram may require a connection order of wiring from the electronic component 81 to the electronic component 82 and further from the electronic component 82 to the electronic component 83. In this case, the ratsnests 84 and 85 that have been automatically operated are different from the correct connection order. In such a case, as shown in FIG. 6B, the main designer S, as shown in FIG. 6B, the arrow graphic 86 from the electronic component 81 to the electronic component 82 and the electronic component 82 in order to accurately indicate the connection order. An arrow graphic 87 is drawn from the head toward the electronic component 83. In the arrow graphic 86, four signal buses extending from the component pin 609 of the electronic component 81 are connected to a predetermined component pin 609 of the electronic component 82, and the arrow graphic 87 is formed of four signals extending from the component pin 609 of the electronic component 82. The signal bus is instructed to be connected to a predetermined component pin 609 of the electronic component 83.

  By performing such drawing, accurate instruction information (FIG. 6B) regarding the wiring order is instructed to the designers A to C of the client terminal devices 11 to 13. As a result, the designers A to C of the client terminal devices 11 to 13 can easily perform correct design. The example shown in FIG. 6 relates to the instruction information of the wiring that straddles the design area C1 and the design area B2. However, it is preferable to create the connection order instruction information 43 for the wiring that only fits in one design area.

  Thus, the connection order instruction information 43 created in step S105 is image information including the arrow graphics 86 and 87 for instructing the connection order and their position data, and the image displayed on the display device 52 in step S101. This is image information to be overlaid with the information 101.

  In step S107, the main designer S operates the priority wiring instruction creation unit 34 to create the priority wiring instruction information 44. The priority wiring instruction information 44 is information for instructing to design a specific wiring with priority over other wirings. For example, a special wiring rule on an electric circuit is required for a clock signal wiring, a bundle wiring that forms a high-speed bus signal, and the like, and it is necessary to design a wiring route in preference to other wiring. Therefore, in step S107, preferential design instruction information for such specific wiring is created.

  FIG. 7 is a diagram illustrating an example of creating the priority wiring instruction information 44. FIG. 7 corresponds to instruct the main designer S to preferentially design a specific wiring based on the printed circuit board 60 shown in FIG. 4 which is the image information 101 displayed in step S101. A figure in which number graphics 701, 702 and 703 are arranged in each of the ratsnests is shown. The ratsnest in which the number graphic 701 and the number graphic 702 are arranged corresponds to the transmission wiring of the high-frequency clock signal, and for these ratsnest, a wiring route is secured in preference to the wiring in which the number graphic is not arranged. At the same time, it is instructed to design in the order of the numbers entered in the number figures 701 and 702. That is, the ratsnest in which the number graphic 701 written with “1” is arranged secures the wiring route by designing the wiring prior to the seven ratsnests 601 intersecting with this, and the number written with “2”. The ratsnest in which the figure 702 is arranged instructs to secure the wiring route by designing the wiring before the five ratsnests 602 intersecting with the ratsnest. Each of the four ratsnests in which the number graphic 703 marked “3” is arranged corresponds to a bus signal wiring, and instructs to design them all at the same time. It is instructed to secure the wiring path before the ratsnest 603.

  Thus, the priority wiring instruction information 44 created in step S107 is image information including number graphics 701, 702 and 703 for instructing priority wiring and their position data, and is displayed on the display device 52 in step S101. This is image information to be overlaid with the image information 101 made.

  In step S109, the main designer S operates the wiring route instruction creating unit 35 to create the wiring route instruction information 45. The wiring route instruction information 45 is information including a graphic designating a wiring route, a wiring position, a wiring layer, or the like in the planned wiring space when the main designer S designs the arrangement of main electronic components. . By following these instruction information by the designers A to C of the client terminal devices 11 to 13, even an inexperienced designer can quickly perform a high quality design without hesitation.

  FIG. 8 is a diagram illustrating an example of creating the wiring route instruction information 45. FIG. 8A is an enlarged view of the substantially upper center portion of the printed circuit board 60 shown in FIG. 4 which is the image information 101 displayed in step S101. FIG. 8B shows the wiring route instruction information 45 superimposed on FIG. 8A.

  In FIG. 8B, two bent line figures 706 indicate the design positions of the four bundle wirings in parallel of the rats nest 607 that connect between the component pins of the electronic component 610 and the electronic component 611. This is a graphic drawn by the designer S based on his own experience. Specifically, FIG. 8B indicates that the two outside wires in the four bundle wires should be designed in the path indicated by the two bent line figures 706, and the two inside wires in the bundle wire are designated. This wiring indicates that wiring is performed in parallel at equal intervals in a portion sandwiched between two bent line figures 706. It should be noted that the path from the left end of the bent line graphic 706 to the component pin 609 of the electronic component 610 and the path from the right end of the bent line graphic 706 to the component pin of the electronic component 611 are not directed during this period. This is because ˜13 designers A to C can easily design without any instruction.

  In FIG. 8B, figures 707, 708, and 709 are also figures drawn by the main designer S based on their own experience. These figures 707 to 709 are formed on the printed circuit board 60 via via holes that are provided with four bundle wires from the four component pins 609 on the lower right side of the electronic component 610 arranged on the surface of the printed circuit board 60. The wiring route to the component pin 609 on the left side of the electronic component 612 arranged on the back surface is designated. Two parallel line figures 707 indicate the design position of the wiring path on the surface of the printed circuit board 60 of the four bundle wiring. Further, a rectangular broken line graphic 708 on the right side indicates a position to provide a via hole for passing each of the four bundle wires from the surface layer to the back layer. Two parallel line figures 709 on the right side indicate the design position of the wiring path in the back layer of the four-bundle wiring. In this way, the position, route and wiring layer where the main wiring should be designed can be indicated by simple graphic information. In addition, it is preferable that the relationship between the figure to be displayed and the instruction content is determined in advance and shared among the designers.

  In this way, the wiring route instruction information 45 created in step S109 is an image including two bent line figures 706, two parallel line figures 707, rectangular broken line figures 708, two parallel line figures 709, and their position data. Information that is superimposed on the image information 101 displayed on the display device 52 in step S101.

  In step S111, the main designer S operates the text format instruction creating unit 36 to create the document format instruction information 46. The document format instruction information 46 is instruction information for performing the design of the wiring to be designed, etc., in a text format, instead of the graphic instruction information as described above.

  FIG. 9 is a diagram showing an example of creating the document format instruction information 46. FIG. 5 shows an excerpt of electronic components related to the description of the document format instruction information 46 from the image information 101 shown in FIG. The wiring designated by the main designer S as the document format instruction information 46 corresponds to both the rats nest 618 extending from the connector 615 and the rats nest 619 connected to the QFP 617 in FIG. Is a power signal wiring for supplying a power signal from QFP 617 to a QFP 617 via a component pin of QFP 616. Here, a wiring name “VC1” is attached to the power signal wiring.

  In this example, the main designer S envisions the wiring of the power supply signal wiring VC1 as follows. Rats nest 618 is a wiring for supplying power to two QFPs 616 and QFP 617, and the wiring pattern width is determined to be 0.30 mm from a current instruction value in a circuit diagram or the like. In the wiring area of the ratsnest 619, a large number of component pins 609 of two QFPs 616 and 617 are close to each other, and a high wiring density is required. For this reason, in this region, the wiring pattern width of the rats nest 619 is set to the minimum value of the allowable range. That is, since the necessary power supply currents of the two QFPs 616 and 617 are the same, the wiring pattern width of the rats nest 619 that supplies power only to the QFP 617 is determined to be 0.15 mm (half the wiring pattern width of the rats nest 618).

  The contents of the text format instruction information 46 for accurately instructing the information designed by the main designer S to the designers A to C of the client terminal devices 11 to 13 are the display device 52 and the client terminal devices 11 to 13. In such a display device, the program is designed so that the cursor appears on the broken line of the ratsnest 618 or 619 of the signal line VC1 using a mouse or the like so that it appears as sentence format information 620 in the balloon frame as shown in FIG. Has been. The text of the text format information 620 indicates that “the wiring pattern width of the power supply signal wiring VC1 is 0.30 mm for the connectors 615 to 616 and 0.15 mm for the QFPs 616 to 617. ”Is input by the main designer S, and the content is instruction information about the wiring mode such as the connection order of the power signal wiring and the wiring pattern width. The designers A to C of the client terminal devices 11 to 13 can efficiently design the power supply signal wiring VC1 with high quality by referring to the instruction information.

  As described above, the document format instruction information 46 created in step S111 is image information of a balloon frame in which a sentence of instruction contents is displayed, which is displayed when the cursor is placed on the line representing the ratsnest.

  When the instruction information is created by the main designer S, the server CAD control unit 40 stores the instruction information created in steps S103 to S111 as instruction information 41 in the database 20 in step S113. FIG. 10 is a diagram illustrating an example of an image superimposed on the instruction information 41 and the image information 101 displayed on the display device 52 in step S101. Note that the instruction information created each time the steps in steps S103 to S111 are completed may be stored in the database 20.

  In the next step S115, the server CAD control unit 40 controls the server CAD device 10 to notify all the client terminal devices 11 to 13 that new instruction information 41 has been created and stored in the database 20. As a result, the designers A to C of the client terminal devices 11 to 13 know that the instruction information 41 for designing the target printed circuit board 60 is stored in the database 20 by this notification, and the client terminal devices The instruction information 41 can be referred to via the network 55 and the server CAD device 10 using each of the instruction information reference units 14 to 16 of 11 to 13. Then, the designers A to C design the printed circuit board 60 in parallel while referring to the image information shown in FIG.

  Thus, the processing operation of the instruction information processing apparatus 30 ends. Note that the order of creation of the instruction information described above is an example, and the order of creation of the five instruction information in steps S103 to S111 is not fixed. Further, it is possible to reduce the instruction information to be created due to the complexity and difficulty of the wiring design of the printed circuit board 60. In addition, the instruction information 41 does not have to be a design instruction for all wirings or all component placements, and an uninstructed part is made based on the skills and discretion of each designer A to C. Is possible.

  The contents of the design work symbolically indicated by the image information and graphics included in each instruction information are organized in advance between the main designer S and the designers A to C of the client terminal devices 11 to 13. However, it is preferable to have a common recognition.

  According to the present embodiment, the designers A to C who operate the client terminal devices 11 to 13 through the processing in the instruction information processing device 30 described above can receive the design information 21 via the network 55 and the server CAD device 10. While referring to the instruction information 41, the design area assigned to itself of the placement / wiring data 28 can be quickly edited without interfering with other designers. Therefore, based on such an environment, a plurality of designers A to C can efficiently and simultaneously perform the wiring design of the target printed circuit board 60 with high quality.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. The second embodiment is targeted by the designers A to C who operate the client terminal devices 11 to 13 based on the instruction information 41 created using the printed circuit board design support system 100 according to the first embodiment. After the design of the printed wiring board 60 to be started is started, the design of the entire arrangement / wiring data 28 already edited by the designers A to C of the client terminal devices 11 to 13 by the main designer S according to the progress of the design. This is related to a process of reviewing the instruction information 41, creating new instruction information for an unwired portion, etc., and updating the instruction information 41. Examples of cases where such processing is necessary include (1) when there is a significant difference in design progress between designers, and (2) between undesignated parts and designers in the first embodiment. The case where the wiring design of the interfering part etc. is stagnant is mentioned.

  FIG. 11 is a flowchart illustrating processing using the instruction information processing apparatus 30 according to the second embodiment. Note that blocks (31 and 40) surrounded by a broken line in FIG. 11 represent processing using the instruction information creation unit 31 and the server CAD control unit 40, respectively, as in FIG.

  First, in step S151, the main designer S obtains the placement / wiring data 28 designed or edited up to that point, and the instruction information 41 and the design information 21 created and stored in the database 20 in the first embodiment. The data is displayed on the display device 52 using the server CAD control unit 40.

  Then, in steps S153 to S161, based on the information displayed on the display device 52 by the main designer S, the design progress, unwired part, defective design part, and between designers based on the arrangement / wiring data 28 at that time. After grasping the interference and the like, the design area instruction information 42, the connection order instruction information 43, the priority wiring instruction information 44, the wiring route instruction information 45, and the text format instruction information 46 are corrected as in the first embodiment.

  In step S163, the corrected instruction information is stored in the database 20 as new instruction information 41. Thereafter, in step S165, the client terminal device is notified that the new instruction information 41 has been stored in the database.

  According to the present embodiment, even when there is a significant difference in progress, or when the wiring design such as an interfering portion between designers is stagnant, the new instruction information 41 is stored in a plurality of directions. By referring to the designers A to C of the client terminal devices 11 to 13 in the same manner as in the first embodiment, the wiring design of the target printed circuit board 60 can be advanced simultaneously and efficiently with high quality. It becomes. The review and correction of the instruction information at the stage where the design has progressed is performed based on the judgment of the main designer S or the requests from the designers A to C of the client terminal devices 11 to 13. And implementation time can be implemented without any restrictions.

  Note that the flowchart shown in FIG. 3 (first embodiment) and the flowchart shown in FIG. 11 (second embodiment) in the embodiment of the present invention can be realized by, for example, a computer executing a program. Also, means for supplying a program to a computer, for example, a computer-readable recording medium such as a CD-ROM recording such a program, or a transmission medium such as the Internet for transmitting such a program is also applied as an embodiment of the present invention. Can do. The above program can also be applied as an embodiment of the present invention. The above program, recording medium, transmission medium, and program product are included in the scope of the present invention.

  According to the present invention, a design area of a printed circuit board targeted by a plurality of designers is divided, and a plurality of designers design simultaneously, thereby reducing design time. It can also be used effectively when a skilled designer OJTs a beginner designer (training to acquire knowledge and techniques necessary for work at the work site).

1 is a block diagram showing a configuration of a printed circuit board design support system 100 according to an embodiment of the present invention. 3 is a functional block diagram showing a functional configuration of an instruction information processing apparatus 30. FIG. It is a flowchart which shows the process using the instruction | indication information processing apparatus 30 in 1st Embodiment. It is a figure which shows the content of the design information. It is a figure which shows the content of the design area instruction | indication information. It is a figure which shows the content of the connection order instruction information 43. FIG. FIG. 4 is a diagram showing the contents of priority wiring instruction information 44. 7 is a diagram showing the contents of wiring route instruction information 45. FIG. 5 is a diagram showing the contents of document format instruction information 46. FIG. It is a figure which shows the example of the image superimposed on the instruction information 41 and the image information 101. FIG. It is a flowchart which shows the process using the instruction | indication information processing apparatus 30 in 2nd Embodiment.

Explanation of symbols

S: Main designer A, B, C: Client terminal device designer 10: Server CAD device 11, 12, 13: Client terminal device 14, 15, 16: Instruction information reference unit 20: Database 21: Design information 28: Arrangement / wiring data 30: Instruction information processing device 31: Instruction information creating unit 39: Interface unit 40: Server CAD control unit 41: Instruction information 51: Input device 52: Display device 53: Storage medium drive 55: Network 60: Print circuit Board 61: Rats nest 70: Area division line 71: Tag 100: Printed circuit board design support system 101: Image information 609: Component pin

Claims (15)

A printed circuit board design support method for supporting design of one printed circuit board by a plurality of designers,
An instruction information creating step for creating instruction information including information on a design area and / or wiring layout of each of the plurality of designers based on the placement / wiring data on which the placement design of the electronic component is performed,
An instruction information storage step of storing the instruction information in a database;
An instruction information notification step of notifying the client terminal device used by the plurality of designers that the instruction information has been created;
A printed circuit board design support method characterized by comprising:   The information related to the design area includes information that divides the printed circuit board into a plurality of design areas, assigns one or more design areas for each designer, and instructs the design order of each design area. The printed circuit board design support method according to claim 1.   3. The design support for a printed circuit board according to claim 2, wherein the information on the design area includes information that design orders are different from each other for adjacent design areas assigned to different designers. Method.   4. The information on the wiring layout includes information indicating a connection order of wirings connected via three or more component pins of different electronic components. A printed circuit board design support method according to claim 1.   5. The printed circuit board design according to claim 1, wherein the information related to the layout of the wiring includes information indicating a wiring that secures a wiring route in preference to another wiring. 6. Support method.   6. The printed circuit board design support method according to claim 1, wherein the information relating to the wiring layout includes information indicating at least one of a wiring design position and a wiring layer. . An editing step of editing the placement / wiring data based on the result of the design by the designer using the client terminal device;
Correcting the instruction information based on the edited placement / wiring data;
Storing the corrected instruction information in the database;
Notifying the client terminal device that the instruction information has been modified;
The printed circuit board design support method according to claim 1, further comprising: A printed circuit board design support system for supporting the design of one printed circuit board by a plurality of designers,
An instruction information creating means for creating instruction information including information on a design area and / or a wiring layout which each of the plurality of designers is in charge of, based on the placement / wiring data in which the placement design of the electronic component is performed;
Instruction information storage means for storing the instruction information in a database;
Instruction information notification means for notifying the client terminal device used by the plurality of designers that the instruction information has been created;
A printed circuit board design support system characterized by comprising:   The information related to the design area includes information that divides the printed circuit board into a plurality of design areas, assigns one or more design areas for each designer, and instructs the design order of each design area. The printed circuit board design support system according to claim 8.   10. The design support for a printed circuit board according to claim 9, wherein the information on the design area includes information that the design order is different between adjacent design areas assigned to different designers. system.   11. The information on the layout of the wiring includes information indicating a connection order of wirings to be connected via three or more component pins of different electronic components. The printed circuit board design support system described in 1.   12. The printed circuit board design according to claim 8, wherein the information relating to the layout of the wiring includes information indicating a wiring that secures a wiring path in preference to another wiring. 13. Support system.   13. The printed circuit board design support system according to claim 8, wherein the information on the layout of the wiring includes information indicating at least one of a wiring design position and a wiring layer. .   14. The printed circuit board design support according to claim 8, wherein the client terminal device includes instruction information reference means for referring to the instruction information of the database via a network. system. A program that allows a computer to support the design of one printed circuit board by a plurality of designers,
On the computer,
A procedure for causing the display device to display layout / wiring data including design information as a reference for designing the printed circuit board and layout design information of the electronic components;
The printed circuit board is divided into a plurality of design areas, and one or more design areas are allocated for each designer, and the adjacent design areas assigned to different designers have different design orders. A procedure for causing the user to input the first instruction information
A procedure for causing a user to input second instruction information for instructing a connection order of wirings connected via three or more component pins of different electronic components;
A procedure for causing the user to input third instruction information for instructing a wiring that secures a wiring route in preference to other wiring;
A procedure for causing a user to input fourth instruction information for instructing at least one of a wiring design position and a wiring layer;
An instruction information storage procedure for storing the first to fourth instruction information in a database;
An instruction information notification procedure for notifying client terminal devices used by the plurality of designers that the first to fourth instruction information has been created;
A program characterized by having executed.

Images