JP2009283657A - Layout generating apparatus and layout designing method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout designing method of a semiconductor integrated circuit which actualizes the suppression of development cost and the shortening of development period, by suppressing the number of mask change to the minimum when a circuit change occurs. <P>SOLUTION: A layout generating apparatus of the semiconductor integrated circuit which generates the layout of every each layer of the semiconductor integrated circuit of multilayer structure based on the connection information of an integrated circuit, has a connection information input means to receive the input of the connection information of the integrated circuit, a standard layout data input means to receive the input of a standard layout data generated based on the connection information of other integrated circuits, a modification layout generating means to generate a new layout performing the modification of a layout constituting a standard layout based on the input connection information, and a modifiable layer assigning means which assigns the modifiable layer of the standard layout when the modification layout generating means performs the layout modification. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a layout design apparatus and layout design method for a semiconductor integrated circuit.

  A semiconductor integrated circuit is manufactured using a plurality of masks in each process such as etching, ion implantation, and wiring formation. If a circuit change occurs at the design stage of the semiconductor integrated circuit, the layout of the cell arrangement, the wiring connection state, etc. is examined according to the change, and a corresponding mask pattern of one layer or two or more layers is newly added. It has been designed and responded to.

  FIG. 1 is a flowchart showing a conventional design change procedure when a circuit change occurs in the layout design of a semiconductor integrated circuit.

  The layout design of the semiconductor integrated circuit is performed using an automatic placement and routing apparatus. Automatic placement and routing equipment is part of EDA (Electronic Design Automation), and automatically places macro cells based on macro cell connection information (ie, logic circuit design results) by an internal program, and automatically between each cell. An apparatus that automatically generates a layout on a semiconductor chip by performing wiring.

  First, the previous layout data before the circuit change is read into the automatic placement and routing apparatus (S101). Next, connection information (net list) of the integrated circuit after the circuit change is input to the automatic placement and routing apparatus (S102).

  Next, the automatic placement and routing apparatus rearranges, deletes, and adds cells based on the connection information (net list) of the changed circuit (S103). For cells that do not correspond to the changed portion, the same arrangement as before the circuit change is maintained. Thereafter, the automatic placement and routing apparatus performs wiring between the cells whose placement has been determined (S104). At this time, for the wiring between cells not corresponding to the changed portion, the wiring is formed so as to maintain the state before the change as much as possible.

  Next, timing verification, SI (Signal Integrity) verification such as crosstalk and IR drop, and power verification are performed on the newly generated layout (S105). Note that crosstalk means that the signal of one wiring is superimposed on the signal of the other wiring due to electromagnetic coupling generated between the wirings. An IR drop refers to a potential drop due to a resistance component of wiring. IR drop often becomes a problem with power lines. As a result of the verification, if it is confirmed that there is no problem in each verification item, the layout data before and after the circuit change is compared, and the mask data of the layer that will change with the circuit change Is extracted (step S106). For layers that do not need to be changed before and after the circuit change, the previously created mask data is maintained as it is. That is, for the layer that does not change, the previously designed mask is used as it is.

Finally, the changed mask data is output and this routine is terminated (step S107). On the other hand, if it is determined in step S105 that there is a problem, a wiring process (step S104), a cell rearrangement process (step S103), a netlist input process (step) Returning to S102), the design is started again.
Japanese Patent Laid-Open No. 10-125792 Japanese Patent Laid-Open No. 11-67917

  However, according to the design change procedure using the above-described conventional automatic placement and routing apparatus, there is no restriction on the number of masks that will cause the change, so there is a possibility that the entire metal wiring layer is always changed. Increasing the number of masks to be changed results in an increase in mask cost and an increase in design period accompanying an increase in the mask manufacturing period. Further, when the number of change masks increases, there is a higher risk that good results cannot be obtained in SI verification, timing verification, and power verification than before the change. As a result, there is an increased risk of reworking, such as a review of the layout and, in the worst case, a review required after changing the circuit (creating a netlist), which also leads to an increase in the design period. .

  The present invention has been made in view of the above points, and by suppressing the number of change masks when a circuit change occurs in the layout design of a semiconductor integrated circuit, the development cost is reduced and the development period is shortened. An object of the present invention is to provide a semiconductor integrated circuit layout generation apparatus and a semiconductor integrated circuit layout design method for realizing the above.

  A layout generation apparatus for a semiconductor integrated circuit according to the present invention is a layout generation apparatus for a semiconductor integrated circuit that generates a layer layout for each layer of a semiconductor integrated circuit having a multilayer structure based on connection information of the integrated circuit. Connection information input means for receiving input of connection information, and reference layout data input means for receiving input of reference layout data corresponding to a reference layout generated based on connection information of another integrated circuit different from the connection information A modified layout generating means for generating a new layout by changing the layout of at least one layer layout constituting the reference layout based on the input connection information, and the changed layout generating means At least one layer layout of the reference layout to be performed A changeable layer designating means for designating a layout of the semiconductor integrated circuit, wherein the modified layout generating means changes the layout only for the layer layout designated by the changeable layer designating means Generator.

  A layout design method for a semiconductor integrated circuit according to the present invention is a layout design method for a semiconductor integrated circuit that designs a layer layout for each layer of a semiconductor integrated circuit having a multilayer structure based on connection information of the integrated circuit, A connection information input step for receiving input of connection information of the integrated circuit; a reference layout data input step for receiving input of reference layout data corresponding to a reference layout generated based on other connection information different from the connection information; Based on the input connection information, at least one layer layout constituting the reference layout is subjected to layout change to generate a new layout, and in the changed layout generation step, the layout change is performed. At least one layer layout to do A changeable layer designating step for designating, wherein the modified layout generating step is a step of changing the layout only for the layer layout designated in the modifiable layer designating step. Layout design method.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, substantially the same or equivalent components or parts are denoted by the same reference numerals.

(First embodiment)
FIG. 2 is a block diagram showing the configuration of the semiconductor integrated circuit layout generation apparatus according to the first embodiment of the present invention. The circuit connection information input unit 10 is a part that receives input of connection information (net list) between terminals of an already created integrated circuit and reads this into the apparatus. When the circuit is changed and the layout design after the change is performed, the circuit connection information input unit 10 reads the connection information of the changed circuit. The input of the connection information of the integrated circuit can be performed, for example, by inputting a created circuit diagram of the integrated circuit. The input integrated circuit connection information is supplied to the automatic placement and routing unit 33 described later.

  The reference layout data input unit 20 is a part that receives input of reference layout data corresponding to a previously created layout before circuit change (hereinafter referred to as a reference layout). The reference layout data input unit 20 reads the data by reading the data from a recording medium inside or inside the apparatus that stores the reference layout data. The inputted reference layout data is supplied to the automatic placement and routing unit 33 described later. Note that the reference layout is a combination of layouts (hereinafter referred to as layer layouts) of a plurality of layers constituting a semiconductor integrated circuit having a multilayer structure.

  The changed layout generation unit 30 performs layout for at least one layer layout constituting the reference layout before the circuit change based on the connection information of the changed circuit under the constraint condition specified by the constraint condition specifying unit 31 described later. By making a change, one or more new layouts reflecting the changed circuit are generated. The modified layout generating unit 30 includes a constraint condition specifying unit 31, a modified mask extracting unit 32, an automatic placement and routing unit 33, a verification unit 34, a modified layout data storage unit 35, and a selection unit 36.

  The constraint condition designating unit 31 is a part that designates a constraint condition related to a mask change accompanying a circuit change. For example, the constraint condition specifying unit 31 directly sets the allowable number of change masks when changing the layout and the mask name that can be changed based on an instruction from the user. give.

  The change mask extraction unit 32 extracts all the combinations of change masks that satisfy the constraint conditions specified by the constraint condition specification unit 31 and supplies the extracted combinations to the automatic placement and routing unit 33.

  The automatic placement and routing unit 33 is a part of EDA (Electronic Design Automation), and automatically arranges macrocells based on macrocell connection information (ie, logic circuit design results) by an internal program, and automatically between each cell. The layout on the semiconductor chip is automatically generated by performing wiring. The automatic placement and routing unit 33 configures a reference layout based on integrated circuit connection information (net list) and reference layout data before circuit change supplied from the circuit connection information input unit 10 and the reference layout data input unit 20. A layout change is performed on at least one layer layout. At this time, the automatic placement and routing unit 33 performs layout generation by limiting the layers whose layout is changed based on each combination of change masks provided from the change mask extraction unit 32.

  The verification unit 34 performs timing verification, SI verification, and power verification on the layout of the changed circuit generated by the automatic placement and routing unit 33, determines whether or not the required specifications are satisfied for each verification item, and reports a verification result report create.

  The changed layout data storage unit 35 stores, as changed layout data, an internal recording medium that satisfies the required specifications as a result of verification by the verification unit 34 among the changed circuit layouts generated by the automatic placement and routing unit 33.

  When two or more pieces of changed layout data are stored in the changed layout data storage unit 35, the selection unit 36 selects one of them. The selection unit 36 selects changed layout data based on a user instruction, for example.

  The output unit 40 is a part that outputs the changed layout data selected by the selecting unit 36 as changed mask data.

  FIG. 3 shows a case in which when a circuit change occurs in the layout design of a semiconductor integrated circuit, the layout generation apparatus of the present invention having the above-described configuration generates a new layout reflecting the change circuit and obtains change mask data. It is a flowchart which shows each process.

  First, the reference layout data input unit 20 reads the previous layout data before the circuit change as reference layout data (step S10). The read reference layout data is used as a base for layout generation by the automatic placement and routing unit 33, and the layout of the changed circuit is generated in such a manner that the reference layout is changed or corrected.

  Next, the circuit connection information input unit 10 receives the input of the connection information (net list) of the changed circuit by a method such as input of a circuit diagram and reads it (step S20).

  Next, the changed layout generation unit 30 changes the layout of the layer layout constituting the read reference layout based on the connection information (net list) of the changed circuit under the specified constraint condition. A new layout reflecting the circuit is generated (step S30).

  Next, the output unit 40 outputs the new layout generated by the changed layout generation unit 30 as changed mask data (step S40).

  FIG. 3 is a flowchart more specifically showing the layout generation process of the change circuit performed in step S30 of FIG.

  Here, in order to facilitate understanding, a specific example will be described. A semiconductor integrated circuit subject to circuit change has first to third metal wiring layers composed of, for example, three layers, and a first via layer and a second metal that connect the first metal wiring layer and the second metal wiring layer. It is assumed that a second via layer that connects the wiring layer and the third metal wiring layer and a contact layer that connects the first metal wiring layer and the semiconductor layer are provided. When a circuit change occurs in the semiconductor integrated circuit having such a structure, the layout generation apparatus of the present invention changes the layout of one or more of the contact layer, each metal wiring layer, and each via layer according to the change contents. To generate change mask data. That is, the layout change is performed for each layer, and a change mask is created for each layer. In the case of this specific example, the contact layer, the first metal wiring layer, the second metal wiring layer, the third metal wiring layer, the first via layer, and the second via layer are objects of layout change, and the layout change One or more mask data of a contact mask, a first metal mask, a second metal mask, a third metal mask, a first via mask, and a second via mask are newly generated.

  In the layout trial process of the changed circuit in step S30, the constraint condition specifying unit 31 accepts the setting of the constraint condition regarding the mask change accompanying the layout change (step S31). Based on the user's instruction, for example, the constraint condition designating unit 31 pre-designates the number of masks that can be changed among the six masks (that is, the number of layers for which the layout is to be changed), or the mask name to be changed (that is, By directly specifying the layout change layer, a constraint condition for generating the layout is given.

  The change mask extraction unit 32 extracts a combination of change masks that satisfy the constraint conditions specified by the constraint condition specification unit 31. For example, in step S31, when the constraint condition that the number of masks that can be changed at the time of layout change is set to three is specified, the change mask extraction unit 32 selects one of the six masks based on the constraint condition. All combinations that select three sheets to be changed are extracted. That is, the change mask extraction unit 32 extracts the 20 combinations of change masks shown in FIG. The change mask extraction unit 32 supplies the extracted 20 combinations to the automatic placement and routing unit 33 (step S32). Each of the combinations of change masks extracted by the change mask extraction unit 32 is a layer that can change the layout with respect to the reference layout before the circuit change when the automatic placement and routing unit 33 generates the layout of the change circuit. It is what you specify.

  Note that the change mask extraction unit 32 does not set the constraint condition in step S31, that is, if the number of masks that can be changed or the name of the mask to be changed is not specified when the layout is changed, All possible combinations of change masks are extracted, and each extracted combination is supplied to the automatic placement and routing unit 33. In other words, in this case, the change mask extraction unit 32 changes six layers that change only one layer among all six layers, fifteen types that change two layers among all six layers, and three layers among all six layers 20. As shown, 15 combinations that change 4 layers out of all 6 layers, 6 combinations that change 5 layers out of all 6 layers, and 1 combination of change masks that change all 6 layers are extracted.

  Next, the automatic placement and routing unit 33 tries to generate the layout of the change circuit based on the read connection information (net list) of the change circuit and the reference layout data. At this time, the automatic placement and routing unit 33 tries to change the layout only for the layer that can be changed by the layout change indicated by each of the combinations of change masks extracted by the change mask extraction unit 32 to satisfy the given constraint conditions. To do. For example, when “contact, first metal, first via” is given as a combination of change masks by the change mask extraction unit 33, the automatic placement and routing unit 33 sets the contact layer, the first metal layer, and the first via. The layout change is tried only for the layer, and the layout generation reflecting the change circuit is tried under such constraints. For other layers, the layout is not changed and the standard layout state is maintained. If the change mask combination (for example, contact, first metal, first via) given by the change mask extraction unit 32 cannot reflect the connection state of the change circuit, the layout generation is performed. Not performed (step S33). The automatic placement and routing unit 33 sequentially tries to generate a layout for all the combinations of change masks extracted by the change mask extraction unit 32 (for example, 20 combinations shown in FIG. 5). When the automatic placement and routing unit 33 performs layout generation, according to the connection information (net list) of the changed circuit, the layout change processing such as cell addition, deletion, and placement change is preceded by the reference layout before the circuit change. After that, wiring change processing such as addition / deletion of wiring and route change is performed.

  If no constraint condition is set in step S31, the automatic placement and routing process is performed in order from the combination with the smallest number of change masks among all the combinations of change masks extracted by the change mask extraction unit 32. . That is, the automatic placement and routing processing unit 33 tries to generate layouts for six combinations that change only one layer, and then tries to generate layouts for 15 combinations that change two layers. Attempt layout generation for the combination to be changed. However, if there is a metal wiring in a cell to be added or deleted by the automatic placement and routing unit 33, or there is a wiring to be changed or deleted, the layout needs to be changed. When a layer is inevitably determined, layout generation is performed in order from the combination including the layer.

  6A to 6C show specific modes of layout change processing performed by the automatic placement and routing unit 33. FIG. FIG. 6A shows a layout before the circuit is changed. The cell 510 includes a pin 503 of the first metal layer, an internal wiring 502 of the second metal layer, and an internal wiring 501 of the first metal layer. The pin 503 is connected to the wiring 504 of the first metal layer and extends in the horizontal direction in the figure. The wiring 504 is connected to the wiring 505 of the second metal layer extending in the vertical direction in the drawing through the via plug 508 of the first via layer. The wiring 505 is connected to the wiring 506 of the third wiring layer extending in the horizontal direction in the drawing through the via plug 509 of the second via layer. In addition, the second metal layer wiring 507 passes in the vertical direction in the drawing above the cell 510.

  FIG. 6B shows a layout after the placement change processing is performed by the automatic placement and routing unit 33. Compared with the layout before the circuit change, the pin 503 of the first metal layer is shifted to the right in the figure, and the cell area is enlarged. Accordingly, the first metal layer wiring 504 is a redundant wiring. Further, the internal wiring 502 of the second metal layer is shifted in the left direction in the figure. Accordingly, the second metal layer wiring 507 and the internal wiring 502 are short-circuited.

  FIG. 6C shows a layout after the wiring change processing is performed by the automatic placement and routing unit 33. The path of the second metal layer wiring 507 is changed so as to bypass the internal wiring 502 of the second metal layer, thereby solving the above-described short circuit problem. Further, the redundant segment is eliminated from the first metal layer wiring 504, thereby eliminating the above-described problem of redundant wiring. In the example shown in FIG. 6, the layers that need to be changed in accordance with the layout change as described above are the first metal layer, the second metal layer, and the first via layer, and the contact layer, the second via layer, and the third layer. The layout of the metal layer has not been changed. That is, the layout change shown in FIG. 6 is an example in which layout generation is performed under the constraint condition indicated by the 11th change mask combination in FIG.

  When the layout generation process is completed, the verification unit 34 performs timing verification, SI verification, and power verification on the generated layout, and creates a report on the verification result (step S34).

  As a result of various verifications by the verification unit 34, when the required specifications are satisfied in all verification items, the generated layout is stored in the changed layout data storage unit 35 as changed layout data together with the verification report. On the other hand, if a problem is confirmed as a result of the verification, the layout is not saved (step S35).

  Next, the automatic placement and routing unit 33 determines whether or not layout generation has been attempted for all combinations of change masks extracted by the change mask extraction unit 32 (step S36). If layout generation trials have not been completed for all combinations of change masks, the process returns to step S33, and layout generation is attempted for new change mask combinations. For example, when a series of processing of layout generation, verification, and storage of changed layout data is completed for the first change mask combination (contact, first metal, first via) shown in FIG. The same processing is performed for the second combination of change masks (contact, first metal, and second metal). Such a series of processes is repeatedly executed until the process is completed for all combinations of change masks extracted by the change mask extraction unit 32.

  FIG. 7 shows an example of a result of the layout generation unit 30 attempting layout generation for each of the change mask combinations shown in FIG. In the example of FIG. 7, the automatic placement and routing unit 33 indicates that the placement and routing processing reflecting the connection state of the change circuit can be performed in the combination of the second and eleventh change masks. This combination indicates that a layout reflecting the connection state of the change circuit could not be generated. FIG. 7 also shows that timing verification, SI verification, and power verification are performed on the two generated layouts, and the timing specification cannot be satisfied in the second combination. On the other hand, in the eleventh combination, it is shown that the required specifications can be satisfied in all the verification items. Note that subsequent verification processing is not performed for those for which layout generation could not be performed. That is, in the example shown in FIG. 7, as a result of trying to generate a layout under the restriction condition that the number of change masks is three, the required specification of the electrical characteristics with the change mask combination shown in FIG. It has been shown that a circuit change satisfying the above has been realized. The layout generated in the combination of the eleventh change mask is stored in the changed layout data storage unit 35 as changed layout data.

  In the modified layout data storage unit 35, modified layout data that satisfies the specified constraint condition, reflects the connection state of the modified circuit, and satisfies the required specifications as a result of performing various verifications is repeatedly executed from step S33 to step S36. It will be saved sequentially through the process. When two or more pieces of changed layout data are stored in the changed layout data storage unit, the selection unit 36 receives a selection instruction for selecting any one (step S37). The selection unit 36 selects one of the two or more changed layout data stored in the changed layout storage unit based on, for example, a selection instruction from the user.

  Based on the selection instruction, the output unit 40 extracts one of the modified layout data stored in the modified layout data storage unit 35 and outputs this as modified mask data. Since the changed mask data is constituted only by the layout of the layer whose layout has been changed with respect to the reference layout, the mask difference extracting step as in the conventional example shown in FIG. 1 can be omitted. That is, the change mask data output from the layout generation apparatus of the present invention can be used as it is when ordering a change mask.

  If no restriction condition is set in step S31, the layout generation of the changed circuit is attempted without any restrictions on the number of change masks, and the required specifications are obtained as a result of various verifications. One or more layout data to be satisfied is stored in the layout data storage unit 35. In this case, in the selection step of step S37, the user selects a layout with the smallest number of change masks, or reports a verification result depending on which of timing, power, and SI is given priority in consideration of circuit specifications. It is possible to select a layout after referring to.

  As is clear from the above description, according to the layout generation apparatus and the semiconductor integrated circuit design method using the same according to the present invention, when a circuit change occurs and a new layout design is performed, the number of change masks and the like are determined in advance. Since constraints are provided and layout generation is attempted within the set constraints, the number of change masks associated with circuit changes can be minimized. As a result, it is possible to reduce the mask cost and shorten the development period.

  In addition, layout generation is attempted for all combinations of change masks that satisfy the specified constraint conditions, and processing from verification and layout data storage is performed in a batch. Wiring processing and only layouts that have cleared various verification items Therefore, there is no rework such as returning to the previous process and reexamining the layout after executing such a series of processes, so that work efficiency can be improved.

  In addition, since the layer for which the layout is changed is set as a constraint condition in advance, the layout is changed only for the permitted layer, and only the layer for which the layout has been changed is output as change mask data. It is possible to reduce the mask difference extraction process executed in the circuit change flow, and the change mask ordering work becomes easy.

(Second embodiment)
FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit layout generation apparatus according to the second embodiment of the present invention. In the layout generation apparatus according to the first embodiment described above, the layout in which the automatic placement and routing unit 33 generates a layout one by one for the combination of the change masks extracted by the change mask extraction unit 32 and the verification unit 34 is created. 1 is verified one by one, and this series of processes is sequentially repeated for all the extracted combinations. In contrast, the apparatus according to the second embodiment is configured to perform parallel processing on a combination of a plurality of extracted change masks.

  That is, the changed layout generation unit 30 ′ according to the present embodiment includes three automatic placement and routing units 33a, 33b, and 33c, and three verification units 34a, 34b, and 34d corresponding to each of these. The automatic placement and routing units 33a, 33b, and 33c try to generate layouts in parallel by sharing the combinations of the plurality of change masks extracted by the change mask extraction unit 32, respectively. The verification units 34a, 34b, and 34c perform various verification processes in parallel on the layouts generated by the automatic placement and routing unit corresponding to the verification units 34a, 34b, and 34c, and create reports on the results.

  As a result of the verification by the verification units 33a, 33b, and 33c, layout data that satisfies the required specifications is stored in the modified layout data storage unit 35 as in the case of the first embodiment.

  When two or more layout data exist in the layout data storage unit 35, the automatic selection unit 36 ′ determines predetermined items (for example, wiring violation, number of change masks, timing, SI, power, etc.). One of the most appropriate layout data is selected in accordance with the priority order of the. That is, the automatic selection unit 36 ′ automatically performs selection based on the results of the verification unit for two or more layouts generated regardless of the user's instruction. Further, the automatic selection unit 36 ′ deletes the layout data that has not been selected from the layout data storage unit 35, and secures a recording area for the changed layout data storage unit 35.

  The output unit 40 extracts one of the data stored in the layout data storage unit 35 based on the selection result by the automatic selection unit 36 ′ and outputs this as change mask data.

  As described above, according to the layout generation apparatus of the second embodiment, a plurality of change mask combinations can be processed in parallel without waiting for a series of processes for one change mask combination to be completed. As a result, the layout modification design time can be greatly reduced.

  In FIG. 8, there are three automatic placement and routing units and verification units each performing parallel processing. However, the present invention is not limited to this, and the number can be appropriately increased or decreased according to the scale of the combination of change masks. . The components that perform parallel processing, that is, the components other than the automatic placement and routing units 33a to 33c, the verification units 34a to 34c, and the automatic selection unit 36 'are the same as those of the apparatus of the first embodiment, and therefore the description thereof is omitted. Is omitted.

It is a flowchart which shows the conventional design change procedure when a circuit change arises. 1 is a block diagram showing a configuration of a semiconductor integrated circuit layout generation apparatus according to an embodiment of the present invention; FIG. It is a flowchart which shows operation | movement of the layout production | generation apparatus which is an Example of this invention. It is a flowchart which shows operation | movement of the layout production | generation apparatus which is an Example of this invention. It is an example of the combination of the change mask extracted by the change mask extraction part which is an Example of this invention. It is a figure which shows the specific aspect of the layout change process by the layout production | generation apparatus which is an Example of this invention. It is a figure which shows an example of the result of having tried the layout production | generation by the layout production | generation apparatus which is an Example of this invention. It is a block diagram which shows the structure of the layout production | generation apparatus of the semiconductor integrated circuit which is the other Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Circuit connection information input part 20 Reference | standard layout data input part 30 Change layout production | generation part 31 Restriction condition designation | designated part 32 Change mask extraction part 33 Automatic place-and-route part 34 Verification part 35 Change layout data storage part 36 Selection part 40 Output part

Claims (14)

A semiconductor integrated circuit layout generation device for generating a layer layout for each layer of a semiconductor integrated circuit having a multilayer structure based on connection information of the integrated circuit,
Connection information input means for receiving input of connection information of the integrated circuit;
Reference layout data input means for receiving input of reference layout data corresponding to a reference layout generated based on connection information of another integrated circuit different from the connection information;
Modified layout generation means for generating a new layout by changing the layout of at least one layer layout constituting the reference layout based on the input connection information;
Changeable layer designating means for designating at least one layer layout of the reference layout to be changed by the modified layout generating means,
The layout generation apparatus for a semiconductor integrated circuit, wherein the change layout generation means changes the layout only for the layer layout designated by the changeable layer designation means. The changeable layer designating means includes a layer number designating means for designating the number of layers of the reference layout to be changed by the changed layout generating means, and the number of layers among a plurality of layer layouts constituting the reference layout. A combination extraction means for extracting all combinations for selecting the number of layers designated by the designation means,
The said change layout production | generation means performs a layout change with respect to each of the layer layout of the said reference | standard layout which concerns on the said combination about each combination extracted by the said combination extraction means. Semiconductor integrated circuit layout generation apparatus. Verification means for verifying predetermined electrical characteristics for the new layout;
3. The semiconductor integrated circuit according to claim 2, further comprising changed layout data storage means for storing changed layout data corresponding to the new layout in a recording medium in accordance with a verification result by the verification means. Layout generation device.   4. The layout generating apparatus for a semiconductor integrated circuit according to claim 3, further comprising selecting means for selecting one of the plurality of modified layout data stored in the recording medium.   5. The layout generation apparatus for a semiconductor integrated circuit according to claim 4, wherein the selection unit performs selection based on a verification result by the verification unit.   4. The semiconductor integrated circuit layout generation apparatus according to claim 3, further comprising change mask data output means for outputting one of the change layout data stored in the recording medium as change mask data.   3. The semiconductor integrated circuit layout generation apparatus according to claim 2, wherein the modified layout generation unit performs layout generation in parallel for each combination extracted by the combination extraction unit. A layout design method for a semiconductor integrated circuit for designing a layer layout for each layer of a semiconductor integrated circuit having a multilayer structure based on connection information of the integrated circuit,
A connection information input step for receiving input of connection information of the integrated circuit;
A reference layout data input step for receiving input of reference layout data corresponding to a reference layout generated based on other connection information different from the connection information;
A modified layout generation step of generating a new layout by performing layout change on at least one layer layout constituting the reference layout based on the input connection information;
A changeable layer designating step of designating at least one layer layout to be subjected to layout change in the modified layout generation step,
The layout design method for a semiconductor integrated circuit, wherein the modified layout generation step is a step of performing layout modification only for the layer layout designated in the modifiable layer designation step. The changeable layer specifying step includes a layer number specifying step of specifying the number of layers of the reference layout to be subjected to layout change in the changed layout generating step, and the number of layers among a plurality of layer layouts constituting the reference layout. A combination extraction step for extracting all combinations for selecting the number of layers designated in the designation step, and
9. The modified layout generation step is a step of performing layout change for each of the layer layouts of the reference layout related to the combination for each combination extracted in the combination extraction step. 2. A layout design method for a semiconductor integrated circuit according to 1. A verification step for verifying predetermined electrical characteristics for the new layout;
10. The layout of a semiconductor integrated circuit according to claim 9, further comprising a layout data storage step of storing, on a recording medium, changed layout data corresponding to the new layout in accordance with a verification result in the verification step. Design method.   11. The layout design method for a semiconductor integrated circuit according to claim 10, further comprising a selecting step of selecting one of the changed layout data stored in the recording medium when there are a plurality of changed layout data.   12. The layout design method for a semiconductor integrated circuit according to claim 11, wherein the selection step is a step of performing selection based on a verification result in the verification step.   11. The layout design method for a semiconductor integrated circuit according to claim 10, further comprising a change mask data output step of outputting one of the changed layout data stored in the recording medium as change mask data.   10. The layout design method for a semiconductor integrated circuit according to claim 9, wherein the modified layout generation step is a step of performing layout generation in parallel for each combination extracted in the combination extraction step.

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