JPH10326300A - Wiring board designing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a wiring board designing device for operating the arrangement or wiring of optimal electronic parts. SOLUTION: This device is provided with a board specification examination layout data preparing/editing part 8 which prepares/edits the layout data of a board based on data stored in a board specification examination preparation data storage part 7 which stores data for specification examination for designing a board on which electronic parts are arranged, board logical drawing data storage part 5 which stores the logical drawing data of the board, or IC interface information storage part 13 which stores the interface information of the IC arranged on the board. Also, this device is provided with simulators 24-27 which examine the prepared/edited layout data, and an IC interface information changing part extracting/reflecting part 16 which extracts a changing point related with the IC interface information from the layout data edited based on the simulation results of the simulators 24-27 by the board specification examination layout data preparing/editing part 8, and changes the IC interface information stored in the IC interface information storage part 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC interface information utilizing various simulations such as timing, waveform, heat, and EMC from an upper stage of board design such as functional design and logic design of a printed wiring board and an MCM board. Has a function to support the study to optimally set the information on the connection between the electronic components constituting the circuit mounted on the board and the information on the board design specifications such as the board layout requirement specifications and the board manufacturing specifications. The present invention relates to a wiring board design device.

[0002]

2. Description of the Related Art As a conventional pin assignment method of an IC, for example, Japanese Patent Application Laid-Open No. 7-297354 discloses an "integrated circuit and an integrated circuit pin assignment method and a mounting method".

First, FIG. 34 used for explaining a conventional IC pin assignment method will be described. FIG. 34 is a diagram showing an example of the pin assignment of the integrated circuit. In FIG. 34, 38 is a straight line X passing through the center of the integrated circuit, and 39 is a set of pin assignments A, B, C, and D.

Next, an outline of a conventional pin assignment method for an IC will be described. Conventional IC pin assignment method,
In the pin assignment, as shown in the figure, a pin assignment set A, B, C, and D39 is a straight line X3 passing through the center of the integrated circuit.
Pin 8 was assigned to mirror image 8. This means that the two integrated circuits which are pin-assigned by this pin assignment method are mounted so as to take positions rotated by 180 degrees with respect to each other on the same surface of the substrate;
Further, it is assumed that the same pin assignments are mounted on different surfaces of the substrate so as to directly face each other across the substrate.

When two integrated circuits to which the pin assignment is performed by this pin assignment method are mounted as expected, the pin assignments which are rotated by 180 degrees on the same surface of the substrate to form a mirror image are opposed to each other. Can be facilitated,
In addition, if the integrated circuits are arranged so as to face the upper and lower surfaces of the substrate, the pin assignments forming a mirror image are directly opposed to each other, so that through-holes can connect the signals in the shortest time. That is, this pin assignment method assumes that two integrated circuits pin-assigned by this method are mounted as a pair on the board as described above, and only minimizes the length of wiring formed on the board. The pin assignment is performed in consideration of this.

In the conventional pin assignment method, provisional layout data is created assuming the actual arrangement and wiring of the IC.
As a result of performing simulations such as timing, waveforms, heat, and EMC to confirm the operability of the board, the arrangement state, and the wiring state, the assignment of pins is not determined. As a result, in the layout design of the board, the layout and wiring of the ICs assumed by this method cannot be realized, or the board may not be redesigned or satisfy the required performance due to an operation failure. It is considered highly likely.

[0007]

In the conventional pin assignment method, when the pin assignment of the IC and the setting of the interface information of the buffer to be used are completed, the information is transferred to the board layout design. It is impossible to optimally set the interface information of the IC in consideration of the arrangement state of the electronic components constituting the device, the wiring state between the electronic components, and mounting problems such as timing, waveform, heat, and EMC. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. A designer of the function and logic of a board creates tentative layout data in which electronic components are arranged and wired in a design upstream stage. Timing, waveform, heat, EM
It is an object of the present invention to obtain a circuit board design apparatus capable of optimally arranging and wiring electronic components as a result of verifying a circuit operation to be mounted on a board by using a simulator such as C easily.

[0009]

According to a first aspect of the present invention, there is provided a wiring board design apparatus, wherein electronic components are arranged and the electronic components are provided as data for designing a substrate formed by wiring connecting the electronic components. A board specification study preparation data storage section for storing specification study data including a shape, design information of the board, and electrical information of the board, and connection information between the electronic component mounted on the board and the electronic component; A board logic diagram data storage unit that stores board logic diagram data expressing the following, an IC interface information storage unit that stores IC interface information including an input / output buffer and pin assignment information of an IC arranged on the board, Using the data stored in the board specification study preparation data storage unit, the board logic diagram data storage unit or the IC interface information storage unit, Create a layout data of the serial board /
A layout specification creating / editing section for editing board specifications, a simulator for verifying the created / edited layout data, and a layout specification creating / editing section for editing board specifications based on the simulation result of the simulator. A change related to the IC interface information is extracted from the layout data, and the I / O information stored in the IC interface information storage unit is extracted.
An IC interface information change portion extraction / reflection unit for changing C interface information is provided.

According to a second aspect of the present invention, there is provided a wiring board designing apparatus, wherein the electronic component shape and the substrate design are used as data for designing a substrate including electronic components arranged therein and wirings connecting the electronic components. A board specification study preparation data storage unit for storing specification study data consisting of information and electrical information of the board, and a board logic for expressing the electronic components mounted on the board and connection information between the electronic components; The layout data of the board is created / edited using the board logic diagram data storage unit for storing the diagram data, and the data stored in the board specification study preparation data storage unit and the board logic diagram data storage unit. A layout data creating / editing unit for examining the board specifications, a simulator for verifying the created / edited layout data, and a layout data for examining the board specifications; From the layout data edited by the creating / editing unit based on the simulation result of the simulator, a change point relating to the board logic diagram data is extracted, and the logic diagram data stored in the board logic diagram data storage unit is changed. And a logic diagram data change portion extraction / reflection unit.

According to a third aspect of the present invention, there is provided an apparatus for designing a wiring board, wherein the shape of the electronic component and the design of the substrate are used as data for designing a substrate on which electronic components are arranged and the wiring is connected between the electronic components. A board specification study preparation data storage unit for storing specification study data consisting of information and electrical information of the board, and a board logic for expressing the electronic components mounted on the board and connection information between the electronic components; The layout data of the board is created / edited using the board logic diagram data storage unit for storing the diagram data, and the data stored in the board specification study preparation data storage unit and the board logic diagram data storage unit. A layout data creating / editing unit for examining the board specifications, a layout data storage unit for examining the board specifications for storing the created / edited layout data, and the board A simulator for verifying the layout data stored in the layout data storage unit for study, a board layout design preparation data storage unit for storing layout design preparation data for designing the board layout, and the board specification study. The layout data creating / editing unit extracts the layout design data from the layout data edited based on the simulation result of the simulator and stored in the board specification study layout data storage unit, and prepares the board layout design preparation. Extraction of board layout requirement specifications for changing the layout design data stored in the data storage unit /
A reflection unit; and a board layout and wiring design unit that performs layout and wiring design of the board based on the connection information stored in the board layout design preparation data storage unit.

According to a fourth aspect of the present invention, there is provided a wiring board designing apparatus, comprising: specification study data stored in the board specification study preparation data storage section; and layout design data stored in the board layout design preparation data storage section. And a preparation data matching processing unit for performing a matching process for sharing data common to both data.

According to a fifth aspect of the present invention, there is provided a wiring board designing apparatus, comprising: information relating to logic diagram data included in layout data created / edited by the layout data creating / editing unit for board specification consideration; And a board net list information generating unit for generating net list information of the board by synthesizing the logic diagram data stored in the board layout design preparation data storage unit.

According to a sixth aspect of the present invention, there is provided a wiring board designing apparatus, comprising: a board layout design data storage unit for storing layout design data designed and arranged by the board arrangement and wiring design unit;
A data diversion processing unit for extracting data to be diverted by the board specification study layout data creating / editing unit from the board layout design data storage unit and storing the extracted data in the board specification study layout data storage unit; .

According to a seventh aspect of the present invention, in the wiring board designing apparatus, undefined data among the specification study data stored in the board specification study preparation data storage unit is created / edited as the board specification study layout data. It is provided with an undefined part creation / editing unit for defining by a unit.

According to a eighth aspect of the present invention, in the wiring board designing apparatus, the electronic components are arranged and displayed on a display device so that the layout data creating / editing section for studying the board specifications creates / edits the layout data of the board. This is provided with an initial arrangement processing unit.

According to a ninth aspect of the present invention, there is provided a wiring board designing apparatus, based on board specification study layout data created / edited by the board specification study layout data creating / editing section.
A logic diagram data generating unit for generating logic diagram data of the board and storing the logic diagram data in the board logic diagram data storage unit;

According to a tenth aspect of the present invention, an error criterion for determining whether there is an error in the simulation result of the simulator is stored, and an error in the simulation result is specified based on the error criterion. And an error analysis result display section for displaying the error specified by the error analysis section.

The wiring board designing apparatus according to an eleventh aspect includes a navigation processing unit for displaying a method of avoiding the error specified by the error analysis unit.

According to a twelfth aspect of the present invention, there is provided a wiring board designing apparatus, comprising:
The simulator includes one of a waveform simulator for analyzing a signal transmission waveform, a heat simulator for analyzing heat distribution of the board, and an EMC simulator for analyzing electromagnetic radiation noise of the board.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, Embodiment 1 of the present invention will be described. FIG. 1 is a configuration diagram of a wiring board design apparatus according to the first embodiment. In the drawing, reference numeral 1 denotes an input unit for inputting information using a keyboard, a mouse, or the like, and 2 denotes a board logic diagram input for storing a logic library such as a logic operation of an electronic component and a logic symbol shape necessary for the board logic diagram input. Preparation data storage unit,
Reference numeral 3 denotes a board logic diagram input unit for defining connection relationships using a logic library stored in the board logic diagram input preparation data storage unit 2 and inputting board logic diagram data. A board specification study signal selection section for selecting a signal for creating specification study layout data from the signals stored in the board logic diagram data storage section 5 is a board input by the board logic diagram input section 3 The board logic diagram data storage unit 7 stores the logic diagram data of (1), as the preparation data for studying the board specifications, (1) the shape of the electronic component,
(2) the layer configuration of the substrate, the width of the conductor generated in the conductor layer,
And board design information consisting of gap values between conductors,
(3) a board specification study preparation data storage unit for storing information on each layer of the board, such as the layer pressure of each layer of the board, the electrical characteristic value of each layer of the board, and the physical property value of each layer of the board;
Is a board logic diagram data storage unit 5, a board specification study signal selection unit 4, a board specification study preparation data storage unit 7, and an IC
A board specification study layout data creating / editing unit that creates layout data for studying board specifications from the interface information storage unit 13 and edits layout data for studying board specifications based on information from the input unit 1. IC interface information storage unit for storing IC pin assignments related to the creation and editing of layout data for examining board specifications of ICs designed in parallel with the IC, and information of usable input / output buffers. Information related to the IC interface information included in the layout data for board specification study stored in the data storage unit 17 and the IC stored in the IC interface information storage unit 13
An IC interface information change portion extraction / reflection unit that extracts a difference from the interface information and updates the IC interface information storage unit 13, and 17 is a board specification review created and edited by the layout data creation / editing unit 8 for board specification review A layout data storage unit 19 for examining board specifications, which stores layout data for a board, is used to input a signal name and an electronic component name for performing a simulation, which will be described later, using the input unit 1.
An analysis signal / component selection unit 21 selects from signal names and electronic component names included in the board specification study layout data stored in 7. Reference numeral 21 denotes a signal name and electronic component selected by the analysis signal / component selection unit 19. Data required for executing a simulation is output from the name, the board specification study layout data stored in the board specification study layout data storage unit 17, and the analysis preparation data stored in the analysis preparation data storage unit 22. Analysis data processing unit,
Reference numeral 2 denotes an analysis preparation data storage unit for storing analysis preparation data necessary for a simulation described later such as electric characteristics and power consumption of electronic components, 24 a timing simulator for verifying whether or not the signal changes, and 25 a signal transmission waveform. , A thermal simulator for analyzing the heat distribution of the substrate, an EMC simulator for analyzing the electromagnetic radiation noise of the substrate, a timing simulation result storage unit for storing the results of the timing simulation, and a waveform simulation for the , A simulation result storage unit for storing the results of the thermal simulation, an EMC simulation result storage unit for storing the results of the EMC simulation, and a result of each simulation. It is a simulation result display unit for display.

FIGS. 2A and 2B are diagrams showing examples of simulation results of timing, waveform, heat, and EMC by the wiring board designing apparatus shown in FIG. 1. FIG. 2A shows a simulation result stored in the timing simulation result storage unit 28. An example of a timing simulation result displayed on the result display unit 32, FIG. 2B is an example of a waveform simulation result stored in the waveform simulation result storage unit 29 and displayed on the simulation result display unit 32, and FIG. FIG. 4D is an example of an EMC simulation result stored in the result storage unit 30 and displayed by the simulation result display unit 32, and FIG. 4D is an example of an EMC simulation result stored in the EMC simulation result storage unit 31 and displayed by the simulation result display unit 32. is there.

FIGS. 3 to 8 show examples of information and data handled by the wiring board designing apparatus of this embodiment.
FIG. 3 is a diagram showing an example of the logic diagram data of the board inputted by the board logic diagram input section 3 and stored in the board logic diagram data storage section 5, where the location numbers of IC1 to IC3 are added. The symbol shape of the component is prepared before inputting the logic diagram, and is a logic library of electronic components AA0 to AA stored in the board logic diagram input preparation data storage unit 2.
2, BB0-BB2, CC0-CC2, DD0-DD2
Is a signal name added to connection information between electronic components, GND is a pin number added to each pin of a logical library of the electronic component, and EXA is a master name of the IC defined by adding properties to the electronic component library IC1. . In FIG. 3, “IC_MASTE” is used as the name of the property added to the logical library to define the master name of the IC.
R "is used, but it is not necessary to fix to this property name, and EXA is added as the IC master name of IC1 by the IC_MASTER property.

FIG. 4 is a diagram showing an example of the board specification study layout data immediately after being created by the board specification study layout data creating / editing section 8.
KIBAN001 is a board registration name defined by adding a property to the board outline, and the symbol shape of the component to which the location number of IC1 to IC3 is added is a board specification study layout stored in the board specification study preparation data storage unit 7. An electronic component library used for creating and editing data. FIG. 5 is a diagram showing an example of the contents of the interface information of the IC master stored in the IC interface information storage unit 13.

FIG. 6 is a diagram showing an example of the board specification study layout data created by editing the board specification study layout data creation / editing section 8 from the board specification study layout data shown in FIG. , In the figure,
BB0 to BB2 and CC0 to CC2 are wirings created by the board specification study layout data creating / editing unit 8. FIG. 7 shows a board capable of realizing the optimal arrangement state and wiring state of electronic components obtained as a result of performing verification of timing, waveform, heat, EMC, etc. on the board specification study layout data shown in FIG. FIG. 4 is a diagram illustrating an example of layout data for specification study. FIG. 8 shows the IC extracted / reflected by the IC interface information changed portion extraction / reflection unit 16 from the board specification study layout data shown in FIG.
FIG. 4 is a diagram illustrating an example of interface information.

FIG. 9 shows an example of a board information reference GUI for referring to a board registration name to be added to the board outline stored in the board specification study preparation data storage unit 7 and board information dependent on the board registration name. is there.

Next, using the wiring board design apparatus shown in FIG. 1, with respect to the board specification study layout data obtained as a result of creating and editing board specification study layout data, , EMC and other simulations to verify the operation of the circuit mounted on the board, confirm that the placement and wiring conditions of the electronic components are good, and then set the IC interface information optimally Is shown below.

The operation of the board logic diagram input unit 3 is described with reference to FIG.
This will be described with reference to FIG. The board logic diagram input unit 3 converts the input information from the input unit 1 and the logic library added with the location numbers of the electronic components IC1 to IC3 stored in the board logic diagram input preparation data storage unit 2 from the board logic diagram. Create logic diagram data of the circuit to be mounted on. In particular,
In the board logic diagram input unit 3, a logic library of electronic components constituting a circuit to be mounted on the board is called from the board logic diagram input preparation data storage unit 2 based on the input information from the input unit 1, and the IC1 is stored in the logic library. , And a unique location number such as IC3 is added. Further, pin numbers 1 to 8 are added to the logical library to which the location numbers of IC1 to IC3 are added.

Next, a line representing a connection relationship is created between the pins of the logic library to which the location numbers of the electronic components IC1 to IC3 are added, and signal names such as AA0 to DD2 are added to the line. In the logic diagram data shown in FIG.
The location numbers of IC1, IC2, and IC3 and the pin numbers 1 to 8 are added to the logical library to which the location numbers of C1 to IC3 are added. Also, in the present embodiment, the logic library to which the location number of IC1 is added is designed in parallel with the board design.
It is assumed that the logic libraries IC2 and IC3 have already been designed. Further, a master name EXA of the IC indicated by the location number of the IC 1 is defined. The logic diagram data created by the board logic diagram input unit 3 is stored in the board logic diagram data storage unit 5.

Next, the board specification reviewing signal selector 4 generates a signal name for creating and editing board specification reviewing layout data from the signal names included in the logic diagram data stored in the board logic diagram data storage 5. Select In the examples shown in FIGS. 4 to 8, it is assumed that signals BB0 to BB2 and signals CC0 to CC2 are selected.

Next, the board specification review layout data creating / editing section 8 stores the signal names (BB0 to BB2, CC0 to CC2) selected by the board specification review signal selection section 4 and the board logic diagram data storage section 5 , The electronic component library (IC1 to IC3 in FIG. 4) for examining the board specifications of the electronic components stored in the board specification study preparation data storage unit 7, and the IC interface The IC interface information (FIG. 5) stored in the information storage unit 13 is input, and first layout data for board specification study (FIG. 4) is created.

Next, the board outline and the board registration name KIBAN0
Enter 01. As a specific input method, in the layout data creating / editing section 8 for examining the board specifications, an outline of the board is drawn using the input section 1, and a board registration name KIBAN001 is added to the created board outline by a property. The board registration name KIBAN001 refers to the board registration name already stored in the board specification study preparation data storage unit 7 by the input unit 1, and selects from the board registration name. Board registration name KIBAN0
For 01, there is a method of directly using the board information reference GUI 7 of FIG. 9 or directly using the input unit 1 to refer to the board specification study preparation data storage unit 7. Referenced board registration name KI
BAN001 is added to the board outline by properties as described above. In FIG. 4, “Board_Tech” is used as a property name to which a board registration name is added, but it is not necessary to fix the property name to “Board_Tech” or a definition method by adding a property.

By defining or changing the board registration name to the board outline by the property, it is possible to set or change the board information of the board used for the board specification study layout data shown in FIG.

FIGS. 10 to 15 show examples of information included in the board information dependent on the board registration name.

FIG. 10 is a diagram showing an example of the layer configuration of the substrate, and the layer names and the attributes of the layers constituting the substrate. FIG.
The four-layer substrate shown in FIG.
The conductor layer specified by the layer name of p and Solder is 2
Two layers, conductor layers specified by GND and VCC layer names in which power supply and signal wiring are created are specified by layer names Lam1, Lam2, and Lam3 that insulate between each conductive layer. Three insulator layers, Comp and Solder
Of the conductor layer specified by the layer name of FIG. To a layer specified by a layer name, an attribute name of the layer indicating physical properties of the layer and design separation is added. In the attribute name of the layer, the layer for forming a signal wiring is Signal, the layer for forming a solid pattern of a conductor for power supply is Plane, and the insulator layer is In.
There is a sulator.

FIG. 11A shows the characteristic impedance (Z0) of each layer constituting the substrate and the delay value (T) per unit length.
FIG. 2B is a diagram showing characteristic impedance (Z0) and a delay value per unit length (Td) when the substrate is assumed to be uniform in all layers. FIG. 11 (a)
As shown in FIG. 11, the characteristic impedance (Z0) and the delay value per unit length (Td) are added for each conductor layer specified by the layer name, or as shown in FIG. It is added as a uniform value of the conductor layer. When both the parameters shown in FIGS. 11A and 11B are set, the parameter set for each conductor layer specified by the layer name has priority.

FIG. 12 shows the thickness of each layer constituting the substrate,
FIG. 4 is a diagram showing a relative dielectric constant (εr) of an insulator layer. As shown in FIG. 12, the thickness of each layer of the substrate and the relative dielectric constant (εr) of the insulator layer specified by the layer name are added. FIG. 13 shows the resistivity (ρ) of the conductor and the relative magnetic permeability of the insulator layer forming the substrate.
(μ), conductivity (σ), and loss angle (TAN). As shown in FIG. 13, the relative magnetic force (μ), conductivity (σ), and loss angle (TAN) are added for each insulator layer specified by a layer name.

FIG. 14 is a diagram showing the wiring width of the conductor formed on the conductor layer constituting the substrate. FIG. 15 (a)
It is a figure which shows the minimum gap value between conductors formed in a conductor layer, and FIG. 6 (b) is a figure which shows the minimum gap value between conductors formed in a conductor layer in which the substrate is made uniform in all layers. . As shown in FIG. 14, the wiring width for each conductor layer is added for each conductor layer specified by the layer name of the substrate. Further, as shown in FIG. 15A, the gap value between the conductors is determined by the pad for mounting the component in the layer specified by the layer name of Comp and Solder for mounting the electronic component and the wiring when the wiring is created. The gap value (Pad to Via) with Via which is a conduction hole for changing the layer to be formed, the gap value (Pad to Line) with Pad and wiring (Line) for mounting the component, and the component mounting Value of Pad to Pad (Pad to Pa
d), the gap value between Vias (Via to Via), and V
The gap value (Via to Line) between ia and Line, and Lin
e and Line gap (Line to Line) and GN
Via and Vi of the layer specified by the layer name of D and VCC
a, Add a gap value between Via and Line, Line and Line, or make Pad and Pa uniform for all conductor layers.
d, Pad and Line, Pad and Pad, Via and Vi
a, a gap value between Via and Line, and a gap value between Line and Line are added. Normally, as shown in FIG. 15 (b), when it is desired to add a gap value between conductors uniform in all conductor layers and change the gap value between conductors for each conductor layer specified by a layer name. The gap value shown in FIG. 15A is added. FIG. 15 (a),
When both of the parameters shown in (b) are added, the parameter set for each conductor layer specified by the layer name has priority.

It is not necessary to set all parameters included in the board information dependent on the board registration name described above. In order to study the board specifications, at least
0 and the parameters shown in FIG. 11 (b), FIG. 14 and FIG. 15 (b) are required. The parameters shown in the other figures are
This is added when creating or editing layout data for examining board specifications at a more detailed level, or performing simulation closer to actual measurement.

That is, since the board specification study is assumed to be performed at the stage of the function and logic design of the board, detailed parameter setting such as board information stored in the board layout design preparation data storage unit 15 is performed. do not need.

Also, in the examples of FIGS. 10 to 15, a four-layer board is assumed, and parameters included in the board information are shown. In this example, the physical layer configuration of the substrate is expressed as a parameter as it is, but in addition, a parameter of a virtual layer configuration that does not match the physical layer configuration can be expressed. For example, there are a single conductor layer having no other layers or a conductor layer having only a plurality of layers. This is the characteristic impedance (Z0) of the board, respectively.
In addition, it is assumed that the method is to examine the delay value per unit length (Td) and to evaluate whether connection information between electronic components of a circuit mounted on a board can be realized as wiring inside the outer shape of the board. Specifically, the former is verified by simulation by increasing or decreasing the characteristic impedance (Z0) and the delay value per unit length (Td) of the board included in the board information dependent on the board registration name defined in the board shape within a certain range. To set the optimum characteristic impedance (Z0) and the delay value per unit length (Td). The latter is used for the board registration name defined in the board outline in the process of creating and editing the layout data for board specification study. If the layer attribute of the substrate included in the dependent substrate information is Sig
While adding a nal conductor layer, it is determined whether wiring is possible or not, and the result is verified by simulation.
This is for setting the number of signal conductor layers.

As described above, the board registration name is defined by the board shape and its properties. In the first board specification study layout data (FIG. 4), an electronic component library for board specification study of an electronic component having a connection relationship with the signal name selected by the board specification study signal selector 4 as a board specification study target (FIG. 4). 4 IC1 to IC3) are collectively arranged at a certain position.

Next, the board specification study layout data creating / editing section 8 uses the input section 1 to input the first board specification study layout data (FIG. 4) to the electronic component library (IC1 to IC1 in FIG. 4). The layout and wiring of the IC 3) are created. Timing, waveforms, heat, EMC for layout specification layout data (Fig. 6)
Perform a simulation such as The simulation procedure is shown below.

The layout of the electronic component library and the creation of the wiring are performed by a manual placement / wiring function manually input by a designer who operates the wiring board designing apparatus, and by an automatic placement / holding function provided by the layout data creating / editing unit 8 for examining the board specifications. Use the wiring function. Create layout data for board specification study /
The results created and edited by the editing unit 8 are stored in the board specification study layout data storage unit 17. From the electronic component names and signal names included in the board specification study layout data stored in the board specification study layout data storage unit 17, the analysis signal / component selection unit 19 and the input unit 1 are used for the analysis signal / component selection unit 19. Use to select. From the layout data for board specification study stored in the board specification study layout data storage unit 17, the layout position and wiring topology information of the electronic part library related to the electronic part names and signal names selected for performing the simulation, etc. The timing, waveform, heat, and data necessary for the EMC simulator are extracted and processed by the analysis data processing unit 21 and output.

The analysis data output from the analysis data processing unit 21 and the data such as the internal delay, electrical characteristics, and power consumption of the electronic components stored in the analysis preparation data storage unit 22 are combined into a timing simulator. 24, a waveform simulator 25, a heat simulator 26, an EMC simulator 27 and the like to execute a simulation. The simulation execution results are stored in a timing simulation result storage unit 28, a waveform simulation result storage unit 29, a thermal simulation result storage unit 30,
The simulation result display unit 32 stores the timing simulation results of FIG. 2A, the waveform simulation results of FIG. 2B, the thermal simulation results of FIG.
This is displayed as the result of the EMC simulation in FIG.

The outline of each simulator will be described below. The information input by the timing simulator 24 includes connection information inside the electronic component, a delay value, and operating conditions of a circuit mounted on the board, which are stored in the analysis preparation data storage unit 22.
The connection information output from the analysis data processing unit 21 includes connection information between electronic components of a circuit mounted on the board, a delay value of a wiring portion of the connection information, and the like. As a delay value of a wiring portion between electronic components, a delay value output from a waveform simulation may be used. The timing simulator 24 simulates the electrical operation timing between the electronic components from the input information described above, and specifies the pins of the electronic component having the timing failure and the signals related to the pins.

The information input by the waveform simulator 25 is
The electrical characteristics of the electronic components stored in the analysis preparation data storage unit 22 and the output from the analysis data processing unit 21
The information includes connection information between electronic components of a circuit mounted on the board, operating conditions and wiring topology information of the connection information, and information on a layer configuration, electrical characteristics, and physical properties of the board. The waveform simulator 25 simulates a transmission waveform of an input / output buffer of an electronic component constituting a circuit mounted on a board from the above-described input information, and detects a defect related to signal transmission such as reflection and crosstalk and overshoot and undershoot. Is detected.

The information input by the thermal simulator 26 includes the power consumption of the electronic components stored in the analysis preparation data storage unit 22 and the arrangement position (the arrangement coordinates and the rotation angle) of the electronic components output from the analysis data processing unit 21. And arrangement surface). The heat simulator 26 calculates the heat and convection of the board from the input information described above, simulates the temperature of each component and the heat distribution of the board, and verifies whether the electronic component is within the operating temperature specified by the manufacturer. Do it.

The information input to the EMC simulator 27 includes the electrical characteristics of the electronic components stored in the analysis preparation data storage unit 22, the wiring shapes of the electronic components output from the analysis data processing unit 21, and the board And physical property information. The EMC simulator 27 simulates electromagnetic radiation generated around the board and the circuit of the board from the input information described above, and verifies whether or not the electronic component is within the operation range specified by the manufacturer.

The timing, waveform, heat, E
Perform simulations such as MC. The layout of the electronic component library is changed using the input unit 1 in the layout data creating / editing unit 8 for examining the board specifications until the normal operation of the circuit can be confirmed by the simulation and a good arrangement state and wiring state can be obtained. , Change of wiring, I
The C interface information is repeatedly changed.
In addition, layout data creation / editing section 8 for board specification study
By using the input unit 1 to change the board registration name added to the board outer shape, the layer structure of the board, the electrical characteristic values of each layer, physical property information, the width and thickness of the conductor of the board, the conductor It is also possible to change substrate information such as a gap value between the substrates and electrical characteristic values of all layers of the substrate.

Next, the IC interface information changed portion extraction / reflection unit 16 uses the input unit 1 in the board specification study layout data creation / editing unit 8 to change the layout of the electronic component library, change the wiring, and change the IC. Based on the board specification study layout data (Fig. 7) obtained as a result of repeatedly changing the interface information, etc., the IC
The changed part related to the interface information is extracted, and the IC interface information stored in the IC interface information storage unit 13 is changed as shown in FIG. The IC interface information set by sufficiently considering the problem of mounting the board is transmitted as information to the layout design of the IC designed in parallel, and the information is used for the automatic layout of the IC used in the layout design of the IC. Use as input data for functions.

In the first embodiment, the layout data creating / editing unit 8 for examining the board specifications uses the input unit 1 to
Although the pin assignment of the interface information and the optimal setting of the driving capability of the input / output buffer to be used have been performed, processing for adding a power supply pin of the IC can also be performed.

The layout data creating / editing unit 8 for examining the board specifications can check the changed IC interface information by using the input unit 1. Check items include the number of pins that change simultaneously, the proximity of input pins and output pins, the proximity of input pins and power supply pins exceeding 10 MHz, and the like. This check processing is usually performed by IC
This is the one used in the layout design.

Although the first embodiment has been described on the assumption that the logic diagram data of the board exists, the layout data creating / editing section 8 for examining the board specifications uses the input section 1 to examine the board specifications. The electronic component library 51 is called from the application preparation data 7 and the IC interface information storage unit 13, connection information between electronic components is defined, arrangement and wiring information are input, and verification of the IC interface information is performed through the above-described various simulations. It is also possible to perform optimal setting work.

As described above, according to the first embodiment, the number of gates estimated from the logic circuit data of the IC, I
The IC master is determined from the conditions such as the operating frequency of C, the maximum number of I / Os, and the number of package pins, or
From the stage where the candidates for the IC master to be used are almost narrowed down, the pin assignment of the IC and the interface information of the buffer to be used are provisionally defined, and further, the temporary layout data of the electronic components connected to the IC by the signal is created and edited. Simulate timing, waveform, heat, EMC, etc. to verify the operation, determine the verification results, pin assignment of the IC that optimizes the board placement state and wiring state, and interface information of the input / output buffer to be used. , It can be handled at the data level to the IC design.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described. The description of the same parts as in the first embodiment will be omitted.

FIG. 16 is a diagram showing a configuration of a wiring board designing apparatus according to the second embodiment. In the figure, reference numeral 11 denotes information relating to the board logic diagram data included in the board specification study layout data stored in the board specification study layout data storage unit 17 and the board logic diagram stored in the board logic diagram data storage unit 5. A logic diagram data changed portion extraction / reflection unit that compares the data with data to extract a changed portion and reflects the changed portion on the board logic diagram data stored in the board logic diagram data storage unit 5. The timing simulator 24, the waveform simulator 25, the heat simulator 26, the EMC simulator 27, the timing simulation result storage unit 28,
The waveform simulation result storage unit 29, the thermal simulation result storage unit 30, the EMC simulation result storage unit 31, and the simulation result display unit 32 are the same as those shown in FIG.

FIG. 17 shows the results of verifying the timing, waveform, heat, EMC, etc. of the layout data for board specification study of FIG. It is a figure which shows an example of the layout data for board specification study which added the passive element to the wiring shown by signal name CC0 using the input part 1, and CHR = R_15 or CHR = EX_R is the passive data added in the above-mentioned process in the figure. These are attributes and values of electronic components such as R / L / C defined by adding properties to the elements, or model names of the electronic components. FIG. 18 shows information related to the logic diagram data of the board included in the board specification study layout data of FIG. 17 by the logic diagram data changed portion extraction / reflection unit 11 and the board stored in the board logic diagram data storage unit 5. FIG. 9 is a diagram showing board logic diagram data in which the changed portion is extracted by comparing the logic portion data with the logic diagram data of FIG. 5 and the changed portion is reflected on the board logic diagram data stored in the board logic diagram data storage section 5; Is the model name of the passive component that has been added or changed.

Next, using the wiring board designing apparatus shown in FIG. 16, layout data for studying board specifications is created and edited, and board operation is confirmed by simulation of timing, waveform, heat, EMC, and the like. Compares the information on the board logic diagram data included in the board study layout data for which the arrangement state and the wiring state of the electronic components are determined to be good with the board logic diagram data stored in the board logic diagram data storage unit The procedure for reflecting the changed portion in the board logic diagram data storage unit will be described below.

The board logic diagram input unit 3 uses the logic library of electronic components stored in the board logic diagram input preparation data storage unit 2 and the information from the input unit 1 to output the logic diagram data of the circuit mounted on the board. Create The creation method is the same as in the first embodiment, and a description thereof will not be repeated. 17 to 18
In the example shown in (1), the electronic component library to which the location numbers of IC1, IC2 and IC3 are added is an IC whose design has already been completed. The board logic diagram data created by the board logic diagram input unit 3 is stored in the board logic diagram data storage unit 5.

Next, the board specification reviewing signal selector 4 retrieves the board specification reviewing signal from the signal names such as AA0 to DD2 included in the logic diagram data (FIG. 3) stored in the board logic diagram data storage 5. Select a signal for creating / editing layout data. 17 and 18, BB0 to BB2 and CC0
It is assumed that a signal of CC2 is selected.

Next, the board specification study layout data creating / editing section 8 stores the signal names (BB0 to BB2, CC0 to CC2) selected by the board specification study signal selection section 4 and the board logic diagram data storage section 5 And the electronic component library (IC1 to IC3 in FIG. 7) stored in the board specification study preparation data storage section 7 and input the board specification study layout data. make,
The board outline and the board registration name are set in the same procedure as in the first embodiment.

Next, the board specification study layout data creating / editing section 8 arranges an electronic component library and creates wiring for the created board specification study layout data. Verification of timing, waveform, heat, EMC, and the like is performed by the procedure described in the first embodiment on the layout data for board specification study (FIG. 7) on which the placement and wiring have been performed. Layout data creation / editing section 8 for board specification study
Until the normal operation of the circuit can be confirmed by simulation and a good placement state and wiring state can be obtained.
The change of the arrangement of the electronic component library, the change of the wiring, the addition and the change of the electronic component library, the addition and the change of the connection information between the electronic component libraries, etc. are repeated. In the same procedure as in the first embodiment, the outer shape of the substrate and the registered name of the substrate are changed, and the layer configuration of the substrate, the electrical characteristic values of each layer, physical property information, the width and thickness of the conductor of the substrate, the conductor Gap value between,
It is also possible to change the electrical characteristic information of the whole substrate.

FIGS. 17 and 18 illustrate an example in which passive components are added to the signal wiring indicated by the signal name CC0. For the added passive component, it is possible to add a property CHR to the passive component and define its component type, characteristic value, and component type name. In the layout data for board specification study shown in FIG. 17, CHR = R_15 or CHR = EX
_R is added to the added passive component. CHR = R
_15 defines that the type of the added passive component is a resistance element and has a value of 15Ω. This is a function for easily changing the type and characteristic value of the passive component and performing each simulation, thereby improving the efficiency of a series of repetitive operations. When changing the type and characteristics of the passive component, CHR = L_20 (inductor 20 nH), CHR
= C_10 (capacitor 10pF).
It is also possible to input CHR = electronic component library name of passive components. The addition of these passive components and the setting and change of the component type name and the characteristic value are performed using the input unit 1 in the layout data creating / editing unit 8 for examining the board specifications.

Next, the logic diagram data change portion extraction / reflection unit 11 uses the input unit 1 in the board specification study layout data creation / editing unit 8 to change the layout of the electronic component library, change the wiring, Information related to the logic diagram data of the board included in the board specification study layout data obtained as a result of repeatedly adding and changing the component library, adding and changing the connection information between the electronic components,
The changed part is extracted by comparing it with the logic diagram data of the board stored in the board logic diagram data storage unit 5 and reflected in the board logic diagram data storage unit 5. In the logic diagram data (FIG. 18) reflecting the result of the board specification study layout data (FIG. 17), the EX_R component library name and the additional resistance are added to the connection information indicated by the signal name CC0.

In the second embodiment, the layout data creating / editing unit 8 for examining the board specifications uses the input unit 1 to add a passive component, and to set or change the component type and characteristic value of the added passive component. However, other processes such as addition and change of electronic components other than passive components and addition and change of connection information between electronic components are also possible.

In the second embodiment, the explanation has been made on the assumption that the logic diagram data of the board exists. However, the layout data creating / editing section 8 for examining the board specifications uses the input section 1 to examine the board specifications. The electronic component library is called from the preparation data storage unit 7, the connection signals between the electronic components are defined, the arrangement and wiring of the electronic component library are created and changed, and the verification described in the first embodiment is performed. Thus, it is also possible to determine whether or not the components constituting the circuit mounted on the board can be used.

As described above, according to the second embodiment, during the period from the start of the function or logic design of the substrate to the stage of almost completing it, the candidates for the electronic components constituting the circuit mounted on the substrate are: Create temporary layout data for the electronic components that are signal-connected to the electronic components,
Verifies the operation by simulating heat, EMC, etc., determines the electronic components and connection information that optimize the verification results and the arrangement state and wiring state of the board, and uses it as the change information of the logic diagram data. It is possible to handle the design at the data level.

Embodiment 3 Hereinafter, a third embodiment of the present invention will be described. The description of the overlapping portions with the first and second embodiments will be omitted.

FIG. 19 is a diagram showing a configuration of a wiring board designing apparatus according to the third embodiment. In the drawing, reference numeral 15 denotes a board layout design preparation data storage unit for storing information such as the shape of electronic components required for board layout design, connection information between electronic components, and board layer configuration, and 18 denotes layout data storage for board specification study. The layout requirement specification such as the layout position of the electronic component library, the wiring length of the signal wiring, and the wiring layer is extracted from the layout data for board specification study stored in the section 17 and is reflected in the board layout design preparation data storage section 15. A layout requirement specification extraction / reflection unit 19 is an analysis signal / component selection unit for selecting a signal name and an electronic component name for performing a simulation, which will be described later, from the layout data storage unit 17 for examining the board specifications or the board layout design data storage unit 23. Using the information in the input unit 1 and the board layout design preparation data storage unit 15 A board layout and wiring design unit 21 for arranging an electronic component library and creating wiring between electronic components is stored in a signal name and an electronic component name selected by the analysis signal / component selection unit 19 and an analysis preparation data storage unit 22. From the analysis preparation data, the board specification study layout data stored in the board specification study layout data storage unit 17, or the board layout design data stored in the board layout design data storage unit 23. An analysis data processing unit that outputs various data;
Is a board layout design data storage unit that stores the layout design data of the board designed in step 2. The timing simulator 24, the waveform simulator 25, the heat simulator 26, the EMC simulator 27, the timing simulation result storage unit 28, the waveform simulation result storage unit 29, the heat simulation result storage unit 30,
The C simulation result storage unit 31 and the simulation result display unit 32 have the same configurations as those shown in FIG.

FIG. 20 shows a board layout requirement specification extraction / reflection section 18 which converts the board specification study layout data shown in FIG.
5 is an example of board layout requirement specification data reflected in No. 5;

Next, using the wiring board design apparatus shown in FIG. 19, the layout data for examining the board specifications is prepared and edited, and the board operation is verified by simulation of timing, waveform, heat, EMC, etc. The following describes the procedure for determining the layout state and wiring state of the board, extracting board layout requirement specifications from the resulting board study layout data, and reflecting the board layout design preparation data on the board layout design preparation data.

The board logic diagram input unit 3 uses the logic library of the electronic components stored in the board logic diagram input preparation data storage unit 2 and the information from the input unit 1 to output the logic diagram data of the circuit mounted on the board. Create The creation method is the same as in the first embodiment, and a description thereof will not be repeated.

Next, the board specification reviewing signal selector 4 uses the signal names such as AA0 to DD2 included in the logic diagram data (FIG. 3) stored in the board logic diagram data storage 5 to determine the board specification. Select a signal name for creating or editing layout data. In FIG. 20, BB0 to BB2 and CC
It is assumed that signals 0 to CC2 have been selected.

Next, the board specification review layout data creating / editing section 8 stores the signal names (BB0-BB2, CC0-CC2) selected by the board specification review signal selection section 4 and the board logic diagram data storage section 5 And the electronic component library (IC1 to IC3 in FIG. 7) stored in the board specification study preparation data storage section 7 and input the board specification study layout data. make,
The board outline and the board registration name are set in the same procedure as in the first embodiment.

Next, the board specification study layout data creating / editing section 8 arranges an electronic component library and creates wiring for the created board specification study layout data. Verification of timing, waveform, heat, EMC, and the like is performed by the procedure described in the first embodiment on the layout data for board specification study (FIG. 7) on which the placement and wiring have been performed. Layout data creation / editing section 8 for board specification study
Until the normal operation of the circuit can be confirmed by simulation and a good placement state and wiring state can be obtained.
The change of the arrangement of the electronic component library, the change of the wiring, the addition and the change of the electronic component library, the addition and the change of the connection information between the electronic component libraries, etc. are repeated. In the same procedure as in the first embodiment, the outer shape of the substrate and the registered name of the substrate are changed, and the layer configuration of the substrate, the electrical characteristic values of each layer, physical property information, the width and thickness of the conductor of the substrate, the conductor Gap value between,
It is also possible to change the electrical characteristic information of the whole substrate.

Next, the board layout requirement specification extraction / reflection unit 18 uses the input unit 1 in the board specification study layout data creation / editing unit 8 to change the layout of the electronic component library, change the wiring, The board layout requirement specification (FIG. 20) is extracted from the board specification study layout data (FIG. 7) obtained as a result of repeatedly adding and changing the connection information between the electronic component libraries, and the like. This is reflected in the layout design preparation data storage unit 15.

The layout requirement specification is a list data in a programmatic format of information on the arrangement and wiring of electronic components contained in the layout data for board specification study stored in the layout data storage section 17 for board specification study. It was done. The layout requirement items that can be expressed in the format include the layout surface, rotation angle, layout position coordinate value of electronic components, total wiring length of signals, wiring order and wiring width and wiring layer for signal pin specification, and Wiring length, wiring width and wiring layer, wiring length to signal branch point, wiring layer and wiring width, wiring length from wiring point, wiring layer and wiring width, branching method, wiring priority in signal board layout design Ranking.

Preparation data storage unit 1 for board layout design
5 is automatically realized by the board layout design data by the automatic placement and automatic routing functions of the board placement and wiring design unit 20.

Although the third embodiment has been described on the assumption that logic diagram data of a board exists, the layout data creating / editing section 8 for studying board specifications uses the input section 1 to examine board specifications. The electronic component library is called from the preparation data storage unit 7, connection information between the electronic component libraries is defined, the operation of the board is confirmed by each simulation, and the arrangement and wiring state of the electronic component library are determined. It is also possible to extract and reflect the layout requirement specification.

As described above, according to the third embodiment, during the period from the start of the function and logic design of the board to the stage of almost completing it, the electronic component group constituting the circuit mounted on the board and its electronic components Creates temporary layout data of electronic components connected to components and signals, and creates timing, waveform, heat, EM
Verify the operation by performing simulations such as C, determine the verification results, the layout position and wiring method of electronic components that optimize the board layout and wiring conditions, extract them as layout required specifications, and proceed to board layout design It is possible to handle at the data level.

Embodiment 4 Hereinafter, a fourth embodiment of the present invention will be described. The description of the overlapping parts with the first to third embodiments will be omitted.

FIG. 21 is a diagram showing a configuration of a wiring board designing apparatus according to the third embodiment. In the figure, reference numeral 6 denotes a board specification study which stores the shapes of electronic components, board layer configuration, electrical characteristics, physical properties, etc. stored in a board specification study preparation data storage section 7 and a board layout design preparation data storage section 15. It is a data matching processing unit for preparing a board specification and preparing a board layout for performing a matching process for sharing with the board layout design. The timing simulator 24, the waveform simulator 25, the heat simulator 26, the EMC simulator 27, the timing simulation result storage unit 2
8, the waveform simulation result storage unit 29, the thermal simulation result storage unit 30, the EMC simulation result storage unit 31, and the simulation result display unit 32 are shown in FIG.
Are omitted since they are the same as those shown in FIG.

Next, using the wiring board design apparatus shown in FIG. 21, a procedure of a matching process for sharing information of the board specification study preparation data storage unit 7 and the board layout design preparation data storage unit 15 is performed. Is shown below.

First, the board specification study preparation data storage unit 7
And the classification of the preparation data stored in the board layout design preparation data storage unit 15 is the same. However, since the stage of conducting the board specification study and the board layout design in the board design and the user of the wiring board design apparatus are different, the board specification study preparation data storage unit 7 and the board layout design preparation data storage unit 15 A difference occurs in the number stored in one storage unit.

The information stored in the board specification study preparation data storage section 7 and the board layout design preparation data storage section 15 is large, and can be classified into information related to electronic components and information related to the board. The information related to the electronic component is the name of the electronic component, the package shape and height of the electronic component, the Pad shape for mounting the electronic component on the board, and the position coordinates of the Pad. Information related to the substrate includes the name including the production use of the substrate, the number of layers, the thickness and material and physical properties of each layer,
The characteristic impedance (Z0) and the delay value per unit length (Td) of each layer, the thickness and width of each layer conductor layer, and the gap value between conductors of the conductor layer.

As means for sharing the board specification study preparation data storage section 7 and the board layout design preparation data storage section 15, an interface for referring to the same file or database or matching different files or databases. There is, to use.

According to the former means, the information in the board specification study preparation data storage section 7 and the board layout design preparation data storage section 15 are the same and are completely shared. The wiring board design apparatus described in the fourth embodiment assumes the latter example.

Preparation of Board Specifications and Preparation of Board Layout Design In the data matching processing section 6, a preparation data storage section 7 for preparing board specifications and a preparation data storage section 1 for preparing board layout design
5, the number of electronic components and the number of boards stored are compared, and the non-inclusive information in each storage unit is periodically or
When addition or change processing of data stored in each storage unit occurs, only non-inclusive data is overwritten and copied to each storage unit.

As described above, according to the fourth embodiment, the shape of the electronic component and the layer structure of the board stored in the board specification study preparation data storage unit 7 and the board layout design preparation data storage unit 15 are described. It is possible to perform a matching process in order to share electrical characteristics and physical information in both directions.

Embodiment 5 Hereinafter, a fifth embodiment of the present invention will be described. The description of the overlapping portions with the first to fourth embodiments will be omitted.

FIG. 22 is a diagram showing a configuration of a wiring board designing apparatus according to the fifth embodiment. In the figure, reference numeral 14 denotes the board logic diagram data stored in the board logic diagram data storage unit 5 and the board logic diagram data included in the board specification study layout data stored in the board specification study layout data storage unit 17. The information and the information related to the logic diagram data of the board included in the information described in the hardware description language such as HDL input from the input unit 1 are combined and input to the board layout design preparation data storage unit 15. By doing so, it is a board netlist information generation unit that generates netlist information of the board. The timing simulator 24, the waveform simulator 25, and the heat simulator 2
6. The EMC simulator 27, the timing simulation result storage unit 28, the waveform simulation result storage unit 29, the thermal simulation result storage unit 30, the EMC simulation result storage unit 31, and the simulation result display unit 32 have the same configuration as that shown in FIG. Therefore, illustration is omitted.

Next, using the wiring board design apparatus shown in FIG. 22, information on the board logic diagram data included in the board specification study layout data, the board logic diagram data and the HD
A procedure for generating a netlist of a board by synthesizing it with information on logic diagram data of a board described in a hardware description language such as L and inputting it to the board layout design preparation data storage unit 15 Is shown below.

Preparation data storage unit 1 for board layout design
The netlist information of the board to be input to 5 is differentiated by a signal name and a mounting part list in which the correspondence between the name of the electronic component used for the board to be designed and the location number such as IC1, U1, or R1 is described. And a connection information list in which connection information is described. An example of the netlist information of the board is shown below. <Mounted component list> Signal name Electronic component name IC1 BUHIN_A IC2 BUHIN_BR1 BUHIN_C <Connection information list> Signal name Location number of connected component-pin number, ..., ... EXA IC1-5, IC2-1; EXC R1-2, IC2-3; IC1-4, R1-1;

The board net list information generation unit 14 receives the logic diagram data stored in the board logic diagram data storage unit 5 and the board specification study layout data stored in the board specification study layout data storage unit 17. And input unit 1
The above-mentioned mounted component list and connection information list are created for each piece of information described in a hardware description language such as HDL, which is input from the PC.

Next, a comparison is made for each of the three types of mounted component list and connection information list, and if there is no comprehensive part in the mutual list, OR processing is performed for each of the three types of mounted component list and connection information list. To generate a netlist for the board. The board netlist information generated by the board netlist information generator 14 is reflected in the board layout design preparation data storage 15.

Further, the created three types of parts correspondence list and connection information list are compared with each other, and if there is an inclusive part in each of the lists, a list having an inclusive relation and an inclusive part are displayed and a netlist of the board is displayed. Aborts the generation process of. After the inclusion is corrected, a netlist of the board is generated again.

In the description of the fifth embodiment, the logic diagram data stored in the board logic diagram data storage unit 5, the board specification study layout data stored in the board specification study layout data storage unit 17, and the input The board netlist is generated from three types of information described in a hardware description language such as HDL input from the unit 1, but there is only one of the above three pieces of information, or , It is possible to generate a netlist of a board even when there are only two.

As described above, according to the fifth embodiment, the board logic diagram data created by the board logic diagram input unit 3 and the board specifications created and edited by the board specification study layout data creation / editing unit 8 The information on the board logic diagram data included in the study layout data and the information on the board logic diagram data included in the information described in HDL or other format are combined and passed to the board layout design. It is possible to generate netlist data and handle it at the data level as preparation data for layout design.

Embodiment 6 FIG. Hereinafter, a sixth embodiment of the present invention will be described. The description of the overlapping portions with the first to fifth embodiments will be omitted.

FIG. 23 is a diagram showing a configuration of a wiring board designing apparatus according to the sixth embodiment. In the figure, reference numeral 98 denotes all or a part of the board layout design data stored or already designed in the board layout design data storage unit 23 used by the board specification study layout data creating / editing unit 8. This is a board layout design data diversion processing unit that performs diversion processing in order to perform diversion processing. The timing simulator 24, the waveform simulator 25, the heat simulator 26, the EMC simulator 27, the timing simulation result storage unit 28, the waveform simulation result storage unit 29, the heat simulation result storage unit 30, the EMC simulation result storage unit 31, the simulation result display unit 32 has the same configuration as that shown in FIG. 1 and is not shown.

Next, a procedure for diverting all or a part of the board layout design data stored in the board layout design data storage unit 23 using the wiring board design apparatus shown in FIG. 23 will be described.

The board layout design data storage unit 23 stores the layout design data of a board that has already been designed or is currently being designed. The board layout design data includes information on the layout position and wiring of electronic components on the board.

The board specification design layout data creating / editing section 8 uses the board layout design data diversion processing section 98 and the input section 1 to store the board layout design data storage section 2.
Extract information on the layout position and wiring of electronic components of the board that you want to use for creating and editing board specification study layout data from the board layout design data stored in 3 and reflect the information in the board specification study layout data I do.

As described above, according to this embodiment,
When creating or editing board specification study layout data using the board specification study layout data creating / editing unit 8 with all or part of the board layout data for which the board layout design has already been completed. In addition, it can be diverted.

Embodiment 7 FIG. Hereinafter, a seventh embodiment of the present invention will be described. The description of the overlapping portions with the first to sixth embodiments will be omitted.

FIG. 24 is a diagram showing a configuration of a wiring board designing apparatus according to the seventh embodiment. In the drawing, reference numeral 12 denotes a board specification reviewing preparation data storage unit 7 which creates and edits board specification review layout data by using the input unit 1 in a board specification review layout data creating / editing unit 8. An undefined component for examining board specifications and an undefined component creation / editing unit for board information, which can define an electronic component library and board information using the input unit 1. The timing simulator 24, the waveform simulator 25, and the heat simulator 2
6. The EMC simulator 27, the timing simulation result storage unit 28, the waveform simulation result storage unit 29, the thermal simulation result storage unit 30, the EMC simulation result storage unit 31, and the simulation result display unit 32 have the same configuration as that shown in FIG. Therefore, illustration is omitted.

FIG. 25A is an example of a GUI for creating and editing an electronic component library, and FIG. 25B is an example of a GUI for referencing, creating and editing board information.

Next, a procedure for defining a library of undefined electronic components and board information in the board specification study preparation data storage unit 7 using the wiring board design apparatus shown in FIG. 24 will be described.

The electronic component library is created and edited by using the input unit 1 in the undefined component creating / editing unit 12 to register and edit the electronic component library registration / editing G shown in FIG.
This is executed by inputting information into the UI and editing the displayed information.

The electronic component library is created by using the input unit 1 in the electronic component library registration / editing GUI.
Enter the name of the electronic component library, which is the call name of the electronic component library in the layout data creation / editing unit 8 for examining the board specifications, and then enter the product type name of the electronic component corresponding to the electronic component library name. The package name of the electronic component library is selected from the package names registered in the board specification study preparation data storage unit 7 shown in the list field, or is directly keyed in, and then the electronic component library for each pin number of the package is selected. Enter the name and pad shape of the pad for mounting on the board, then enter the package shape, height, and pin generation position coordinates for each pin number, and select the OK button at the bottom of the electronic component library registration / editing GUI. Thus, the electronic component library is defined, and the board specification study preparation data storage unit 7 is updated.

The electronic part library is edited by using the input unit 1 in the electronic part library registration / editing GUI.
Either key-in all the electronic component library names to be the calling names of the electronic component library of the layout data creating / editing unit 8 for examining the board specifications, or use a wildcard.
Enter a character string including (*), execute a search, and enter the desired electronic component library name. Next, a pad name, a pad shape, a package shape, and a height of the electronic component substrate mounted on the electronic component library for each product type name, package name, and package pin number displayed on the electronic component library registration / editing GUI. And edit the pin generation position for each pin number, and click O at the bottom of the GUI for electronic component library registration / edit.
By selecting the K button, the electronic component library is edited, and the board specification study preparation data storage unit 7 is updated.

The creation and editing of board information is performed by inputting information to the board information registration / editing GUI shown in FIG. 25B using the input unit 1 in the undefined part creating / editing unit 12 and displayed. It is executed by editing information.

The board information is created by using the input unit 1 in the board information registration / editing GUI, and a board registration name, which is a board information call name of the board specification study layout data creating / editing unit 8, is shown in a list field. Select from the registered board names registered in the board specification study preparation data storage unit 7 or directly enter a key-in, and then name and attribute of each layer constituting the board and the layer thickness and material as additional information of the layer. And the physical property value, the characteristic impedance (Z0) of the layer, the delay value per unit length (Td), the thickness and width of the conductor layer, the gap value between the conductors of the conductor layer, and the like. By selecting the OK button at the bottom of the editing GUI, the board information is defined, and the board specification study preparation data storage unit 7 is updated.

To edit the board information, the input unit 1 is used in the board information registration / editing GUI, and all the board registration names which are the board information call names of the board specification study layout data creating / editing unit 8 are keyed in. Alternatively, a character string including a wild card (*) is entered and a search is executed to enter a desired electronic component library name, or a board specification study preparation data storage unit 7 shown in a list field
Select and input from the registered board registration name. Next, the name and attribute of each layer constituting the board and the additional information of the layer displayed on the board information registration / editing GUI are edited, and the OK button at the bottom of the board information registration / editing GUI is selected. The information is edited, and the board specification study preparation data storage unit 7 is updated.

As described above, according to the seventh embodiment, it is possible to create and edit the electronic component library and the board information while creating and editing the board specification study layout data. The edited electronic component library and board information can be stored as board specification study preparation data.

Embodiment 8 FIG. Hereinafter, an eighth embodiment of the present invention will be described. The description of the overlapping parts with the first to seventh embodiments will be omitted.

FIG. 26 is a diagram showing a configuration of a wiring board designing apparatus according to the eighth embodiment. In the figure, reference numeral 9 denotes a board specification reviewing board that performs processing for easily arranging an electronic component library on a matrix with respect to the board specification reviewing layout data initially created by the board specification reviewing layout data creating / editing unit 8. This is an initial arrangement processing unit. The timing simulator 24, the waveform simulator 25, the heat simulator 26, the EMC simulator 27, the timing simulation result storage unit 28, the waveform simulation result storage unit 29, and the heat simulation result storage unit 3
0, the EMC simulation result storage unit 31 and the simulation result display unit 32 are not shown because they have the same configuration as that shown in FIG.

FIG. 27A shows the board specification study layout data first created by the board specification study layout data creating / editing section 8, and FIG. 27B shows the board specification study layout data. This is layout data for board specification study as a result of simple layout processing performed by the board layout study initial placement processing unit 9.

Next, using the wiring board designing apparatus shown in FIG.
The procedure for simply arranging the electronic component library of the board specification study layout data created first in the above will be described below.

In the layout data for board specification study first created by the board specification study layout data creating / editing section 8, the electronic component library is set to a certain coordinate value in the layout data as shown in FIG. Automatically concentrated and arranged.

The board specification study initial placement processing section 9 automatically arranges the electronic component libraries of the board specification study layout data created first so that they do not touch each other as shown in FIG. 27 (b). I do. In the eighth embodiment, the arrangement direction of the electronic component library is defined as the direction from the lower left corner to the lower right corner of the board outer shape.

In the eighth embodiment, an example has been described in which the electronic component libraries of the layout data for board specification study created first are automatically arranged so that they do not touch each other. Using the tension method, which is an automatic component placement algorithm, the electronic component libraries do not touch each other, and the average value of the distance between pins that defines the connection information between the electronic component libraries is minimized. It is also possible to arrange.

As described above, according to this embodiment,
When creating and editing board specification study layout data, electronic components can be simply and automatically arranged.

Embodiment 9 FIG. Hereinafter, a ninth embodiment of the present invention will be described. The description of the overlapping parts with the first to eighth embodiments will be omitted.

FIG. 28 is a diagram showing a configuration of a wiring board designing apparatus according to the ninth embodiment. In the drawing, reference numeral 10 denotes a logic diagram data generation unit that generates board logic diagram data from the board specification study layout data held in the board specification study layout data storage unit 17 and stores the board logic diagram data in the board logic diagram data storage unit 5. . The timing simulator 24, the waveform simulator 25, the heat simulator 26, the EMC simulator 27, the timing simulation result storage unit 2
8, the waveform simulation result storage unit 29, the thermal simulation result storage unit 30, the EMC simulation result storage unit 31, and the simulation result display unit 32 are shown in FIG.
Are omitted since they are the same as those shown in FIG.

Next, a procedure for generating board logic diagram data from board specification study layout data using the wiring board design apparatus shown in FIG. 28 will be described.

The board logic diagram data generation unit 10 described in the ninth embodiment generates the board specification study layout data without the board designer or logic designer creating the board logic diagram data. Edit layout data for board specification study with verification by simulation,
When most of the circuits to be mounted on the board are realized by the layout data for board specification study, instead of re-inputting the logic diagram data of the board from the beginning, the logic diagram data of the board is generated from the layout data for board specification study. It is possible to get the maximum effect when utilizing it.

The board logic diagram data is differentiated by the correspondence information between the names of the electronic components used for the board to be designed and the unique location numbers of all the electronic components used, such as IC1, U1, R1, and the signal names. Holds connection-related information. The board specification study layout data stored in the board specification study layout data storage unit 17 includes all of the above two types of information.

The logic diagram data generation unit 10 extracts the above two types of information from the board specification study layout data stored in the board specification study layout data storage unit 17 and converts the information into a logic diagram data description format. To generate board logic diagram data.

As described above, according to this embodiment,
Logic diagram data of a board can be generated from layout data created and edited for board specification study layout data.

Embodiment 10 FIG. Hereinafter, a tenth embodiment of the present invention will be described. The description of the overlapping portions with the first to ninth embodiments will be omitted.

FIG. 29 is a diagram showing a configuration of a wiring board designing apparatus according to the tenth embodiment. In the figure, reference numeral 33 denotes a timing simulation result storage unit 28, a waveform simulation result storage unit 29, and a thermal simulation result storage unit 3.
0, and an error analysis unit that analyzes each simulation result input from the EMC simulation result storage unit 31 based on an error criterion set for each simulation input from the input unit 1. Reference numeral 34 denotes an error analysis result display unit that displays information determined as an error in the error analysis unit 33 as a report and an image.

FIG. 30A is a diagram showing a waveform simulation result in which the waveform simulation result of one signal in the circuit mounted on the board, stored in the waveform simulation result storage unit 29, is displayed in the simulation result storage unit 32. In the drawing, reference numeral 71 denotes a reference value of an overshoot error, and reference numeral 72 denotes a reference value of an undershoot error. FIG. 7B is a diagram showing a report display example of a result determined as an error by the error analysis unit 33. FIG. 9C is a diagram showing layout data in which the signal wiring determined to be an error in the error analysis unit 33 is highlighted, and reference numeral 75 in the figure denotes a signal wiring determined to be an error and highlighted.

Next, the procedure of error analysis and error result display using the wiring board designing apparatus shown in FIG. 29 will be described below.

The error analysis section 33 stores an error reference value for discriminating an error with respect to each simulation result and each simulation result into a timing simulation result storage section 28, a waveform simulation result storage section 29, and a thermal simulation result storage section. Part 30, and EM
A signal input from the C simulation result storage unit 31 is analyzed for a signal determined as an error, a name of a component, an error type, and an error occurrence location.

The error analysis result display section 34 displays a report and an image based on the result analyzed by the error analysis section 33.

For example, FIGS. 30B and 30C show an example of displaying the error analysis result. The waveform of the waveform simulation result image 70 exceeds the overshoot reference value 71 and the undershoot reference value 72, and the error analysis unit 33 confirms the overshoot error and the undershoot error, receives the results, and displays the error analysis result. The unit 34 displays a report display as shown in FIG. 30B and layout data in which the signal wiring 75 in which an error has occurred as shown in FIG. 30C is highlighted.

As described above, according to this embodiment,
It is possible to analyze the execution result of the simulator, identify an error that has an adverse effect on the circuit mounted on the board, and display the location where the error has occurred, so that the designer can recognize the error portion.

Embodiment 11 FIG. Hereinafter, an eleventh embodiment of the present invention will be described. The description of the overlapping parts with the first to tenth embodiments will be omitted.

FIG. 31 is a diagram showing a configuration of a wiring board designing apparatus according to the eleventh embodiment. In the figure, reference numeral 35 denotes a navigation processing unit for instructing a method of correcting and treating a board specification study layout data and a board layout design data holding signals and electronic components determined to be errors by the error analysis unit 33; This is a navigation result display unit that displays a report of the instruction result of the processing unit 35.

FIG. 32 shows a report of the method of avoiding overshoot and undershoot errors in the waveform simulation given as an example in the tenth embodiment by the navigation result display section 36.

Next, the procedure of navigation processing and navigation result display using the wiring board design apparatus shown in FIG. 31 will be described below.

A means for avoiding the result of the error analysis in the error analysis section 33 is instructed by the navigation processing section 35, and the navigation result display section 36 displays the contents of the instruction in a report.

For example, FIG. 32 shows an example of handling the overshoot error and the undershoot error shown in FIG. Upon receiving the results of the overshoot error and the undershoot error in the error analysis unit 33, the navigation processing unit 35 determines means for avoiding the overshoot error and the undershoot error, and the navigation result display unit 36 displays a report of the instruction content. .

As described above, according to this embodiment,
By analyzing the execution result of the simulator and displaying a report on a means for avoiding an error that adversely affects the circuit mounted on the board, the design quality can be made high and uniform.

Embodiment 12 FIG. Hereinafter, a twelfth embodiment of the present invention will be described. In a twelfth embodiment, as another effective example of using the wiring board designing apparatus described in the first to eleventh embodiments, a description will be given of a board specification study of a signal that extends over a plurality of boards. The description of the same parts as those in the first to eleventh embodiments will be omitted.

First, FIG. 3 used for describing the twelfth embodiment will be described.
3 will be described. FIG. 33 (a) is a diagram showing a signal straddling a plurality of substrates.
0 is a substrate. FIG. 33 (b) shows an electronic component library constituting signals crossing a plurality of boards shown in FIG. 33 (a), and board specification study layout data 82 representing the above-mentioned three boards 78, 79 and 80. , 83, 84. FIG.

Next, a procedure for optimally setting the layout requirement specification of a signal across a plurality of substrates will be described below.

Using the input unit 1 in the board specification study layout data creating / editing unit 8, the board outline and the registered name of the board are input in the same procedure as in the first embodiment. Next, an electronic component library, which constitutes a signal extending over a plurality of boards described in the diagram of FIG. Create layout data for When creating the layout data for board specification study, all or a part of the layout design data of the board that has already been designed or is being designed by the board layout design data diversion processing unit 98 described in the sixth embodiment. It is also possible to divert.

Each of the above-described simulations is performed on the created board specification study layout data (FIG. 33B) to verify the operation of the board. The modification of the layout data for board specification examination such as the change of the electronic component library and the change of the wiring is repeatedly executed until the verification result by simulation and the arrangement and the wiring state become good.

The operation has been confirmed by simulation.
In addition, from the layout data for examining the board specifications in which the arrangement and the wiring state are good, the board layout requirement specifications for the board specification study layout data 82, 83, and 84 of the signal that straddles a plurality of boards are reflected in the board layout requirement specification extraction and reflection unit 18. And reflects it on the board layout design preparation data.

In addition, if there is an IC being designed in the IC design for a component constituting a signal that crosses a plurality of boards, the layout data for studying the board specifications is created and edited while performing each simulation in the same manner as described above. It is also possible to determine the interface information of the IC being designed optimally using the IC interface information changed portion extraction / reflection unit 16 described in the first embodiment.

In addition, a signal that straddles a plurality of substrates is
In the same manner as described above, the layout data for examining the board specifications is created and edited while performing each simulation, and the logic diagram data changed portion extraction / reflection unit 11 described in the second embodiment and the logic described in the ninth embodiment are executed. Using the diagram data generation unit 10, the addition and change of electronic components and the creation and change information of connection information of the board specification study layout data generated by editing the board specification study layout data based on the simulation verification results It is also possible to extract / reflect a created or changed part as board logic diagram data.

In the twelfth embodiment, a signal that crosses a plurality of substrates has been described as an example.
A simulation is performed using all layout data for examining a plurality of board specifications, such as electronic components inside a CM to electronic components on a board, and the layout data optimized by the simulation is used in the twelfth embodiment.
It is possible to output information similar to.

[0156]

According to a first aspect of the present invention, there is provided a wiring board design apparatus, which temporarily defines IC interface information including an IC pin assignment and an input / output buffer to be used, and temporarily prepares temporary layout data of an electronic component connected to the IC. Create, simulate and verify the operation. After confirming the verification results and the optimal placement and wiring conditions of the board, determine the pin assignment of the IC and the IC interface information of the buffer used, and proceed to IC design. By handling at the data level, it is possible to set the interface information of the IC whose operation is guaranteed, and furthermore, it is effective in preventing the intervention of human error when setting it.

According to a second aspect of the present invention, a circuit board designing apparatus creates tentative layout data of electronic component candidates constituting a circuit to be mounted on a board and electronic components connected to the electronic components by signals, performs simulation, and verifies the operation. After confirming the verification results and the optimal placement and wiring conditions of the board, determine the electronic components and connection information, and use that information as change information for the board's logic diagram data to the board's logic design. In this way, it is possible to determine the electronic components and the connection information whose operation is guaranteed, and further has the effect of preventing the intervention of a human error when the information is reflected on the logic diagram data.

According to a third aspect of the present invention, there is provided a wiring board designing apparatus which creates temporary layout data of an electronic component constituting a circuit to be mounted on a board and electronic components connected to the electronic component and performs signal simulation to verify operation. After confirming the verification results and the optimal placement and wiring conditions of the board,
By deciding the placement position and wiring method of electronic components and handling them at the data level to the board layout design as layout required specifications, it is possible to determine the placement position and wiring method of electronic components that guarantee product operation. Yes,
In addition, there is an effect of preventing human error when the layout requirement specification is transferred to the layout design of the board.

According to a fourth aspect of the present invention, there is provided a wiring board design apparatus, wherein the shape of an electronic component, the layer structure of a board, the electrical characteristics of the board, and the physical properties of the board are stored in the board specification study preparation data and the board layout design preparation data. By performing consistency processing to share information, data consistency can be ensured.
This has the effect of reducing the load of the preparation work.

According to a fifth aspect of the present invention, there is provided a wiring board designing apparatus, wherein information relating to logic diagram data included in the layout data created / edited by the board specification study layout data creating / editing unit is stored in the board logic diagram data storage unit. By synthesizing with the logic diagram data stored in the above and generating the netlist information of the board necessary for the board layout design, there is an effect that the netlist information of the board can be efficiently created.

According to the wiring board designing apparatus of the sixth aspect, the layout design of the board is diverted at the time of creating the layout data for the board specification study, so that the layout data for the board specification study can be easily created.

In the wiring board designing apparatus according to the present invention, an optimum board specification can be efficiently determined by defining an undefined electronic component library and board information while creating / editing layout data for board specification study. effective.

According to the eighth aspect of the present invention, the electronic component library is simply automatically arranged and displayed during the creation / editing of the board specification study layout data, so that the board specification study layout data is efficiently provided. There is an effect that can be created.

According to the ninth aspect of the present invention, the circuit diagram designing apparatus generates the logic diagram data of the board from the layout data obtained as a result of creating / editing the layout data for examining the board specifications, thereby reducing the load of creating the logic diagram data. effective.

According to a tenth aspect of the present invention, a circuit board designing apparatus analyzes an execution result of a simulator, identifies an error that adversely affects the operation of a circuit mounted on a board, and displays a location where the error has occurred. This has the effect of allowing the designer to recognize the error part.

According to an eleventh aspect of the present invention, a circuit board designing apparatus analyzes a result of execution of a simulator and presents a means for avoiding an error which adversely affects the operation of a circuit mounted on a board, thereby achieving a high and uniform design quality. Has the effect of doing

Since the wiring board designing apparatus according to the twelfth aspect can perform various simulations such as timing, waveform, heat, and EMC, there is an effect that the operation of the designed wiring board is surely guaranteed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a wiring board design apparatus according to a first embodiment.

FIG. 2 is a diagram illustrating an example of simulation results of timing, waveform, heat, and EMC by the wiring board design apparatus of the first embodiment.

FIG. 3 is a diagram showing an example of board logic diagram data.

FIG. 4 is a view showing an example of board specification study layout data immediately after creation;

FIG. 5 is a diagram showing an example of IC interface information.

FIG. 6 is a diagram illustrating an example of board specification study layout data in which the arrangement and wiring of an electronic component library are input.

FIG. 7 is a diagram showing an example of layout data for board specification study of an optimal arrangement and wiring state whose operation has been confirmed by simulation.

FIG. 8 is a diagram showing an example of IC interface information in which optimal settings have been made.

FIG. 9 is a diagram illustrating an example of a board information reference GUI for referring to a board registration name and board information.

FIG. 10 is a diagram illustrating an example of a layer configuration of a substrate and an example of correspondence between a layer name of each layer configuring the substrate and an attribute name of the layer.

FIG. 11 is a diagram illustrating an example of a characteristic impedance of each layer constituting a substrate and a delay value per unit length.

FIG. 12 is a diagram showing an example of a layer thickness of each layer constituting a substrate and a relative dielectric constant of an insulator layer.

FIG. 13 shows the resistivity of a conductor, the relative magnetic permeability of an insulator layer,
It is a figure showing an example of conductivity and a loss angle.

FIG. 14 is a diagram illustrating an example of a wiring width of a conductor formed on a conductor layer.

FIG. 15 is a diagram illustrating an example of a minimum gap value between conductors formed in a conductor layer.

FIG. 16 is a diagram showing a configuration of a wiring board design apparatus according to a second embodiment.

FIG. 17 is a diagram showing layout data for board specification study to which a passive element is added.

FIG. 18 is a diagram showing board logic diagram data reflecting a changed portion.

FIG. 19 is a diagram illustrating a configuration of a wiring board design apparatus according to a third embodiment.

FIG. 20 is a board layout design preparation data storage unit 1
FIG. 11 is a diagram showing an example of board layout requirement specification data reflected in No. 5;

FIG. 21 is a diagram illustrating a configuration of a wiring board design apparatus according to a fourth embodiment.

FIG. 22 is a diagram illustrating a configuration of a wiring board design apparatus according to a fifth embodiment.

FIG. 23 is a diagram illustrating a configuration of a wiring board design apparatus according to a sixth embodiment.

FIG. 24 is a diagram illustrating a configuration of a wiring board designing apparatus according to a seventh embodiment.

FIG. 25 is a diagram illustrating an example of a GUI for defining an electronic component library and board information by the wiring board design apparatus of the seventh embodiment.

FIG. 26 is a diagram showing a configuration of a wiring board designing apparatus according to an eighth embodiment.

FIG. 27 is a diagram illustrating an arrangement of an electronic component library by the wiring board design apparatus according to the eighth embodiment.

FIG. 28 is a diagram illustrating a configuration of a wiring board design apparatus according to a ninth embodiment;

FIG. 29 is a diagram showing a configuration of a wiring board designing apparatus according to a tenth embodiment.

FIG. 30 is a diagram for explaining error processing by the wiring board design apparatus of the tenth embodiment.

FIG. 31 is a diagram illustrating a configuration of a wiring board design apparatus according to an eleventh embodiment.

FIG. 32 is a diagram illustrating a display example of an error avoidance method selected by the navigation processing unit.

FIG. 33 is a diagram showing board specification study layout data expressing a signal extending over a plurality of boards.

FIG. 34 is a diagram showing a conventional pin assignment method.

[Explanation of symbols]

1 input unit, 2 board logic diagram input preparation data storage unit,
3 Board logic diagram input section, 4 Board specification study signal selection section, 5 Board logic diagram data storage section, 6 Preparation data matching processing section, 7 Board specification study preparation data storage section, 8 Board specification study layout data creation / Editing unit, 9 Initial layout processing unit for examining board specifications, 10 Logical diagram data generation unit, 11 Logic diagram data changed part extraction / reflection unit, 12
Undefined component creation / editing unit, 13 IC interface information storage unit, 14 board net list information generation unit, 15
Board layout design preparation data storage section, 16 IC interface information changed portion extraction / reflection section, 17 Board specification study layout data storage section, 18 Board layout requirement specification extraction / reflection section, 19 Analysis signal / component selection section, 20 Board Placement and routing design unit, 21 analysis data processing unit, 22 analysis preparation data storage unit, 23 board layout design data storage unit, 24 timing simulator, 25 waveform simulator, 26 heat simulator,
27 EMC simulator, 28 Timing simulation result storage unit, 29 Waveform simulation result storage unit, 30 Thermal simulation result storage unit, 31
EMC simulation result storage unit, 32 simulation result display unit, 33 error analysis unit, 34 error analysis result display unit, 35 navigation processing unit, 36
Navigation result display section, 98 Board layout design data diversion processing section.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G06F 15/60 664K 668A

Claims (12)

[Claims] An electronic component is arranged, and as data for designing a substrate constituted by wirings connecting the electronic components, a shape of the electronic component, design information of the substrate, and electrical data of the substrate are provided. A board specification study preparation data storage unit for storing specification study data consisting of information; and a board logic diagram for storing board logic diagram data expressing the electronic components mounted on the board and connection information between the electronic components. A data storage unit; an IC interface information storage unit for storing IC interface information including an input / output buffer of an IC arranged on the board and pin assignment information; a board specification study preparation data storage unit; and the board logic diagram Using the data stored in the data storage unit or the IC interface information storage unit, create / edit layout data of the board A layout data creating / editing unit for examining the board specifications; a simulator for verifying the created / edited layout data; and the simulator edited based on the simulation result of the simulator by the board specification examining layout data creating / editing unit. An IC interface information change portion extraction / reflection unit that extracts a change point related to the IC interface information from the layout data and changes the IC interface information stored in the IC interface information storage unit. Wiring board design equipment. 2. The data for designing a board, on which electronic components are arranged and configured by wiring connecting the electronic components, include a shape of the electronic component, design information of the board, and electrical data of the board. A board specification study preparation data storage unit for storing specification study data consisting of information; and a board logic diagram for storing board logic diagram data expressing the electronic components mounted on the board and connection information between the electronic components. Using a data storage unit and data stored in the board specification study preparation data storage unit and the board logic diagram data storage unit, creating / editing board layout data for creating / editing board layout data. An editing unit, a simulator for verifying the created / edited layout data, and the board specification study layout data creating / editing unit. A logic diagram data changing portion for extracting a change related to the board logic diagram data from the layout data edited based on the simulation result of the emulator and changing the logic diagram data stored in the board logic diagram data storage unit A wiring board designing apparatus comprising an extraction / reflection unit. 3. The data for designing a substrate on which electronic components are arranged and configured by wiring connecting the electronic components, the shape of the electronic components, the design information of the substrate, and the electrical information of the substrate. A board specification study preparation data storage unit for storing specification study data consisting of information; and a board logic diagram for storing board logic diagram data expressing the electronic components mounted on the board and connection information between the electronic components. Using a data storage unit and data stored in the board specification study preparation data storage unit and the board logic diagram data storage unit, creating / editing board layout data for creating / editing board layout data. An editing unit; a board specification study layout data storage unit for storing the created / edited layout data; and a board specification study layout data. A simulator for verifying the layout data stored in the storage unit; a board layout design preparation data storage unit for storing layout design preparation data for designing the layout of the board; The layout unit extracts the layout design data from the layout data edited by the editing unit based on the simulation result of the simulator and stored in the board specification study layout data storage unit, and stored in the board layout design preparation data storage unit. A board layout requirement specification extraction / reflection unit for changing the layout design data, and a board layout for implementing the board layout and wiring design based on the connection information stored in the board layout design preparation data storage unit Wiring design department Wiring board design equipment. 4. A data common to both the specification study data stored in the board specification study preparation data storage unit and the layout design data stored in the board layout design preparation data storage unit. 4. The wiring board designing apparatus according to claim 3, further comprising a preparation data matching processing unit for performing a matching process for sharing. 5. Information relating to logic diagram data included in the layout data created / edited by the board specification study layout data creating / editing unit, and logic diagram data stored in the board logic diagram data storage unit. 4. The wiring board designing apparatus according to claim 3, further comprising: a board net list information generating unit that generates net list information of the board by synthesizing the board net list information and stores the generated net list information in the board layout design preparation data storage unit. 6. A board layout design data storage section for storing layout design data designed and arranged by said board arrangement and wiring design section, and said board layout data created / edited by said board specification study layout data creating / editing section. 4. The wiring board designing apparatus according to claim 3, further comprising: a data diversion processing unit that extracts the data from the design data storage unit and stores the extracted data in the board specification study layout data storage unit. 7. An undefined component in which undefined data among the specification study data stored in the board specification study preparation data storage unit is defined by the board specification study layout data creating / editing unit. The wiring board designing apparatus according to any one of claims 1 to 3, further comprising a creating / editing unit. 8. An initial arrangement processing section for arranging and displaying the electronic components on a display device so that the board specification review layout data creating / editing section creates / edits the board layout data. The wiring board designing apparatus according to claim 1, wherein: 9. A logic diagram data of the board is generated based on the board specification study layout data created / edited by the board specification study layout data creating / editing unit and stored in the board logic diagram data storage unit. The wiring board designing apparatus according to any one of claims 1 to 3, further comprising a logic diagram data generation unit that causes the logic diagram data to be generated. 10. An error analysis unit for storing an error criterion for determining whether there is an error in the simulation result of the simulator, and identifying an error in the simulation result based on the error criterion; The wiring board design apparatus according to any one of claims 1 to 3, further comprising: an error analysis result display unit that displays the error specified by the analysis unit. 11. The wiring board designing apparatus according to claim 10, further comprising a navigation processing unit for displaying a method of avoiding the error specified by the error analysis unit. 12. The simulator according to claim 1, wherein the simulator is a timing simulator for verifying whether the signal is at a change point, a waveform simulator for analyzing a transmission waveform of the signal, a heat simulator for analyzing a heat distribution of the board, or an electromagnetic radiation noise of the board. The wiring board designing apparatus according to any one of claims 1 to 3, wherein the wiring board designing apparatus is an EMC simulator for analyzing the circuit board.