GB1452015A - Testing data processing apparatus - Google Patents

Abstract

1452015 Testing a data processing system INTERNATIONAL BUSINESS MACHINES CORP 17 Sept 1974 [8 Oct 1973] 40377/74 Heading G4A [Also in Division H4] A data processing system is tested by transmitting via modems and a transmission line a suitable test micro-program to it from a remotely located central test station, executing the program on the system to generate result data, and transmitting the result data to the central test station for analysis. The central test station and the system under test may be similar and comprise a micro-program controlled processor with a writable program store, an input keyboard, a display, an auxiliary magnetic disc program store, a printer etc. Micro-programs are transmitted to and stored in the system under test and are executed to generate result data. The programs are then deleted from the system under test and the result data is transmitted to the central station where it may be compared with similar data developed by executing the same programs on the central system. The micro-programs in the system under test may be modified from the central station in order to correct faulty operation. The transmissions are controlled by transmit and receive micro-programs resident in both systems which are arranged such that data keyed into and displayed at one, may be displayed at the other. The data is handled in parallel in bytes in the data processing systems and is transmitted serially by bit over the transmission line. Each transmission consists of a number, e.g. 13, of header bytes, the bits in the first twelve of which are different from byte to byte and equal within a byte, the bits in the last byte alternating; a length counter field having a length indicative of the length of the data; an error field containing error detection data; the data field; and two trailer bytes. Synchronization between transmitter and receiver is achieved by causing a signal transition at the end of each byte, inserting an accurately determined delay following the transition, and transmitting the next byte after the delay. The bits are scanned, at the receiver under the control of micro-program loops, and following the scan of the last bit of a byte the scanning frequency is drastically increased. The byte terminating transition and the subsequent delay can thus be measured accurately. At the end of the delay scanning of the next byte resumes at the normal frequency. If the terminating transition is not detected a predetermined time after the scan frequency is increased, the receiver discontinues receipt of the data and selects a resynchronizing routine which, on receipt of the next set of header bytes, resynchronizes the system. On receipt of the data an error field is calculated and compared with the received error field to indicate transmission errors.