FR2407519A1 - CENTRAL PROCESSING UNIT CAPABLE OF EXECUTING VARIABLE LENGTH INSTRUCTIONS - Google Patents

CENTRAL PROCESSING UNIT CAPABLE OF EXECUTING VARIABLE LENGTH INSTRUCTIONS

Info

Publication number
FR2407519A1
FR2407519A1 FR7830344A FR7830344A FR2407519A1 FR 2407519 A1 FR2407519 A1 FR 2407519A1 FR 7830344 A FR7830344 A FR 7830344A FR 7830344 A FR7830344 A FR 7830344A FR 2407519 A1 FR2407519 A1 FR 2407519A1
Authority
FR
France
Prior art keywords
operand
opcode
instruction
variable length
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7830344A
Other languages
French (fr)
Other versions
FR2407519B1 (en
Inventor
William D Strecker
Richard F Lary
Steven F Rothman
Thomas N Hastings
David P Rodgers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of FR2407519A1 publication Critical patent/FR2407519A1/en
Application granted granted Critical
Publication of FR2407519B1 publication Critical patent/FR2407519B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

a. Système de traitement de données numériques comprenant une unité centrale de traitement destinée à répondre à diverses instructions caractérisées en ce qu'elles sont de longueur variable. b. Chaque instruction comprend un code d'opération. Certaines instructions comprennent en outre un ou plusieurs spécificateurs d'opérande. Chaque spécificateur d'opérande peut comprendre un ou plusieurs multiplets de données. Chaque instruction passe dans une mémoire tampon d'instructions. Des circuits de commande dans l'unité centrale décodent le code d'opération et, en succession, chaque multiplet spécificateur d'opérande. Les spécificateurs d'opérande et les informations extraites du code d'opération concernant chaque spécificateur d'opérande sont combinés pour obtenir l'adresse de laquelle l'opérande doit être récupérée ou à laquelle une opérande doit être transférée. La réponse de l'unité centrale à une instruction demandant l'addition de deux termes situés dans des première et seconde positions de mémoire et le stockage de la somme dans une troisième position et les instructions destinées à appeler une sous-routine et à renvoyer la sous-routine à la routine d'appel sont décrites. c. Applications courantes.at. Digital data processing system comprising a central processing unit intended to respond to various instructions characterized in that they are of variable length. b. Each instruction includes an opcode. Some instructions further include one or more operand specifiers. Each operand specifier can include one or more bytes of data. Each instruction goes into an instruction buffer. Control circuits in the central unit decode the opcode and, in succession, each operand specifier byte. The operand specifiers and the information extracted from the opcode about each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. The response from the CPU to an instruction requesting the addition of two terms located in first and second memory locations and storing the sum in a third location and the instructions for calling a subroutine and returning the subroutines to the calling routine are described. vs. Common applications.

FR7830344A 1977-10-25 1978-10-25 CENTRAL PROCESSING UNIT THAT CAN EXECUTE VARIABLE LENGTH INSTRUCTIONS Expired FR2407519B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84505577A 1977-10-25 1977-10-25

Publications (2)

Publication Number Publication Date
FR2407519A1 true FR2407519A1 (en) 1979-05-25
FR2407519B1 FR2407519B1 (en) 1987-08-28

Family

ID=25294286

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7830344A Expired FR2407519B1 (en) 1977-10-25 1978-10-25 CENTRAL PROCESSING UNIT THAT CAN EXECUTE VARIABLE LENGTH INSTRUCTIONS

Country Status (9)

Country Link
JP (1) JPS5931733B2 (en)
AU (1) AU518656B2 (en)
BR (1) BR7807060A (en)
CA (1) CA1114515A (en)
DE (1) DE2846520A1 (en)
ES (1) ES474427A1 (en)
FR (1) FR2407519B1 (en)
GB (1) GB2007887B (en)
IN (1) IN150275B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4415969A (en) * 1980-02-07 1983-11-15 Intel Corporation Macroinstruction translator unit for use in a microprocessor
US4491908A (en) * 1981-12-01 1985-01-01 Honeywell Information Systems Inc. Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit
US4586130A (en) * 1983-10-03 1986-04-29 Digital Equipment Corporation Central processing unit for a digital computer
US5761491A (en) * 1996-04-15 1998-06-02 Motorola Inc. Data processing system and method for storing and restoring a stack pointer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573851A (en) * 1968-07-11 1971-04-06 Texas Instruments Inc Memory buffer for vector streaming
US3577189A (en) * 1969-01-15 1971-05-04 Ibm Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614740A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with circuits for transferring between operating routines, interruption routines and subroutines
US3614741A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with instruction addresses identifying one of a plurality of registers including the program counter
US3710324A (en) * 1970-04-01 1973-01-09 Digital Equipment Corp Data processing system
US3999163A (en) * 1974-01-10 1976-12-21 Digital Equipment Corporation Secondary storage facility for data processing systems
DE2419837B2 (en) * 1974-04-24 1976-12-02 Nixdorf Computer Ag, 4790 Paderborn CIRCUIT ARRANGEMENT FOR ADDRESSING A MICROPROGRAM IN DATA PROCESSING DEVICES AND METHODS FOR EXECUTING JUMP COMMANDS
JPS5145946A (en) * 1974-10-17 1976-04-19 Fujitsu Ltd DEETASHORISHI SUTEMU
JPS5282149A (en) * 1975-12-29 1977-07-09 Fujitsu Ltd Instruction address control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573851A (en) * 1968-07-11 1971-04-06 Texas Instruments Inc Memory buffer for vector streaming
US3577189A (en) * 1969-01-15 1971-05-04 Ibm Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays

Also Published As

Publication number Publication date
JPS5484943A (en) 1979-07-06
DE2846520C2 (en) 1991-10-24
JPS5931733B2 (en) 1984-08-03
IN150275B (en) 1982-08-28
BR7807060A (en) 1979-07-17
AU518656B2 (en) 1981-10-15
AU4104578A (en) 1980-05-01
GB2007887B (en) 1982-07-28
ES474427A1 (en) 1979-04-16
DE2846520A1 (en) 1979-04-26
CA1114515A (en) 1981-12-15
FR2407519B1 (en) 1987-08-28
GB2007887A (en) 1979-05-23

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