ES474427A1 - Central processor unit for executing instruction of variable length - Google Patents

Central processor unit for executing instruction of variable length

Info

Publication number
ES474427A1
ES474427A1 ES474427A ES474427A ES474427A1 ES 474427 A1 ES474427 A1 ES 474427A1 ES 474427 A ES474427 A ES 474427A ES 474427 A ES474427 A ES 474427A ES 474427 A1 ES474427 A1 ES 474427A1
Authority
ES
Spain
Prior art keywords
operand
address
central processor
instruction
specifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES474427A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of ES474427A1 publication Critical patent/ES474427A1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

A digital data processing system includes a central processor responding to variable length instructions. Each instruction includes an operation code 50 and one or more operand specifiers 51- 53. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code 50 and, in succession, each operand specifier byte. Each operand specifier includes a register mode field 54 which indicates if the operand specifier includes the operand or the address of a register from which the operand is to be retrieved or to which an operand is to be transferred. The contents of the addressed register may instead be the memory address of the operand, which may be incremented or decremented before being applied to the memory, or may be the memory address at which the memory address of the operand is stored or may be an index address to be added to the address supplied by a send operand specifier byte to form the operand address. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.
ES474427A 1977-10-25 1978-10-23 Central processor unit for executing instruction of variable length Expired ES474427A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84505577A 1977-10-25 1977-10-25

Publications (1)

Publication Number Publication Date
ES474427A1 true ES474427A1 (en) 1979-04-16

Family

ID=25294286

Family Applications (1)

Application Number Title Priority Date Filing Date
ES474427A Expired ES474427A1 (en) 1977-10-25 1978-10-23 Central processor unit for executing instruction of variable length

Country Status (9)

Country Link
JP (1) JPS5931733B2 (en)
AU (1) AU518656B2 (en)
BR (1) BR7807060A (en)
CA (1) CA1114515A (en)
DE (1) DE2846520A1 (en)
ES (1) ES474427A1 (en)
FR (1) FR2407519B1 (en)
GB (1) GB2007887B (en)
IN (1) IN150275B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4415969A (en) * 1980-02-07 1983-11-15 Intel Corporation Macroinstruction translator unit for use in a microprocessor
US4491908A (en) * 1981-12-01 1985-01-01 Honeywell Information Systems Inc. Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit
US4586130A (en) * 1983-10-03 1986-04-29 Digital Equipment Corporation Central processing unit for a digital computer
US5761491A (en) * 1996-04-15 1998-06-02 Motorola Inc. Data processing system and method for storing and restoring a stack pointer

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573851A (en) * 1968-07-11 1971-04-06 Texas Instruments Inc Memory buffer for vector streaming
US3577189A (en) * 1969-01-15 1971-05-04 Ibm Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays
US3614740A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with circuits for transferring between operating routines, interruption routines and subroutines
US3614741A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with instruction addresses identifying one of a plurality of registers including the program counter
US3710324A (en) * 1970-04-01 1973-01-09 Digital Equipment Corp Data processing system
US3999163A (en) * 1974-01-10 1976-12-21 Digital Equipment Corporation Secondary storage facility for data processing systems
DE2419837B2 (en) * 1974-04-24 1976-12-02 Nixdorf Computer Ag, 4790 Paderborn CIRCUIT ARRANGEMENT FOR ADDRESSING A MICROPROGRAM IN DATA PROCESSING DEVICES AND METHODS FOR EXECUTING JUMP COMMANDS
JPS5145946A (en) * 1974-10-17 1976-04-19 Fujitsu Ltd DEETASHORISHI SUTEMU
JPS5282149A (en) * 1975-12-29 1977-07-09 Fujitsu Ltd Instruction address control system

Also Published As

Publication number Publication date
JPS5484943A (en) 1979-07-06
DE2846520C2 (en) 1991-10-24
JPS5931733B2 (en) 1984-08-03
IN150275B (en) 1982-08-28
BR7807060A (en) 1979-07-17
AU518656B2 (en) 1981-10-15
AU4104578A (en) 1980-05-01
GB2007887B (en) 1982-07-28
FR2407519A1 (en) 1979-05-25
DE2846520A1 (en) 1979-04-26
CA1114515A (en) 1981-12-15
FR2407519B1 (en) 1987-08-28
GB2007887A (en) 1979-05-23

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