CN209747520U - Novel enhanced semiconductor device - Google Patents

Abstract

The utility model relates to a novel enhancement mode semiconductor device. The device comprises a substrate, a semiconductor epitaxial layer, a gate, a source and a drain. The epitaxial layers include a nitride nucleation layer, a nitride stress buffer layer, a nitride channel layer, a primary epitaxial nitride barrier layer, a p-type nitride layer, and a secondary epitaxial nitride barrier layer. And (4) reserving the p-type nitride in the gate region through etching to realize the pinch-off of the gate channel. Through maskless secondary epitaxy, a secondary epitaxy nitride barrier layer grows on the primary epitaxy barrier layer and the p-type nitride layer of the grid region, and a high-conduction access region is achieved. The secondary epitaxy can effectively repair the etching damage, and the requirement on the etching process is also reduced. And by regulating and controlling the thickness and components of the primary epitaxial nitride barrier layer and the secondary epitaxial nitride barrier layer, better gate turn-off and access area conduction capacities are realized. The utility model discloses can realize high threshold voltage, high enhancement mode semiconductor device who switches on, high stability, low electric leakage.

Description

Novel enhanced semiconductor device

Technical Field

The utility model relates to a semiconductor device technical field, it is more specific, relate to a novel enhancement mode semiconductor device.

Background

Third generation semiconductor materials represented by GaN materials have a large development space in the fields of high temperature, high frequency, radiation resistance and high power applications due to the advantages of wide forbidden band width, high thermal conductivity, high breakdown electric field and the like.

The GaN-based electronic device generally works by utilizing two-dimensional electron gas with high concentration and high mobility at an AlGaN/GaN heterostructure interface, so that the device has the advantages of small on-resistance, large output current and high switching speed. However, it is also due to this AlGaN/GaN heterostructure (high two-dimensional electron gas, 2DEG) that the device is also naturally on, i.e. depletion mode operation, with zero applied gate bias.

The realization of high-performance normally enhanced devices is an important challenge facing GaN-based electronic devices, and requires more correct threshold voltage to simplify the peripheral circuits of the devices and ensure the failure safety of the system, thereby ensuring the reliable operation of the devices. The general idea for implementing a normally-off device is to keep the 2DEG with a high turn-on of the access region, i.e., not to affect the on-resistance of the device, and simultaneously deplete the channel 2DEG under the gate, so as to implement that the gate of the device is also in a turn-off state without applying a voltage. At present, 3 methods are commonly used in the industry to realize normally-off GaN-based DEVICES (IEEE TRANSACTIONS ON electric DEVICES, vol.64, No.3, MARCH 2017, Page 779-: (1) an insulated trench gate structure (MOSFET), (2) a Cascode structure (Cascode) (3) a p-type gate structure (p-GaN gate, as shown in fig. 1).

In the structure, the p-type gate device has the advantages of simple structure, good threshold voltage stability and the like, and is concerned by the academic and industrial fields. Currently, p-type gate devices have been commercialized, and main companies that have pursued such structural devices include Panasonic corporation in japan, EPC corporation in the united states, and GaN Systems corporation in canada. In particular, Panasonic company adopts a technical scheme combining groove etching, secondary growth and p-type layer etching to prepare a p-type gate device (IEEE TRANSACTIONELECTRON DEVICES, VOL.64, NO.3, MARCH 2017, Page 1026) 1031 with better threshold voltage characteristics. At present, regarding the implementation of a p-type gate normally-off AlGaN/GaN HEMT device, an etching technical scheme is mainly adopted in the industry, and the technology is a method commonly adopted in the industry due to easy implementation, however, the method has many disadvantages, for example, when an access region p-GaN material is removed by etching, due to poor etching uniformity and over-etching problems, and the etching may bring lattice damage to the surface of an AlGaN barrier layer and introduce an additional defect level, the electrical characteristics of an access region 2DEG may be degraded, thereby affecting the performance uniformity and stability of the device. Another technical solution selective area growth p-GaN technique is also adopted (as shown in fig. 2), i.e. selective area growth of p-GaN layer is performed on the AlGaN/GaN heterostructure, so as to realize a structure that the gate region forms the p-GaN layer, and the access region does not have the p-GaN layer (Materials Science in Semiconductor Processing, vol.78,2018, Pages 96-106). However, due to the influence of epitaxial growth kinetics, when the gate length of the device is small, i.e. the growth window is narrow, the selective growth of the p-GaN material is difficult to control and the doping is not uniform, and there is no breakthrough progress in these aspects. Furthermore, a patterned mask layer needs to be additionally formed on the surface of the wafer during selective area growth, the SiO2 mask layer is most commonly adopted, SiO2 is easy to decompose at high temperature to generate Si and O elements, the Si and O elements are easy to diffuse into an epitaxial layer to form donor type doping, so that electric leakage is caused, the epitaxial crystal quality is seriously influenced, and the influence of the mask layer on the epitaxial growth kinetics is not negligible. In addition, the hole concentration of the p-GaN layer is generally not high, and currently, the mainstream reported value is not substantially higher than 1 × 1018cm-3, so that the Al composition of the AlGaN barrier layer below the p-GaN layer is generally required to be lower than 20% and the thickness is lower than 18nm, which is beneficial to realizing enhancement operation, but simultaneously, the resistance of an access region is increased, and the relatively thin AlGaN barrier layer also enables a doping element (such as magnesium) in the p-GaN layer to be more easily diffused to a channel, thereby affecting the reliability of the device.

SUMMERY OF THE UTILITY MODEL

The utility model discloses an overcome above-mentioned prior art at least a defect, provide a novel enhancement mode semiconductor device, can realize higher threshold voltage, lower on-resistance, lower leakage current to and more stable operating condition.

In order to solve the technical problem, the utility model discloses a technical scheme is: a novel enhancement mode semiconductor device comprises a substrate, a semiconductor epitaxial layer grown on the substrate, a grid electrode, a source electrode and a drain electrode. The epitaxial layer comprises a nitride nucleating layer, a nitride stress buffer layer, a nitride channel layer, a primary epitaxial nitride barrier layer, a p-type nitride layer and a secondary epitaxial nitride barrier layer from bottom to top; the p-type nitride layer is only reserved on the primary epitaxial nitride barrier layer of the grid region, and the pinch-off of a two-dimensional electron gas channel below the grid is realized; the secondary epitaxy is maskless, and the secondary epitaxy nitride barrier layer grows on the primary epitaxy barrier layer and the p-type nitride layer of the grid region.

And etching the p-type nitride outside the gate region, and leaving the p-type nitride in the gate region to realize the pinch-off of the gate channel. The secondary growth process is free from the influence of a mask, and the secondary epitaxial nitride barrier layer grows on the primary epitaxial barrier layer and the p-type nitride layer in the grid region, so that a high-conduction access region is realized. Meanwhile, by regulating and controlling the thickness and the components of the primary epitaxial nitride barrier layer and the secondary epitaxial nitride barrier layer, a better grid turn-off capability and a high-conductivity grid source access region and a high-conductivity grid drain access region are realized. And the method can effectively repair the access area damage caused by etching, and the requirement on the etching process is also reduced. Finally, the enhanced semiconductor device with high threshold voltage, high conductivity and high stability is realized.

further, the substrate is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate, a GaN free-standing substrate, or AlN.

Furthermore, the nitride stress buffer layer is any one or combination of AlN, AlGaN, GaN and SiN; the nitride nucleating layer is an Al-containing nitride layer.

furthermore, the nitride channel layer is a GaN or AlGaN layer.

Further, the primary epitaxial nitride barrier layer is made of one or a combination of any more of AlGaN, AlInN, InGaN, AlInGaN and AlN, the Al component is 1-30%, and the thickness is 1-30 nm;

further, the secondary epitaxial nitride barrier layer is one or a combination of any more of AlGaN, AlInN, InGaN, AlInGaN and AlN, the Al component is 1-40%, and the thickness is 1-40 nm;

Furthermore, the p-type nitride layer is GaN, AlGaN, AlInN or AlInGaN, and the thickness is not less than 5 nm.

furthermore, an AlN space isolating layer is inserted between the primary epitaxial nitride barrier layer and the nitride channel layer, and the thickness of the AlN space isolating layer is 0.3nm-3 nm.

furthermore, an AlN barrier layer is inserted between the p-type nitride layer and the primary epitaxial nitride barrier layer, and the thickness of the AlN barrier layer is 0.3nm-5 nm.

Further, the secondary epitaxial nitride barrier layer generally has a higher aluminum composition than the primary epitaxial nitride barrier layer.

Further, the p-type nitride layer of the gate region is retained, and the primary epitaxial nitride barrier layer of the region other than the region below the p-type nitride layer of the gate region is partially removed, with the remaining primary epitaxial nitride barrier layer having a thickness of 1-30 nm.

further, a cap layer and a passivation layer are grown on the secondary epitaxial nitride barrier layer in place; the cap layer is GaN with the thickness of 0.5-8 nm; the passivation layer is SiN with the thickness of 1-100 nm.

Furthermore, the source electrode and the drain electrode are in ohmic contact, and the grid electrode is in ohmic contact or Schottky contact.

Furthermore, the gate metal can be directly contacted with the secondary epitaxial nitride barrier layer, or directly contacted with the p-type nitride layer after etching off part of the secondary epitaxial nitride barrier layer above the p-type nitride layer.

the preparation method of the novel enhanced semiconductor device comprises the following steps:

S1, growing a nitride nucleation layer on a substrate;

S2, growing a nitride nucleation layer on the substrate;

S3, growing a nitride channel layer on the nitride stress buffer layer;

S4, growing a primary epitaxial nitride barrier layer on the nitride channel layer;

S5, growing a p-type nitride layer on the primary epitaxial nitride barrier layer;

S6, forming a p-type gate structure by a photoetching patterning and etching method;

S7, growing a secondary epitaxial nitride barrier layer;

S8, activating acceptor doping elements in the p-type nitride layer through high-temperature annealing;

S9, completing device isolation by dry etching, and etching ohmic contact regions of a source electrode and a drain electrode at the same time;

S10, forming ohmic contact metal of a source electrode and a drain electrode on the source electrode area and the drain electrode area;

S11, forming grid metal on the p-type nitride layer of the grid region.

In the background art, the conventional etching scheme is used for preparing a p-type gate enhancement device, so that the requirements on equipment and a process are very strict, and the problems caused by over-etching and etching damage exist, so that the characteristics of the device are seriously deteriorated. The patent of the utility model provides an adopt the sculpture scheme to combine the secondary growth technique: the method comprises the following steps of removing the p-type nitride layer and part of the primary epitaxial nitride barrier layer outside the gate region through dry etching, and reserving the p-type nitride layer and the primary epitaxial nitride barrier layer in the gate region, so that the gate channel is pinched off. And then carrying out secondary epitaxy, carrying out MOCVD (metal organic chemical vapor deposition) on-line high-temperature repair on etching damage of the primary epitaxial barrier layer (which can be in the environment of nitrogen, ammonia or mixed gas thereof), and then growing a secondary epitaxial nitride barrier layer, thereby realizing a high-conductivity access region channel outside the gate region. The side (nonpolar or semipolar, hardly generating 2DEG) and upper side of the p-type nitride layer of the gate region can also grow a secondary epitaxial barrier layer, and due to the depletion effect of the holes in the p-type nitride layer, the turn-off can also be completely guaranteed at the two sides. And then, the primary extension barrier layer and the secondary extension barrier layer of the device can be redesigned, including the composition of aluminum element in the barrier layers and the thickness design of the barrier layers, so that the switching characteristic is remarkably improved.

Compared with the prior art, the beneficial effects are: the utility model provides a pair of novel enhancement mode semiconductor device adopts the secondary technique of extending, and this also provides the feasibility for the regional nitride barrier layer design of access area beyond the grid region and grid, once extends nitride barrier layer and the epitaxial nitride barrier layer structure of secondary through the design to reasonable while has realized the turn-off characteristic of grid below heterojunction channel and the conductivity of access area heterojunction channel beyond the grid region, and this advantage adopts present existing etching scheme or select the epitaxial p-GaN scheme of district not possess. The utility model discloses the technique can effectively realize high threshold voltage, high conductivity, low electric leakage, high stability's enhancement device finally.

Drawings

Figure 1 is a schematic diagram of an enhancement device in a prior art etch scheme.

Fig. 2 is a schematic diagram of an enhancement mode device in a conventional selective epitaxial p-GaN scheme.

Fig. 3 to 11 are schematic process views of a device manufacturing method according to embodiment 1 of the present invention.

fig. 12 is a final step of the process flow of the device manufacturing method according to embodiment 1 of the present invention, and is a schematic view of the overall structure of the device according to embodiment 1.

Fig. 13 is a schematic structural diagram of a device according to embodiment 2 of the present invention.

Fig. 14 is a schematic structural diagram of a device according to embodiment 3 of the present invention.

Fig. 15 is a schematic structural diagram of a device according to embodiment 4 of the present invention.

Fig. 16 is a schematic structural diagram of a device according to embodiment 5 of the present invention.

Fig. 17 is a schematic structural diagram of a device according to embodiment 6 of the present invention.

Fig. 18 is a schematic structural diagram of a device according to embodiment 7 of the present invention.

Fig. 19 is a schematic structural diagram of a device according to embodiment 8 of the present invention.

Fig. 20 is a schematic structural diagram of a device according to embodiment 9 of the present invention.

fig. 21 is a schematic structural diagram of a device according to embodiment 10 of the present invention.

Fig. 22 is a schematic structural diagram of a device according to embodiment 11 of the present invention.

fig. 23 is a schematic structural diagram of a device in embodiment 12 of the present invention.

Fig. 24 is a schematic structural diagram of a device according to embodiment 13 of the present invention.

in the figure, 1-substrate; a 2-nitride nucleation layer; a 3-nitride stress buffer layer; a 4-nitride channel layer; 5-primary epitaxial nitride barrier layer; a 6-p type nitride layer; 7-secondary epitaxial nitride barrier layer; an 8-source electrode; 9-a drain electrode; 10-a gate; 11-AlN space isolation layer; 12-a secondary epitaxial nitride channel layer; 13-capping layer or passivation layer in place; 14-a passivation layer; 15-source field plate; 16-cross over dielectric layer; 17-a thick drain electrode; an 18-SiO2 mask layer.

Detailed Description

the drawings are for illustrative purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.

example 1:

As shown in fig. 12, which is a schematic view of the device structure of this embodiment, a semiconductor enhancement type transistor includes a substrate 1, a semiconductor epitaxial layer grown on the substrate 1, a gate 10, a source 8, and a drain 9. The epitaxial layer comprises a nitride nucleation layer 2, a nitride stress buffer layer 3, a nitride channel layer 4, a primary epitaxial nitride barrier layer 5, a p-type nitride layer 6 and a secondary epitaxial nitride barrier layer 7 from bottom to top. The p-type nitride layer 6 only remains on the primary epitaxial nitride barrier layer 5 in the region of the gate 10, enabling pinch-off of the two-dimensional electron gas channel below the gate 10. The secondary epitaxy is maskless and the secondary epitaxial nitride barrier layer 7 is grown on the primary epitaxial barrier layer and the p-type nitride layer 6 in the region of the gate 10.

The method for manufacturing the semiconductor enhancement transistor is shown in fig. 3-12, and comprises the following steps:

S1, growing a nitride nucleation layer 2 on a substrate 1, as shown in figure 3;

s2, growing a nitride stress buffer layer 3 on the nitride nucleation layer 2, as shown in figure 4;

S3, growing a nitride channel layer 4 on the nitride stress buffer layer 3, as shown in figure 5;

S4, growing a primary epitaxial nitride barrier layer 5 on the nitride channel layer 4, as shown in FIG. 6;

S5, growing a p-type nitride layer 6 on the primary epitaxial nitride barrier layer 5, as shown in FIG. 7;

S6, removing all the p-type nitride layer 6 outside the gate 10 region by a photoetching patterning and etching method, and removing part of the primary epitaxial nitride barrier layer 5 outside the gate 10 region, as shown in FIG. 8;

s8, repairing the crystal lattice damage caused by etching through high-temperature online annealing, and further growing a secondary epitaxial nitride barrier layer 7 as shown in FIG. 9;

S9, activating an acceptor doping element in the p-type nitride layer 6 through high-temperature annealing;

S11, completing device isolation by dry etching, as shown in FIG. 10;

S12, forming ohmic contact metal of the source electrode 8 and the drain electrode 9 on the source electrode 8 and the drain electrode 9 areas, as shown in figure 11;

S13. form the gate 10 metal on the p-type nitride layer 6 in the gate 10 area, as shown in fig. 12.

Thus, the whole device manufacturing process is completed. Fig. 12 is a schematic view of the device structure of example 1.

Example 2

Fig. 13 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: in example 2, an AlN space isolation layer 11 is further interposed between the nitride channel layer 4 and the primary epitaxial nitride barrier layer 5, and has a thickness of 0.3 to 3 nm. For improving the two-dimensional electron gas characteristics of the channel.

Example 3

Fig. 14 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: example 1 was a case where the portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region was removed, while the portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region remained intact in example 3. Example 3 requires a more demanding etch recipe, such as more advanced equipment, or self-terminating etch conditions containing oxygen or fluorine, than example 1.

Example 4

fig. 15 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: example 1 is a case where the portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region is removed, whereas example 4 is a case where the entire portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region is removed. In embodiment 4, a thin AlN space isolation layer 11 may also be grown to a thickness of 0.3-3nm prior to the growth of the secondary epitaxial nitride barrier layer 7.

Example 5

fig. 16 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: in example 1, a portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region was removed, whereas in example 5, the primary epitaxial nitride barrier layer 5 outside the gate 10 region was completely removed, and a portion of the nitride channel layer 4 was further removed. In embodiment 5, a thin AlN space isolation layer 11 may also be grown to a thickness of 0.3-3nm prior to the growth of the secondary epitaxial nitride barrier layer 7.

Example 6

Fig. 17 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: in example 1, the portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region was removed, whereas in example 6, the entire portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region was removed, and further a portion of the nitride channel layer 4 was removed, and a secondary epitaxial nitride channel layer 12 was sandwiched in the secondary growth. Wherein the thickness of the secondary epitaxial nitride channel layer 12 is 1-10 nm. In embodiment 6, a thin AlN space isolation layer 11 may also be grown to a thickness of 0.3-3nm prior to the growth of the secondary epitaxial nitride barrier layer 7.

Example 7

Fig. 18 is a schematic view of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: in embodiment 7, the second epitaxial nitride barrier layer 7 in the ohmic contact region is etched, or further etched into the first epitaxial nitride barrier layer 5, to achieve better ohmic contact characteristics, and the thickness of the finally remaining barrier layer is 1-10 nm.

example 8

fig. 19 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: in example 8, there is also an in-situ grown cap or passivation layer 13 over the secondary epitaxial nitride barrier layer 7. The cap layer is GaN and has a thickness of 0-8 nm. The in-place passivation layer is made of SiNx, SiO2, Al2O3, AlOxNy, GaOx and GaOxNy, and the thickness is 0-100 nm.

example 9

Fig. 20 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: in example 9, a passivation layer 14 is formed by ex-situ growth on the secondary epitaxial nitride barrier layer 7. The passivation layer 14 is a high-k dielectric such as SiNx, SiO2, Al2O3, or a stacked structure thereof, and the growth process is LPCVD, PECVD, RTCVD, ALD, PEALD, or the like.

Example 10

Fig. 21 is a schematic diagram of the device structure of the present embodiment, which is different from the structures of embodiment 1 and embodiment 9 only in that: in example 10, the device gate 10 contains a field plate structure.

Example 11

Fig. 22 is a schematic diagram of the device structure of the present embodiment, which is different from the structures of embodiment 1 and embodiment 10 only in that: in example 10, the device source electrode 8 includes a field plate structure.

example 12

Fig. 23 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: in example 1, the p-type nitride layer 6 was rectangular in shape; in example 12, the p-type nitride layer had a trapezoidal shape 6. In addition, it is obvious that the p-type nitride shape can also be an arc-shaped structure, a step-shaped structure and the like.

Example 13

Fig. 24 is a schematic view of the device structure of this embodiment, which is different from embodiment 1 only in that: in embodiment 1, the gate 10 metal is in direct contact with the secondary epitaxial nitride barrier layer 7. In example 13, the gate 10 metal may be directly in contact with the p-type nitride barrier layer by etching openings to a portion of the secondary epitaxial barrier layer above the p-type nitride barrier layer. Furthermore, it is clear that the depth of the etched opening can vary: firstly, the etching opening depth can be smaller than the thickness of the secondary epitaxial barrier layer, and the etching depth is 1-30 nm; secondly, the depth of the etched opening can be larger than the thickness of the secondary epitaxial barrier layer, namely the p-type nitride layer 6 can also be etched, and the etching depth range of the p-type nitride layer 6 is preferably 1-10 nm. Furthermore, the width of the etched opening may be varied, i.e. the width of the opening is less than or equal to the width of the p-type nitride layer 6.

It is obvious that the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not limitations to the embodiments of the present invention. The utility model discloses a secondary epitaxial barrier layer after core content is p type nitride layer sculpture again can reduce the requirement to the sculpture technology on the one hand, and on the other hand can once be through the thickness and the component of epitaxial nitride barrier layer of design and secondary epitaxial nitride barrier layer, and then obtains the enhancement device of high threshold voltage, high conductivity, high stability. The present invention only utilizes several device structures to clarify the related art, but is still feasible in other similar device schemes through deformation or combination, and is not described one by one here. It will be apparent to those skilled in the art that various other changes and modifications can be made based on the above description, and the technical solutions in the embodiments including the selection of the step sequence, the material kind and parameters, the selection of the process method and parameters, etc., can be combined and changed as appropriate, and can be combined with each other as appropriate, to form other embodiments understood by those skilled in the art. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims (7)

1. a novel enhancement type semiconductor device comprises a substrate (1), a semiconductor epitaxial layer grown on the substrate (1), a grid electrode (10), a source electrode (8) and a drain electrode (9); the epitaxial layer is characterized by comprising a nitride nucleating layer (2), a nitride stress buffer layer (3), a nitride channel layer (4), a primary epitaxial nitride barrier layer (5), a p-type nitride layer (6) and a secondary epitaxial nitride barrier layer (7) from bottom to top; the p-type nitride layer (6) is only reserved on the primary epitaxial nitride barrier layer (5) in the area of the grid electrode (10), and the two-dimensional electron gas channel below the grid electrode (10) is pinched off; the secondary epitaxial nitride barrier layer (7) is free of mask in the growth process; the secondary epitaxial nitride barrier layer (7) is located on the primary epitaxial nitride barrier layer (5) and the p-type nitride layer (6) in the region of the gate (10).

2. a new enhancement mode semiconductor device according to claim 1, wherein an AlN space isolation layer (11) is further interposed between the primary epitaxial nitride barrier layer (5) and the nitride channel layer (4), the AlN space isolation layer (11) having a thickness of 0.3nm to 3 nm.

3. A new enhancement-mode semiconductor device according to claim 1, characterized in that an AlN barrier layer is further interposed between the p-type nitride layer (6) and the primary epitaxial nitride barrier layer (5), the AlN barrier layer having a thickness of 0.3nm to 5 nm.

4. A new enhancement-mode semiconductor device according to claim 1, characterized in that said secondary epitaxial nitride barrier layer (7) has a higher aluminum composition than said primary epitaxial nitride barrier layer (5).

5. a new enhancement-mode semiconductor device according to any one of claims 1 to 4, characterized in that the p-type nitride layer (6) in the region of the gate (10) is retained and the primary epitaxial nitride barrier layer (5) in the region of the gate (10) other than below the p-type nitride layer (6) is partially removed, the primary epitaxial nitride barrier layer (5) having a thickness of 1-30 nm.

6. A new type of enhancement mode semiconductor device according to claim 5 characterized in that a cap or passivation layer (13) is also grown in place on top of said secondary epitaxial nitride barrier layer (7); the cap layer is GaN with the thickness of 0.5-8 nm; the passivation layer is made of SiNx, SiO2, Al2O3, AlOxNy, GaOx and GaOxNy, and the thickness of the passivation layer is 1-100 nm.

7. a novel enhancement mode semiconductor device according to claim 6 wherein the source (8) and drain (9) are ohmic contacts and the gate (10) is an ohmic or Schottky contact; the metal of the grid electrode (10) can be directly contacted with the secondary epitaxial nitride barrier layer (7), or after part of the secondary epitaxial nitride barrier layer (7) above the p-type nitride layer (6) is etched, the metal of the grid electrode (10) can be directly contacted with the p-type nitride layer (6).