CN213184300U

CN213184300U - Nitride device with high reliability

Info

Publication number: CN213184300U
Application number: CN202021997202.5U
Authority: CN
Inventors: 刘扬; 何亮
Original assignee: Sun Yat Sen University
Current assignee: Sun Yat Sen University
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2021-05-11
Anticipated expiration: 2030-09-14

Abstract

The utility model relates to a nitride device with high reliability. The semiconductor device comprises a substrate, a semiconductor epitaxial layer grown on the substrate, a grid electrode, a source electrode and a drain electrode; the epitaxial layer sequentially comprises a nitride nucleating layer, a nitride stress buffer layer, a nitride channel layer, a primary epitaxial nitride barrier layer, a p-type nitride layer, a secondary epitaxial nitride barrier layer and a secondary epitaxial insulating medium layer from bottom to top; the p-type nitride layer only remains on the primary epitaxial nitride barrier layer in the gate region; no mask is used in the process of growing the secondary epitaxial nitride barrier layer; the secondary epitaxial nitride barrier layer and the secondary epitaxial insulating medium layer are positioned on the primary epitaxial nitride barrier layer and the p-type nitride layer of the grid region; and forming a stacking structure containing a secondary extension insulating medium layer, a secondary extension nitride barrier layer, a p-type nitride layer and a primary extension nitride barrier layer on the grid. The semiconductor device with high threshold voltage, high conduction, high stability and low electric leakage is effectively realized.

Description

Nitride device with high reliability

Technical Field

The present invention relates to the field of semiconductor device technology, and more particularly, to a nitride device having high reliability.

Background

The third generation semiconductor material of gallium nitride (GaN) material has the advantages of wide forbidden band, high thermal conductivity, high breakdown electric field and the like, so the third generation semiconductor material has huge application prospect in the fields of high power, high frequency and the like. Due to the high concentration and high mobility of the two-dimensional electron gas (2DEG) at the AlGaN/GaN heterostructure interface, the device has the advantages of small on-resistance, large output current, and fast switching speed, but it is naturally in a depletion mode. The realization of high-performance normally enhanced devices is an important challenge facing GaN-based electronic devices, and requires more correct threshold voltage to simplify the peripheral circuits of the devices and ensure the failure safety of the system, thereby ensuring the reliable operation of the devices. The general idea for implementing a normally-off device is to keep the 2DEG with a high turn-on of the access region, i.e., not to affect the on-resistance of the device, and simultaneously deplete the channel 2DEG under the gate, so as to implement that the gate of the device is also in a turn-off state without applying a voltage. Currently, 3 methods are commonly adopted in the industry to realize normally-off GaN-based devices: (1) an insulated trench gate structure (MOSFET), (2) a Cascode structure (Cascode), (3) a p-type gate structure (p-GaN gate HEMT).

At present, regarding the implementation of a p-type gate normally-off AlGaN/GaN HEMT device, an etching technical scheme is mainly adopted in the industry, and the technology is a method commonly adopted in the industry due to easy implementation, however, the method has many disadvantages, for example, when an access region p-GaN material is removed by etching, due to poor etching uniformity and over-etching problems, and the etching may bring lattice damage to the surface of an AlGaN barrier layer and introduce an additional defect level, the electrical characteristics of an access region 2DEG may be degraded, thereby affecting the performance uniformity and stability of the device. Another technical proposal is that a p-GaN technology is adopted for growing a selective area, namely, the selective area growth of a p-GaN layer is carried out on an AlGaN/GaN heterostructure, thereby realizing the structure that the p-GaN layer is formed in a grid area and the p-GaN layer is not arranged in an access area. However, due to the influence of epitaxial growth kinetics, when the gate length of the device is small, i.e. the growth window is narrow, the selective growth of the p-GaN material is difficult to control and the doping is not uniform, and there is no breakthrough progress in these aspects. Furthermore, selective area growth requires an additional patterned mask layer to be formed on the wafer surface, and SiO is most commonly used₂Mask layer, SiO at high temperature₂Easily decomposed to generate Si and OThe elements, which diffuse into the epitaxial layer tend to form donor-type dopants, causing leakage and seriously affecting the epitaxial crystal quality, and also the influence of the mask layer on the epitaxial growth kinetics are not negligible. In addition, the hole concentration of the p-GaN layer is generally not high, and the current mainstream report value is not basically higher than 1 × 10¹⁸cm^-3Therefore, the Al composition of the AlGaN barrier layer below the p-GaN layer is generally required to be lower than 20% and the thickness is lower than 18nm, which is beneficial to achieving enhancement operation, but at the same time, the resistance of the access region is increased, and the relatively thin AlGaN barrier layer also makes the doping element (such as magnesium) in the p-GaN layer easier to diffuse to the channel, thereby affecting the reliability of the device. Furthermore, the p-GaN-gate HEMT structure is a metal-semiconductor contact structure formed by the gate, so that the gate leakage is large, the reliability of the device is low, and the p-GaN-gate HEMT structure cannot be compatible with the gate drive of the current Si-based device, thereby greatly limiting the advantages and application expansion of the GaN device.

SUMMERY OF THE UTILITY MODEL

The utility model discloses an overcome at least one defect among the above-mentioned prior art, provide a nitride device and preparation method with high reliability, can realize high threshold voltage, high conduction, high stability, high reliability, the enhancement mode semiconductor device of low electric leakage, promote the practicality of device.

In order to solve the technical problem, the utility model discloses a technical scheme is: a nitride device with high reliability comprises a substrate, a semiconductor epitaxial layer grown on the substrate, a gate, a source and a drain; the epitaxial layer sequentially comprises a nitride nucleating layer, a nitride stress buffer layer, a nitride channel layer, a primary epitaxial nitride barrier layer, a p-type nitride layer, a secondary epitaxial nitride barrier layer and a secondary epitaxial insulating medium layer from bottom to top; the p-type nitride layer is only reserved on the primary epitaxial nitride barrier layer of the grid region, and the pinch-off of a two-dimensional electron gas channel below the grid is realized; the secondary epitaxial nitride barrier layer growing process is maskless; the secondary epitaxial nitride barrier layer and the secondary epitaxial insulating medium layer are positioned on the primary epitaxial nitride barrier layer and the p-type nitride layer of the grid region, so that a high-conduction access region is realized, and effective passivation is carried out; meanwhile, by regulating and controlling the thickness and components of the primary epitaxial nitride barrier layer and the secondary epitaxial nitride barrier layer, a better grid turn-off capability and a high-conductivity grid source access region and a high-conductivity grid drain access region are realized; and forming a stacking structure containing a secondary extension insulating medium layer, a secondary extension nitride barrier layer, a p-type nitride layer and a primary extension nitride barrier layer on the grid. And a metal-insulating medium-semiconductor contact stacking structure is formed in the grid region, so that the grid reliability and the threshold voltage are improved. Finally, the enhanced semiconductor device with high threshold voltage, high conduction, high stability, high reliability and low electric leakage is realized.

In one embodiment, the substrate is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate, a GaN self-supporting substrate, or AlN.

In one embodiment, the nitride stress buffer layer is any one or combination of AlN, AlGaN, GaN and SiN.

In one embodiment, the nitride nucleation layer is an Al-containing nitride layer; the nitride channel layer is a GaN or AlGaN layer.

In one embodiment, the primary epitaxial nitride barrier layer is one or a combination of any several of AlGaN, AlInN, InGaN, AlInGaN and AlN, the Al component is 1% -30%, and the thickness is 1nm-30 nm.

In one embodiment, the secondary epitaxial nitride barrier layer is one or a combination of any several of AlGaN, AlInN, InGaN, AlInGaN and AlN, the Al component is 1% -40%, and the thickness is 1nm-40 nm.

In one embodiment, the p-type nitride layer is GaN, AlGaN, AlInN or AlInGaN, and the thickness is not less than 5 nm.

In one embodiment, an AlN space isolating layer is further inserted between the primary epitaxial nitride barrier layer and the nitride channel layer, and the thickness of the AlN space isolating layer is 0.3nm-3 nm.

In one embodiment, an AlN barrier layer is further inserted between the p-type nitride layer and the primary epitaxial nitride barrier layer, and the thickness of the AlN barrier layer is 0.3nm-5 nm.

In one embodiment, the secondary epitaxial nitride barrier layer has a higher aluminum composition content than the primary epitaxial nitride barrier layer.

In one embodiment, the secondary epitaxial insulating dielectric layer is SiN_x，SiO₂，SiO_xN_y，Al₂O₃，AlO_xN_y，GaO_x，GaO_xN_yOne or the combination of any several of the above-mentioned materials, its thickness is 1-100 nm.

In one embodiment, the p-type nitride layer of the gate region is retained, while the primary epitaxial nitride barrier layer of the region other than the region under the p-type nitride layer of the gate region is partially removed, the primary epitaxial nitride barrier layer having a thickness of 1nm to 30 nm.

In one embodiment, the source electrode and the drain electrode are ohmic contacts, and the grid electrode is a metal-insulating medium-semiconductor contact; the grid metal is directly contacted with the secondary epitaxial insulating medium layer.

Compared with the prior art, the beneficial effects are: the utility model provides a pair of nitride device with high reliability, adopt the secondary technique of extending, eliminate the sculpture scheme drawback, through design epitaxial nitride barrier layer and secondary epitaxial nitride barrier layer structure can realize the turn-off characteristic of grid below heterojunction channel and the conductivity of the regional access area heterojunction channel of grid outside simultaneously, and can be through online secondary epitaxial dielectric layer simultaneously, realize effectual access area passivation and grid reliability promotion, these advantages adopt present existing sculpture scheme or select the epitaxial p-GaN scheme of district not possess. The utility model provides a technical scheme can effectively realize finally that high threshold voltage, high switch on, high stability, high reliability, the enhancement mode semiconductor device of low electric leakage.

Drawings

Fig. 1-11 are schematic views of the device manufacturing method and process flow of embodiment 1 of the present invention.

Fig. 12 is a schematic view of a device structure in embodiment 2 of the present invention.

Fig. 13 is a schematic structural diagram of a device in embodiment 3 of the present invention.

Fig. 14 is a schematic structural diagram of a device in embodiment 4 of the present invention.

Detailed Description

The drawings are for illustrative purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.

Example 1:

as shown in fig. 11, the present embodiment provides a nitride device with high reliability, including a substrate 1, a semiconductor epitaxial layer grown on the substrate 1, a gate electrode 10, a source electrode 8, and a drain electrode 9; the epitaxial layer comprises a nitride nucleating layer 2, a nitride stress buffer layer 3, a nitride channel layer 4, a primary epitaxial nitride barrier layer 5, a p-type nitride layer 6, a secondary epitaxial nitride barrier layer 71 and a secondary epitaxial insulating medium layer 72 from bottom to top in sequence; the p-type nitride layer 6 is only remained on the primary epitaxial nitride barrier layer 5 in the area of the grid 10, so that the two-dimensional electron gas channel below the grid 10 is pinched off; the secondary epitaxial nitride barrier layer 71 is free of mask in the growth process; the secondary epitaxial nitride barrier layer 71 and the secondary epitaxial insulating medium layer 72 are positioned on the primary epitaxial nitride barrier layer 5 and the p-type nitride layer 6 in the gate 10 region, so that a high-conductivity access region is realized, and effective passivation is performed; meanwhile, by regulating and controlling the thickness and components of the primary epitaxial nitride barrier layer 5 and the secondary epitaxial nitride barrier layer 71, a better gate 10 turn-off capability and a high-conductivity gate source access region and a high-conductivity gate drain access region are realized; the gate 10 forms a stacked structure including a secondary epitaxial insulating dielectric layer 72, a secondary epitaxial nitride barrier layer 71, a p-type nitride layer 6, and a primary epitaxial nitride barrier layer 5. And a metal-insulating medium-semiconductor contact stacking structure is formed in the area of the grid 10, so that the reliability and the threshold voltage of the grid 10 are improved. Finally, the enhanced semiconductor device with high threshold voltage, high conduction, high stability, high reliability and low electric leakage is realized.

The method for manufacturing the nitride semiconductor device, as shown in fig. 1 to 11, includes the steps of:

s1, growing a nitride nucleation layer 2 on a substrate 1, as shown in figure 1;

s2, growing a nitride stress buffer layer 3 on the nitride nucleation layer 2, as shown in figure 2;

s3, growing a nitride channel layer 4 on the nitride stress buffer layer 3, as shown in figure 3;

s4, growing a primary epitaxial nitride barrier layer 5 on the nitride channel layer 4, as shown in FIG. 4;

s5, growing a p-type nitride layer 6 on the primary epitaxial nitride barrier layer 5, as shown in FIG. 5;

s6, removing all the p-type nitride layer 6 outside the gate 10 region by a photoetching patterning and etching method, and removing part of the primary epitaxial nitride barrier layer 5 outside the gate 10 region, as shown in FIG. 6;

s8, carrying out high-temperature online annealing to repair the lattice damage caused by etching, and growing a secondary epitaxial nitride barrier layer 71 as shown in FIG. 7;

s9, growing a secondary epitaxial insulating medium layer 72 on the secondary epitaxial nitride barrier layer 71 on line, as shown in FIG. 8;

s9, activating an acceptor doping element in the p-type nitride layer 6 through high-temperature annealing;

s11, completing device isolation by dry etching, as shown in FIG. 9;

s12, forming ohmic contact metal of the source electrode 8 and the drain electrode 9 on the source electrode 8 and the drain electrode 9 areas, as shown in figure 10;

s13, forming grid 10 metal on the secondary epitaxial insulating medium layer 72 in the grid 10 area, as shown in figure 11.

Thus, the whole device manufacturing process is completed. Fig. 11 is a schematic view of the device structure of example 1.

In the background art, the conventional etching scheme is used for preparing a p-type gate enhancement device, so that the requirements on equipment and a process are very strict, and the problems caused by over-etching and etching damage exist, so that the characteristics of the device are seriously deteriorated. The patent of the utility model provides an adopt the sculpture scheme to combine the secondary growth technique: the method comprises the following steps of removing the p-type nitride layer and part of the primary epitaxial nitride barrier layer outside the gate region through dry etching, and reserving the p-type nitride layer and the primary epitaxial nitride barrier layer in the gate region, so that the gate channel is pinched off. And then carrying out secondary epitaxy, carrying out MOCVD on-line high-temperature repair on the etching damage of the primary epitaxial barrier layer, and growing a secondary epitaxial nitride barrier layer under the environment of nitrogen, ammonia or mixed gas thereof, so as to realize a high-conductivity access region channel outside the gate region. The side (nonpolar or semipolar, hardly generating 2DEG) and upper side of the p-type nitride layer of the gate region can also grow a secondary epitaxial barrier layer, and due to the depletion effect of the holes in the p-type nitride layer, the turn-off can also be completely guaranteed at the two sides. And then, the primary extension barrier layer and the secondary extension barrier layer of the device can be redesigned, including the composition of aluminum element in the barrier layers and the thickness design of the barrier layers, so that the switching characteristic is remarkably improved. In addition, the secondary epitaxial insulating medium layer on the secondary epitaxial barrier layer can effectively passivate the surface of the access area, a metal-insulating medium layer-semiconductor stacking mechanism is formed on the grid, and the insulating medium layer-semiconductor interfaces of the access area and the grid area are formed by MOCVD (metal organic chemical vapor deposition) online growth, so that the passivation effect of the access area and the interface characteristic of the grid area can be obviously improved, and the dynamic resistance, the stability of threshold voltage, the reliability of the grid and other performances of the device are greatly improved.

Example 2

As shown in fig. 12, is a schematic view of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: example 1 was a case where the portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region was removed, while the portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region remained intact in example 2. Example 2 requires a more demanding etch recipe, such as more advanced equipment, or self-terminating etch conditions containing oxygen or fluorine, than example 1.

Example 3

As shown in fig. 13, is a schematic view of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: example 1 is a case where the portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region is removed, whereas example 3 is a case where the entire portion of the primary epitaxial nitride barrier layer 5 outside the gate 10 region is removed. In embodiment 3, a thin AlN space-separating layer may also be grown to a thickness of 0.3-3nm prior to the growth of the secondary epitaxial nitride barrier layer 71.

Example 4

As shown in fig. 14, is a schematic view of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: in example 1, the p-type nitride layer 6 was rectangular in shape; in example 4, the p-type nitride layer 6 had a trapezoidal shape. In addition, it is obvious that the p-type nitride shape can also be an arc-shaped structure, a step-shaped structure and the like.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present application, unless expressly stated or limited otherwise, the first feature may be directly on or directly under the second feature or indirectly via intermediate members. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the scope of the present invention.

It is obvious that the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not limitations to the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A nitride device with high reliability comprises a substrate (1), a semiconductor epitaxial layer grown on the substrate (1), a gate (10), a source (8) and a drain (9); the epitaxial layer is characterized by comprising a nitride nucleating layer (2), a nitride stress buffer layer (3), a nitride channel layer (4), a primary epitaxial nitride barrier layer (5), a p-type nitride layer (6), a secondary epitaxial nitride barrier layer (71) and a secondary epitaxial insulating medium layer (72) from bottom to top in sequence; the p-type nitride layer (6) is only reserved on the primary epitaxial nitride barrier layer (5) in the area of the grid electrode (10), and the two-dimensional electron gas channel below the grid electrode (10) is pinched off; the secondary epitaxial nitride barrier layer (71) is free of mask in the growing process; the secondary epitaxial nitride barrier layer (71) and the secondary epitaxial insulating medium layer (72) are positioned on the p-type nitride layer (6) in the primary epitaxial nitride barrier layer (5) and the grid electrode (10) region; the gate (10) forms a stacked structure including a secondary epitaxial insulating dielectric layer (72), a secondary epitaxial nitride barrier layer (71), a p-type nitride layer (6), and a primary epitaxial nitride barrier layer (5).

2. The nitride device with high reliability according to claim 1, characterized in that the primary epitaxial nitride barrier layer (5) has a thickness of 1nm-30 nm; the thickness of the secondary epitaxial nitride barrier layer (71) is 1nm-40 nm.

3. The nitride device with high reliability according to claim 1, characterized in that the thickness of the p-type nitride layer (6) is not less than 5 nm.

4. The nitride device with high reliability according to claim 1, characterized in that an AlN space isolation layer is further interposed between the primary epitaxial nitride barrier layer (5) and the nitride channel layer (4), the AlN space isolation layer having a thickness of 0.3nm-3 nm.

5. The nitride device with high reliability according to claim 1, characterized in that an AlN barrier layer is further interposed between the p-type nitride layer (6) and the primary epitaxial nitride barrier layer (5), the AlN barrier layer having a thickness of 0.3nm to 5 nm.

6. A nitride device with high reliability according to claim 3, characterized in that the aluminum composition content of the secondary epitaxial nitride barrier layer (71) is higher than that of the primary epitaxial nitride barrier layer (5).

7. The nitride device with high reliability according to claim 1, characterized in that the secondary epitaxial insulating dielectric layer (72) has a thickness of 1-100 nm.

8. The nitride device with high reliability according to any of claims 1 to 7, characterized in that the p-type nitride layer (6) of the gate (10) area is retained, while the primary epitaxial nitride barrier layer (5) of the area outside the area under the p-type nitride layer (6) of the gate (10) area is partially removed, the primary epitaxial nitride barrier layer (5) having a thickness of 1nm-30 nm.

9. The nitride device with high reliability according to claim 8, characterized in that the source (8) and drain (9) are ohmic contacts and the gate (10) is a metal-insulator-semiconductor contact; the metal of the grid (10) is directly contacted with the secondary epitaxial insulating medium layer (72).