CN216413092U

CN216413092U - Power transistor and electronic equipment

Info

Publication number: CN216413092U
Application number: CN202122776448.0U
Authority: CN
Inventors: 夏令
Original assignee: Dingnuo Microelectronics Beijing Co ltd
Current assignee: Dingnuo Microelectronics Beijing Co ltd
Priority date: 2021-11-06
Filing date: 2021-11-06
Publication date: 2022-04-29
Anticipated expiration: 2031-11-06

Abstract

The present application relates to a power transistor comprising an insulating substrate; the insulating medium layer is positioned above the insulating substrate and provided with an opening; a first semiconductor layer formed by epitaxial growth from the opening region of the dielectric layer; a channel buffer layer located above the first semiconductor layer; a barrier layer located above the channel buffer layer; a gate, a source, and a drain over the barrier layer; wherein a partial region of the first semiconductor layer located below the source electrode is doped to form a conductive field plate, the field plate and the source electrode are coupled through an electrical connection structure, and a side edge of the field plate is located between a gate side edge adjacent to the same side thereof and a drain side edge adjacent to the same side thereof. The application also provides related electronic equipment.

Description

Power transistor and electronic equipment

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a power transistor and an electronic device including an insulating substrate.

Background

III-V semiconductors such as GaN power circuits benefit from the characteristics of high frequency, low resistance and low capacitance, and have great potential to replace silicon power circuits. The commercial use of GaN devices has been preliminarily validated and has entered the rapid growth phase. Many GaN power device technologies currently use conductive (111) silicon as the substrate material. The main consideration is that the cost of silicon-based GaN is lower than that of SiC-based GaN, and the heat dissipation property is better than that of sapphire-based GaN, which belongs to a choice of price and performance compromise.

Silicon-based GaN suffers from a number of problems. Firstly, the lattice mismatch between the silicon substrate and the GaN epitaxial layer in silicon-based GaN reaches 16%, which is greater than the mismatch between SiC and sapphire. This results in a higher defect density of GaN-on-si, which affects device performance. Secondly, the thermal mismatch ratio of Si and GaN is also the highest of the three, reaching 60%. This may lead to non-uniformity in the growth of silicon-based GaN. Finally, there is a conductive path between the conductive silicon substrate and the crystalline layer AlN or the buffer layer, which leads to a lower breakdown voltage of the si-based epitaxy than the other two (with the same buffer layer thickness).

In order to alleviate the above-described problems in Si-based GaN, the following methods are often employed.

For the lattice mismatch aspect: the defect density of the epitaxial layer is reduced by optimizing the material collocation of the buffer layer epitaxy, but the effect is limited; and (3) adopting selective Epitaxy or lateral Epitaxy (epitaxix lateral Epitaxy), namely blocking part of the substrate region through a dielectric mask so that epitaxial defects grow and turn without reaching the top of the epitaxial layer.

In terms of the thermal mismatch problem: different materials (AlN/AlGaN/GaN or superlattice and the like) are used in combination to optimize the compressive stress and tensile stress period in the growth process, so that the wafer warpage caused by thermal adaptation is relieved; instead of a large portion of the Si substrate, a ceramic substrate with a thermal expansion coefficient close to that of GaN is used, for example.

For substrate induced leakage or breakdown voltage reduction: the thickness of the buffer layer is increased, but the defects are increased and the cost is increased; the Si substrate of the drain portion is removed.

Therefore, the silicon-based GaN has a plurality of technical difficulties. However, a major technical obstacle in implementing a power device by using sapphire-based GaN epitaxy is that sapphire is an insulating substrate, and the back grounding function of the device is lost, so that the sapphire-based GaN device is very easy to have the problem of Dynamic resistance (Dynamic Ron) or Current collapse (Current collepse).

Fig. 1 is a schematic diagram of the variation of power device current with voltage, as shown,R_{DS_on}is the on-resistance R 'of the existing power device in a static state'_{DS_on}The on-resistance of the existing power device is shown in the dynamic condition after being stressed and is larger than the R in the static state_{DS_on}. Because the electron distribution is influenced by the high-voltage electric field, the off-state voltage stress of the power device can cause the on-state resistance of the device to be increased by more than several times. Therefore, the conventional power device is not suitable for a power circuit which needs to operate in a high frequency state because the dynamic resistance is too large in the high frequency operation state.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problems in the prior art, the application provides a power transistor, which comprises an insulating substrate; the insulating medium layer is positioned above the insulating substrate and provided with an opening; a first semiconductor layer formed by epitaxial growth from the opening region of the dielectric layer; a channel buffer layer located above the first semiconductor layer; a barrier layer located above the channel buffer layer; a gate, a source, and a drain over the barrier layer; wherein a partial region of the first semiconductor layer located below the source electrode is doped to form a conductive field plate, the field plate and the source electrode are coupled through an electrical connection structure, and a side edge of the field plate is located between a gate side edge adjacent to the same side thereof and a drain side edge adjacent to the same side thereof.

In particular, the linear distance between the side edge of the field plate and the nearest point between the side edge of the drain electrode adjacent to the same side is smaller than or equal to the linear distance between the side edge of the drain electrode adjacent to the same side and the side edge of the gate electrode adjacent to the same side.

In particular, the side edge of the field plate is located at the middle line position between the side edge of the drain electrode adjacent to the same side of the field plate and the side edge of the gate electrode adjacent to the same side of the field plate.

In particular, the distance between the side edge of the field plate and the side edge of the drain electrode adjacent to the same side along the vertical long line is larger than the thickness of the channel buffer layer.

Particularly, the power transistor further comprises an isolation structure which is positioned below the drain electrode and is positioned between the drain electrode and the insulating medium layer.

In particular, the isolation structure comprises a metallic material or an insulating dielectric material, and/or the isolation structure comprises a solid or hollow structure.

Particularly, the power transistor further comprises a seed crystal layer positioned above the insulating substrate and an underlying buffer layer positioned above the seed crystal layer; wherein the insulating medium layer is located above the base buffer layer.

In particular, the power transistor further comprises a diffusion barrier layer located around the field plate, and the channel buffer layer is located above the upper surface of the diffusion barrier layer.

In particular, the insulating substrate comprises SiC, Al₂O₃GaN, diamond material.

In particular, the first semiconductor layer and/or the channel buffer layer include GaN or AlGaN or AlN.

In particular, the field plate has a doping concentration of at least 10¹⁷。

Particularly, the channel buffer layer or the basic buffer layer also comprises an AlN layer.

The present application further provides an electronic device comprising a power transistor as described in any of the preceding.

The application also provides a preparation method of the power transistor, which comprises the steps of forming an insulating medium layer above the insulating substrate; patterning the insulating medium layer to form a plurality of openings; epitaxially growing a first semiconductor layer in the opening region, and doping the first semiconductor layer to form a conductive field plate; stopping doping of the first semiconductor layer epitaxially grown in adjacent opening regions before the first semiconductor layers are connected to each other; epitaxially growing a channel buffer layer on the first semiconductor layer; forming a barrier layer over the channel buffer layer; forming a conductive structure over the conductive field plate that penetrates through the barrier layer and the channel buffer layer and is electrically connected to the conductive field plate; forming a source, a drain, a gate over the barrier layer, wherein the source is electrically connected with a respective conductive structure.

In particular, the method further comprises forming a diffusion barrier layer around the conductive field plates after forming the conductive field plates, and continuing epitaxy to form undoped first semiconductor layers between adjacent conductive field plates.

In particular, the method further comprises forming a seed layer over the insulating substrate prior to forming the insulating dielectric layer; forming a base buffer layer over the seed layer; and forming the insulating medium layer above the basic buffer layer.

In particular, the method further includes forming an isolation structure through the barrier layer and the channel buffer layer and in contact with the insulating dielectric layer over the first semiconductor layer between adjacent field plates; wherein the drain is formed over the isolation structure.

In particular, a linear distance between a closest point between the side edge of the insulated field plate and the side edge of the drain adjacent to the same side is less than or equal to a linear distance between the side edge of the drain adjacent to the same side and the side edge of the gate adjacent to the same side.

Drawings

Preferred embodiments of the present application will now be described in further detail with reference to the accompanying drawings, in which:

FIG. 1 is a diagram illustrating the performance of a conventional insulated substrate power transistor;

FIG. 2 is a schematic diagram of a power device according to an embodiment of the present application;

fig. 3 is a schematic diagram of a power transistor structure according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a power transistor according to an embodiment of the present application;

FIGS. 5A-5C are partial schematic views of power transistors according to various embodiments of the present disclosure;

fig. 6 is a schematic diagram of a power transistor according to another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.

To solve the problem of excessive dynamic resistance of the power device on the insulating substrate described above, the present application provides the following power transistor structure.

Fig. 2 is a schematic diagram of a power device according to an embodiment of the present application.

According to one embodiment, the power device may include a substrate 200, which may be an insulating or semi-insulating substrate, such as sapphire, diamond, SiC, GaN, Ga₂O₃、AlN、Al₂O₃And the like.

According to an embodiment, the power device may further comprise an insulating dielectric layer 210, such as SiN or SiO, over the substrate 200₂。

According to an embodiment, the dielectric layer 210 may comprise a plurality of openings, and the power device may further comprise a III-V semiconductor layer 220 epitaxially grown on the area provided with the openings, such as GaN or AlGaN or AlN. The following description will be made by taking GaN as an example.

According to various embodiments, the GaN layer 220 corresponds to the open area of the dielectric layerThe domains and their adjacent portions may be heavily doped N-type or P-type to form an electrically conductive field plate. And, the doping concentration is relatively high, e.g. 10¹⁷The above. According to one embodiment, adjacent conductive field plates are electrically isolated from each other by undoped GaN regions.

Alternatively, according to an embodiment, the power device may further comprise a diffusion barrier layer 230 located around the conductive field plate. The material of the diffusion barrier 230 may include, for example, AlN, SiC, or the like. The thickness of the diffusion barrier layer 230 may be several nanometers to several hundred nanometers as desired. The diffusion barrier layer functions to limit diffusion of impurities of the conductive field plate into the subsequently grown epitaxial material. If the GaN layer 220 contains impurities which are not intentionally doped in the regions except the field plate region, the content of the impurities can directly affect the breakdown voltage of the power device, so that the problem caused by the unintentional doping can be effectively avoided by arranging the diffusion barrier layer around the conductive field plate. In addition, the portion of the diffusion barrier layer above the conductive field plate helps to extend the critical thickness (critical thickness) of the epitaxially grown channel buffer layer 240.

According to an embodiment, the power device may further include a channel buffer layer 240, such as an epitaxially grown intrinsic GaN layer, located above the GaN layer 220. According to an embodiment, a layer of AlN (not shown) may be disposed in the middle of the channel buffer layer to increase the thickness of the channel buffer layer 240.

According to an embodiment, the power device may further include a barrier layer 250 over the channel buffer layer 240.

According to one embodiment, a gate (G), a source (S), and a drain (D) may be disposed on the barrier layer 250. The heterojunction interface between the channel buffer layer 240 and the barrier layer 250 forms an electron well in which a two-dimensional electron gas is formed, thereby forming a conductive channel between the buffer layer and the barrier layer that allows the directional transport of electrons from the source to the drain.

According to one embodiment, the source of the power device is electrically connected to a conductive field plate in the respective GaN layer 220 below it. For example, as shown in fig. 2, an electrical connection structure 260 is provided beneath the source electrode, through the barrier layer 250 and the channel buffer layer 240, which structure directly contacts the conductive field plate beneath the source electrode. According to one embodiment, the source electrode may or may not be aligned with the corresponding opening of the insulating dielectric layer 210, as long as it is ensured that the source electrode is electrically connected to the conductive field plate through the electrical connection structure 260. With such a structure, a voltage can be applied to the field plate. Therefore, the field plate having the same potential as the source electrode can disperse an electric field between the adjacent drain and gate electrodes, thereby reducing the dynamic resistance of the power transistor. Meanwhile, the distance between the field plate and the adjacent drain electrode also meets a specific limiting condition so as to reduce leakage current and prevent the breakdown voltage of the power transistor from being reduced.

Fig. 3 is a schematic diagram of a power transistor structure according to another embodiment of the present application. The power device differs from the power device shown in fig. 2 in that the power device comprises a seed layer 302 located above a substrate 300, and the material of the seed layer 302 may comprise AlN.

According to an embodiment, the power device may further include an underlying buffer layer 304 over the seed layer 302, the underlying buffer layer material may include, for example, GaN, AlGaN, AlN. An insulating dielectric layer 310 is formed over the underlying buffer layer 304. According to one embodiment, an AlN layer (not shown) may be included in the middle of the underlying buffer layer 304 to increase the thickness of the underlying buffer layer 304.

The power device shown in fig. 3 has the advantage of providing lower leakage current and higher breakdown voltage.

Fig. 4 is a schematic diagram of a power transistor according to an embodiment of the present application. The gate s is electrically connected to the field plate 4201 through an electrical connection structure 460 penetrating the barrier layer 450 and the channel buffer layer 440.

As shown, AA ', BB', CC 'are respectively the gate S side edge (AA') and the drain D side edge (CC ') adjacent to the same side at the edge (BB') of one field plate 4201. According to one embodiment, the edge BB ' of the field plate may be arranged between AA ' and CC ', e.g. at the position of the middle line between AA ' and CC ', in order to spread the electric field between the drain and the gate and thereby reduce the dynamic resistance. At the same time, field plate edge BB 'cannot be too close to drain edge CC' because too close this distance will reduce the breakdown voltage between the gate and drain.

According to one embodiment, for example, the thickness T of the channel epitaxial layer 440 over the field plate may be 1-5 microns and the distance between AA 'and CC' may be 5-20 microns (e.g., for 650V GaN devices). The distance between BB 'and CC' is greater than the distance of T and the field plate may be 0.1-200 microns, for example 20 microns, in length. According to one embodiment, the distance between the plates may be the sum of the length of the drain and 2 times the distance between BB 'and CC'.

According to one embodiment, D in fig. 4 is the closest point to the drain on the same side on the edge of the field plate, E is the closest point to the field plate on the edge of the drain, F is the closest point to the drain on the same side on the edge of the source, and the linear distance between two points EF should be smaller than the distance between AA 'and CC', and under the precondition, the linear distance between EF is made as large as possible. Of course, the specific value needs to be designed according to the distribution condition of the electric field, and relates to the specific parameters of the structure and material combination of the device, and the specific value is related to the gate-drain bias condition under different working conditions.

Fig. 5A-5C are schematic views illustrating partial structures of power transistors according to various embodiments of the present disclosure. According to various embodiments, the shape of the conductive field plate may be controlled by controlling parameters of the epitaxial growth. Fig. 5A shows a conductive field plate having a substantially rectangular side cross-section, fig. 5B shows a conductive field plate having a substantially trapezoidal side cross-section, and fig. 5C shows a conductive field plate having a substantially triangular side cross-section. Whatever shape of the epitaxially grown conductive field plate is required, its edges satisfy the above positional relationship with the adjacent gate and drain electrodes. In a way, the shape of the field plate with triangular or trapezoidal side interface near the drain edge is a bevel edge, which more easily satisfies the above requirements on the distance between the side edge of the field plate, the side edge of the drain and the side edge of the gate adjacent to the same side.

Fig. 6 is a schematic diagram of a power transistor according to another embodiment of the present application. An isolation structure 670 passing through the barrier layer 650 and the epitaxial layer of the channel buffer layer 640 may be included under the drain in the power transistor. Further, the isolation structure 670 may be in contact with a conductive field plate in the GaN layer 620, for example. The isolation structure 670 may comprise a metal or insulating dielectric material, and may be a solid structure or a hollow structure. The isolation structure 670 may remove the high defect density region of the selectively epitaxial GaN layer 620 at the lateral junction of the non-conducting field plate portions to avoid its adverse effects.

There is also provided, in accordance with an embodiment of the present application, a method of making a power device, including

Optionally, a seed layer is formed on the insulating substrate.

Optionally, an underlying buffer layer is formed on the seed layer.

An insulating dielectric layer is formed over the insulating substrate (directly or on the underlying buffer layer), and according to one embodiment, the dielectric layer may be formed immediately after the growth of the underlying buffer layer in the same vacuum environment (in-situ) or may be formed in two steps by another process (ex-situ).

The insulating dielectric layer is patterned and a plurality of open regions are formed.

Performing epitaxial growth on the opening region to form a first semiconductor layer, and performing heavy doping on the first semiconductor layer to form a conductive field plate while forming the first semiconductor layer in the opening region and the region near the opening region, for example, the doping concentration reaches 10¹⁷The above. According to one embodiment, the epitaxial Growth may be Selective epitaxial Growth (SAG), that is, the epitaxial Growth of the first semiconductor layer only occurs in the open region not covered by the insulating dielectric layer, and no epitaxial Growth occurs in the region covered by the insulating dielectric layer. According to one embodiment, when the first semiconductor layer epitaxially grown outside the opening region exceeds the opening region, the first semiconductor layer can be laterally grown (laterally grown) by process control to cover at least part of the insulating dielectric layer. According to one embodiment, the doping is stopped before the epitaxially grown first semiconductor layers of adjacent opening regions merge together, i.e., the length of the heavily doped region or field plate is controlled. According to one embodiment, the first semiconductor layer may comprise GaN or other III-V semiconductors.

Optionally, a diffusion barrier layer is formed around the conductive field plate.

After the doping is finished, the first semiconductor layers are bonded to one another by epitaxial growth on the basis of the open regions. It can be seen that the first semiconductor layer between the conductive field plates is an undoped intrinsic semiconductor.

A channel buffer layer is grown over the first semiconductor layer, wherein the first semiconductor layer and the channel buffer layer may comprise the same III-V semiconductor material, and the channel buffer layer is an intrinsic semiconductor layer.

A barrier layer is formed on the channel buffer layer, and optionally a top GaN layer may also be formed on the barrier layer.

An electrical connection structure is formed through the barrier layer, the channel buffer layer and coupled or electrically connected to the field plate, which may include a conductive material, such as a metal. According to one embodiment, the electrical connection structure may be realized by a process of etching, which in some cases may not have a way to stop just at the interface between the trench buffer layer and the field plate, thereby allowing a moderate penetration of the electrical connection structure into the field plate.

Alternatively, an isolation structure is formed through the barrier layer, the channel buffer layer and in contact with the insulating dielectric layer, which may comprise a conductive or insulating material, and which may comprise a solid or hollow structure.

A gate, a source, and a drain are formed on the barrier layer, the source coupled to the electrical connection structure by metallization, and the optional drain may be in contact with the isolation structure.

The power transistor disclosed by the application can solve the problem of dynamic resistance of a GaN device on an insulating substrate due to the lack of a conductive substrate. Therefore, the application of the insulating substrate GaN in power devices can be developed, and various difficulties faced in Si-based GaN are avoided. Even facing substrate materials having both insulating and conductive types, such as SiC, using this structure enables similar breakdown voltage levels to be achieved on insulating substrates with thinner channel buffer layers than required for similar conductive substrates, thereby reducing product cost.

The above-described embodiments are provided for illustrative purposes only and are not intended to be limiting, and various changes and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and therefore, all equivalent technical solutions should fall within the scope of the present disclosure.

Claims

1. A power transistor, comprising

An insulating substrate;

the insulating medium layer is positioned above the insulating substrate and provided with an opening;

a first semiconductor layer formed by epitaxial growth from the opening region of the dielectric layer;

a channel buffer layer located above the first semiconductor layer;

a barrier layer located above the channel buffer layer; and

a gate, a source, and a drain over the barrier layer;

wherein a partial region of the first semiconductor layer located below the source electrode is doped to form a conductive field plate, the field plate and the source electrode are coupled through an electrical connection structure, and a side edge of the field plate is located between a gate side edge adjacent to the same side thereof and a drain side edge adjacent to the same side thereof.

2. The power transistor of claim 1, wherein a linear distance between a side edge of said field plate and a closest point between drain side edges adjacent to the same side thereof is less than or equal to a linear distance between said drain side edge adjacent to the same side thereof and said gate side edge adjacent to the same side thereof.

3. The power transistor of claim 2, wherein a side edge of said field plate is located at a centerline position between said drain side edge adjacent to said same side thereof and said gate side edge adjacent to said same side thereof.

4. The power transistor of claim 1, wherein a distance between the field plate side edge vertical elongation line and a drain side edge adjacent thereto on the same side along the vertical elongation line is greater than a thickness of the channel buffer layer.

5. The power transistor of claim 1 or 2, further comprising an isolation structure located below the drain between the drain and the insulating dielectric layer.

6. The power transistor of claim 5, in which the isolation structure comprises a metallic material or an insulating dielectric material, and/or the isolation structure comprises a solid or hollow structure.

7. The power transistor of claim 1, further comprising a seed layer over the insulating substrate and an underlying buffer layer over the seed layer; wherein the insulating medium layer is located above the base buffer layer.

8. The power transistor of claim 1, further comprising a diffusion barrier layer located around said field plate, said channel buffer layer being located above an upper surface of said diffusion barrier layer.

9. The power transistor of claim 1, wherein the first semiconductor layer and/or the channel buffer layer comprises GaN or AlGaN or AlN.

10. The power transistor of claim 1, further comprising an AlN layer in between said channel buffer layers.

11. The power transistor of claim 7, further comprising an AlN layer in between said underlying buffer layers.

12. An electronic device comprising a power transistor according to any of claims 1-11.